1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6450 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6450.h>
36 static struct clksrc_clk clk_mout_dpll = {
41 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
45 static u32 epll_div[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
51 static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
53 unsigned int epll_con, epll_con_k;
56 if (clk->rate == rate) /* Return if nothing changed */
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
83 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
91 static struct clk_ops s5p6450_epll_ops = {
92 .get_rate = s5p_epll_get_rate,
93 .set_rate = s5p6450_epll_set_rate,
96 static struct clksrc_clk clk_dout_epll = {
100 .parent = &clk_mout_epll.clk,
102 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
105 static struct clksrc_clk clk_mout_hclk_sel = {
107 .name = "mout_hclk_sel",
110 .sources = &clkset_hclk_low,
111 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
114 static struct clk *clkset_hclk_list[] = {
115 &clk_mout_hclk_sel.clk,
119 static struct clksrc_sources clkset_hclk = {
120 .sources = clkset_hclk_list,
121 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
124 static struct clksrc_clk clk_hclk = {
129 .sources = &clkset_hclk,
130 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
131 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
134 static struct clksrc_clk clk_pclk = {
138 .parent = &clk_hclk.clk,
140 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
142 static struct clksrc_clk clk_dout_pwm_ratio0 = {
144 .name = "clk_dout_pwm_ratio0",
146 .parent = &clk_mout_hclk_sel.clk,
148 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
151 static struct clksrc_clk clk_pclk_to_wdt_pwm = {
153 .name = "clk_pclk_to_wdt_pwm",
155 .parent = &clk_dout_pwm_ratio0.clk,
157 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
160 static struct clksrc_clk clk_hclk_low = {
162 .name = "clk_hclk_low",
165 .sources = &clkset_hclk_low,
166 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
167 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
170 static struct clksrc_clk clk_pclk_low = {
172 .name = "clk_pclk_low",
174 .parent = &clk_hclk_low.clk,
176 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
180 * The following clocks will be disabled during clock initialization. It is
181 * recommended to keep the following clocks disabled until the driver requests
182 * for enabling the clock.
184 static struct clk init_clocks_off[] = {
188 .parent = &clk_hclk_low.clk,
189 .enable = s5p64x0_hclk0_ctrl,
194 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk0_ctrl,
196 .ctrlbit = (1 << 12),
200 .parent = &clk_hclk_low.clk,
201 .enable = s5p64x0_hclk0_ctrl,
202 .ctrlbit = (1 << 17),
206 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk0_ctrl,
208 .ctrlbit = (1 << 18),
212 .parent = &clk_hclk_low.clk,
213 .enable = s5p64x0_hclk0_ctrl,
214 .ctrlbit = (1 << 19),
218 .parent = &clk_hclk_low.clk,
219 .enable = s5p64x0_hclk0_ctrl,
220 .ctrlbit = (1 << 20),
225 .enable = s5p64x0_hclk1_ctrl,
230 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl,
236 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl,
242 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 12),
248 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 17),
254 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 21),
260 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 22),
266 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 26),
272 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 15),
278 .parent = &clk_pclk_low.clk,
279 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 16),
284 .parent = &clk_pclk_low.clk,
285 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 27),
290 .parent = &clk_pclk.clk,
291 .enable = s5p64x0_pclk_ctrl,
292 .ctrlbit = (1 << 30),
297 * The following clocks will be enabled during clock initialization.
299 static struct clk init_clocks[] = {
303 .parent = &clk_hclk.clk,
304 .enable = s5p64x0_hclk0_ctrl,
309 .parent = &clk_hclk.clk,
310 .enable = s5p64x0_hclk0_ctrl,
311 .ctrlbit = (1 << 21),
315 .parent = &clk_pclk_low.clk,
316 .enable = s5p64x0_pclk_ctrl,
321 .parent = &clk_pclk_low.clk,
322 .enable = s5p64x0_pclk_ctrl,
327 .parent = &clk_pclk_low.clk,
328 .enable = s5p64x0_pclk_ctrl,
333 .parent = &clk_pclk_low.clk,
334 .enable = s5p64x0_pclk_ctrl,
339 .parent = &clk_pclk_to_wdt_pwm.clk,
340 .enable = s5p64x0_pclk_ctrl,
345 .parent = &clk_pclk_low.clk,
346 .enable = s5p64x0_pclk_ctrl,
347 .ctrlbit = (1 << 18),
351 static struct clk *clkset_uart_list[] = {
356 static struct clksrc_sources clkset_uart = {
357 .sources = clkset_uart_list,
358 .nr_sources = ARRAY_SIZE(clkset_uart_list),
361 static struct clk *clkset_mali_list[] = {
367 static struct clksrc_sources clkset_mali = {
368 .sources = clkset_mali_list,
369 .nr_sources = ARRAY_SIZE(clkset_mali_list),
372 static struct clk *clkset_group2_list[] = {
378 static struct clksrc_sources clkset_group2 = {
379 .sources = clkset_group2_list,
380 .nr_sources = ARRAY_SIZE(clkset_group2_list),
383 static struct clk *clkset_dispcon_list[] = {
390 static struct clksrc_sources clkset_dispcon = {
391 .sources = clkset_dispcon_list,
392 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
395 static struct clk *clkset_hsmmc44_list[] = {
403 static struct clksrc_sources clkset_hsmmc44 = {
404 .sources = clkset_hsmmc44_list,
405 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
408 static struct clk *clkset_sclk_audio0_list[] = {
409 [0] = &clk_dout_epll.clk,
410 [1] = &clk_dout_mpll.clk,
411 [2] = &clk_ext_xtal_mux,
416 static struct clksrc_sources clkset_sclk_audio0 = {
417 .sources = clkset_sclk_audio0_list,
418 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
421 static struct clksrc_clk clk_sclk_audio0 = {
425 .enable = s5p64x0_sclk_ctrl,
427 .parent = &clk_dout_epll.clk,
429 .sources = &clkset_sclk_audio0,
430 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
431 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
434 static struct clksrc_clk clksrcs[] = {
439 .ctrlbit = (1 << 24),
440 .enable = s5p64x0_sclk_ctrl,
442 .sources = &clkset_group2,
443 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
444 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
449 .ctrlbit = (1 << 25),
450 .enable = s5p64x0_sclk_ctrl,
452 .sources = &clkset_group2,
453 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
454 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
459 .ctrlbit = (1 << 26),
460 .enable = s5p64x0_sclk_ctrl,
462 .sources = &clkset_group2,
463 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
464 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
470 .enable = s5p64x0_sclk_ctrl,
472 .sources = &clkset_uart,
473 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
474 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
479 .ctrlbit = (1 << 20),
480 .enable = s5p64x0_sclk_ctrl,
482 .sources = &clkset_group2,
483 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
484 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
489 .ctrlbit = (1 << 21),
490 .enable = s5p64x0_sclk_ctrl,
492 .sources = &clkset_group2,
493 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
494 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
499 .ctrlbit = (1 << 10),
500 .enable = s5p64x0_sclk_ctrl,
502 .sources = &clkset_group2,
503 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
504 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
510 .enable = s5p64x0_sclk1_ctrl,
512 .sources = &clkset_mali,
513 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
514 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
519 .ctrlbit = (1 << 12),
520 .enable = s5p64x0_sclk_ctrl,
522 .sources = &clkset_mali,
523 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
524 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
530 .enable = s5p64x0_sclk_ctrl,
532 .sources = &clkset_group2,
533 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
534 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
537 .name = "sclk_camif",
540 .enable = s5p64x0_sclk_ctrl,
542 .sources = &clkset_group2,
543 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
544 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
547 .name = "sclk_dispcon",
550 .enable = s5p64x0_sclk1_ctrl,
552 .sources = &clkset_dispcon,
553 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
554 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
557 .name = "sclk_hsmmc44",
559 .ctrlbit = (1 << 30),
560 .enable = s5p64x0_sclk_ctrl,
562 .sources = &clkset_hsmmc44,
563 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
564 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
568 /* Clock initialization code */
569 static struct clksrc_clk *sysclks[] = {
577 &clk_dout_pwm_ratio0,
578 &clk_pclk_to_wdt_pwm,
586 void __init_or_cpufreq s5p6450_setup_clocks(void)
588 struct clk *xtal_clk;
593 unsigned long hclk_low;
595 unsigned long pclk_low;
603 /* Set S5P6450 functions for clk_fout_epll */
605 clk_fout_epll.enable = s5p_epll_enable;
606 clk_fout_epll.ops = &s5p6450_epll_ops;
608 clk_48m.enable = s5p64x0_clk48m_ctrl;
610 xtal_clk = clk_get(NULL, "ext_xtal");
611 BUG_ON(IS_ERR(xtal_clk));
613 xtal = clk_get_rate(xtal_clk);
616 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
617 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
618 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
619 __raw_readl(S5P64X0_EPLL_CON_K));
620 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
621 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
623 clk_fout_apll.rate = apll;
624 clk_fout_mpll.rate = mpll;
625 clk_fout_epll.rate = epll;
626 clk_fout_dpll.rate = dpll;
628 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
629 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
630 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
633 fclk = clk_get_rate(&clk_armclk.clk);
634 hclk = clk_get_rate(&clk_hclk.clk);
635 pclk = clk_get_rate(&clk_pclk.clk);
636 hclk_low = clk_get_rate(&clk_hclk_low.clk);
637 pclk_low = clk_get_rate(&clk_pclk_low.clk);
639 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
640 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
641 print_mhz(hclk), print_mhz(hclk_low),
642 print_mhz(pclk), print_mhz(pclk_low));
648 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
649 s3c_set_clksrc(&clksrcs[ptr], true);
652 void __init s5p6450_register_clocks(void)
656 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
657 s3c_register_clksrc(sysclks[ptr], 1);
659 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
660 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
662 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
663 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));