1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6440 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6440.h>
36 static u32 epll_div[][5] = {
37 { 36000000, 0, 48, 1, 4 },
38 { 48000000, 0, 32, 1, 3 },
39 { 60000000, 0, 40, 1, 3 },
40 { 72000000, 0, 48, 1, 3 },
41 { 84000000, 0, 28, 1, 2 },
42 { 96000000, 0, 32, 1, 2 },
43 { 32768000, 45264, 43, 1, 4 },
44 { 45158000, 6903, 30, 1, 3 },
45 { 49152000, 50332, 32, 1, 3 },
46 { 67738000, 10398, 45, 1, 3 },
47 { 73728000, 9961, 49, 1, 3 }
50 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
52 unsigned int epll_con, epll_con_k;
55 if (clk->rate == rate) /* Return if nothing changed */
58 epll_con = __raw_readl(S5P64X0_EPLL_CON);
59 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61 epll_con_k &= ~(PLL90XX_KDIV_MASK);
62 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65 if (epll_div[i][0] == rate) {
66 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
68 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
69 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
74 if (i == ARRAY_SIZE(epll_div)) {
75 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
79 __raw_writel(epll_con, S5P64X0_EPLL_CON);
80 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
90 static struct clk_ops s5p6440_epll_ops = {
91 .get_rate = s5p_epll_get_rate,
92 .set_rate = s5p6440_epll_set_rate,
95 static struct clksrc_clk clk_hclk = {
99 .parent = &clk_armclk.clk,
101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
104 static struct clksrc_clk clk_pclk = {
108 .parent = &clk_hclk.clk,
110 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
112 static struct clksrc_clk clk_hclk_low = {
114 .name = "clk_hclk_low",
117 .sources = &clkset_hclk_low,
118 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
119 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
122 static struct clksrc_clk clk_pclk_low = {
124 .name = "clk_pclk_low",
126 .parent = &clk_hclk_low.clk,
128 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
132 * The following clocks will be disabled during clock initialization. It is
133 * recommended to keep the following clocks disabled until the driver requests
134 * for enabling the clock.
136 static struct clk init_clocks_off[] = {
140 .parent = &clk_hclk.clk,
141 .enable = s5p64x0_mem_ctrl,
146 .parent = &clk_hclk_low.clk,
147 .enable = s5p64x0_hclk0_ctrl,
152 .parent = &clk_hclk.clk,
153 .enable = s5p64x0_hclk0_ctrl,
158 .parent = &clk_hclk_low.clk,
159 .enable = s5p64x0_hclk0_ctrl,
160 .ctrlbit = (1 << 12),
164 .parent = &clk_hclk_low.clk,
165 .enable = s5p64x0_hclk0_ctrl,
166 .ctrlbit = (1 << 17),
170 .parent = &clk_hclk_low.clk,
171 .enable = s5p64x0_hclk0_ctrl,
172 .ctrlbit = (1 << 18),
176 .parent = &clk_hclk_low.clk,
177 .enable = s5p64x0_hclk0_ctrl,
178 .ctrlbit = (1 << 19),
182 .parent = &clk_hclk_low.clk,
183 .enable = s5p64x0_hclk0_ctrl,
188 .parent = &clk_hclk.clk,
189 .enable = s5p64x0_hclk0_ctrl,
190 .ctrlbit = (1 << 25),
194 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk1_ctrl,
198 .name = "hclk_fimgvg",
200 .parent = &clk_hclk.clk,
201 .enable = s5p64x0_hclk1_ctrl,
206 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk1_ctrl,
212 .parent = &clk_pclk_low.clk,
213 .enable = s5p64x0_pclk_ctrl,
218 .parent = &clk_pclk_low.clk,
219 .enable = s5p64x0_pclk_ctrl,
224 .parent = &clk_pclk_low.clk,
225 .enable = s5p64x0_pclk_ctrl,
230 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl,
236 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 12),
242 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 17),
248 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 21),
254 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 22),
260 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 25),
266 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 26),
272 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 28),
278 .parent = &clk_pclk.clk,
279 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 29),
284 .parent = &clk_pclk.clk,
285 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 30),
288 .name = "pclk_fimgvg",
290 .parent = &clk_pclk.clk,
291 .enable = s5p64x0_pclk_ctrl,
292 .ctrlbit = (1 << 31),
294 .name = "sclk_spi_48",
297 .enable = s5p64x0_sclk_ctrl,
298 .ctrlbit = (1 << 22),
300 .name = "sclk_spi_48",
303 .enable = s5p64x0_sclk_ctrl,
304 .ctrlbit = (1 << 23),
309 .enable = s5p64x0_sclk_ctrl,
310 .ctrlbit = (1 << 27),
315 .enable = s5p64x0_sclk_ctrl,
316 .ctrlbit = (1 << 28),
321 .enable = s5p64x0_sclk_ctrl,
322 .ctrlbit = (1 << 29),
327 * The following clocks will be enabled during clock initialization.
329 static struct clk init_clocks[] = {
333 .parent = &clk_hclk.clk,
334 .enable = s5p64x0_hclk0_ctrl,
339 .parent = &clk_hclk.clk,
340 .enable = s5p64x0_hclk0_ctrl,
341 .ctrlbit = (1 << 21),
345 .parent = &clk_pclk_low.clk,
346 .enable = s5p64x0_pclk_ctrl,
351 .parent = &clk_pclk_low.clk,
352 .enable = s5p64x0_pclk_ctrl,
357 .parent = &clk_pclk_low.clk,
358 .enable = s5p64x0_pclk_ctrl,
363 .parent = &clk_pclk_low.clk,
364 .enable = s5p64x0_pclk_ctrl,
369 .parent = &clk_pclk_low.clk,
370 .enable = s5p64x0_pclk_ctrl,
371 .ctrlbit = (1 << 18),
375 static struct clk clk_iis_cd_v40 = {
376 .name = "iis_cdclk_v40",
380 static struct clk clk_pcm_cd = {
385 static struct clk *clkset_group1_list[] = {
391 static struct clksrc_sources clkset_group1 = {
392 .sources = clkset_group1_list,
393 .nr_sources = ARRAY_SIZE(clkset_group1_list),
396 static struct clk *clkset_uart_list[] = {
401 static struct clksrc_sources clkset_uart = {
402 .sources = clkset_uart_list,
403 .nr_sources = ARRAY_SIZE(clkset_uart_list),
406 static struct clk *clkset_audio_list[] = {
414 static struct clksrc_sources clkset_audio = {
415 .sources = clkset_audio_list,
416 .nr_sources = ARRAY_SIZE(clkset_audio_list),
419 static struct clksrc_clk clksrcs[] = {
424 .ctrlbit = (1 << 24),
425 .enable = s5p64x0_sclk_ctrl,
427 .sources = &clkset_group1,
428 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
434 .ctrlbit = (1 << 25),
435 .enable = s5p64x0_sclk_ctrl,
437 .sources = &clkset_group1,
438 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
439 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
444 .ctrlbit = (1 << 26),
445 .enable = s5p64x0_sclk_ctrl,
447 .sources = &clkset_group1,
448 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
449 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
455 .enable = s5p64x0_sclk_ctrl,
457 .sources = &clkset_uart,
458 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
459 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
464 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl,
467 .sources = &clkset_group1,
468 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
474 .ctrlbit = (1 << 21),
475 .enable = s5p64x0_sclk_ctrl,
477 .sources = &clkset_group1,
478 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
479 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
484 .ctrlbit = (1 << 10),
485 .enable = s5p64x0_sclk_ctrl,
487 .sources = &clkset_group1,
488 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
489 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
492 .name = "sclk_dispcon",
495 .enable = s5p64x0_sclk1_ctrl,
497 .sources = &clkset_group1,
498 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
499 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
502 .name = "sclk_fimgvg",
505 .enable = s5p64x0_sclk1_ctrl,
507 .sources = &clkset_group1,
508 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
509 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
512 .name = "sclk_audio2",
514 .ctrlbit = (1 << 11),
515 .enable = s5p64x0_sclk_ctrl,
517 .sources = &clkset_audio,
518 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
519 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
523 /* Clock initialization code */
524 static struct clksrc_clk *sysclks[] = {
536 void __init_or_cpufreq s5p6440_setup_clocks(void)
538 struct clk *xtal_clk;
543 unsigned long hclk_low;
545 unsigned long pclk_low;
552 /* Set S5P6440 functions for clk_fout_epll */
554 clk_fout_epll.enable = s5p_epll_enable;
555 clk_fout_epll.ops = &s5p6440_epll_ops;
557 clk_48m.enable = s5p64x0_clk48m_ctrl;
559 xtal_clk = clk_get(NULL, "ext_xtal");
560 BUG_ON(IS_ERR(xtal_clk));
562 xtal = clk_get_rate(xtal_clk);
565 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
566 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
567 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
568 __raw_readl(S5P64X0_EPLL_CON_K));
570 clk_fout_apll.rate = apll;
571 clk_fout_mpll.rate = mpll;
572 clk_fout_epll.rate = epll;
574 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
576 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
578 fclk = clk_get_rate(&clk_armclk.clk);
579 hclk = clk_get_rate(&clk_hclk.clk);
580 pclk = clk_get_rate(&clk_pclk.clk);
581 hclk_low = clk_get_rate(&clk_hclk_low.clk);
582 pclk_low = clk_get_rate(&clk_pclk_low.clk);
584 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
585 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
586 print_mhz(hclk), print_mhz(hclk_low),
587 print_mhz(pclk), print_mhz(pclk_low));
593 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
594 s3c_set_clksrc(&clksrcs[ptr], true);
597 static struct clk *clks[] __initdata = {
603 void __init s5p6440_register_clocks(void)
607 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
609 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
610 s3c_register_clksrc(sysclks[ptr], 1);
612 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
613 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
615 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
616 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));