cgroup: superblock can't be released with active dentries
[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-s3c64xx / mach-real6410.c
1 /* linux/arch/arm/mach-s3c64xx/mach-real6410.c
2  *
3  * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4  * Copyright 2008 Openmoko, Inc.
5  * Copyright 2008 Simtec Electronics
6  *      Ben Dooks <ben@simtec.co.uk>
7  *      http://armlinux.simtec.co.uk/
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13 */
14
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/fb.h>
18 #include <linux/gpio.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/dm9000.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/platform_device.h>
25 #include <linux/serial_core.h>
26 #include <linux/types.h>
27
28 #include <asm/hardware/vic.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32
33 #include <mach/map.h>
34 #include <mach/regs-gpio.h>
35 #include <mach/regs-modem.h>
36 #include <mach/regs-srom.h>
37
38 #include <plat/adc.h>
39 #include <plat/cpu.h>
40 #include <plat/devs.h>
41 #include <plat/fb.h>
42 #include <plat/nand.h>
43 #include <plat/regs-serial.h>
44 #include <plat/ts.h>
45 #include <plat/regs-fb-v4.h>
46
47 #include <video/platform_lcd.h>
48
49 #include "common.h"
50
51 #define UCON S3C2410_UCON_DEFAULT
52 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
53 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
54
55 static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
56         [0] = {
57                 .hwport = 0,
58                 .flags  = 0,
59                 .ucon   = UCON,
60                 .ulcon  = ULCON,
61                 .ufcon  = UFCON,
62         },
63         [1] = {
64                 .hwport = 1,
65                 .flags  = 0,
66                 .ucon   = UCON,
67                 .ulcon  = ULCON,
68                 .ufcon  = UFCON,
69         },
70         [2] = {
71                 .hwport = 2,
72                 .flags  = 0,
73                 .ucon   = UCON,
74                 .ulcon  = ULCON,
75                 .ufcon  = UFCON,
76         },
77         [3] = {
78                 .hwport = 3,
79                 .flags  = 0,
80                 .ucon   = UCON,
81                 .ulcon  = ULCON,
82                 .ufcon  = UFCON,
83         },
84 };
85
86 /* DM9000AEP 10/100 ethernet controller */
87
88 static struct resource real6410_dm9k_resource[] = {
89         [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
90         [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
91         [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
92                                         | IORESOURCE_IRQ_HIGHLEVEL),
93 };
94
95 static struct dm9000_plat_data real6410_dm9k_pdata = {
96         .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
97 };
98
99 static struct platform_device real6410_device_eth = {
100         .name           = "dm9000",
101         .id             = -1,
102         .num_resources  = ARRAY_SIZE(real6410_dm9k_resource),
103         .resource       = real6410_dm9k_resource,
104         .dev            = {
105                 .platform_data  = &real6410_dm9k_pdata,
106         },
107 };
108
109 static struct s3c_fb_pd_win real6410_fb_win[] = {
110         {
111                 .win_mode       = {     /* 4.3" 480x272 */
112                         .left_margin    = 3,
113                         .right_margin   = 2,
114                         .upper_margin   = 1,
115                         .lower_margin   = 1,
116                         .hsync_len      = 40,
117                         .vsync_len      = 1,
118                         .xres           = 480,
119                         .yres           = 272,
120                 },
121                 .max_bpp        = 32,
122                 .default_bpp    = 16,
123         }, {
124                 .win_mode       = {     /* 7.0" 800x480 */
125                         .left_margin    = 8,
126                         .right_margin   = 13,
127                         .upper_margin   = 7,
128                         .lower_margin   = 5,
129                         .hsync_len      = 3,
130                         .vsync_len      = 1,
131                         .xres           = 800,
132                         .yres           = 480,
133                 },
134                 .max_bpp        = 32,
135                 .default_bpp    = 16,
136         },
137 };
138
139 static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
140         .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
141         .win[0]         = &real6410_fb_win[0],
142         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
143         .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
144 };
145
146 static struct mtd_partition real6410_nand_part[] = {
147         [0] = {
148                 .name   = "uboot",
149                 .size   = SZ_1M,
150                 .offset = 0,
151         },
152         [1] = {
153                 .name   = "kernel",
154                 .size   = SZ_2M,
155                 .offset = SZ_1M,
156         },
157         [2] = {
158                 .name   = "rootfs",
159                 .size   = MTDPART_SIZ_FULL,
160                 .offset = SZ_1M + SZ_2M,
161         },
162 };
163
164 static struct s3c2410_nand_set real6410_nand_sets[] = {
165         [0] = {
166                 .name           = "nand",
167                 .nr_chips       = 1,
168                 .nr_partitions  = ARRAY_SIZE(real6410_nand_part),
169                 .partitions     = real6410_nand_part,
170         },
171 };
172
173 static struct s3c2410_platform_nand real6410_nand_info = {
174         .tacls          = 25,
175         .twrph0         = 55,
176         .twrph1         = 40,
177         .nr_sets        = ARRAY_SIZE(real6410_nand_sets),
178         .sets           = real6410_nand_sets,
179 };
180
181 static struct platform_device *real6410_devices[] __initdata = {
182         &real6410_device_eth,
183         &s3c_device_hsmmc0,
184         &s3c_device_hsmmc1,
185         &s3c_device_fb,
186         &s3c_device_nand,
187         &s3c_device_adc,
188         &s3c_device_ts,
189         &s3c_device_ohci,
190 };
191
192 static void __init real6410_map_io(void)
193 {
194         u32 tmp;
195
196         s3c64xx_init_io(NULL, 0);
197         s3c24xx_init_clocks(12000000);
198         s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
199
200         /* set the LCD type */
201         tmp = __raw_readl(S3C64XX_SPCON);
202         tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
203         tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
204         __raw_writel(tmp, S3C64XX_SPCON);
205
206         /* remove the LCD bypass */
207         tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
208         tmp &= ~MIFPCON_LCD_BYPASS;
209         __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
210 }
211
212 /*
213  * real6410_features string
214  *
215  * 0-9 LCD configuration
216  *
217  */
218 static char real6410_features_str[12] __initdata = "0";
219
220 static int __init real6410_features_setup(char *str)
221 {
222         if (str)
223                 strlcpy(real6410_features_str, str,
224                         sizeof(real6410_features_str));
225         return 1;
226 }
227
228 __setup("real6410=", real6410_features_setup);
229
230 #define FEATURE_SCREEN (1 << 0)
231
232 struct real6410_features_t {
233         int done;
234         int lcd_index;
235 };
236
237 static void real6410_parse_features(
238                 struct real6410_features_t *features,
239                 const char *features_str)
240 {
241         const char *fp = features_str;
242
243         features->done = 0;
244         features->lcd_index = 0;
245
246         while (*fp) {
247                 char f = *fp++;
248
249                 switch (f) {
250                 case '0'...'9': /* tft screen */
251                         if (features->done & FEATURE_SCREEN) {
252                                 printk(KERN_INFO "REAL6410: '%c' ignored, "
253                                         "screen type already set\n", f);
254                         } else {
255                                 int li = f - '0';
256                                 if (li >= ARRAY_SIZE(real6410_fb_win))
257                                         printk(KERN_INFO "REAL6410: '%c' out "
258                                                 "of range LCD mode\n", f);
259                                 else {
260                                         features->lcd_index = li;
261                                 }
262                         }
263                         features->done |= FEATURE_SCREEN;
264                         break;
265                 }
266         }
267 }
268
269 static void __init real6410_machine_init(void)
270 {
271         u32 cs1;
272         struct real6410_features_t features = { 0 };
273
274         printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
275                         real6410_features_str);
276
277         /* Parse the feature string */
278         real6410_parse_features(&features, real6410_features_str);
279
280         real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
281
282         printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
283                 real6410_lcd_pdata.win[0]->win_mode.xres,
284                 real6410_lcd_pdata.win[0]->win_mode.yres);
285
286         s3c_fb_set_platdata(&real6410_lcd_pdata);
287         s3c_nand_set_platdata(&real6410_nand_info);
288         s3c24xx_ts_set_platdata(NULL);
289
290         /* configure nCS1 width to 16 bits */
291
292         cs1 = __raw_readl(S3C64XX_SROM_BW) &
293                 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
294         cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
295                 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
296                 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
297                         S3C64XX_SROM_BW__NCS1__SHIFT;
298         __raw_writel(cs1, S3C64XX_SROM_BW);
299
300         /* set timing for nCS1 suitable for ethernet chip */
301
302         __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
303                 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
304                 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
305                 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
306                 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
307                 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
308                 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
309
310         gpio_request(S3C64XX_GPF(15), "LCD power");
311
312         platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
313 }
314
315 MACHINE_START(REAL6410, "REAL6410")
316         /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
317         .atag_offset    = 0x100,
318
319         .init_irq       = s3c6410_init_irq,
320         .handle_irq     = vic_handle_irq,
321         .map_io         = real6410_map_io,
322         .init_machine   = real6410_machine_init,
323         .timer          = &s3c24xx_timer,
324         .restart        = s3c64xx_restart,
325 MACHINE_END