arch/arm/mach-s3c64xx/common.c

   1 /*
   2  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Copyright 2008 Openmoko, Inc.
   6  * Copyright 2008 Simtec Electronics
   7  *      Ben Dooks <ben@simtec.co.uk>
   8  *      http://armlinux.simtec.co.uk/
   9  *
  10  * Common Codes for S3C64XX machines
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/ioport.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/reboot.h>
  25 #include <linux/io.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/irq.h>
  28 #include <linux/gpio.h>
  29 #include <linux/irqchip/arm-vic.h>
  30
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/map.h>
  33 #include <asm/system_misc.h>
  34
  35 #include <mach/map.h>
  36 #include <mach/hardware.h>
  37 #include <mach/regs-gpio.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/clock.h>
  41 #include <plat/devs.h>
  42 #include <plat/pm.h>
  43 #include <plat/gpio-cfg.h>
  44 #include <plat/irq-uart.h>
  45 #include <plat/irq-vic-timer.h>
  46 #include <plat/regs-irqtype.h>
  47 #include <plat/regs-serial.h>
  48 #include <plat/watchdog-reset.h>
  49
  50 #include "common.h"
  51
  52 /* uart registration process */
  53
  54 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  55 {
  56         s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
  57 }
  58
  59 /* table of supported CPUs */
  60
  61 static const char name_s3c6400[] = "S3C6400";
  62 static const char name_s3c6410[] = "S3C6410";
  63
  64 static struct cpu_table cpu_ids[] __initdata = {
  65         {
  66                 .idcode         = S3C6400_CPU_ID,
  67                 .idmask         = S3C64XX_CPU_MASK,
  68                 .map_io         = s3c6400_map_io,
  69                 .init_clocks    = s3c6400_init_clocks,
  70                 .init_uarts     = s3c64xx_init_uarts,
  71                 .init           = s3c6400_init,
  72                 .name           = name_s3c6400,
  73         }, {
  74                 .idcode         = S3C6410_CPU_ID,
  75                 .idmask         = S3C64XX_CPU_MASK,
  76                 .map_io         = s3c6410_map_io,
  77                 .init_clocks    = s3c6410_init_clocks,
  78                 .init_uarts     = s3c64xx_init_uarts,
  79                 .init           = s3c6410_init,
  80                 .name           = name_s3c6410,
  81         },
  82 };
  83
  84 /* minimal IO mapping */
  85
  86 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
  87 #define UART_OFFS (S3C_PA_UART & 0xfffff)
  88
  89 static struct map_desc s3c_iodesc[] __initdata = {
  90         {
  91                 .virtual        = (unsigned long)S3C_VA_SYS,
  92                 .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
  93                 .length         = SZ_4K,
  94                 .type           = MT_DEVICE,
  95         }, {
  96                 .virtual        = (unsigned long)S3C_VA_MEM,
  97                 .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
  98                 .length         = SZ_4K,
  99                 .type           = MT_DEVICE,
 100         }, {
 101                 .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
 102                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 103                 .length         = SZ_4K,
 104                 .type           = MT_DEVICE,
 105         }, {
 106                 .virtual        = (unsigned long)VA_VIC0,
 107                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
 108                 .length         = SZ_16K,
 109                 .type           = MT_DEVICE,
 110         }, {
 111                 .virtual        = (unsigned long)VA_VIC1,
 112                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
 113                 .length         = SZ_16K,
 114                 .type           = MT_DEVICE,
 115         }, {
 116                 .virtual        = (unsigned long)S3C_VA_TIMER,
 117                 .pfn            = __phys_to_pfn(S3C_PA_TIMER),
 118                 .length         = SZ_16K,
 119                 .type           = MT_DEVICE,
 120         }, {
 121                 .virtual        = (unsigned long)S3C64XX_VA_GPIO,
 122                 .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
 123                 .length         = SZ_4K,
 124                 .type           = MT_DEVICE,
 125         }, {
 126                 .virtual        = (unsigned long)S3C64XX_VA_MODEM,
 127                 .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
 128                 .length         = SZ_4K,
 129                 .type           = MT_DEVICE,
 130         }, {
 131                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 132                 .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
 133                 .length         = SZ_4K,
 134                 .type           = MT_DEVICE,
 135         }, {
 136                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 137                 .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
 138                 .length         = SZ_1K,
 139                 .type           = MT_DEVICE,
 140         },
 141 };
 142
 143 static struct bus_type s3c64xx_subsys = {
 144         .name           = "s3c64xx-core",
 145         .dev_name       = "s3c64xx-core",
 146 };
 147
 148 static struct device s3c64xx_dev = {
 149         .bus    = &s3c64xx_subsys,
 150 };
 151
 152 /* read cpu identification code */
 153
 154 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 155 {
 156         /* initialise the io descriptors we need for initialisation */
 157         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 158         iotable_init(mach_desc, size);
 159
 160         /* detect cpu id */
 161         s3c64xx_init_cpu();
 162
 163         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 164 }
 165
 166 static __init int s3c64xx_dev_init(void)
 167 {
 168         subsys_system_register(&s3c64xx_subsys, NULL);
 169         return device_register(&s3c64xx_dev);
 170 }
 171 core_initcall(s3c64xx_dev_init);
 172
 173 /*
 174  * setup the sources the vic should advertise resume
 175  * for, even though it is not doing the wake
 176  * (set_irq_wake needs to be valid)
 177  */
 178 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
 179 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
 180                          1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
 181                          1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
 182                          1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
 183                          1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 184
 185 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 186 {
 187         /*
 188          * FIXME: there is no better place to put this at the moment
 189          * (samsung_wdt_reset_init needs clocks)
 190          */
 191         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 192
 193         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 194
 195         /* initialise the pair of VICs */
 196         vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
 197         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 198
 199         /* add the timer sub-irqs */
 200         s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 201 }
 202
 203 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 204 #define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
 205
 206 static inline void s3c_irq_eint_mask(struct irq_data *data)
 207 {
 208         u32 mask;
 209
 210         mask = __raw_readl(S3C64XX_EINT0MASK);
 211         mask |= (u32)data->chip_data;
 212         __raw_writel(mask, S3C64XX_EINT0MASK);
 213 }
 214
 215 static void s3c_irq_eint_unmask(struct irq_data *data)
 216 {
 217         u32 mask;
 218
 219         mask = __raw_readl(S3C64XX_EINT0MASK);
 220         mask &= ~((u32)data->chip_data);
 221         __raw_writel(mask, S3C64XX_EINT0MASK);
 222 }
 223
 224 static inline void s3c_irq_eint_ack(struct irq_data *data)
 225 {
 226         __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
 227 }
 228
 229 static void s3c_irq_eint_maskack(struct irq_data *data)
 230 {
 231         /* compiler should in-line these */
 232         s3c_irq_eint_mask(data);
 233         s3c_irq_eint_ack(data);
 234 }
 235
 236 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
 237 {
 238         int offs = eint_offset(data->irq);
 239         int pin, pin_val;
 240         int shift;
 241         u32 ctrl, mask;
 242         u32 newvalue = 0;
 243         void __iomem *reg;
 244
 245         if (offs > 27)
 246                 return -EINVAL;
 247
 248         if (offs <= 15)
 249                 reg = S3C64XX_EINT0CON0;
 250         else
 251                 reg = S3C64XX_EINT0CON1;
 252
 253         switch (type) {
 254         case IRQ_TYPE_NONE:
 255                 printk(KERN_WARNING "No edge setting!\n");
 256                 break;
 257
 258         case IRQ_TYPE_EDGE_RISING:
 259                 newvalue = S3C2410_EXTINT_RISEEDGE;
 260                 break;
 261
 262         case IRQ_TYPE_EDGE_FALLING:
 263                 newvalue = S3C2410_EXTINT_FALLEDGE;
 264                 break;
 265
 266         case IRQ_TYPE_EDGE_BOTH:
 267                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 268                 break;
 269
 270         case IRQ_TYPE_LEVEL_LOW:
 271                 newvalue = S3C2410_EXTINT_LOWLEV;
 272                 break;
 273
 274         case IRQ_TYPE_LEVEL_HIGH:
 275                 newvalue = S3C2410_EXTINT_HILEV;
 276                 break;
 277
 278         default:
 279                 printk(KERN_ERR "No such irq type %d", type);
 280                 return -1;
 281         }
 282
 283         if (offs <= 15)
 284                 shift = (offs / 2) * 4;
 285         else
 286                 shift = ((offs - 16) / 2) * 4;
 287         mask = 0x7 << shift;
 288
 289         ctrl = __raw_readl(reg);
 290         ctrl &= ~mask;
 291         ctrl |= newvalue << shift;
 292         __raw_writel(ctrl, reg);
 293
 294         /* set the GPIO pin appropriately */
 295
 296         if (offs < 16) {
 297                 pin = S3C64XX_GPN(offs);
 298                 pin_val = S3C_GPIO_SFN(2);
 299         } else if (offs < 23) {
 300                 pin = S3C64XX_GPL(offs + 8 - 16);
 301                 pin_val = S3C_GPIO_SFN(3);
 302         } else {
 303                 pin = S3C64XX_GPM(offs - 23);
 304                 pin_val = S3C_GPIO_SFN(3);
 305         }
 306
 307         s3c_gpio_cfgpin(pin, pin_val);
 308
 309         return 0;
 310 }
 311
 312 static struct irq_chip s3c_irq_eint = {
 313         .name           = "s3c-eint",
 314         .irq_mask       = s3c_irq_eint_mask,
 315         .irq_unmask     = s3c_irq_eint_unmask,
 316         .irq_mask_ack   = s3c_irq_eint_maskack,
 317         .irq_ack        = s3c_irq_eint_ack,
 318         .irq_set_type   = s3c_irq_eint_set_type,
 319         .irq_set_wake   = s3c_irqext_wake,
 320 };
 321
 322 /* s3c_irq_demux_eint
 323  *
 324  * This function demuxes the IRQ from the group0 external interrupts,
 325  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 326  * the specific handlers s3c_irq_demux_eintX_Y.
 327  */
 328 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
 329 {
 330         u32 status = __raw_readl(S3C64XX_EINT0PEND);
 331         u32 mask = __raw_readl(S3C64XX_EINT0MASK);
 332         unsigned int irq;
 333
 334         status &= ~mask;
 335         status >>= start;
 336         status &= (1 << (end - start + 1)) - 1;
 337
 338         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 339                 if (status & 1)
 340                         generic_handle_irq(irq);
 341
 342                 status >>= 1;
 343         }
 344 }
 345
 346 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 347 {
 348         s3c_irq_demux_eint(0, 3);
 349 }
 350
 351 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 352 {
 353         s3c_irq_demux_eint(4, 11);
 354 }
 355
 356 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
 357 {
 358         s3c_irq_demux_eint(12, 19);
 359 }
 360
 361 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
 362 {
 363         s3c_irq_demux_eint(20, 27);
 364 }
 365
 366 static int __init s3c64xx_init_irq_eint(void)
 367 {
 368         int irq;
 369
 370         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
 371                 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
 372                 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
 373                 set_irq_flags(irq, IRQF_VALID);
 374         }
 375
 376         irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
 377         irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
 378         irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
 379         irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 380
 381         return 0;
 382 }
 383 arch_initcall(s3c64xx_init_irq_eint);
 384
 385 void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 386 {
 387         if (mode != REBOOT_SOFT)
 388                 samsung_wdt_reset();
 389
 390         /* if all else fails, or mode was for soft, jump to 0 */
 391         soft_restart(0);
 392 }
 393
 394 void __init s3c64xx_init_late(void)
 395 {
 396         s3c64xx_pm_late_initcall();
 397 }