2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * Common Codes for S3C64XX machines
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
22 #include <linux/serial_core.h>
23 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/gpio.h>
28 #include <linux/irqchip/arm-vic.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/system_misc.h>
35 #include <mach/hardware.h>
36 #include <mach/regs-gpio.h>
39 #include <plat/clock.h>
40 #include <plat/devs.h>
42 #include <plat/gpio-cfg.h>
43 #include <plat/irq-uart.h>
44 #include <plat/irq-vic-timer.h>
45 #include <plat/regs-irqtype.h>
46 #include <plat/regs-serial.h>
47 #include <plat/watchdog-reset.h>
51 /* uart registration process */
53 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
55 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
58 /* table of supported CPUs */
60 static const char name_s3c6400[] = "S3C6400";
61 static const char name_s3c6410[] = "S3C6410";
63 static struct cpu_table cpu_ids[] __initdata = {
65 .idcode = S3C6400_CPU_ID,
66 .idmask = S3C64XX_CPU_MASK,
67 .map_io = s3c6400_map_io,
68 .init_clocks = s3c6400_init_clocks,
69 .init_uarts = s3c64xx_init_uarts,
73 .idcode = S3C6410_CPU_ID,
74 .idmask = S3C64XX_CPU_MASK,
75 .map_io = s3c6410_map_io,
76 .init_clocks = s3c6410_init_clocks,
77 .init_uarts = s3c64xx_init_uarts,
83 /* minimal IO mapping */
85 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
86 #define UART_OFFS (S3C_PA_UART & 0xfffff)
88 static struct map_desc s3c_iodesc[] __initdata = {
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
95 .virtual = (unsigned long)S3C_VA_MEM,
96 .pfn = __phys_to_pfn(S3C64XX_PA_SROM),
100 .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
101 .pfn = __phys_to_pfn(S3C_PA_UART),
105 .virtual = (unsigned long)VA_VIC0,
106 .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
110 .virtual = (unsigned long)VA_VIC1,
111 .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
115 .virtual = (unsigned long)S3C_VA_TIMER,
116 .pfn = __phys_to_pfn(S3C_PA_TIMER),
120 .virtual = (unsigned long)S3C64XX_VA_GPIO,
121 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
125 .virtual = (unsigned long)S3C64XX_VA_MODEM,
126 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
130 .virtual = (unsigned long)S3C_VA_WATCHDOG,
131 .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
135 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
136 .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
142 static struct bus_type s3c64xx_subsys = {
143 .name = "s3c64xx-core",
144 .dev_name = "s3c64xx-core",
147 static struct device s3c64xx_dev = {
148 .bus = &s3c64xx_subsys,
151 /* read cpu identification code */
153 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
155 /* initialise the io descriptors we need for initialisation */
156 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
157 iotable_init(mach_desc, size);
162 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
165 static __init int s3c64xx_dev_init(void)
167 subsys_system_register(&s3c64xx_subsys, NULL);
168 return device_register(&s3c64xx_dev);
170 core_initcall(s3c64xx_dev_init);
173 * setup the sources the vic should advertise resume
174 * for, even though it is not doing the wake
175 * (set_irq_wake needs to be valid)
177 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
178 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
179 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
180 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
181 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
182 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
184 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
187 * FIXME: there is no better place to put this at the moment
188 * (samsung_wdt_reset_init needs clocks)
190 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
192 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
194 /* initialise the pair of VICs */
195 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
196 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
198 /* add the timer sub-irqs */
199 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
202 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
203 #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
205 static inline void s3c_irq_eint_mask(struct irq_data *data)
209 mask = __raw_readl(S3C64XX_EINT0MASK);
210 mask |= (u32)data->chip_data;
211 __raw_writel(mask, S3C64XX_EINT0MASK);
214 static void s3c_irq_eint_unmask(struct irq_data *data)
218 mask = __raw_readl(S3C64XX_EINT0MASK);
219 mask &= ~((u32)data->chip_data);
220 __raw_writel(mask, S3C64XX_EINT0MASK);
223 static inline void s3c_irq_eint_ack(struct irq_data *data)
225 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
228 static void s3c_irq_eint_maskack(struct irq_data *data)
230 /* compiler should in-line these */
231 s3c_irq_eint_mask(data);
232 s3c_irq_eint_ack(data);
235 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
237 int offs = eint_offset(data->irq);
248 reg = S3C64XX_EINT0CON0;
250 reg = S3C64XX_EINT0CON1;
254 printk(KERN_WARNING "No edge setting!\n");
257 case IRQ_TYPE_EDGE_RISING:
258 newvalue = S3C2410_EXTINT_RISEEDGE;
261 case IRQ_TYPE_EDGE_FALLING:
262 newvalue = S3C2410_EXTINT_FALLEDGE;
265 case IRQ_TYPE_EDGE_BOTH:
266 newvalue = S3C2410_EXTINT_BOTHEDGE;
269 case IRQ_TYPE_LEVEL_LOW:
270 newvalue = S3C2410_EXTINT_LOWLEV;
273 case IRQ_TYPE_LEVEL_HIGH:
274 newvalue = S3C2410_EXTINT_HILEV;
278 printk(KERN_ERR "No such irq type %d", type);
283 shift = (offs / 2) * 4;
285 shift = ((offs - 16) / 2) * 4;
288 ctrl = __raw_readl(reg);
290 ctrl |= newvalue << shift;
291 __raw_writel(ctrl, reg);
293 /* set the GPIO pin appropriately */
296 pin = S3C64XX_GPN(offs);
297 pin_val = S3C_GPIO_SFN(2);
298 } else if (offs < 23) {
299 pin = S3C64XX_GPL(offs + 8 - 16);
300 pin_val = S3C_GPIO_SFN(3);
302 pin = S3C64XX_GPM(offs - 23);
303 pin_val = S3C_GPIO_SFN(3);
306 s3c_gpio_cfgpin(pin, pin_val);
311 static struct irq_chip s3c_irq_eint = {
313 .irq_mask = s3c_irq_eint_mask,
314 .irq_unmask = s3c_irq_eint_unmask,
315 .irq_mask_ack = s3c_irq_eint_maskack,
316 .irq_ack = s3c_irq_eint_ack,
317 .irq_set_type = s3c_irq_eint_set_type,
318 .irq_set_wake = s3c_irqext_wake,
321 /* s3c_irq_demux_eint
323 * This function demuxes the IRQ from the group0 external interrupts,
324 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
325 * the specific handlers s3c_irq_demux_eintX_Y.
327 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
329 u32 status = __raw_readl(S3C64XX_EINT0PEND);
330 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
335 status &= (1 << (end - start + 1)) - 1;
337 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
339 generic_handle_irq(irq);
345 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
347 s3c_irq_demux_eint(0, 3);
350 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
352 s3c_irq_demux_eint(4, 11);
355 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
357 s3c_irq_demux_eint(12, 19);
360 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
362 s3c_irq_demux_eint(20, 27);
365 static int __init s3c64xx_init_irq_eint(void)
369 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
370 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
371 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
372 set_irq_flags(irq, IRQF_VALID);
375 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
376 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
377 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
378 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
382 arch_initcall(s3c64xx_init_irq_eint);
384 void s3c64xx_restart(char mode, const char *cmd)
389 /* if all else fails, or mode was for soft, jump to 0 */
393 void __init s3c64xx_init_late(void)
395 s3c64xx_pm_late_initcall();