1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
23 #include <mach/hardware.h>
26 #include <mach/regs-clock.h>
29 #include <plat/devs.h>
30 #include <plat/cpu-freq.h>
31 #include <plat/clock.h>
32 #include <plat/clock-clksrc.h>
37 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
38 * ext_xtal_mux for want of an actual name from the manual.
41 static struct clk clk_ext_xtal_mux = {
45 #define clk_fin_apll clk_ext_xtal_mux
46 #define clk_fin_mpll clk_ext_xtal_mux
47 #define clk_fin_epll clk_ext_xtal_mux
49 #define clk_fout_mpll clk_mpll
50 #define clk_fout_epll clk_epll
57 struct clk clk_27m = {
62 static int clk_48m_ctrl(struct clk *clk, int enable)
67 /* can't rely on clock lock, this register has other usages */
68 local_irq_save(flags);
70 val = __raw_readl(S3C64XX_OTHERS);
72 val |= S3C64XX_OTHERS_USBMASK;
74 val &= ~S3C64XX_OTHERS_USBMASK;
76 __raw_writel(val, S3C64XX_OTHERS);
77 local_irq_restore(flags);
82 struct clk clk_48m = {
85 .enable = clk_48m_ctrl,
88 struct clk clk_xusbxti = {
93 static int inline s3c64xx_gate(void __iomem *reg,
97 unsigned int ctrlbit = clk->ctrlbit;
100 con = __raw_readl(reg);
107 __raw_writel(con, reg);
111 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
113 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
116 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
118 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
121 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
123 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
126 static struct clk init_clocks_off[] = {
133 .enable = s3c64xx_pclk_ctrl,
134 .ctrlbit = S3C_CLKCON_PCLK_RTC,
138 .enable = s3c64xx_pclk_ctrl,
139 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
142 .devname = "s3c2440-i2c.0",
144 .enable = s3c64xx_pclk_ctrl,
145 .ctrlbit = S3C_CLKCON_PCLK_IIC,
148 .devname = "s3c2440-i2c.1",
150 .enable = s3c64xx_pclk_ctrl,
151 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
155 .enable = s3c64xx_pclk_ctrl,
156 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
159 .devname = "s3c6410-spi.0",
161 .enable = s3c64xx_pclk_ctrl,
162 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
165 .devname = "s3c6410-spi.1",
167 .enable = s3c64xx_pclk_ctrl,
168 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
171 .devname = "s3c-sdhci.0",
173 .enable = s3c64xx_sclk_ctrl,
174 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
177 .devname = "s3c-sdhci.1",
179 .enable = s3c64xx_sclk_ctrl,
180 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
183 .devname = "s3c-sdhci.2",
185 .enable = s3c64xx_sclk_ctrl,
186 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
190 .ctrlbit = S3C_CLKCON_PCLK_AC97,
194 .enable = s3c64xx_hclk_ctrl,
195 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
199 .enable = s3c64xx_hclk_ctrl,
200 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
204 .enable = s3c64xx_hclk_ctrl,
205 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
209 .enable = s3c64xx_hclk_ctrl,
210 .ctrlbit = S3C_CLKCON_HCLK_3DSE,
212 .name = "hclk_secur",
214 .enable = s3c64xx_hclk_ctrl,
215 .ctrlbit = S3C_CLKCON_HCLK_SECUR,
219 .enable = s3c64xx_hclk_ctrl,
220 .ctrlbit = S3C_CLKCON_HCLK_SDMA1,
224 .enable = s3c64xx_hclk_ctrl,
225 .ctrlbit = S3C_CLKCON_HCLK_SDMA0,
229 .enable = s3c64xx_hclk_ctrl,
230 .ctrlbit = S3C_CLKCON_HCLK_JPEG,
234 .enable = s3c64xx_hclk_ctrl,
235 .ctrlbit = S3C_CLKCON_HCLK_CAMIF,
237 .name = "hclk_scaler",
239 .enable = s3c64xx_hclk_ctrl,
240 .ctrlbit = S3C_CLKCON_HCLK_SCALER,
244 .enable = s3c64xx_hclk_ctrl,
245 .ctrlbit = S3C_CLKCON_HCLK_2D,
249 .enable = s3c64xx_hclk_ctrl,
250 .ctrlbit = S3C_CLKCON_HCLK_TV,
254 .enable = s3c64xx_hclk_ctrl,
255 .ctrlbit = S3C_CLKCON_HCLK_POST0,
259 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_ROT,
264 .enable = s3c64xx_hclk_ctrl,
265 .ctrlbit = S3C_CLKCON_HCLK_MFC,
269 .enable = s3c64xx_pclk_ctrl,
270 .ctrlbit = S3C_CLKCON_PCLK_MFC,
273 .enable = s3c64xx_sclk_ctrl,
274 .ctrlbit = S3C_CLKCON_SCLK_DAC27,
277 .enable = s3c64xx_sclk_ctrl,
278 .ctrlbit = S3C_CLKCON_SCLK_TV27,
281 .enable = s3c64xx_sclk_ctrl,
282 .ctrlbit = S3C_CLKCON_SCLK_SCALER27,
284 .name = "sclk_scaler",
285 .enable = s3c64xx_sclk_ctrl,
286 .ctrlbit = S3C_CLKCON_SCLK_SCALER,
289 .enable = s3c64xx_sclk_ctrl,
290 .ctrlbit = S3C_CLKCON_SCLK_POST0_27,
293 .enable = s3c64xx_sclk_ctrl,
294 .ctrlbit = S3C_CLKCON_SCLK_SECUR,
297 .enable = s3c64xx_sclk_ctrl,
298 .ctrlbit = S3C_CLKCON_SCLK_MFC,
301 .enable = s3c64xx_sclk_ctrl,
302 .ctrlbit = S3C_CLKCON_SCLK_JPEG,
306 static struct clk clk_48m_spi0 = {
308 .devname = "s3c6410-spi.0",
310 .enable = s3c64xx_sclk_ctrl,
311 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
314 static struct clk clk_48m_spi1 = {
316 .devname = "s3c6410-spi.1",
318 .enable = s3c64xx_sclk_ctrl,
319 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
322 static struct clk clk_i2s0 = {
324 .devname = "samsung-i2s.0",
326 .enable = s3c64xx_pclk_ctrl,
327 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
330 static struct clk clk_i2s1 = {
332 .devname = "samsung-i2s.1",
334 .enable = s3c64xx_pclk_ctrl,
335 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
338 #ifdef CONFIG_CPU_S3C6410
339 static struct clk clk_i2s2 = {
341 .devname = "samsung-i2s.2",
343 .enable = s3c64xx_pclk_ctrl,
344 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
348 static struct clk init_clocks[] = {
352 .enable = s3c64xx_hclk_ctrl,
353 .ctrlbit = S3C_CLKCON_HCLK_LCD,
357 .enable = s3c64xx_pclk_ctrl,
358 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
362 .enable = s3c64xx_hclk_ctrl,
363 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
367 .enable = s3c64xx_hclk_ctrl,
368 .ctrlbit = S3C_CLKCON_HCLK_USB,
372 .enable = s3c64xx_pclk_ctrl,
373 .ctrlbit = S3C_CLKCON_PCLK_PWM,
376 .devname = "s3c6400-uart.0",
378 .enable = s3c64xx_pclk_ctrl,
379 .ctrlbit = S3C_CLKCON_PCLK_UART0,
382 .devname = "s3c6400-uart.1",
384 .enable = s3c64xx_pclk_ctrl,
385 .ctrlbit = S3C_CLKCON_PCLK_UART1,
388 .devname = "s3c6400-uart.2",
390 .enable = s3c64xx_pclk_ctrl,
391 .ctrlbit = S3C_CLKCON_PCLK_UART2,
394 .devname = "s3c6400-uart.3",
396 .enable = s3c64xx_pclk_ctrl,
397 .ctrlbit = S3C_CLKCON_PCLK_UART3,
401 .ctrlbit = S3C_CLKCON_PCLK_WDT,
405 static struct clk clk_hsmmc0 = {
407 .devname = "s3c-sdhci.0",
409 .enable = s3c64xx_hclk_ctrl,
410 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
413 static struct clk clk_hsmmc1 = {
415 .devname = "s3c-sdhci.1",
417 .enable = s3c64xx_hclk_ctrl,
418 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
421 static struct clk clk_hsmmc2 = {
423 .devname = "s3c-sdhci.2",
425 .enable = s3c64xx_hclk_ctrl,
426 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
429 static struct clk clk_fout_apll = {
433 static struct clk *clk_src_apll_list[] = {
435 [1] = &clk_fout_apll,
438 static struct clksrc_sources clk_src_apll = {
439 .sources = clk_src_apll_list,
440 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
443 static struct clksrc_clk clk_mout_apll = {
447 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
448 .sources = &clk_src_apll,
451 static struct clk *clk_src_epll_list[] = {
453 [1] = &clk_fout_epll,
456 static struct clksrc_sources clk_src_epll = {
457 .sources = clk_src_epll_list,
458 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
461 static struct clksrc_clk clk_mout_epll = {
465 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
466 .sources = &clk_src_epll,
469 static struct clk *clk_src_mpll_list[] = {
471 [1] = &clk_fout_mpll,
474 static struct clksrc_sources clk_src_mpll = {
475 .sources = clk_src_mpll_list,
476 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
479 static struct clksrc_clk clk_mout_mpll = {
483 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
484 .sources = &clk_src_mpll,
487 static unsigned int armclk_mask;
489 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
491 unsigned long rate = clk_get_rate(clk->parent);
494 /* divisor mask starts at bit0, so no need to shift */
495 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
497 return rate / (clkdiv + 1);
500 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
503 unsigned long parent = clk_get_rate(clk->parent);
509 div = (parent / rate) - 1;
510 if (div > armclk_mask)
513 return parent / (div + 1);
516 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
518 unsigned long parent = clk_get_rate(clk->parent);
522 if (rate < parent / (armclk_mask + 1))
525 rate = clk_round_rate(clk, rate);
526 div = clk_get_rate(clk->parent) / rate;
528 val = __raw_readl(S3C_CLK_DIV0);
531 __raw_writel(val, S3C_CLK_DIV0);
537 static struct clk clk_arm = {
539 .parent = &clk_mout_apll.clk,
540 .ops = &(struct clk_ops) {
541 .get_rate = s3c64xx_clk_arm_get_rate,
542 .set_rate = s3c64xx_clk_arm_set_rate,
543 .round_rate = s3c64xx_clk_arm_round_rate,
547 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
549 unsigned long rate = clk_get_rate(clk->parent);
551 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
553 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
559 static struct clk_ops clk_dout_ops = {
560 .get_rate = s3c64xx_clk_doutmpll_get_rate,
563 static struct clk clk_dout_mpll = {
565 .parent = &clk_mout_mpll.clk,
566 .ops = &clk_dout_ops,
569 static struct clk *clkset_spi_mmc_list[] = {
576 static struct clksrc_sources clkset_spi_mmc = {
577 .sources = clkset_spi_mmc_list,
578 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
581 static struct clk *clkset_irda_list[] = {
588 static struct clksrc_sources clkset_irda = {
589 .sources = clkset_irda_list,
590 .nr_sources = ARRAY_SIZE(clkset_irda_list),
593 static struct clk *clkset_uart_list[] = {
600 static struct clksrc_sources clkset_uart = {
601 .sources = clkset_uart_list,
602 .nr_sources = ARRAY_SIZE(clkset_uart_list),
605 static struct clk *clkset_uhost_list[] = {
612 static struct clksrc_sources clkset_uhost = {
613 .sources = clkset_uhost_list,
614 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
617 /* The peripheral clocks are all controlled via clocksource followed
618 * by an optional divider and gate stage. We currently roll this into
619 * one clock which hides the intermediate clock from the mux.
621 * Note, the JPEG clock can only be an even divider...
623 * The scaler and LCD clocks depend on the S3C64XX version, and also
624 * have a common parent divisor so are not included here.
627 /* clocks that feed other parts of the clock source tree */
629 static struct clk clk_iis_cd0 = {
630 .name = "iis_cdclk0",
633 static struct clk clk_iis_cd1 = {
634 .name = "iis_cdclk1",
637 static struct clk clk_iisv4_cd = {
638 .name = "iis_cdclk_v4",
641 static struct clk clk_pcm_cd = {
645 static struct clk *clkset_audio0_list[] = {
646 [0] = &clk_mout_epll.clk,
647 [1] = &clk_dout_mpll,
653 static struct clksrc_sources clkset_audio0 = {
654 .sources = clkset_audio0_list,
655 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
658 static struct clk *clkset_audio1_list[] = {
659 [0] = &clk_mout_epll.clk,
660 [1] = &clk_dout_mpll,
666 static struct clksrc_sources clkset_audio1 = {
667 .sources = clkset_audio1_list,
668 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
671 #ifdef CONFIG_CPU_S3C6410
672 static struct clk *clkset_audio2_list[] = {
673 [0] = &clk_mout_epll.clk,
674 [1] = &clk_dout_mpll,
680 static struct clksrc_sources clkset_audio2 = {
681 .sources = clkset_audio2_list,
682 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
686 static struct clksrc_clk clksrcs[] = {
689 .name = "usb-bus-host",
690 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
691 .enable = s3c64xx_sclk_ctrl,
693 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
694 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
695 .sources = &clkset_uhost,
699 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
700 .enable = s3c64xx_sclk_ctrl,
702 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
703 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
704 .sources = &clkset_irda,
708 .ctrlbit = S3C_CLKCON_SCLK_CAM,
709 .enable = s3c64xx_sclk_ctrl,
712 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
716 /* Where does UCLK0 come from? */
717 static struct clksrc_clk clk_sclk_uclk = {
720 .ctrlbit = S3C_CLKCON_SCLK_UART,
721 .enable = s3c64xx_sclk_ctrl,
723 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
724 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
725 .sources = &clkset_uart,
728 static struct clksrc_clk clk_sclk_mmc0 = {
731 .devname = "s3c-sdhci.0",
732 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
733 .enable = s3c64xx_sclk_ctrl,
735 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
736 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
737 .sources = &clkset_spi_mmc,
740 static struct clksrc_clk clk_sclk_mmc1 = {
743 .devname = "s3c-sdhci.1",
744 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
745 .enable = s3c64xx_sclk_ctrl,
747 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
748 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
749 .sources = &clkset_spi_mmc,
752 static struct clksrc_clk clk_sclk_mmc2 = {
755 .devname = "s3c-sdhci.2",
756 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
757 .enable = s3c64xx_sclk_ctrl,
759 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
760 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
761 .sources = &clkset_spi_mmc,
764 static struct clksrc_clk clk_sclk_spi0 = {
767 .devname = "s3c6410-spi.0",
768 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
769 .enable = s3c64xx_sclk_ctrl,
771 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
772 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
773 .sources = &clkset_spi_mmc,
776 static struct clksrc_clk clk_sclk_spi1 = {
779 .devname = "s3c6410-spi.1",
780 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
781 .enable = s3c64xx_sclk_ctrl,
783 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
784 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
785 .sources = &clkset_spi_mmc,
788 static struct clksrc_clk clk_audio_bus0 = {
791 .devname = "samsung-i2s.0",
792 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
793 .enable = s3c64xx_sclk_ctrl,
795 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
796 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
797 .sources = &clkset_audio0,
800 static struct clksrc_clk clk_audio_bus1 = {
803 .devname = "samsung-i2s.1",
804 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
805 .enable = s3c64xx_sclk_ctrl,
807 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
808 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
809 .sources = &clkset_audio1,
812 #ifdef CONFIG_CPU_S3C6410
813 static struct clksrc_clk clk_audio_bus2 = {
816 .devname = "samsung-i2s.2",
817 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
818 .enable = s3c64xx_sclk_ctrl,
820 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
821 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
822 .sources = &clkset_audio2,
825 /* Clock initialisation code */
827 static struct clksrc_clk *init_parents[] = {
833 static struct clksrc_clk *clksrc_cdev[] = {
844 static struct clk *clk_cdev[] = {
854 static struct clk_lookup s3c64xx_clk_lookup[] = {
855 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
856 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
857 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
860 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
861 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
862 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
863 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
864 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
865 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
866 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
867 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
868 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
869 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk),
870 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
871 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk),
872 #ifdef CONFIG_CPU_S3C6410
873 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
874 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk),
878 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
880 void __init_or_cpufreq s3c64xx_setup_clocks(void)
882 struct clk *xtal_clk;
894 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
896 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
897 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
899 xtal_clk = clk_get(NULL, "xtal");
900 BUG_ON(IS_ERR(xtal_clk));
902 xtal = clk_get_rate(xtal_clk);
905 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
907 /* For now assume the mux always selects the crystal */
908 clk_ext_xtal_mux.parent = xtal_clk;
910 epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
911 __raw_readl(S3C_EPLL_CON1));
912 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
913 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
917 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
920 if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
921 /* Synchronous mode */
922 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
924 /* Asynchronous mode */
925 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
927 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
928 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
930 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
933 clk_fout_mpll.rate = mpll;
934 clk_fout_epll.rate = epll;
935 clk_fout_apll.rate = apll;
942 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
943 s3c_set_clksrc(init_parents[ptr], true);
945 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
946 s3c_set_clksrc(&clksrcs[ptr], true);
949 static struct clk *clks1[] __initdata = {
961 static struct clk *clks[] __initdata = {
971 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
972 * @xtal: The rate for the clock crystal feeding the PLLs.
973 * @armclk_divlimit: Divisor mask for ARMCLK.
975 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
976 * as ARMCLK as well as the necessary parent clocks.
978 * This call does not setup the clocks, which is left to the
979 * s3c64xx_setup_clocks() call which may be needed by the cpufreq
980 * or resume code to re-set the clocks if the bootloader has changed
983 void __init s3c64xx_register_clocks(unsigned long xtal,
984 unsigned armclk_divlimit)
988 armclk_mask = armclk_divlimit;
990 s3c24xx_register_baseclocks(xtal);
991 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
993 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
995 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
996 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
998 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
999 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
1000 s3c_disable_clocks(clk_cdev[cnt], 1);
1002 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
1003 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1004 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
1005 s3c_register_clksrc(clksrc_cdev[cnt], 1);
1006 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));