arch/arm/mach-s3c24xx/common.c

   1 /* linux/arch/arm/plat-s3c24xx/cpu.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Common code for S3C24XX machines
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ioport.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/delay.h>
  32 #include <linux/io.h>
  33
  34 #include <mach/hardware.h>
  35 #include <mach/regs-clock.h>
  36 #include <asm/irq.h>
  37 #include <asm/cacheflush.h>
  38 #include <asm/system_info.h>
  39 #include <asm/system_misc.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/map.h>
  43
  44 #include <mach/regs-clock.h>
  45 #include <mach/regs-gpio.h>
  46 #include <plat/regs-serial.h>
  47
  48 #include <plat/cpu.h>
  49 #include <plat/devs.h>
  50 #include <plat/clock.h>
  51 #include <plat/s3c2410.h>
  52 #include <plat/s3c2412.h>
  53 #include <plat/s3c2416.h>
  54 #include <plat/s3c244x.h>
  55 #include <plat/s3c2443.h>
  56 #include <plat/cpu-freq.h>
  57 #include <plat/pll.h>
  58
  59 /* table of supported CPUs */
  60
  61 static const char name_s3c2410[]  = "S3C2410";
  62 static const char name_s3c2412[]  = "S3C2412";
  63 static const char name_s3c2416[]  = "S3C2416/S3C2450";
  64 static const char name_s3c2440[]  = "S3C2440";
  65 static const char name_s3c2442[]  = "S3C2442";
  66 static const char name_s3c2442b[]  = "S3C2442B";
  67 static const char name_s3c2443[]  = "S3C2443";
  68 static const char name_s3c2410a[] = "S3C2410A";
  69 static const char name_s3c2440a[] = "S3C2440A";
  70
  71 static struct cpu_table cpu_ids[] __initdata = {
  72         {
  73                 .idcode         = 0x32410000,
  74                 .idmask         = 0xffffffff,
  75                 .map_io         = s3c2410_map_io,
  76                 .init_clocks    = s3c2410_init_clocks,
  77                 .init_uarts     = s3c2410_init_uarts,
  78                 .init           = s3c2410_init,
  79                 .name           = name_s3c2410
  80         },
  81         {
  82                 .idcode         = 0x32410002,
  83                 .idmask         = 0xffffffff,
  84                 .map_io         = s3c2410_map_io,
  85                 .init_clocks    = s3c2410_init_clocks,
  86                 .init_uarts     = s3c2410_init_uarts,
  87                 .init           = s3c2410a_init,
  88                 .name           = name_s3c2410a
  89         },
  90         {
  91                 .idcode         = 0x32440000,
  92                 .idmask         = 0xffffffff,
  93                 .map_io         = s3c2440_map_io,
  94                 .init_clocks    = s3c244x_init_clocks,
  95                 .init_uarts     = s3c244x_init_uarts,
  96                 .init           = s3c2440_init,
  97                 .name           = name_s3c2440
  98         },
  99         {
 100                 .idcode         = 0x32440001,
 101                 .idmask         = 0xffffffff,
 102                 .map_io         = s3c2440_map_io,
 103                 .init_clocks    = s3c244x_init_clocks,
 104                 .init_uarts     = s3c244x_init_uarts,
 105                 .init           = s3c2440_init,
 106                 .name           = name_s3c2440a
 107         },
 108         {
 109                 .idcode         = 0x32440aaa,
 110                 .idmask         = 0xffffffff,
 111                 .map_io         = s3c2442_map_io,
 112                 .init_clocks    = s3c244x_init_clocks,
 113                 .init_uarts     = s3c244x_init_uarts,
 114                 .init           = s3c2442_init,
 115                 .name           = name_s3c2442
 116         },
 117         {
 118                 .idcode         = 0x32440aab,
 119                 .idmask         = 0xffffffff,
 120                 .map_io         = s3c2442_map_io,
 121                 .init_clocks    = s3c244x_init_clocks,
 122                 .init_uarts     = s3c244x_init_uarts,
 123                 .init           = s3c2442_init,
 124                 .name           = name_s3c2442b
 125         },
 126         {
 127                 .idcode         = 0x32412001,
 128                 .idmask         = 0xffffffff,
 129                 .map_io         = s3c2412_map_io,
 130                 .init_clocks    = s3c2412_init_clocks,
 131                 .init_uarts     = s3c2412_init_uarts,
 132                 .init           = s3c2412_init,
 133                 .name           = name_s3c2412,
 134         },
 135         {                       /* a newer version of the s3c2412 */
 136                 .idcode         = 0x32412003,
 137                 .idmask         = 0xffffffff,
 138                 .map_io         = s3c2412_map_io,
 139                 .init_clocks    = s3c2412_init_clocks,
 140                 .init_uarts     = s3c2412_init_uarts,
 141                 .init           = s3c2412_init,
 142                 .name           = name_s3c2412,
 143         },
 144         {                       /* a strange version of the s3c2416 */
 145                 .idcode         = 0x32450003,
 146                 .idmask         = 0xffffffff,
 147                 .map_io         = s3c2416_map_io,
 148                 .init_clocks    = s3c2416_init_clocks,
 149                 .init_uarts     = s3c2416_init_uarts,
 150                 .init           = s3c2416_init,
 151                 .name           = name_s3c2416,
 152         },
 153         {
 154                 .idcode         = 0x32443001,
 155                 .idmask         = 0xffffffff,
 156                 .map_io         = s3c2443_map_io,
 157                 .init_clocks    = s3c2443_init_clocks,
 158                 .init_uarts     = s3c2443_init_uarts,
 159                 .init           = s3c2443_init,
 160                 .name           = name_s3c2443,
 161         },
 162 };
 163
 164 /* minimal IO mapping */
 165
 166 static struct map_desc s3c_iodesc[] __initdata = {
 167         IODESC_ENT(GPIO),
 168         IODESC_ENT(IRQ),
 169         IODESC_ENT(MEMCTRL),
 170         IODESC_ENT(UART)
 171 };
 172
 173 /* read cpu identificaiton code */
 174
 175 static unsigned long s3c24xx_read_idcode_v5(void)
 176 {
 177 #if defined(CONFIG_CPU_S3C2416)
 178         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
 179
 180         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
 181
 182         /* test for s3c2416 or similar device */
 183         if ((gs >> 16) == 0x3245)
 184                 return gs;
 185 #endif
 186
 187 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 188         return __raw_readl(S3C2412_GSTATUS1);
 189 #else
 190         return 1UL;     /* don't look like an 2400 */
 191 #endif
 192 }
 193
 194 static unsigned long s3c24xx_read_idcode_v4(void)
 195 {
 196         return __raw_readl(S3C2410_GSTATUS1);
 197 }
 198
 199 static void s3c24xx_default_idle(void)
 200 {
 201         unsigned long tmp;
 202         int i;
 203
 204         /* idle the system by using the idle mode which will wait for an
 205          * interrupt to happen before restarting the system.
 206          */
 207
 208         /* Warning: going into idle state upsets jtag scanning */
 209
 210         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
 211                      S3C2410_CLKCON);
 212
 213         /* the samsung port seems to do a loop and then unset idle.. */
 214         for (i = 0; i < 50; i++)
 215                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
 216
 217         /* this bit is not cleared on re-start... */
 218
 219         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
 220                      S3C2410_CLKCON);
 221 }
 222
 223 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 224 {
 225         arm_pm_idle = s3c24xx_default_idle;
 226
 227         /* initialise the io descriptors we need for initialisation */
 228         iotable_init(mach_desc, size);
 229         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 230
 231         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 232                 samsung_cpu_id = s3c24xx_read_idcode_v5();
 233         } else {
 234                 samsung_cpu_id = s3c24xx_read_idcode_v4();
 235         }
 236         s3c24xx_init_cpu();
 237
 238         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 239 }
 240
 241 /* Serial port registrations */
 242
 243 static struct resource s3c2410_uart0_resource[] = {
 244         [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
 245         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
 246                         IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
 247                         NULL, IORESOURCE_IRQ)
 248 };
 249
 250 static struct resource s3c2410_uart1_resource[] = {
 251         [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
 252         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
 253                         IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
 254                         NULL, IORESOURCE_IRQ)
 255 };
 256
 257 static struct resource s3c2410_uart2_resource[] = {
 258         [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
 259         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
 260                         IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
 261                         NULL, IORESOURCE_IRQ)
 262 };
 263
 264 static struct resource s3c2410_uart3_resource[] = {
 265         [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
 266         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
 267                         IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
 268                         NULL, IORESOURCE_IRQ)
 269 };
 270
 271 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
 272         [0] = {
 273                 .resources      = s3c2410_uart0_resource,
 274                 .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
 275         },
 276         [1] = {
 277                 .resources      = s3c2410_uart1_resource,
 278                 .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
 279         },
 280         [2] = {
 281                 .resources      = s3c2410_uart2_resource,
 282                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
 283         },
 284         [3] = {
 285                 .resources      = s3c2410_uart3_resource,
 286                 .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
 287         },
 288 };
 289
 290 /* initialise all the clocks */
 291
 292 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
 293                                            unsigned long hclk,
 294                                            unsigned long pclk)
 295 {
 296         clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
 297                                         clk_xtal.rate);
 298
 299         clk_mpll.rate = fclk;
 300         clk_h.rate = hclk;
 301         clk_p.rate = pclk;
 302         clk_f.rate = fclk;
 303 }