1 /* linux/arch/arm/mach-s3c2416/clock.c
3 * Copyright (c) 2010 Simtec Electronics
4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
6 * S3C2416 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/clk.h>
17 #include <plat/s3c2416.h>
18 #include <plat/s3c2443.h>
19 #include <plat/clock.h>
20 #include <plat/clock-clksrc.h>
23 #include <plat/cpu-freq.h>
24 #include <plat/pll6553x.h>
27 #include <asm/mach/map.h>
29 #include <mach/regs-clock.h>
30 #include <mach/regs-s3c2443-clock.h>
32 static unsigned int armdiv[8] = {
41 static struct clksrc_clk hsmmc_div[] = {
46 .parent = &clk_esysclk.clk,
48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
54 .parent = &clk_esysclk.clk,
56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
60 static struct clksrc_clk hsmmc_mux[] = {
66 .enable = s3c2443_clkcon_enable_s,
68 .sources = &(struct clksrc_sources) {
70 .sources = (struct clk *[]) {
71 [0] = &hsmmc_div[0].clk,
72 [1] = NULL, /* to fix */
75 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
82 .enable = s3c2443_clkcon_enable_s,
84 .sources = &(struct clksrc_sources) {
86 .sources = (struct clk *[]) {
87 [0] = &hsmmc_div[1].clk,
88 [1] = NULL, /* to fix */
91 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
95 static struct clk hsmmc0_clk = {
99 .enable = s3c2443_clkcon_enable_h,
100 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
103 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
105 clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
107 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
110 void __init_or_cpufreq s3c2416_setup_clocks(void)
112 s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
116 static struct clksrc_clk *clksrcs[] __initdata = {
123 void __init s3c2416_init_clocks(int xtal)
125 u32 epllcon = __raw_readl(S3C2443_EPLLCON);
126 u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
129 /* s3c2416 EPLL compatible with s3c64xx */
130 clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
132 clk_epll.parent = &clk_epllref.clk;
134 s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
136 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
137 s3c_register_clksrc(clksrcs[ptr], 1);
139 s3c24xx_register_clock(&hsmmc0_clk);