arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 #if defined(CONFIG_ROCKCHIP_IOMMU)\r
  47 //#define CONFIG_VCODEC_MMU\r
  48 #endif\r
  49 \r
  50 #ifdef CONFIG_VCODEC_MMU\r
  51 #include <linux/rockchip/iovmm.h>\r
  52 #include <linux/rockchip/sysmmu.h>\r
  53 #include <linux/dma-buf.h>\r
  54 #endif\r
  55 \r
  56 #ifdef CONFIG_DEBUG_FS\r
  57 #include <linux/debugfs.h>\r
  58 #endif\r
  59 \r
  60 #if defined(CONFIG_ARCH_RK319X)\r
  61 #include <mach/grf.h>\r
  62 #endif\r
  63 \r
  64 #include "vcodec_service.h"\r
  65 \r
  66 #define HEVC_TEST_ENABLE    0\r
  67 #define HEVC_SIM_ENABLE     0\r
  68 #define VCODEC_CLOCK_ENABLE 1\r
  69 \r
  70 typedef enum {\r
  71         VPU_DEC_ID_9190         = 0x6731,\r
  72         VPU_ID_8270             = 0x8270,\r
  73         VPU_ID_4831             = 0x4831,\r
  74     HEVC_ID         = 0x6867,\r
  75 } VPU_HW_ID;\r
  76 \r
  77 typedef enum {\r
  78         VPU_DEC_TYPE_9190       = 0,\r
  79         VPU_ENC_TYPE_8270       = 0x100,\r
  80         VPU_ENC_TYPE_4831       ,\r
  81 } VPU_HW_TYPE_E;\r
  82 \r
  83 typedef enum VPU_FREQ {\r
  84         VPU_FREQ_200M,\r
  85         VPU_FREQ_266M,\r
  86         VPU_FREQ_300M,\r
  87         VPU_FREQ_400M,\r
  88     VPU_FREQ_500M,\r
  89     VPU_FREQ_600M,\r
  90         VPU_FREQ_DEFAULT,\r
  91         VPU_FREQ_BUT,\r
  92 } VPU_FREQ;\r
  93 \r
  94 typedef struct {\r
  95         VPU_HW_ID               hw_id;\r
  96         unsigned long           hw_addr;\r
  97         unsigned long           enc_offset;\r
  98         unsigned long           enc_reg_num;\r
  99         unsigned long           enc_io_size;\r
 100         unsigned long           dec_offset;\r
 101         unsigned long           dec_reg_num;\r
 102         unsigned long           dec_io_size;\r
 103 } VPU_HW_INFO_E;\r
 104 \r
 105 #define VPU_SERVICE_SHOW_TIME                   0\r
 106 \r
 107 #if VPU_SERVICE_SHOW_TIME\r
 108 static struct timeval enc_start, enc_end;\r
 109 static struct timeval dec_start, dec_end;\r
 110 static struct timeval pp_start,  pp_end;\r
 111 #endif\r
 112 \r
 113 #define MHZ                                     (1000*1000)\r
 114 \r
 115 #define REG_NUM_9190_DEC                        (60)\r
 116 #define REG_NUM_9190_PP                         (41)\r
 117 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 118 \r
 119 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 120 \r
 121 #define REG_NUM_ENC_8270                        (96)\r
 122 #define REG_SIZE_ENC_8270                       (0x200)\r
 123 #define REG_NUM_ENC_4831                        (164)\r
 124 #define REG_SIZE_ENC_4831                       (0x400)\r
 125 \r
 126 #define REG_NUM_HEVC_DEC            (68)\r
 127 \r
 128 #define SIZE_REG(reg)                           ((reg)*4)\r
 129 \r
 130 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 131         [0] = {\r
 132                 .hw_id          = VPU_ID_8270,\r
 133                 .hw_addr        = 0,\r
 134                 .enc_offset     = 0x0,\r
 135                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 136                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 137                 .dec_offset     = REG_SIZE_ENC_8270,\r
 138                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 139                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 140         },\r
 141         [1] = {\r
 142                 .hw_id          = VPU_ID_4831,\r
 143                 .hw_addr        = 0,\r
 144                 .enc_offset     = 0x0,\r
 145                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 146                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 147                 .dec_offset     = REG_SIZE_ENC_4831,\r
 148                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 149                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 150         },\r
 151     [2] = {\r
 152         .hw_id      = HEVC_ID,\r
 153         .hw_addr    = 0,\r
 154         .dec_offset = 0x0,\r
 155         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 156         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 157     },\r
 158 };\r
 159 \r
 160 \r
 161 #define DEC_INTERRUPT_REGISTER                  1\r
 162 #define PP_INTERRUPT_REGISTER                   60\r
 163 #define ENC_INTERRUPT_REGISTER                  1\r
 164 \r
 165 #define DEC_INTERRUPT_BIT                       0x100\r
 166 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 167 #define PP_INTERRUPT_BIT                        0x100\r
 168 #define ENC_INTERRUPT_BIT                       0x1\r
 169 \r
 170 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 171 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 172 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 173 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 174 \r
 175 #define VPU_REG_EN_ENC                          14\r
 176 #define VPU_REG_ENC_GATE                        2\r
 177 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 178 \r
 179 #define VPU_REG_EN_DEC                          1\r
 180 #define VPU_REG_DEC_GATE                        2\r
 181 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 182 #define VPU_REG_EN_PP                           0\r
 183 #define VPU_REG_PP_GATE                         1\r
 184 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 185 #define VPU_REG_EN_DEC_PP                       1\r
 186 #define VPU_REG_DEC_PP_GATE                     61\r
 187 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 188 \r
 189 #if defined(CONFIG_VCODEC_MMU)\r
 190 static u8 addr_tbl_vpu_dec[] = {\r
 191     12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 192 };\r
 193 \r
 194 static u8 addr_tbl_vpu_enc[] = {\r
 195     5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 196 };\r
 197 \r
 198 static u8 addr_tbl_hevc_dec[] = {\r
 199     4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
 200 };\r
 201 #endif\r
 202 \r
 203 /**\r
 204  * struct for process session which connect to vpu\r
 205  *\r
 206  * @author ChenHengming (2011-5-3)\r
 207  */\r
 208 typedef struct vpu_session {\r
 209         VPU_CLIENT_TYPE         type;\r
 210         /* a linked list of data so we can access them for debugging */\r
 211         struct list_head        list_session;\r
 212         /* a linked list of register data waiting for process */\r
 213         struct list_head        waiting;\r
 214         /* a linked list of register data in processing */\r
 215         struct list_head        running;\r
 216         /* a linked list of register data processed */\r
 217         struct list_head        done;\r
 218         wait_queue_head_t       wait;\r
 219         pid_t                   pid;\r
 220         atomic_t                task_running;\r
 221 } vpu_session;\r
 222 \r
 223 /**\r
 224  * struct for process register set\r
 225  *\r
 226  * @author ChenHengming (2011-5-4)\r
 227  */\r
 228 typedef struct vpu_reg {\r
 229         VPU_CLIENT_TYPE         type;\r
 230         VPU_FREQ                    freq;\r
 231         vpu_session             *session;\r
 232         struct list_head        session_link;           /* link to vpu service session */\r
 233         struct list_head        status_link;            /* link to register set list */\r
 234         unsigned long           size;\r
 235 #if defined(CONFIG_VCODEC_MMU)    \r
 236     struct list_head    mem_region_list;\r
 237 #endif    \r
 238         unsigned long           *reg;\r
 239 } vpu_reg;\r
 240 \r
 241 typedef struct vpu_device {\r
 242         atomic_t                irq_count_codec;\r
 243         atomic_t                irq_count_pp;\r
 244         unsigned long           iobaseaddr;\r
 245         unsigned int            iosize;\r
 246         volatile u32            *hwregs;\r
 247 } vpu_device;\r
 248 \r
 249 enum vcodec_device_id {\r
 250         VCODEC_DEVICE_ID_VPU,\r
 251         VCODEC_DEVICE_ID_HEVC\r
 252 };\r
 253 \r
 254 struct vcodec_mem_region {\r
 255     struct list_head srv_lnk;\r
 256     struct list_head reg_lnk;\r
 257     struct list_head session_lnk;\r
 258     unsigned long iova;              /* virtual address for iommu */\r
 259     unsigned long len;\r
 260     struct ion_handle *hdl;\r
 261 };\r
 262 \r
 263 typedef struct vpu_service_info {\r
 264         struct wake_lock        wake_lock;\r
 265         struct delayed_work     power_off_work;\r
 266         struct mutex            lock;\r
 267         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 268         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 269         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 270         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 271         atomic_t                total_running;\r
 272         bool                    enabled;\r
 273         vpu_reg                 *reg_codec;\r
 274         vpu_reg                 *reg_pproc;\r
 275         vpu_reg                 *reg_resev;\r
 276         VPUHwDecConfig_t        dec_config;\r
 277         VPUHwEncConfig_t        enc_config;\r
 278         VPU_HW_INFO_E           *hw_info;\r
 279         unsigned long           reg_size;\r
 280         bool                    auto_freq;\r
 281         bool                    bug_dec_addr;\r
 282         atomic_t                freq_status;\r
 283 \r
 284     struct clk *aclk_vcodec;\r
 285     struct clk *hclk_vcodec;\r
 286     struct clk *clk_core;\r
 287     struct clk *clk_cabac;\r
 288     struct clk *pd_video;\r
 289 \r
 290     int irq_dec;\r
 291     int irq_enc;\r
 292 \r
 293     vpu_device enc_dev;\r
 294     vpu_device dec_dev;\r
 295 \r
 296     struct device   *dev;\r
 297 \r
 298     struct cdev     cdev;\r
 299     dev_t           dev_t;\r
 300     struct class    *cls;\r
 301     struct device   *child_dev;\r
 302 \r
 303     struct dentry   *debugfs_dir;\r
 304     struct dentry   *debugfs_file_regs;\r
 305 \r
 306     u32 irq_status;\r
 307 #if defined(CONFIG_ION_ROCKCHIP)        \r
 308         struct ion_client * ion_client;\r
 309 #endif  \r
 310 \r
 311 #if defined(CONFIG_VCODEC_MMU)\r
 312     struct list_head mem_region_list;\r
 313 #endif\r
 314 \r
 315         enum vcodec_device_id dev_id;\r
 316 \r
 317     struct delayed_work simulate_work;\r
 318 } vpu_service_info;\r
 319 \r
 320 typedef struct vpu_request\r
 321 {\r
 322         unsigned long   *req;\r
 323         unsigned long   size;\r
 324 } vpu_request;\r
 325 \r
 326 /// global variable\r
 327 //static struct clk *pd_video;\r
 328 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 329 \r
 330 #ifdef CONFIG_DEBUG_FS\r
 331 static int vcodec_debugfs_init(void);\r
 332 static void vcodec_debugfs_exit(void);\r
 333 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 334 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 335 \r
 336 static const struct file_operations debug_vcodec_fops = {\r
 337     .open = debug_vcodec_open,\r
 338     .read = seq_read,\r
 339     .llseek = seq_lseek,\r
 340     .release = single_release,\r
 341 };\r
 342 #endif\r
 343 \r
 344 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 345 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 346 \r
 347 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 348 \r
 349 static int vpu_get_clk(struct vpu_service_info *pservice)\r
 350 {\r
 351 #if VCODEC_CLOCK_ENABLE\r
 352     do {\r
 353         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 354         if (IS_ERR(pservice->aclk_vcodec)) {\r
 355             dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 356             break;\r
 357         }\r
 358     \r
 359         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 360         if (IS_ERR(pservice->hclk_vcodec)) {\r
 361             dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 362             break;\r
 363         }\r
 364     \r
 365         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 366             pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 367             if (IS_ERR(pservice->clk_core)) {\r
 368                 dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 369                 break;\r
 370             }\r
 371     \r
 372             pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 373             if (IS_ERR(pservice->clk_cabac)) {\r
 374                 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 375                 break;\r
 376             }\r
 377             \r
 378             pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
 379             if (IS_ERR(pservice->pd_video)) {\r
 380                 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
 381                 break;\r
 382             }\r
 383         } else {\r
 384             pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
 385             if (IS_ERR(pservice->pd_video)) {\r
 386                 dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
 387                 break;\r
 388             }\r
 389         }\r
 390         \r
 391         return 0;\r
 392     } while (0);\r
 393     \r
 394     return -1;\r
 395 #endif\r
 396 }\r
 397 \r
 398 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 399 {\r
 400 #if VCODEC_CLOCK_ENABLE\r
 401     if (pservice->pd_video) {\r
 402         devm_clk_put(pservice->dev, pservice->pd_video);\r
 403     }\r
 404 \r
 405     if (pservice->aclk_vcodec) {\r
 406         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 407     }\r
 408 \r
 409     if (pservice->hclk_vcodec) {\r
 410         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 411     }\r
 412 \r
 413     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 414         if (pservice->clk_core) {\r
 415             devm_clk_put(pservice->dev, pservice->clk_core);\r
 416         }\r
 417         \r
 418         if (pservice->clk_cabac) {\r
 419             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 420         }\r
 421     }\r
 422 #endif\r
 423 }\r
 424 \r
 425 static void vpu_reset(struct vpu_service_info *pservice)\r
 426 {\r
 427 #if defined(CONFIG_ARCH_RK29)\r
 428         clk_disable(aclk_ddr_vepu);\r
 429         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 430         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 431         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 432         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 433         mdelay(10);\r
 434         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 435         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 436         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 437         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 438         clk_enable(aclk_ddr_vepu);\r
 439 #elif defined(CONFIG_ARCH_RK30)\r
 440         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 441         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 442         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 443         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 444         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 445         mdelay(1);\r
 446         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 447         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 448         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 449         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 450         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 451 #endif\r
 452         pservice->reg_codec = NULL;\r
 453         pservice->reg_pproc = NULL;\r
 454         pservice->reg_resev = NULL;\r
 455 }\r
 456 \r
 457 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 458 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 459 {\r
 460         vpu_reg *reg, *n;\r
 461         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 462                 reg_deinit(pservice, reg);\r
 463         }\r
 464         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 465                 reg_deinit(pservice, reg);\r
 466         }\r
 467         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 468                 reg_deinit(pservice, reg);\r
 469         }\r
 470 }\r
 471 \r
 472 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 473 {\r
 474         int running;\r
 475         vpu_reg *reg, *reg_tmp;\r
 476         vpu_session *session, *session_tmp;\r
 477 \r
 478         running = atomic_read(&pservice->total_running);\r
 479         printk("total_running %d\n", running);\r
 480 \r
 481         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 482         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 483         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 484 \r
 485         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 486                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 487                 running = atomic_read(&session->task_running);\r
 488                 printk("task_running %d\n", running);\r
 489                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 490                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 491                 }\r
 492                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 493                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 494                 }\r
 495                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 496                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 497                 }\r
 498         }\r
 499 }\r
 500 \r
 501 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 502 {\r
 503     int total_running;\r
 504     if (!pservice->enabled) {\r
 505         return;\r
 506     }\r
 507 \r
 508     pservice->enabled = false;\r
 509     total_running = atomic_read(&pservice->total_running);\r
 510     if (total_running) {\r
 511         pr_alert("alert: power off when %d task running!!\n", total_running);\r
 512         mdelay(50);\r
 513         pr_alert("alert: delay 50 ms for running task\n");\r
 514         vpu_service_dump(pservice);\r
 515     }\r
 516 \r
 517     printk("%s: power off...", dev_name(pservice->dev));\r
 518     udelay(10);\r
 519 #if VCODEC_CLOCK_ENABLE\r
 520     clk_disable_unprepare(pservice->pd_video);\r
 521     clk_disable_unprepare(pservice->hclk_vcodec);\r
 522     clk_disable_unprepare(pservice->aclk_vcodec);\r
 523     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 524         clk_disable_unprepare(pservice->clk_core);\r
 525         clk_disable_unprepare(pservice->clk_cabac);\r
 526     }\r
 527 #endif\r
 528     wake_unlock(&pservice->wake_lock);\r
 529     printk("done\n");\r
 530 }\r
 531 \r
 532 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 533 {\r
 534         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 535 }\r
 536 \r
 537 static void vpu_power_off_work(struct work_struct *work_s)\r
 538 {\r
 539     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 540     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 541 \r
 542         if (mutex_trylock(&pservice->lock)) {\r
 543                 vpu_service_power_off(pservice);\r
 544                 mutex_unlock(&pservice->lock);\r
 545         } else {\r
 546                 /* Come back later if the device is busy... */\r
 547                 vpu_queue_power_off_work(pservice);\r
 548         }\r
 549 }\r
 550 \r
 551 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 552 {\r
 553     static ktime_t last;\r
 554     ktime_t now = ktime_get();\r
 555     if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 556         cancel_delayed_work_sync(&pservice->power_off_work);\r
 557         vpu_queue_power_off_work(pservice);\r
 558         last = now;\r
 559     }\r
 560     if (pservice->enabled)\r
 561         return ;\r
 562 \r
 563     pservice->enabled = true;\r
 564     printk("%s: power on\n", dev_name(pservice->dev));\r
 565 \r
 566 #if VCODEC_CLOCK_ENABLE\r
 567     clk_prepare_enable(pservice->aclk_vcodec);\r
 568     clk_prepare_enable(pservice->hclk_vcodec);\r
 569 \r
 570     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 571         clk_prepare_enable(pservice->clk_core);\r
 572         clk_prepare_enable(pservice->clk_cabac);\r
 573     }\r
 574     \r
 575     clk_prepare_enable(pservice->pd_video);\r
 576 #endif\r
 577 \r
 578 #if defined(CONFIG_ARCH_RK319X)\r
 579     /// select aclk_vepu as vcodec clock source. \r
 580     #define BIT_VCODEC_SEL  (1<<7)\r
 581     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 582 #endif\r
 583     \r
 584     udelay(10);\r
 585     wake_lock(&pservice->wake_lock);\r
 586 }\r
 587 \r
 588 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 589 {\r
 590         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 591         return ((type == 8) || (type == 4));\r
 592 }\r
 593 \r
 594 static inline bool reg_check_interlace(vpu_reg *reg)\r
 595 {\r
 596         unsigned long type = (reg->reg[3] & (1 << 23));\r
 597         return (type > 0);\r
 598 }\r
 599 \r
 600 static inline bool reg_check_avc(vpu_reg *reg)\r
 601 {\r
 602         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 603         return (type == 0);\r
 604 }\r
 605 \r
 606 static inline int reg_probe_width(vpu_reg *reg)\r
 607 {\r
 608     int width_in_mb = reg->reg[4] >> 23;\r
 609     \r
 610     return width_in_mb * 16;\r
 611 }\r
 612 \r
 613 #if defined(CONFIG_VCODEC_MMU)\r
 614 \r
 615 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
 616 {\r
 617     int i;\r
 618     int usr_fd = 0;\r
 619     int offset = 0;\r
 620     \r
 621     if (tbl == NULL || size <= 0) {\r
 622         dev_err(pservice->dev, "input arguments invalidate\n");\r
 623         return -1;\r
 624     }\r
 625     \r
 626     vpu_service_power_on(pservice);\r
 627     \r
 628     for (i=0; i<size; i++) {\r
 629 #if 0\r
 630         if (copy_from_user(&usr_fd, &reg->reg[addr_tbl_vpu_dec[i]], sizeof(usr_fd)))\r
 631             return -EFAULT;\r
 632 #else\r
 633         usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
 634         offset = reg->reg[tbl[i]] >> 10;\r
 635         \r
 636 #endif\r
 637         if (usr_fd != 0) {\r
 638             struct ion_handle *hdl;\r
 639             \r
 640             hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 641             if (IS_ERR(hdl)) {\r
 642                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
 643                 return PTR_ERR(hdl);\r
 644             }\r
 645 \r
 646 #if 0\r
 647             {\r
 648                 ion_phys_addr_t phy_addr;\r
 649                 size_t len;\r
 650                 ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
 651     \r
 652                 reg->reg[tbl[i]] = phy_addr + offset;\r
 653                 \r
 654                 ion_free(pservice->ion_client, hdl);\r
 655             }\r
 656 #else \r
 657             {\r
 658                 int ret;\r
 659                 struct vcodec_mem_region *mem_region;\r
 660                 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 661      \r
 662                 if (mem_region == NULL) {\r
 663                     dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 664                     ion_free(pservice->ion_client, hdl);\r
 665                     return -1;\r
 666                 }\r
 667                 \r
 668                 mem_region->hdl = hdl;\r
 669                 \r
 670                 ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
 671                 if (ret < 0) {\r
 672                     dev_err(pservice->dev, "ion map iommu failed\n");\r
 673                     kfree(mem_region);\r
 674                     ion_free(pservice->ion_client, hdl);\r
 675                     return ret;\r
 676                 }\r
 677                 \r
 678                 reg->reg[tbl[i]] = mem_region->iova + offset;\r
 679                 INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 680                 list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 681             }\r
 682 #endif\r
 683         }\r
 684     }\r
 685     \r
 686     return 0;\r
 687 }\r
 688 \r
 689 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 690 {\r
 691     VPU_HW_ID hw_id;\r
 692     u8 *tbl;\r
 693     int size = 0;\r
 694     \r
 695     hw_id = pservice->hw_info->hw_id;\r
 696     \r
 697     if (hw_id == HEVC_ID) {\r
 698         tbl = addr_tbl_hevc_dec;\r
 699         size = sizeof(addr_tbl_hevc_dec);\r
 700     } else {\r
 701         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 702             tbl = addr_tbl_vpu_dec;\r
 703             size = sizeof(addr_tbl_vpu_dec);\r
 704         } else if (reg->type == VPU_ENC) {\r
 705             tbl = addr_tbl_vpu_enc;\r
 706             size = sizeof(addr_tbl_vpu_enc);\r
 707         }\r
 708     }\r
 709     \r
 710     if (size != 0) {\r
 711         return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
 712     } else {\r
 713         return -1;\r
 714     }\r
 715 }\r
 716 #endif\r
 717 \r
 718 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 719 {\r
 720         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 721         if (NULL == reg) {\r
 722                 pr_err("error: kmalloc fail in reg_init\n");\r
 723                 return NULL;\r
 724         }\r
 725 \r
 726         if (size > pservice->reg_size) {\r
 727                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 728                 size = pservice->reg_size;\r
 729         }\r
 730         reg->session = session;\r
 731         reg->type = session->type;\r
 732         reg->size = size;\r
 733         reg->freq = VPU_FREQ_DEFAULT;\r
 734         reg->reg = (unsigned long *)&reg[1];\r
 735         INIT_LIST_HEAD(&reg->session_link);\r
 736         INIT_LIST_HEAD(&reg->status_link);\r
 737 \r
 738 #if defined(CONFIG_VCODEC_MMU)    \r
 739     INIT_LIST_HEAD(&reg->mem_region_list);\r
 740 #endif    \r
 741 \r
 742         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 743                 pr_err("error: copy_from_user failed in reg_init\n");\r
 744                 kfree(reg);\r
 745                 return NULL;\r
 746         }\r
 747 \r
 748 #if defined(CONFIG_VCODEC_MMU)\r
 749     if (0 > vcodec_reg_address_translate(pservice, reg)) {\r
 750         pr_err("error: translate reg address failed\n");\r
 751         kfree(reg);\r
 752         return NULL;\r
 753     }\r
 754 #endif\r
 755 \r
 756         mutex_lock(&pservice->lock);\r
 757         list_add_tail(&reg->status_link, &pservice->waiting);\r
 758         list_add_tail(&reg->session_link, &session->waiting);\r
 759         mutex_unlock(&pservice->lock);\r
 760 \r
 761         if (pservice->auto_freq) {\r
 762                 if (!soc_is_rk2928g()) {\r
 763                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 764                                 if (reg_check_rmvb_wmv(reg)) {\r
 765                                         reg->freq = VPU_FREQ_200M;\r
 766                                 } else if (reg_check_avc(reg)) {\r
 767                     if (reg_probe_width(reg) > 3200) {\r
 768                         // raise frequency for 4k avc.\r
 769                         reg->freq = VPU_FREQ_500M;\r
 770                     }\r
 771                 } else {\r
 772                                         if (reg_check_interlace(reg)) {\r
 773                                                 reg->freq = VPU_FREQ_400M;\r
 774                                         }\r
 775                                 }\r
 776                         }\r
 777                         if (reg->type == VPU_PP) {\r
 778                                 reg->freq = VPU_FREQ_400M;\r
 779                         }\r
 780                 }\r
 781         }\r
 782 \r
 783         return reg;\r
 784 }\r
 785 \r
 786 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 787 {\r
 788 #if defined(CONFIG_VCODEC_MMU)    \r
 789     struct vcodec_mem_region *mem_region = NULL, *n;\r
 790 #endif\r
 791     \r
 792     list_del_init(&reg->session_link);\r
 793     list_del_init(&reg->status_link);\r
 794     if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
 795     if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
 796     \r
 797 #if defined(CONFIG_VCODEC_MMU)\r
 798     // release memory region attach to this registers table.\r
 799     list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 800         ion_unmap_iommu(pservice->dev, pservice->ion_client, mem_region->hdl);\r
 801         ion_free(pservice->ion_client, mem_region->hdl);\r
 802         list_del_init(&mem_region->reg_lnk);\r
 803         kfree(mem_region);\r
 804     }\r
 805 #endif    \r
 806     \r
 807     kfree(reg);\r
 808 }\r
 809 \r
 810 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 811 {\r
 812     list_del_init(&reg->status_link);\r
 813         list_add_tail(&reg->status_link, &pservice->running);\r
 814 \r
 815         list_del_init(&reg->session_link);\r
 816         list_add_tail(&reg->session_link, &reg->session->running);\r
 817 }\r
 818 \r
 819 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 820 {\r
 821         int i;\r
 822         u32 *dst = (u32 *)&reg->reg[0];\r
 823         for (i = 0; i < count; i++)\r
 824         *dst++ = *src++;\r
 825 }\r
 826 \r
 827 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 828 {\r
 829     int irq_reg = -1;\r
 830         list_del_init(&reg->status_link);\r
 831         list_add_tail(&reg->status_link, &pservice->done);\r
 832 \r
 833         list_del_init(&reg->session_link);\r
 834         list_add_tail(&reg->session_link, &reg->session->done);\r
 835 \r
 836         switch (reg->type) {\r
 837         case VPU_ENC : {\r
 838                 pservice->reg_codec = NULL;\r
 839                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 840                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 841                 break;\r
 842         }\r
 843         case VPU_DEC : {\r
 844         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 845                 pservice->reg_codec = NULL;\r
 846                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 847                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 848                 break;\r
 849         }\r
 850         case VPU_PP : {\r
 851                 pservice->reg_pproc = NULL;\r
 852                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 853                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 854                 break;\r
 855         }\r
 856         case VPU_DEC_PP : {\r
 857                 pservice->reg_codec = NULL;\r
 858                 pservice->reg_pproc = NULL;\r
 859                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 860                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 861                 break;\r
 862         }\r
 863         default : {\r
 864                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 865                 break;\r
 866         }\r
 867         }\r
 868 \r
 869     if (irq_reg != -1) {\r
 870         reg->reg[irq_reg] = pservice->irq_status;\r
 871     }\r
 872 \r
 873         atomic_sub(1, &reg->session->task_running);\r
 874         atomic_sub(1, &pservice->total_running);\r
 875         wake_up(&reg->session->wait);\r
 876 }\r
 877 \r
 878 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 879 {\r
 880         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 881         if (curr == reg->freq) {\r
 882                 return ;\r
 883         }\r
 884         atomic_set(&pservice->freq_status, reg->freq);\r
 885         switch (reg->freq) {\r
 886         case VPU_FREQ_200M : {\r
 887                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 888                 //printk("default: 200M\n");\r
 889         } break;\r
 890         case VPU_FREQ_266M : {\r
 891                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 892                 //printk("default: 266M\n");\r
 893         } break;\r
 894         case VPU_FREQ_300M : {\r
 895                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 896                 //printk("default: 300M\n");\r
 897         } break;\r
 898         case VPU_FREQ_400M : {\r
 899                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 900                 //printk("default: 400M\n");\r
 901         } break;\r
 902     case VPU_FREQ_500M : {\r
 903         clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
 904     } break;\r
 905     case VPU_FREQ_600M : {\r
 906         clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
 907     } break;\r
 908         default : {\r
 909                 if (soc_is_rk2928g()) {\r
 910                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 911                 } else {\r
 912                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 913                 }\r
 914                 //printk("default: 300M\n");\r
 915         } break;\r
 916         }\r
 917 }\r
 918 \r
 919 #if HEVC_SIM_ENABLE\r
 920 static void simulate_start(struct vpu_service_info *pservice);\r
 921 #endif\r
 922 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 923 {\r
 924         int i;\r
 925         u32 *src = (u32 *)&reg->reg[0];\r
 926         atomic_add(1, &pservice->total_running);\r
 927         atomic_add(1, &reg->session->task_running);\r
 928         if (pservice->auto_freq) {\r
 929                 vpu_service_set_freq(pservice, reg);\r
 930         }\r
 931         switch (reg->type) {\r
 932         case VPU_ENC : {\r
 933                 int enc_count = pservice->hw_info->enc_reg_num;\r
 934                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 935 #if 0\r
 936                 if (pservice->bug_dec_addr) {\r
 937 #if !defined(CONFIG_ARCH_RK319X)\r
 938                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 939 #endif\r
 940                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 941                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 942 #if !defined(CONFIG_ARCH_RK319X)\r
 943                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 944 #endif\r
 945                 }\r
 946 #endif\r
 947                 pservice->reg_codec = reg;\r
 948 \r
 949                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
 950 \r
 951                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
 952                         dst[i] = src[i];\r
 953 \r
 954                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
 955                         dst[i] = src[i];\r
 956 \r
 957                 dsb();\r
 958 \r
 959                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
 960                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
 961 \r
 962 #if VPU_SERVICE_SHOW_TIME\r
 963                 do_gettimeofday(&enc_start);\r
 964 #endif\r
 965 \r
 966         } break;\r
 967         case VPU_DEC : {\r
 968                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 969 \r
 970                 pservice->reg_codec = reg;\r
 971 \r
 972         if (pservice->hw_info->hw_id != HEVC_ID) {\r
 973                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
 974                                 dst[i] = src[i];\r
 975         } else {\r
 976             for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
 977                                 dst[i] = src[i];\r
 978             }\r
 979                 }\r
 980 \r
 981                 dsb();\r
 982 \r
 983                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
 984                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
 985                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
 986                 } else {\r
 987                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
 988                 }\r
 989 \r
 990         dsb();\r
 991         dmb();\r
 992 \r
 993 #if VPU_SERVICE_SHOW_TIME\r
 994                 do_gettimeofday(&dec_start);\r
 995 #endif\r
 996 \r
 997         } break;\r
 998         case VPU_PP : {\r
 999                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
1000                 pservice->reg_pproc = reg;\r
1001 \r
1002                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1003 \r
1004                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1005                         dst[i] = src[i];\r
1006 \r
1007                 dsb();\r
1008 \r
1009                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1010 \r
1011 #if VPU_SERVICE_SHOW_TIME\r
1012                 do_gettimeofday(&pp_start);\r
1013 #endif\r
1014 \r
1015         } break;\r
1016         case VPU_DEC_PP : {\r
1017                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1018                 pservice->reg_codec = reg;\r
1019                 pservice->reg_pproc = reg;\r
1020 \r
1021                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1022                         dst[i] = src[i];\r
1023 \r
1024                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1025                 dsb();\r
1026 \r
1027                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1028                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1029                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1030 \r
1031 #if VPU_SERVICE_SHOW_TIME\r
1032                 do_gettimeofday(&dec_start);\r
1033 #endif\r
1034 \r
1035         } break;\r
1036         default : {\r
1037                 pr_err("error: unsupport session type %d", reg->type);\r
1038                 atomic_sub(1, &pservice->total_running);\r
1039                 atomic_sub(1, &reg->session->task_running);\r
1040                 break;\r
1041         }\r
1042         }\r
1043 \r
1044 #if HEVC_SIM_ENABLE\r
1045     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1046         simulate_start(pservice);\r
1047     }\r
1048 #endif\r
1049 }\r
1050 \r
1051 static void try_set_reg(struct vpu_service_info *pservice)\r
1052 {\r
1053         // first get reg from reg list\r
1054         if (!list_empty(&pservice->waiting)) {\r
1055                 int can_set = 0;\r
1056                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1057 \r
1058                 vpu_service_power_on(pservice);\r
1059 \r
1060                 switch (reg->type) {\r
1061                 case VPU_ENC : {\r
1062                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1063                                 can_set = 1;\r
1064                 } break;\r
1065                 case VPU_DEC : {\r
1066                         if (NULL == pservice->reg_codec)\r
1067                                 can_set = 1;\r
1068                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1069                                 can_set = 0;\r
1070                         }\r
1071                 } break;\r
1072                 case VPU_PP : {\r
1073                         if (NULL == pservice->reg_codec) {\r
1074                                 if (NULL == pservice->reg_pproc)\r
1075                                         can_set = 1;\r
1076                         } else {\r
1077                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1078                                         can_set = 1;\r
1079                                 // can not charge frequency when vpu is working\r
1080                                 if (pservice->auto_freq) {\r
1081                                         can_set = 0;\r
1082                                 }\r
1083                         }\r
1084                 } break;\r
1085                 case VPU_DEC_PP : {\r
1086                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1087                                 can_set = 1;\r
1088                         } break;\r
1089                 default : {\r
1090                         printk("undefined reg type %d\n", reg->type);\r
1091                 } break;\r
1092                 }\r
1093                 if (can_set) {\r
1094                         reg_from_wait_to_run(pservice, reg);\r
1095                         reg_copy_to_hw(pservice, reg);\r
1096                 }\r
1097         }\r
1098 }\r
1099 \r
1100 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1101 {\r
1102         int ret = 0;\r
1103         switch (reg->type) {\r
1104         case VPU_ENC : {\r
1105                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1106                         ret = -EFAULT;\r
1107                 break;\r
1108         }\r
1109         case VPU_DEC : {\r
1110         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1111                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1112                         ret = -EFAULT;\r
1113                 break;\r
1114         }\r
1115         case VPU_PP : {\r
1116                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1117                         ret = -EFAULT;\r
1118                 break;\r
1119         }\r
1120         case VPU_DEC_PP : {\r
1121                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1122                         ret = -EFAULT;\r
1123                 break;\r
1124         }\r
1125         default : {\r
1126                 ret = -EFAULT;\r
1127                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1128                 break;\r
1129         }\r
1130         }\r
1131         reg_deinit(pservice, reg);\r
1132         return ret;\r
1133 }\r
1134 \r
1135 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1136 {\r
1137     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1138         vpu_session *session = (vpu_session *)filp->private_data;\r
1139         if (NULL == session) {\r
1140                 return -EINVAL;\r
1141         }\r
1142 \r
1143         switch (cmd) {\r
1144         case VPU_IOC_SET_CLIENT_TYPE : {\r
1145                 session->type = (VPU_CLIENT_TYPE)arg;\r
1146                 break;\r
1147         }\r
1148         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1149                 vpu_request req;\r
1150                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1151                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1152                         return -EFAULT;\r
1153                 } else {\r
1154                         if (VPU_ENC != session->type) {\r
1155                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1156                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1157                                         return -EFAULT;\r
1158                                 }\r
1159                         } else {\r
1160                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1161                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1162                                         return -EFAULT;\r
1163                                 }\r
1164                         }\r
1165                 }\r
1166 \r
1167                 break;\r
1168         }\r
1169         case VPU_IOC_SET_REG : {\r
1170                 vpu_request req;\r
1171                 vpu_reg *reg;\r
1172                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1173                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1174                         return -EFAULT;\r
1175                 }\r
1176                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1177                 if (NULL == reg) {\r
1178                         return -EFAULT;\r
1179                 } else {\r
1180                         mutex_lock(&pservice->lock);\r
1181                         try_set_reg(pservice);\r
1182                         mutex_unlock(&pservice->lock);\r
1183                 }\r
1184 \r
1185                 break;\r
1186         }\r
1187         case VPU_IOC_GET_REG : {\r
1188                 vpu_request req;\r
1189                 vpu_reg *reg;\r
1190                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1191                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1192                         return -EFAULT;\r
1193                 } else {\r
1194                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1195                         if (!list_empty(&session->done)) {\r
1196                                 if (ret < 0) {\r
1197                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1198                                 }\r
1199                                 ret = 0;\r
1200                         } else {\r
1201                                 if (unlikely(ret < 0)) {\r
1202                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1203                                 } else if (0 == ret) {\r
1204                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1205                                         ret = -ETIMEDOUT;\r
1206                                 }\r
1207                         }\r
1208                         if (ret < 0) {\r
1209                                 int task_running = atomic_read(&session->task_running);\r
1210                                 mutex_lock(&pservice->lock);\r
1211                                 vpu_service_dump(pservice);\r
1212                                 if (task_running) {\r
1213                                         atomic_set(&session->task_running, 0);\r
1214                                         atomic_sub(task_running, &pservice->total_running);\r
1215                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1216                                         vpu_reset(pservice);\r
1217                                         printk("done\n");\r
1218                                 }\r
1219                                 vpu_service_session_clear(pservice, session);\r
1220                                 mutex_unlock(&pservice->lock);\r
1221                                 return ret;\r
1222                         }\r
1223                 }\r
1224                 mutex_lock(&pservice->lock);\r
1225                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1226                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1227                 mutex_unlock(&pservice->lock);\r
1228                 break;\r
1229         }\r
1230         default : {\r
1231                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1232                 break;\r
1233         }\r
1234         }\r
1235 \r
1236         return 0;\r
1237 }\r
1238 \r
1239 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1240 {\r
1241         int ret = -EINVAL, i = 0;\r
1242         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1243         u32 enc_id = *tmp;\r
1244 \r
1245 #if HEVC_SIM_ENABLE\r
1246     /// temporary, hevc driver test.\r
1247     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1248         p->hw_info = &vpu_hw_set[2];\r
1249         return 0;\r
1250     }\r
1251 #endif\r
1252 \r
1253         enc_id = (enc_id >> 16) & 0xFFFF;\r
1254         pr_info("checking hw id %x\n", enc_id);\r
1255     p->hw_info = NULL;\r
1256         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1257                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1258                         p->hw_info = &vpu_hw_set[i];\r
1259                         ret = 0;\r
1260                         break;\r
1261                 }\r
1262         }\r
1263         iounmap((void *)tmp);\r
1264         return ret;\r
1265 }\r
1266 \r
1267 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1268 {\r
1269     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1270         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1271         if (NULL == session) {\r
1272                 pr_err("error: unable to allocate memory for vpu_session.");\r
1273                 return -ENOMEM;\r
1274         }\r
1275 \r
1276         session->type   = VPU_TYPE_BUTT;\r
1277         session->pid    = current->pid;\r
1278         INIT_LIST_HEAD(&session->waiting);\r
1279         INIT_LIST_HEAD(&session->running);\r
1280         INIT_LIST_HEAD(&session->done);\r
1281         INIT_LIST_HEAD(&session->list_session);\r
1282         init_waitqueue_head(&session->wait);\r
1283         atomic_set(&session->task_running, 0);\r
1284         mutex_lock(&pservice->lock);\r
1285         list_add_tail(&session->list_session, &pservice->session);\r
1286         filp->private_data = (void *)session;\r
1287         mutex_unlock(&pservice->lock);\r
1288 \r
1289         pr_debug("dev opened\n");\r
1290         return nonseekable_open(inode, filp);\r
1291 }\r
1292 \r
1293 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1294 {\r
1295     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1296         int task_running;\r
1297         vpu_session *session = (vpu_session *)filp->private_data;\r
1298         if (NULL == session)\r
1299                 return -EINVAL;\r
1300 \r
1301         task_running = atomic_read(&session->task_running);\r
1302         if (task_running) {\r
1303                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1304                 msleep(50);\r
1305         }\r
1306         wake_up(&session->wait);\r
1307 \r
1308         mutex_lock(&pservice->lock);\r
1309         /* remove this filp from the asynchronusly notified filp's */\r
1310         list_del_init(&session->list_session);\r
1311         vpu_service_session_clear(pservice, session);\r
1312         kfree(session);\r
1313         filp->private_data = NULL;\r
1314         mutex_unlock(&pservice->lock);\r
1315 \r
1316     pr_debug("dev closed\n");\r
1317         return 0;\r
1318 }\r
1319 \r
1320 static const struct file_operations vpu_service_fops = {\r
1321         .unlocked_ioctl = vpu_service_ioctl,\r
1322         .open           = vpu_service_open,\r
1323         .release        = vpu_service_release,\r
1324         //.fasync       = vpu_service_fasync,\r
1325 };\r
1326 \r
1327 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1328 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1329 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1330 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1331 static void get_hw_info(struct vpu_service_info *pservice);\r
1332 \r
1333 #if HEVC_SIM_ENABLE\r
1334 static void simulate_work(struct work_struct *work_s)\r
1335 {\r
1336     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1337     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1338     vpu_device *dev = &pservice->dec_dev;\r
1339 \r
1340     if (!list_empty(&pservice->running)) {\r
1341         atomic_add(1, &dev->irq_count_codec);\r
1342         vdpu_isr(0, (void*)pservice);\r
1343     } else {\r
1344         //simulate_start(pservice);\r
1345         pr_err("empty running queue\n");\r
1346     }\r
1347 }\r
1348 \r
1349 static void simulate_init(struct vpu_service_info *pservice)\r
1350 {\r
1351     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1352 }\r
1353 \r
1354 static void simulate_start(struct vpu_service_info *pservice)\r
1355 {\r
1356     cancel_delayed_work_sync(&pservice->power_off_work);\r
1357     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1358 }\r
1359 #endif\r
1360 \r
1361 #if HEVC_TEST_ENABLE\r
1362 static int hevc_test_case0(vpu_service_info *pservice);\r
1363 #endif\r
1364 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1365 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1366 #endif\r
1367 static int vcodec_probe(struct platform_device *pdev)\r
1368 {\r
1369     int ret = 0;\r
1370     struct resource *res = NULL;\r
1371     struct device *dev = &pdev->dev;\r
1372     void __iomem *regs = NULL;\r
1373     struct device_node *np = pdev->dev.of_node;\r
1374     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1375     char *prop = (char*)dev_name(dev);\r
1376 #if defined(CONFIG_VCODEC_MMU)\r
1377     struct device *mmu_dev = NULL;\r
1378     char mmu_dev_dts_name[40];\r
1379 #endif\r
1380 \r
1381     pr_info("probe device %s\n", dev_name(dev));\r
1382 \r
1383     of_property_read_string(np, "name", (const char**)&prop);\r
1384     dev_set_name(dev, prop);\r
1385 \r
1386     if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1387         pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1388     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1389         pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1390     } else {\r
1391         dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1392         return -1;\r
1393     }\r
1394 \r
1395     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1396     INIT_LIST_HEAD(&pservice->waiting);\r
1397     INIT_LIST_HEAD(&pservice->running);\r
1398     INIT_LIST_HEAD(&pservice->done);\r
1399     INIT_LIST_HEAD(&pservice->session);\r
1400     mutex_init(&pservice->lock);\r
1401     pservice->reg_codec = NULL;\r
1402     pservice->reg_pproc = NULL;\r
1403     atomic_set(&pservice->total_running, 0);\r
1404     pservice->enabled = false;\r
1405 \r
1406     pservice->dev = dev;\r
1407 \r
1408     if (0 > vpu_get_clk(pservice)) {\r
1409         goto err;\r
1410     }\r
1411 \r
1412     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1413 \r
1414     vpu_service_power_on(pservice);\r
1415 \r
1416     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1417 \r
1418     regs = devm_ioremap_resource(pservice->dev, res);\r
1419     if (IS_ERR(regs)) {\r
1420         ret = PTR_ERR(regs);\r
1421         goto err;\r
1422     }\r
1423 \r
1424     ret = vpu_service_check_hw(pservice, res->start);\r
1425     if (ret < 0) {\r
1426         pr_err("error: hw info check faild\n");\r
1427         goto err;\r
1428     }\r
1429 \r
1430     /// define regs address.\r
1431     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1432     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1433 \r
1434     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1435 \r
1436     pservice->reg_size   = pservice->dec_dev.iosize;\r
1437 \r
1438     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1439         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1440         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1441 \r
1442         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1443 \r
1444         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1445 \r
1446         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1447         if (pservice->irq_enc < 0) {\r
1448             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1449             ret = -ENXIO;\r
1450             goto err;\r
1451         }\r
1452 \r
1453         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1454         if (ret) {\r
1455             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1456             goto err;\r
1457         }\r
1458     }\r
1459 \r
1460     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1461     if (pservice->irq_dec < 0) {\r
1462         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1463         ret = -ENXIO;\r
1464         goto err;\r
1465     }\r
1466 \r
1467     /* get the IRQ line */\r
1468     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1469     if (ret) {\r
1470         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1471         goto err;\r
1472     }\r
1473 \r
1474     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1475     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1476     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1477     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1478 \r
1479     /// create device\r
1480     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1481     if (ret) {\r
1482         dev_err(dev, "alloc dev_t failed\n");\r
1483         goto err;\r
1484     }\r
1485 \r
1486     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1487 \r
1488     pservice->cdev.owner = THIS_MODULE;\r
1489     pservice->cdev.ops = &vpu_service_fops;\r
1490 \r
1491     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1492 \r
1493     if (ret) {\r
1494         dev_err(dev, "add dev_t failed\n");\r
1495         goto err;\r
1496     }\r
1497 \r
1498     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1499 \r
1500     if (IS_ERR(pservice->cls)) {\r
1501         ret = PTR_ERR(pservice->cls);\r
1502         dev_err(dev, "class_create err:%d\n", ret);\r
1503         goto err;\r
1504     }\r
1505 \r
1506     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1507 \r
1508     platform_set_drvdata(pdev, pservice);\r
1509 \r
1510     get_hw_info(pservice);\r
1511 \r
1512 \r
1513 #ifdef CONFIG_DEBUG_FS\r
1514     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1515     \r
1516     if (pservice->debugfs_dir == NULL) {\r
1517         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1518     }\r
1519 \r
1520     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1521                     pservice->debugfs_dir, pservice,\r
1522                     &debug_vcodec_fops);\r
1523 #endif\r
1524 \r
1525 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1526     pservice->ion_client = rockchip_ion_client_create("vpu");\r
1527     if (IS_ERR(pservice->ion_client)) {\r
1528         dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1529         return PTR_ERR(pservice->ion_client);\r
1530     } else {\r
1531         dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1532     }\r
1533     \r
1534     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1535         sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
1536     } else {\r
1537         sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
1538     }\r
1539     \r
1540     mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1541     \r
1542     if (mmu_dev) {\r
1543         platform_set_sysmmu(mmu_dev, pservice->dev);\r
1544         iovmm_activate(pservice->dev);\r
1545     }\r
1546 #endif\r
1547 \r
1548     vpu_service_power_off(pservice);\r
1549     pr_info("init success\n");\r
1550 \r
1551 #if HEVC_SIM_ENABLE\r
1552     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1553         simulate_init(pservice);\r
1554     }\r
1555 #endif\r
1556 \r
1557 #if HEVC_TEST_ENABLE\r
1558     hevc_test_case0(pservice);\r
1559 #endif\r
1560 \r
1561     return 0;\r
1562 \r
1563 err:\r
1564     pr_info("init failed\n");\r
1565     vpu_service_power_off(pservice);\r
1566     vpu_put_clk(pservice);\r
1567     wake_lock_destroy(&pservice->wake_lock);\r
1568 \r
1569     if (res) {\r
1570         if (regs) {\r
1571             devm_ioremap_release(&pdev->dev, res);\r
1572         }\r
1573         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1574     }\r
1575 \r
1576     if (pservice->irq_enc > 0) {\r
1577         free_irq(pservice->irq_enc, (void *)pservice);\r
1578     }\r
1579 \r
1580     if (pservice->irq_dec > 0) {\r
1581         free_irq(pservice->irq_dec, (void *)pservice);\r
1582     }\r
1583 \r
1584     if (pservice->child_dev) {\r
1585         device_destroy(pservice->cls, pservice->dev_t);\r
1586         cdev_del(&pservice->cdev);\r
1587         unregister_chrdev_region(pservice->dev_t, 1);\r
1588     }\r
1589 \r
1590     if (pservice->cls) {\r
1591         class_destroy(pservice->cls);\r
1592     }\r
1593 \r
1594     return ret;\r
1595 }\r
1596 \r
1597 static int vcodec_remove(struct platform_device *pdev)\r
1598 {\r
1599     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1600     struct resource *res;\r
1601 \r
1602     device_destroy(pservice->cls, pservice->dev_t);\r
1603     class_destroy(pservice->cls);\r
1604     cdev_del(&pservice->cdev);\r
1605     unregister_chrdev_region(pservice->dev_t, 1);\r
1606 \r
1607     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1608     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1609     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1610     devm_ioremap_release(&pdev->dev, res);\r
1611     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1612     vpu_put_clk(pservice);\r
1613     wake_lock_destroy(&pservice->wake_lock);\r
1614     \r
1615 #ifdef CONFIG_DEBUG_FS\r
1616     if (pservice->debugfs_file_regs) {\r
1617         debugfs_remove(pservice->debugfs_file_regs);\r
1618     }\r
1619 \r
1620     if (pservice->debugfs_dir) {\r
1621         debugfs_remove(pservice->debugfs_dir);\r
1622     }\r
1623 #endif\r
1624 \r
1625     return 0;\r
1626 }\r
1627 \r
1628 #if defined(CONFIG_OF)\r
1629 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1630     {.compatible = "vpu_service",},\r
1631     {.compatible = "rockchip,hevc_service",},\r
1632     {},\r
1633 };\r
1634 #endif\r
1635 \r
1636 static struct platform_driver vcodec_driver = {\r
1637     .probe     = vcodec_probe,\r
1638     .remove        = vcodec_remove,\r
1639     .driver = {\r
1640         .name = "vcodec",\r
1641         .owner = THIS_MODULE,\r
1642 #if defined(CONFIG_OF)\r
1643         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1644 #endif\r
1645     },\r
1646 };\r
1647 \r
1648 static void get_hw_info(struct vpu_service_info *pservice)\r
1649 {\r
1650     VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1651     VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1652 \r
1653     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {             \r
1654         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1655         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1656     \r
1657         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1658         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1659         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1660             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1661         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1662         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1663         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1664         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1665         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1666         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1667     \r
1668         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1669             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1670         } else {\r
1671             dec->maxDecPicWidth = 4096;\r
1672         }\r
1673     \r
1674         /* 2nd Config register */\r
1675         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1676         if (dec->refBufSupport) {\r
1677             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1678                 dec->refBufSupport |= 2;\r
1679             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1680                 dec->refBufSupport |= 4;\r
1681         }\r
1682         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1683         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1684         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1685         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1686     \r
1687         /* JPEG xtensions */\r
1688         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1689             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1690         } else {\r
1691             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1692         }\r
1693     \r
1694         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1695             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1696         } else {\r
1697             dec->rvSupport = RV_NOT_SUPPORTED;\r
1698         }\r
1699     \r
1700         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1701     \r
1702         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1703             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1704         }\r
1705     \r
1706         /// invalidate fuse register value in rk319x vpu and following.\r
1707         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1708             VPUHwFuseStatus_t hwFuseSts;\r
1709             /* Decoder fuse configuration */\r
1710             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1711     \r
1712             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1713             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1714             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1715             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1716             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1717             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1718             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1719             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1720             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1721             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1722             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1723             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1724             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1725             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1726     \r
1727             /* check max. decoder output width */\r
1728     \r
1729             if (fuseReg & 0x8000U)\r
1730                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1731             else if (fuseReg & 0x4000U)\r
1732                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1733             else if (fuseReg & 0x2000U)\r
1734                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1735             else if (fuseReg & 0x1000U)\r
1736                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1737             else    /* remove warning */\r
1738                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1739     \r
1740             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1741     \r
1742             /* Pp configuration */\r
1743             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1744     \r
1745             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1746                 dec->ppSupport = 1;\r
1747                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1748                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1749                 dec->ppConfig = configReg;\r
1750             } else {\r
1751                 dec->ppSupport = 0;\r
1752                 dec->maxPpOutPicWidth = 0;\r
1753                 dec->ppConfig = 0;\r
1754             }\r
1755     \r
1756             /* check the HW versio */\r
1757             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1758                 /* Pp configuration */\r
1759                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1760     \r
1761                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1762                     /* Pp fuse configuration */\r
1763                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1764     \r
1765                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1766                         hwFuseSts.ppSupportFuse = 1;\r
1767                         /* check max. pp output width */\r
1768                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1769                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1770                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1771                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1772                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1773                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1774                     } else {\r
1775                         hwFuseSts.ppSupportFuse = 0;\r
1776                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1777                         hwFuseSts.ppConfigFuse = 0;\r
1778                     }\r
1779                 } else {\r
1780                     hwFuseSts.ppSupportFuse = 0;\r
1781                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1782                     hwFuseSts.ppConfigFuse = 0;\r
1783                 }\r
1784     \r
1785                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1786                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1787                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1788                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1789                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1790                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1791                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1792                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1793                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1794                     dec->jpegSupport = JPEG_BASELINE;\r
1795                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1796                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1797                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1798                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1799                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1800                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1801     \r
1802                 /* check the pp config vs fuse status */\r
1803                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1804                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1805                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1806                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1807                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1808     \r
1809                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1810                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1811                 }\r
1812                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1813                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1814                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1815                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1816                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1817             }\r
1818         }\r
1819     \r
1820         configReg = pservice->enc_dev.hwregs[63];\r
1821         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1822         enc->h264Enabled = (configReg >> 27) & 1;\r
1823         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1824         enc->jpegEnabled = (configReg >> 25) & 1;\r
1825         enc->vsEnabled = (configReg >> 24) & 1;\r
1826         enc->rgbEnabled = (configReg >> 28) & 1;\r
1827         //enc->busType = (configReg >> 20) & 15;\r
1828         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1829         //enc->busWidth = (configReg >> 12) & 15;\r
1830         enc->reg_size = pservice->reg_size;\r
1831         enc->reserv[0] = enc->reserv[1] = 0;\r
1832     \r
1833         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
1834         if (pservice->auto_freq) {\r
1835             pr_info("vpu_service set to auto frequency mode\n");\r
1836             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1837         }\r
1838         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1839         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1840     } else {\r
1841         // disable frequency switch in hevc.\r
1842         pservice->auto_freq = false;\r
1843     }\r
1844 }\r
1845 \r
1846 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1847 {\r
1848     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1849     vpu_device *dev = &pservice->dec_dev;\r
1850     u32 raw_status;\r
1851     u32 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1852 \r
1853         pr_debug("dec_irq\n");\r
1854 \r
1855         if (irq_status & DEC_INTERRUPT_BIT) {\r
1856                 pr_debug("dec_isr dec %x\n", irq_status);\r
1857                 if ((irq_status & 0x40001) == 0x40001)\r
1858                 {\r
1859                         do {\r
1860                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1861                         } while ((irq_status & 0x40001) == 0x40001);\r
1862                 }\r
1863 \r
1864                 /* clear dec IRQ */\r
1865         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1866             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1867         } else {\r
1868             /*writel(irq_status \r
1869               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1870                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1871 \r
1872             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1873         }\r
1874                 atomic_add(1, &dev->irq_count_codec);\r
1875         }\r
1876 \r
1877     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1878         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1879         if (irq_status & PP_INTERRUPT_BIT) {\r
1880             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1881             /* clear pp IRQ */\r
1882             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1883             atomic_add(1, &dev->irq_count_pp);\r
1884         }\r
1885     }\r
1886 \r
1887     pservice->irq_status = raw_status;\r
1888 \r
1889         return IRQ_WAKE_THREAD;\r
1890 }\r
1891 \r
1892 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1893 {\r
1894     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1895     vpu_device *dev = &pservice->dec_dev;\r
1896 \r
1897         mutex_lock(&pservice->lock);\r
1898         if (atomic_read(&dev->irq_count_codec)) {\r
1899 #if VPU_SERVICE_SHOW_TIME\r
1900                 do_gettimeofday(&dec_end);\r
1901                 pr_info("dec task: %ld ms\n",\r
1902                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1903                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1904 #endif\r
1905                 atomic_sub(1, &dev->irq_count_codec);\r
1906                 if (NULL == pservice->reg_codec) {\r
1907                         pr_err("error: dec isr with no task waiting\n");\r
1908                 } else {\r
1909                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1910                 }\r
1911         }\r
1912 \r
1913         if (atomic_read(&dev->irq_count_pp)) {\r
1914 \r
1915 #if VPU_SERVICE_SHOW_TIME\r
1916                 do_gettimeofday(&pp_end);\r
1917                 printk("pp  task: %ld ms\n",\r
1918                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1919                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1920 #endif\r
1921 \r
1922                 atomic_sub(1, &dev->irq_count_pp);\r
1923                 if (NULL == pservice->reg_pproc) {\r
1924                         pr_err("error: pp isr with no task waiting\n");\r
1925                 } else {\r
1926                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1927                 }\r
1928         }\r
1929         try_set_reg(pservice);\r
1930         mutex_unlock(&pservice->lock);\r
1931         return IRQ_HANDLED;\r
1932 }\r
1933 \r
1934 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1935 {\r
1936         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1937     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1938     vpu_device *dev = &pservice->enc_dev;\r
1939         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1940 \r
1941         pr_debug("vepu_irq irq status %x\n", irq_status);\r
1942 \r
1943 #if VPU_SERVICE_SHOW_TIME\r
1944         do_gettimeofday(&enc_end);\r
1945         pr_info("enc task: %ld ms\n",\r
1946                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
1947                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
1948 #endif\r
1949     \r
1950         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
1951                 /* clear enc IRQ */\r
1952                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1953                 atomic_add(1, &dev->irq_count_codec);\r
1954         }\r
1955     \r
1956     pservice->irq_status = irq_status;\r
1957 \r
1958         return IRQ_WAKE_THREAD;\r
1959 }\r
1960 \r
1961 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
1962 {\r
1963         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1964     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1965     vpu_device *dev = &pservice->enc_dev;\r
1966 \r
1967         mutex_lock(&pservice->lock);\r
1968         if (atomic_read(&dev->irq_count_codec)) {\r
1969                 atomic_sub(1, &dev->irq_count_codec);\r
1970                 if (NULL == pservice->reg_codec) {\r
1971                         pr_err("error: enc isr with no task waiting\n");\r
1972                 } else {\r
1973                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1974                 }\r
1975         }\r
1976         try_set_reg(pservice);\r
1977         mutex_unlock(&pservice->lock);\r
1978         return IRQ_HANDLED;\r
1979 }\r
1980 \r
1981 static int __init vcodec_service_init(void)\r
1982 {\r
1983     int ret;\r
1984 \r
1985     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
1986         pr_err("Platform device register failed (%d).\n", ret);\r
1987         return ret;\r
1988     }\r
1989 \r
1990 #ifdef CONFIG_DEBUG_FS\r
1991     vcodec_debugfs_init();\r
1992 #endif\r
1993 \r
1994     return ret;\r
1995 }\r
1996 \r
1997 static void __exit vcodec_service_exit(void)\r
1998 {\r
1999 #ifdef CONFIG_DEBUG_FS\r
2000     vcodec_debugfs_exit();\r
2001 #endif\r
2002 \r
2003         platform_driver_unregister(&vcodec_driver);\r
2004 }\r
2005 \r
2006 module_init(vcodec_service_init);\r
2007 module_exit(vcodec_service_exit);\r
2008 \r
2009 #ifdef CONFIG_DEBUG_FS\r
2010 #include <linux/seq_file.h>\r
2011 \r
2012 static int vcodec_debugfs_init()\r
2013 {\r
2014     parent = debugfs_create_dir("vcodec", NULL);\r
2015     if (!parent)\r
2016         return -1;\r
2017 \r
2018     return 0;\r
2019 }\r
2020 \r
2021 static void vcodec_debugfs_exit()\r
2022 {\r
2023     debugfs_remove(parent);\r
2024 }\r
2025 \r
2026 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2027 {\r
2028     return debugfs_create_dir(dirname, parent);\r
2029 }\r
2030 \r
2031 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2032 {\r
2033         struct vpu_service_info *pservice = s->private;\r
2034     unsigned int i, n;\r
2035         vpu_reg *reg, *reg_tmp;\r
2036         vpu_session *session, *session_tmp;\r
2037 \r
2038         mutex_lock(&pservice->lock);\r
2039         vpu_service_power_on(pservice);\r
2040     if (pservice->hw_info->hw_id != HEVC_ID) {\r
2041         seq_printf(s, "\nENC Registers:\n");\r
2042         n = pservice->enc_dev.iosize >> 2;\r
2043         for (i = 0; i < n; i++) {\r
2044             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2045         }\r
2046     }\r
2047         seq_printf(s, "\nDEC Registers:\n");\r
2048         n = pservice->dec_dev.iosize >> 2;\r
2049         for (i = 0; i < n; i++) {\r
2050                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2051         }\r
2052 \r
2053         seq_printf(s, "\nvpu service status:\n");\r
2054         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2055                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2056                 //seq_printf(s, "waiting reg set %d\n");\r
2057                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2058                         seq_printf(s, "waiting register set\n");\r
2059                 }\r
2060                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2061                         seq_printf(s, "running register set\n");\r
2062                 }\r
2063                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2064                         seq_printf(s, "done    register set\n");\r
2065                 }\r
2066         }\r
2067         mutex_unlock(&pservice->lock);\r
2068 \r
2069     return 0;\r
2070 }\r
2071 \r
2072 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2073 {\r
2074         return single_open(file, debug_vcodec_show, inode->i_private);\r
2075 }\r
2076 \r
2077 #endif\r
2078 \r
2079 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2080 #include "hevc_test_inc/pps_00.h"\r
2081 #include "hevc_test_inc/register_00.h"\r
2082 #include "hevc_test_inc/rps_00.h"\r
2083 #include "hevc_test_inc/scaling_list_00.h"\r
2084 #include "hevc_test_inc/stream_00.h"\r
2085 \r
2086 #include "hevc_test_inc/pps_01.h"\r
2087 #include "hevc_test_inc/register_01.h"\r
2088 #include "hevc_test_inc/rps_01.h"\r
2089 #include "hevc_test_inc/scaling_list_01.h"\r
2090 #include "hevc_test_inc/stream_01.h"\r
2091 \r
2092 #include "hevc_test_inc/cabac.h"\r
2093 \r
2094 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2095 \r
2096 static struct ion_client *ion_client = NULL;\r
2097 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2098 {\r
2099         int size = (len+15) & (~15);\r
2100     struct ion_handle *handle;\r
2101         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2102 \r
2103     if (ion_client == NULL) {\r
2104         ion_client = rockchip_ion_client_create("vcodec");\r
2105     }\r
2106 \r
2107     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2108 \r
2109     ptr = ion_map_kernel(ion_client, handle);\r
2110 \r
2111     ion_phys(ion_client, handle, phy, &size);\r
2112 \r
2113         memcpy(ptr, tbl, len);\r
2114 \r
2115         return ptr;\r
2116 }\r
2117 \r
2118 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2119 {\r
2120         int size = (len+15) & (~15);\r
2121     struct ion_handle *handle;\r
2122         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2123 \r
2124     if (ion_client == NULL) {\r
2125         ion_client = rockchip_ion_client_create("vcodec");\r
2126     }\r
2127 \r
2128     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2129 \r
2130     ptr = ion_map_kernel(ion_client, handle);\r
2131 \r
2132     ion_phys(ion_client, handle, phy, &size);\r
2133 \r
2134         return ptr;\r
2135 }\r
2136 \r
2137 #define TEST_CNT    2\r
2138 static int hevc_test_case0(vpu_service_info *pservice)\r
2139 {\r
2140     vpu_session session;\r
2141     vpu_reg *reg; \r
2142     unsigned long size = 272;//sizeof(register_00); // registers array length\r
2143     int testidx = 0;\r
2144     int ret = 0;\r
2145 \r
2146     u8 *pps_tbl[TEST_CNT];\r
2147     u8 *register_tbl[TEST_CNT];\r
2148     u8 *rps_tbl[TEST_CNT];\r
2149     u8 *scaling_list_tbl[TEST_CNT];\r
2150     u8 *stream_tbl[TEST_CNT];\r
2151 \r
2152         int stream_size[2];\r
2153         int pps_size[2];\r
2154         int rps_size[2];\r
2155         int scl_size[2];\r
2156         int cabac_size[2];\r
2157         \r
2158     u32 phy_pps;\r
2159     u32 phy_rps;\r
2160     u32 phy_scl;\r
2161     u32 phy_str;\r
2162     u32 phy_yuv;\r
2163     u32 phy_ref;\r
2164     u32 phy_cabac;\r
2165 \r
2166         volatile u8 *stream_buf;\r
2167         volatile u8 *pps_buf;\r
2168         volatile u8 *rps_buf;\r
2169         volatile u8 *scl_buf;\r
2170         volatile u8 *yuv_buf;\r
2171         volatile u8 *cabac_buf;\r
2172         volatile u8 *ref_buf;\r
2173 \r
2174     u8 *pps;\r
2175     u8 *yuv[2];\r
2176     int i;\r
2177     \r
2178     pps_tbl[0] = pps_00;\r
2179     pps_tbl[1] = pps_01;\r
2180 \r
2181     register_tbl[0] = register_00;\r
2182     register_tbl[1] = register_01;\r
2183     \r
2184     rps_tbl[0] = rps_00;\r
2185     rps_tbl[1] = rps_01;\r
2186     \r
2187     scaling_list_tbl[0] = scaling_list_00;\r
2188     scaling_list_tbl[1] = scaling_list_01;\r
2189 \r
2190     stream_tbl[0] = stream_00;\r
2191     stream_tbl[1] = stream_01;\r
2192 \r
2193     stream_size[0] = sizeof(stream_00);\r
2194     stream_size[1] = sizeof(stream_01);\r
2195 \r
2196         pps_size[0] = sizeof(pps_00);\r
2197         pps_size[1] = sizeof(pps_01);\r
2198 \r
2199         rps_size[0] = sizeof(rps_00);\r
2200         rps_size[1] = sizeof(rps_01);\r
2201 \r
2202         scl_size[0] = sizeof(scaling_list_00);\r
2203         scl_size[1] = sizeof(scaling_list_01);\r
2204         \r
2205         cabac_size[0] = sizeof(Cabac_table);\r
2206         cabac_size[1] = sizeof(Cabac_table);\r
2207 \r
2208     // create session\r
2209     session.pid = current->pid;\r
2210     session.type = VPU_DEC;\r
2211     INIT_LIST_HEAD(&session.waiting);\r
2212         INIT_LIST_HEAD(&session.running);\r
2213         INIT_LIST_HEAD(&session.done);\r
2214         INIT_LIST_HEAD(&session.list_session);\r
2215         init_waitqueue_head(&session.wait);\r
2216         atomic_set(&session.task_running, 0);\r
2217         list_add_tail(&session.list_session, &pservice->session);\r
2218 \r
2219     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2220     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2221 \r
2222         while (testidx < TEST_CNT) {\r
2223         \r
2224         // create registers\r
2225         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2226         if (NULL == reg) {\r
2227             pr_err("error: kmalloc fail in reg_init\n");\r
2228             return -1;\r
2229         }\r
2230 \r
2231 \r
2232         if (size > pservice->reg_size) {\r
2233             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2234             size = pservice->reg_size;\r
2235         }\r
2236         reg->session = &session;\r
2237         reg->type = session.type;\r
2238         reg->size = size;\r
2239         reg->freq = VPU_FREQ_DEFAULT;\r
2240         reg->reg = (unsigned long *)&reg[1];\r
2241         INIT_LIST_HEAD(&reg->session_link);\r
2242         INIT_LIST_HEAD(&reg->status_link);\r
2243 \r
2244         // TODO: stuff registers\r
2245         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2246 \r
2247                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2248                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2249                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2250                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2251                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2252 \r
2253                 pps = pps_buf;\r
2254 \r
2255         // TODO: replace reigster address\r
2256 \r
2257         for (i=0; i<64; i++) {\r
2258             u32 scaling_offset;\r
2259             u32 tmp;\r
2260 \r
2261             scaling_offset = (u32)pps[i*80+74];\r
2262             scaling_offset += (u32)pps[i*80+75] << 8;\r
2263             scaling_offset += (u32)pps[i*80+76] << 16;\r
2264             scaling_offset += (u32)pps[i*80+77] << 24;\r
2265 \r
2266             tmp = phy_scl + scaling_offset;\r
2267 \r
2268             pps[i*80+74] = tmp & 0xff;\r
2269             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2270             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2271             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2272         }\r
2273 \r
2274         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2275 \r
2276         reg->reg[1] = 0x21;\r
2277         reg->reg[4] = phy_str;\r
2278         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2279         reg->reg[6] = phy_cabac;\r
2280         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2281         reg->reg[42] = phy_pps;\r
2282         reg->reg[43] = phy_rps;\r
2283         for (i = 10; i <= 24; i++) {\r
2284             reg->reg[i] = phy_yuv;\r
2285         }\r
2286 \r
2287         mutex_lock(&pservice->lock);\r
2288         list_add_tail(&reg->status_link, &pservice->waiting);\r
2289         list_add_tail(&reg->session_link, &session.waiting);\r
2290         mutex_unlock(&pservice->lock);\r
2291 \r
2292         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2293 \r
2294         // stuff hardware\r
2295         try_set_reg(pservice);\r
2296 \r
2297         // wait for result\r
2298         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2299         if (!list_empty(&session.done)) {\r
2300             if (ret < 0) {\r
2301                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2302             }\r
2303             ret = 0;\r
2304         } else {\r
2305             if (unlikely(ret < 0)) {\r
2306                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2307             } else if (0 == ret) {\r
2308                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2309                 ret = -ETIMEDOUT;\r
2310             }\r
2311         }\r
2312         if (ret < 0) {\r
2313             int task_running = atomic_read(&session.task_running);\r
2314             int n;\r
2315             mutex_lock(&pservice->lock);\r
2316             vpu_service_dump(pservice);\r
2317             if (task_running) {\r
2318                 atomic_set(&session.task_running, 0);\r
2319                 atomic_sub(task_running, &pservice->total_running);\r
2320                 printk("%d task is running but not return, reset hardware...", task_running);\r
2321                 vpu_reset(pservice);\r
2322                 printk("done\n");\r
2323             }\r
2324             vpu_service_session_clear(pservice, &session);\r
2325             mutex_unlock(&pservice->lock);\r
2326 \r
2327             printk("\nDEC Registers:\n");\r
2328                 n = pservice->dec_dev.iosize >> 2;\r
2329                 for (i=0; i<n; i++) {\r
2330                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2331                 }\r
2332 \r
2333             pr_err("test index %d failed\n", testidx);\r
2334             break;\r
2335         } else {\r
2336             pr_info("test index %d success\n", testidx);\r
2337 \r
2338             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2339 \r
2340             for (i=0; i<68; i++) {\r
2341                 if (i % 4 == 0) {\r
2342                     printk("%02d: ", i);\r
2343                 }\r
2344                 printk("%08x ", reg->reg[i]);\r
2345                 if ((i+1) % 4 == 0) {\r
2346                     printk("\n");\r
2347                 }\r
2348             }\r
2349 \r
2350             testidx++;\r
2351         }\r
2352 \r
2353         reg_deinit(pservice, reg);\r
2354     }\r
2355 \r
2356     return 0;\r
2357 }\r
2358 \r
2359 #endif\r
2360 \r