arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 //#define CONFIG_VCODEC_MMU\r
  47 \r
  48 #ifdef CONFIG_VCODEC_MMU\r
  49 #include <linux/rockchip/iovmm.h>\r
  50 #include <linux/rockchip/sysmmu.h>\r
  51 #include <linux/dma-buf.h>\r
  52 #endif\r
  53 \r
  54 #ifdef CONFIG_DEBUG_FS\r
  55 #include <linux/debugfs.h>\r
  56 #endif\r
  57 \r
  58 #if defined(CONFIG_ARCH_RK319X)\r
  59 #include <mach/grf.h>\r
  60 #endif\r
  61 \r
  62 #include "vcodec_service.h"\r
  63 \r
  64 #define HEVC_TEST_ENABLE    0\r
  65 #define HEVC_SIM_ENABLE         0\r
  66 #define VCODEC_CLOCK_ENABLE 1\r
  67 \r
  68 typedef enum {\r
  69         VPU_DEC_ID_9190         = 0x6731,\r
  70         VPU_ID_8270             = 0x8270,\r
  71         VPU_ID_4831             = 0x4831,\r
  72     HEVC_ID         = 0x6867,\r
  73 } VPU_HW_ID;\r
  74 \r
  75 typedef enum {\r
  76         VPU_DEC_TYPE_9190       = 0,\r
  77         VPU_ENC_TYPE_8270       = 0x100,\r
  78         VPU_ENC_TYPE_4831       ,\r
  79 } VPU_HW_TYPE_E;\r
  80 \r
  81 typedef enum VPU_FREQ {\r
  82         VPU_FREQ_200M,\r
  83         VPU_FREQ_266M,\r
  84         VPU_FREQ_300M,\r
  85         VPU_FREQ_400M,\r
  86     VPU_FREQ_500M,\r
  87     VPU_FREQ_600M,\r
  88         VPU_FREQ_DEFAULT,\r
  89         VPU_FREQ_BUT,\r
  90 } VPU_FREQ;\r
  91 \r
  92 typedef struct {\r
  93         VPU_HW_ID               hw_id;\r
  94         unsigned long           hw_addr;\r
  95         unsigned long           enc_offset;\r
  96         unsigned long           enc_reg_num;\r
  97         unsigned long           enc_io_size;\r
  98         unsigned long           dec_offset;\r
  99         unsigned long           dec_reg_num;\r
 100         unsigned long           dec_io_size;\r
 101 } VPU_HW_INFO_E;\r
 102 \r
 103 #define VPU_SERVICE_SHOW_TIME                   0\r
 104 \r
 105 #if VPU_SERVICE_SHOW_TIME\r
 106 static struct timeval enc_start, enc_end;\r
 107 static struct timeval dec_start, dec_end;\r
 108 static struct timeval pp_start,  pp_end;\r
 109 #endif\r
 110 \r
 111 #define MHZ                                     (1000*1000)\r
 112 \r
 113 #define REG_NUM_9190_DEC                        (60)\r
 114 #define REG_NUM_9190_PP                         (41)\r
 115 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 116 \r
 117 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 118 \r
 119 #define REG_NUM_ENC_8270                        (96)\r
 120 #define REG_SIZE_ENC_8270                       (0x200)\r
 121 #define REG_NUM_ENC_4831                        (164)\r
 122 #define REG_SIZE_ENC_4831                       (0x400)\r
 123 \r
 124 #define REG_NUM_HEVC_DEC            (68)\r
 125 \r
 126 #define SIZE_REG(reg)                           ((reg)*4)\r
 127 \r
 128 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 129         [0] = {\r
 130                 .hw_id          = VPU_ID_8270,\r
 131                 .hw_addr        = 0,\r
 132                 .enc_offset     = 0x0,\r
 133                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 134                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 135                 .dec_offset     = REG_SIZE_ENC_8270,\r
 136                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 137                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 138         },\r
 139         [1] = {\r
 140                 .hw_id          = VPU_ID_4831,\r
 141                 .hw_addr        = 0,\r
 142                 .enc_offset     = 0x0,\r
 143                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 144                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 145                 .dec_offset     = REG_SIZE_ENC_4831,\r
 146                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 147                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 148         },\r
 149     [2] = {\r
 150         .hw_id      = HEVC_ID,\r
 151         .hw_addr    = 0,\r
 152         .dec_offset = 0x0,\r
 153         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 154         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 155     },\r
 156 };\r
 157 \r
 158 \r
 159 #define DEC_INTERRUPT_REGISTER                  1\r
 160 #define PP_INTERRUPT_REGISTER                   60\r
 161 #define ENC_INTERRUPT_REGISTER                  1\r
 162 \r
 163 #define DEC_INTERRUPT_BIT                       0x100\r
 164 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 165 #define PP_INTERRUPT_BIT                        0x100\r
 166 #define ENC_INTERRUPT_BIT                       0x1\r
 167 \r
 168 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 169 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 170 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 171 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 172 \r
 173 #define VPU_REG_EN_ENC                          14\r
 174 #define VPU_REG_ENC_GATE                        2\r
 175 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 176 \r
 177 #define VPU_REG_EN_DEC                          1\r
 178 #define VPU_REG_DEC_GATE                        2\r
 179 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 180 #define VPU_REG_EN_PP                           0\r
 181 #define VPU_REG_PP_GATE                         1\r
 182 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 183 #define VPU_REG_EN_DEC_PP                       1\r
 184 #define VPU_REG_DEC_PP_GATE                     61\r
 185 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 186 \r
 187 static u8 addr_tbl_vpu_dec[] = {\r
 188         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 189 };\r
 190 \r
 191 static u8 addr_tbl_vpu_enc[] = {\r
 192         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 193 };\r
 194 \r
 195 static u8 addr_tbl_hevc_dec[] = {\r
 196     4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
 197 };\r
 198 \r
 199 /**\r
 200  * struct for process session which connect to vpu\r
 201  *\r
 202  * @author ChenHengming (2011-5-3)\r
 203  */\r
 204 typedef struct vpu_session {\r
 205         VPU_CLIENT_TYPE         type;\r
 206         /* a linked list of data so we can access them for debugging */\r
 207         struct list_head        list_session;\r
 208         /* a linked list of register data waiting for process */\r
 209         struct list_head        waiting;\r
 210         /* a linked list of register data in processing */\r
 211         struct list_head        running;\r
 212         /* a linked list of register data processed */\r
 213         struct list_head        done;\r
 214         wait_queue_head_t       wait;\r
 215         pid_t                   pid;\r
 216         atomic_t                task_running;\r
 217 } vpu_session;\r
 218 \r
 219 /**\r
 220  * struct for process register set\r
 221  *\r
 222  * @author ChenHengming (2011-5-4)\r
 223  */\r
 224 typedef struct vpu_reg {\r
 225         VPU_CLIENT_TYPE         type;\r
 226         VPU_FREQ                    freq;\r
 227         vpu_session             *session;\r
 228         struct list_head        session_link;           /* link to vpu service session */\r
 229         struct list_head        status_link;            /* link to register set list */\r
 230         unsigned long           size;\r
 231 #if defined(CONFIG_VCODEC_MMU)    \r
 232     struct list_head    mem_region_list;\r
 233 #endif    \r
 234         unsigned long           *reg;\r
 235 } vpu_reg;\r
 236 \r
 237 typedef struct vpu_device {\r
 238         atomic_t                irq_count_codec;\r
 239         atomic_t                irq_count_pp;\r
 240         unsigned long           iobaseaddr;\r
 241         unsigned int            iosize;\r
 242         volatile u32            *hwregs;\r
 243 } vpu_device;\r
 244 \r
 245 enum vcodec_device_id {\r
 246         VCODEC_DEVICE_ID_VPU,\r
 247         VCODEC_DEVICE_ID_HEVC\r
 248 };\r
 249 \r
 250 struct vcodec_mem_region {\r
 251     struct list_head srv_lnk;\r
 252     struct list_head reg_lnk;\r
 253     struct list_head session_lnk;\r
 254     dma_addr_t       iova;              /* virtual address for iommu */\r
 255     struct dma_buf   *buf;\r
 256     struct dma_buf_attachment *attachment;\r
 257     struct sg_table *sg_table;\r
 258     struct ion_handle *hdl;\r
 259 };\r
 260 \r
 261 typedef struct vpu_service_info {\r
 262         struct wake_lock        wake_lock;\r
 263         struct delayed_work     power_off_work;\r
 264         struct mutex            lock;\r
 265         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 266         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 267         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 268         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 269         atomic_t                total_running;\r
 270         bool                    enabled;\r
 271         vpu_reg                 *reg_codec;\r
 272         vpu_reg                 *reg_pproc;\r
 273         vpu_reg                 *reg_resev;\r
 274         VPUHwDecConfig_t        dec_config;\r
 275         VPUHwEncConfig_t        enc_config;\r
 276         VPU_HW_INFO_E           *hw_info;\r
 277         unsigned long           reg_size;\r
 278         bool                    auto_freq;\r
 279         bool                    bug_dec_addr;\r
 280         atomic_t                freq_status;\r
 281 \r
 282     struct clk *aclk_vcodec;\r
 283     struct clk *hclk_vcodec;\r
 284     struct clk *clk_core;\r
 285     struct clk *clk_cabac;\r
 286 \r
 287     int irq_dec;\r
 288     int irq_enc;\r
 289 \r
 290     vpu_device enc_dev;\r
 291     vpu_device dec_dev;\r
 292 \r
 293     struct device   *dev;\r
 294 \r
 295     struct cdev     cdev;\r
 296     dev_t           dev_t;\r
 297     struct class    *cls;\r
 298     struct device   *child_dev;\r
 299 \r
 300     struct dentry   *debugfs_dir;\r
 301     struct dentry   *debugfs_file_regs;\r
 302 \r
 303     u32 irq_status;\r
 304 #if defined(CONFIG_ION_ROCKCHIP)        \r
 305         struct ion_client * ion_client;\r
 306 #endif  \r
 307 \r
 308 #if defined(CONFIG_VCODEC_MMU)\r
 309     struct list_head mem_region_list;\r
 310 #endif\r
 311 \r
 312         enum vcodec_device_id dev_id;\r
 313 \r
 314     struct delayed_work simulate_work;\r
 315 } vpu_service_info;\r
 316 \r
 317 typedef struct vpu_request\r
 318 {\r
 319         unsigned long   *req;\r
 320         unsigned long   size;\r
 321 } vpu_request;\r
 322 \r
 323 /// global variable\r
 324 //static struct clk *pd_video;\r
 325 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 326 \r
 327 #ifdef CONFIG_DEBUG_FS\r
 328 static int vcodec_debugfs_init(void);\r
 329 static void vcodec_debugfs_exit(void);\r
 330 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 331 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 332 \r
 333 static const struct file_operations debug_vcodec_fops = {\r
 334         .open = debug_vcodec_open,\r
 335         .read = seq_read,\r
 336         .llseek = seq_lseek,\r
 337         .release = single_release,\r
 338 };\r
 339 #endif\r
 340 \r
 341 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 342 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 343 \r
 344 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 345 \r
 346 static void vpu_get_clk(struct vpu_service_info *pservice)\r
 347 {\r
 348 #if VCODEC_CLOCK_ENABLE\r
 349         /*pd_video      = clk_get(NULL, "pd_video");\r
 350         if (IS_ERR(pd_video)) {\r
 351                 pr_err("failed on clk_get pd_video\n");\r
 352         }*/\r
 353 \r
 354         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 355         if (IS_ERR(pservice->aclk_vcodec)) {\r
 356                 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 357         }\r
 358 \r
 359         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 360         if (IS_ERR(pservice->hclk_vcodec)) {\r
 361                 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 362         }\r
 363 \r
 364         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 365                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 366                 if (IS_ERR(pservice->clk_core)) {\r
 367                         dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 368                 }\r
 369 \r
 370                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 371                 if (IS_ERR(pservice->clk_cabac)) {\r
 372                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 373                 }\r
 374         }\r
 375 #endif\r
 376 }\r
 377 \r
 378 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 379 {\r
 380 #if VCODEC_CLOCK_ENABLE\r
 381     //clk_put(pd_video);\r
 382 \r
 383     if (pservice->aclk_vcodec) {\r
 384         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 385     }\r
 386 \r
 387     if (pservice->hclk_vcodec) {\r
 388         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 389     }\r
 390 \r
 391     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 392         if (pservice->clk_core) {\r
 393             devm_clk_put(pservice->dev, pservice->clk_core);\r
 394         }\r
 395         \r
 396         if (pservice->clk_cabac) {\r
 397             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 398         }\r
 399     }\r
 400 #endif\r
 401 }\r
 402 \r
 403 static void vpu_reset(struct vpu_service_info *pservice)\r
 404 {\r
 405 #if defined(CONFIG_ARCH_RK29)\r
 406         clk_disable(aclk_ddr_vepu);\r
 407         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 408         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 409         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 410         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 411         mdelay(10);\r
 412         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 413         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 414         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 415         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 416         clk_enable(aclk_ddr_vepu);\r
 417 #elif defined(CONFIG_ARCH_RK30)\r
 418         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 419         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 420         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 421         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 422         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 423         mdelay(1);\r
 424         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 425         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 426         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 427         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 428         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 429 #endif\r
 430         pservice->reg_codec = NULL;\r
 431         pservice->reg_pproc = NULL;\r
 432         pservice->reg_resev = NULL;\r
 433 }\r
 434 \r
 435 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 436 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 437 {\r
 438         vpu_reg *reg, *n;\r
 439         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 440                 reg_deinit(pservice, reg);\r
 441         }\r
 442         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 443                 reg_deinit(pservice, reg);\r
 444         }\r
 445         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 446                 reg_deinit(pservice, reg);\r
 447         }\r
 448 }\r
 449 \r
 450 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 451 {\r
 452         int running;\r
 453         vpu_reg *reg, *reg_tmp;\r
 454         vpu_session *session, *session_tmp;\r
 455 \r
 456         running = atomic_read(&pservice->total_running);\r
 457         printk("total_running %d\n", running);\r
 458 \r
 459         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 460         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 461         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 462 \r
 463         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 464                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 465                 running = atomic_read(&session->task_running);\r
 466                 printk("task_running %d\n", running);\r
 467                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 468                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 469                 }\r
 470                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 471                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 472                 }\r
 473                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 474                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 475                 }\r
 476         }\r
 477 }\r
 478 \r
 479 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 480 {\r
 481         int total_running;\r
 482         if (!pservice->enabled) {\r
 483                 return;\r
 484         }\r
 485 \r
 486         pservice->enabled = false;\r
 487         total_running = atomic_read(&pservice->total_running);\r
 488         if (total_running) {\r
 489                 pr_alert("alert: power off when %d task running!!\n", total_running);\r
 490                 mdelay(50);\r
 491                 pr_alert("alert: delay 50 ms for running task\n");\r
 492                 vpu_service_dump(pservice);\r
 493         }\r
 494 \r
 495         printk("%s: power off...", dev_name(pservice->dev));\r
 496 #ifdef CONFIG_ARCH_RK29\r
 497         pmu_set_power_domain(PD_VCODEC, false);\r
 498 #else\r
 499         //clk_disable(pd_video);\r
 500 #endif\r
 501         udelay(10);\r
 502 #if VCODEC_CLOCK_ENABLE\r
 503         clk_disable_unprepare(pservice->hclk_vcodec);\r
 504         clk_disable_unprepare(pservice->aclk_vcodec);\r
 505     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 506         clk_disable_unprepare(pservice->clk_core);\r
 507         clk_disable_unprepare(pservice->clk_cabac);\r
 508     }\r
 509 #endif\r
 510         wake_unlock(&pservice->wake_lock);\r
 511         printk("done\n");\r
 512 }\r
 513 \r
 514 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 515 {\r
 516         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 517 }\r
 518 \r
 519 static void vpu_power_off_work(struct work_struct *work_s)\r
 520 {\r
 521     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 522     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 523 \r
 524         if (mutex_trylock(&pservice->lock)) {\r
 525                 vpu_service_power_off(pservice);\r
 526                 mutex_unlock(&pservice->lock);\r
 527         } else {\r
 528                 /* Come back later if the device is busy... */\r
 529                 vpu_queue_power_off_work(pservice);\r
 530         }\r
 531 }\r
 532 \r
 533 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 534 {\r
 535         static ktime_t last;\r
 536         ktime_t now = ktime_get();\r
 537         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 538                 cancel_delayed_work_sync(&pservice->power_off_work);\r
 539                 vpu_queue_power_off_work(pservice);\r
 540                 last = now;\r
 541         }\r
 542         if (pservice->enabled)\r
 543                 return ;\r
 544 \r
 545         pservice->enabled = true;\r
 546         printk("%s: power on\n", dev_name(pservice->dev));\r
 547 \r
 548 #if VCODEC_CLOCK_ENABLE\r
 549     clk_prepare_enable(pservice->aclk_vcodec);\r
 550         clk_prepare_enable(pservice->hclk_vcodec);\r
 551 \r
 552     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 553         clk_prepare_enable(pservice->clk_core);\r
 554         clk_prepare_enable(pservice->clk_cabac);\r
 555     }\r
 556 #endif\r
 557 \r
 558 #if defined(CONFIG_ARCH_RK319X)\r
 559     /// select aclk_vepu as vcodec clock source. \r
 560     #define BIT_VCODEC_SEL  (1<<7)\r
 561     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 562 #endif\r
 563         udelay(10);\r
 564 #ifdef CONFIG_ARCH_RK29\r
 565         pmu_set_power_domain(PD_VCODEC, true);\r
 566 #else\r
 567         //clk_enable(pd_video);\r
 568 #endif\r
 569         udelay(10);\r
 570         wake_lock(&pservice->wake_lock);\r
 571 }\r
 572 \r
 573 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 574 {\r
 575         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 576         return ((type == 8) || (type == 4));\r
 577 }\r
 578 \r
 579 static inline bool reg_check_interlace(vpu_reg *reg)\r
 580 {\r
 581         unsigned long type = (reg->reg[3] & (1 << 23));\r
 582         return (type > 0);\r
 583 }\r
 584 \r
 585 static inline bool reg_check_avc(vpu_reg *reg)\r
 586 {\r
 587         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 588         return (type == 0);\r
 589 }\r
 590 \r
 591 static inline int reg_probe_width(vpu_reg *reg)\r
 592 {\r
 593     int width_in_mb = reg->reg[4] >> 23;\r
 594     \r
 595     return width_in_mb * 16;\r
 596 }\r
 597 \r
 598 #if defined(CONFIG_VCODEC_MMU)\r
 599 \r
 600 static unsigned int vcodec_map_ion_handle(vpu_service_info *pservice, \r
 601                                           vpu_reg *reg,\r
 602                                           struct ion_handle *ion_handle,\r
 603                                           struct dma_buf *buf, int offset)\r
 604 {\r
 605     struct vcodec_mem_region *mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 606     if (mem_region == NULL) {\r
 607         dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 608         return -1;\r
 609     }\r
 610     \r
 611     mem_region->buf = buf;\r
 612     mem_region->hdl = ion_handle;\r
 613     \r
 614     mem_region->attachment = dma_buf_attach(buf, pservice->dev);\r
 615     if (IS_ERR_OR_NULL(mem_region->attachment)) {\r
 616         dev_err(pservice->dev, "dma_buf_attach() failed: %ld\n", PTR_ERR(mem_region->attachment));\r
 617         goto err_buf_map_attach;\r
 618     }\r
 619     \r
 620     mem_region->sg_table = dma_buf_map_attachment(mem_region->attachment, DMA_BIDIRECTIONAL);\r
 621     if (IS_ERR_OR_NULL(mem_region->sg_table)) {\r
 622         dev_err(pservice->dev, "dma_buf_map_attachment() failed: %ld\n", PTR_ERR(mem_region->sg_table));\r
 623         goto err_buf_map_attachment;\r
 624     }\r
 625     \r
 626     mem_region->iova = iovmm_map(pservice->dev, mem_region->sg_table->sgl, offset, buf->size);\r
 627     if (mem_region->iova == 0 || IS_ERR_VALUE(mem_region->iova)) {\r
 628         dev_err(pservice->dev, "iovmm_map() failed: %d\n", mem_region->iova);\r
 629         goto err_iovmm_map;\r
 630     }\r
 631     \r
 632     INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 633     list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 634     \r
 635     return mem_region->iova;\r
 636     \r
 637 err_iovmm_map:\r
 638         dma_buf_unmap_attachment(mem_region->attachment, mem_region->sg_table, DMA_BIDIRECTIONAL);\r
 639 err_buf_map_attachment:\r
 640         dma_buf_detach(buf, mem_region->attachment);\r
 641 err_buf_map_attach:\r
 642     kfree(mem_region);\r
 643         return 0;\r
 644 }\r
 645 \r
 646 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 647 {\r
 648         VPU_HW_ID hw_id;\r
 649         int i;\r
 650 \r
 651         hw_id = pservice->hw_info->hw_id;\r
 652 \r
 653     if (hw_id == HEVC_ID) {\r
 654 \r
 655     } else {\r
 656         if (reg->type == VPU_DEC) {\r
 657             for (i=0; i<sizeof(addr_tbl_vpu_dec); i++) {\r
 658                                 int usr_fd;\r
 659                                 struct ion_handle *hdl;\r
 660                                 //ion_phys_addr_t phy_addr;\r
 661                 struct dma_buf *buf;\r
 662                                 //size_t len;\r
 663                                 int offset;\r
 664 \r
 665 #if 0\r
 666                                 if (copy_from_user(&usr_fd, &reg->reg[addr_tbl_vpu_dec[i]], sizeof(usr_fd)))\r
 667                                         return -EFAULT;\r
 668 #else\r
 669                                 usr_fd = reg->reg[addr_tbl_vpu_dec[i]] & 0xFF;\r
 670                                 offset = reg->reg[addr_tbl_vpu_dec[i]] >> 8;\r
 671 #endif\r
 672                 if (usr_fd != 0) {\r
 673 \r
 674                                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 675                     if (IS_ERR(hdl)) {\r
 676                                                 pr_err("import dma-buf from fd %d failed\n", usr_fd);\r
 677                                                 return PTR_ERR(hdl);\r
 678                     }\r
 679 \r
 680 #if 0\r
 681                                         ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
 682 \r
 683                                         reg->reg[addr_tbl_vpu_dec[i]] = phy_addr + offset;\r
 684                     \r
 685                     ion_free(pservice->ion_client, hdl);\r
 686 #else \r
 687                     buf = ion_share_dma_buf(pservice->ion_client, hdl);\r
 688                     if (IS_ERR_OR_NULL(buf)) {\r
 689                         dev_err(pservice->dev, "ion_share_dma_buf() failed\n");\r
 690                         ion_free(pservice->ion_client, hdl);\r
 691                         return PTR_ERR(buf);\r
 692                     }\r
 693                     \r
 694                     reg->reg[addr_tbl_vpu_dec[i]] = vcodec_map_ion_handle(pservice, reg, hdl, buf, offset);\r
 695 #endif\r
 696                                         \r
 697                 }\r
 698             }\r
 699         } else if (reg->type == VPU_ENC) {\r
 700 \r
 701         }\r
 702         }\r
 703 \r
 704         return 0;\r
 705 }\r
 706 #endif\r
 707 \r
 708 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 709 {\r
 710         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 711         if (NULL == reg) {\r
 712                 pr_err("error: kmalloc fail in reg_init\n");\r
 713                 return NULL;\r
 714         }\r
 715 \r
 716         if (size > pservice->reg_size) {\r
 717                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 718                 size = pservice->reg_size;\r
 719         }\r
 720         reg->session = session;\r
 721         reg->type = session->type;\r
 722         reg->size = size;\r
 723         reg->freq = VPU_FREQ_DEFAULT;\r
 724         reg->reg = (unsigned long *)&reg[1];\r
 725         INIT_LIST_HEAD(&reg->session_link);\r
 726         INIT_LIST_HEAD(&reg->status_link);\r
 727 \r
 728 #if defined(CONFIG_VCODEC_MMU)    \r
 729     INIT_LIST_HEAD(&reg->mem_region_list);\r
 730 #endif    \r
 731 \r
 732         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 733                 pr_err("error: copy_from_user failed in reg_init\n");\r
 734                 kfree(reg);\r
 735                 return NULL;\r
 736         }\r
 737 \r
 738 #if defined(CONFIG_VCODEC_MMU)\r
 739     if (0 > vcodec_reg_address_translate(pservice, reg)) {\r
 740                 pr_err("error: translate reg address failed\n");\r
 741                 kfree(reg);\r
 742                 return NULL;\r
 743     }\r
 744 #endif\r
 745 \r
 746         mutex_lock(&pservice->lock);\r
 747         list_add_tail(&reg->status_link, &pservice->waiting);\r
 748         list_add_tail(&reg->session_link, &session->waiting);\r
 749         mutex_unlock(&pservice->lock);\r
 750 \r
 751         if (pservice->auto_freq) {\r
 752                 if (!soc_is_rk2928g()) {\r
 753                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 754                                 if (reg_check_rmvb_wmv(reg)) {\r
 755                                         reg->freq = VPU_FREQ_200M;\r
 756                                 } else if (reg_check_avc(reg)) {\r
 757                     if (reg_probe_width(reg) > 3200) {\r
 758                         // raise frequency for 4k avc.\r
 759                         reg->freq = VPU_FREQ_500M;\r
 760                     }\r
 761                 } else {\r
 762                                         if (reg_check_interlace(reg)) {\r
 763                                                 reg->freq = VPU_FREQ_400M;\r
 764                                         }\r
 765                                 }\r
 766                         }\r
 767                         if (reg->type == VPU_PP) {\r
 768                                 reg->freq = VPU_FREQ_400M;\r
 769                         }\r
 770                 }\r
 771         }\r
 772 \r
 773         return reg;\r
 774 }\r
 775 \r
 776 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 777 {\r
 778 #if defined(CONFIG_VCODEC_MMU)    \r
 779     struct vcodec_mem_region *mem_region = NULL, *n;\r
 780 #endif\r
 781     \r
 782         list_del_init(&reg->session_link);\r
 783         list_del_init(&reg->status_link);\r
 784         if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
 785         if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
 786     \r
 787 #if defined(CONFIG_VCODEC_MMU)\r
 788     // release memory region attach to this registers table.\r
 789     list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 790         iovmm_unmap(pservice->dev, mem_region->iova);\r
 791         \r
 792         dma_buf_unmap_attachment(mem_region->attachment, mem_region->sg_table, DMA_BIDIRECTIONAL);\r
 793         dma_buf_detach(mem_region->buf, mem_region->attachment);\r
 794         \r
 795         dma_buf_put(mem_region->buf);\r
 796         ion_free(pservice->ion_client, mem_region->hdl);\r
 797         \r
 798         list_del_init(&mem_region->reg_lnk);\r
 799         \r
 800         kfree(mem_region);\r
 801     }\r
 802 #endif    \r
 803     \r
 804     kfree(reg);\r
 805 }\r
 806 \r
 807 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 808 {\r
 809     list_del_init(&reg->status_link);\r
 810         list_add_tail(&reg->status_link, &pservice->running);\r
 811 \r
 812         list_del_init(&reg->session_link);\r
 813         list_add_tail(&reg->session_link, &reg->session->running);\r
 814 }\r
 815 \r
 816 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 817 {\r
 818         int i;\r
 819         u32 *dst = (u32 *)&reg->reg[0];\r
 820         for (i = 0; i < count; i++)\r
 821         *dst++ = *src++;\r
 822 }\r
 823 \r
 824 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 825 {\r
 826     int irq_reg = -1;\r
 827         list_del_init(&reg->status_link);\r
 828         list_add_tail(&reg->status_link, &pservice->done);\r
 829 \r
 830         list_del_init(&reg->session_link);\r
 831         list_add_tail(&reg->session_link, &reg->session->done);\r
 832 \r
 833         switch (reg->type) {\r
 834         case VPU_ENC : {\r
 835                 pservice->reg_codec = NULL;\r
 836                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 837                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 838                 break;\r
 839         }\r
 840         case VPU_DEC : {\r
 841         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 842                 pservice->reg_codec = NULL;\r
 843                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 844                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 845                 break;\r
 846         }\r
 847         case VPU_PP : {\r
 848                 pservice->reg_pproc = NULL;\r
 849                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 850                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 851                 break;\r
 852         }\r
 853         case VPU_DEC_PP : {\r
 854                 pservice->reg_codec = NULL;\r
 855                 pservice->reg_pproc = NULL;\r
 856                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 857                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 858                 break;\r
 859         }\r
 860         default : {\r
 861                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 862                 break;\r
 863         }\r
 864         }\r
 865 \r
 866     if (irq_reg != -1) {\r
 867         reg->reg[irq_reg] = pservice->irq_status;\r
 868     }\r
 869 \r
 870         atomic_sub(1, &reg->session->task_running);\r
 871         atomic_sub(1, &pservice->total_running);\r
 872         wake_up(&reg->session->wait);\r
 873 }\r
 874 \r
 875 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 876 {\r
 877         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 878         if (curr == reg->freq) {\r
 879                 return ;\r
 880         }\r
 881         atomic_set(&pservice->freq_status, reg->freq);\r
 882         switch (reg->freq) {\r
 883         case VPU_FREQ_200M : {\r
 884                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 885                 //printk("default: 200M\n");\r
 886         } break;\r
 887         case VPU_FREQ_266M : {\r
 888                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 889                 //printk("default: 266M\n");\r
 890         } break;\r
 891         case VPU_FREQ_300M : {\r
 892                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 893                 //printk("default: 300M\n");\r
 894         } break;\r
 895         case VPU_FREQ_400M : {\r
 896                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 897                 //printk("default: 400M\n");\r
 898         } break;\r
 899     case VPU_FREQ_500M : {\r
 900         clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
 901     } break;\r
 902     case VPU_FREQ_600M : {\r
 903         clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
 904     } break;\r
 905         default : {\r
 906                 if (soc_is_rk2928g()) {\r
 907                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 908                 } else {\r
 909                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 910                 }\r
 911                 //printk("default: 300M\n");\r
 912         } break;\r
 913         }\r
 914 }\r
 915 \r
 916 #if HEVC_SIM_ENABLE\r
 917 static void simulate_start(struct vpu_service_info *pservice);\r
 918 #endif\r
 919 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 920 {\r
 921         int i;\r
 922         u32 *src = (u32 *)&reg->reg[0];\r
 923         atomic_add(1, &pservice->total_running);\r
 924         atomic_add(1, &reg->session->task_running);\r
 925         if (pservice->auto_freq) {\r
 926                 vpu_service_set_freq(pservice, reg);\r
 927         }\r
 928         switch (reg->type) {\r
 929         case VPU_ENC : {\r
 930                 int enc_count = pservice->hw_info->enc_reg_num;\r
 931                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 932 #if 0\r
 933                 if (pservice->bug_dec_addr) {\r
 934 #if !defined(CONFIG_ARCH_RK319X)\r
 935                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 936 #endif\r
 937                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 938                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 939 #if !defined(CONFIG_ARCH_RK319X)\r
 940                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 941 #endif\r
 942                 }\r
 943 #endif\r
 944                 pservice->reg_codec = reg;\r
 945 \r
 946                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
 947 \r
 948                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
 949                         dst[i] = src[i];\r
 950 \r
 951                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
 952                         dst[i] = src[i];\r
 953 \r
 954                 dsb();\r
 955 \r
 956                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
 957                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
 958 \r
 959 #if VPU_SERVICE_SHOW_TIME\r
 960                 do_gettimeofday(&enc_start);\r
 961 #endif\r
 962 \r
 963         } break;\r
 964         case VPU_DEC : {\r
 965                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 966 \r
 967                 pservice->reg_codec = reg;\r
 968 \r
 969         if (pservice->hw_info->hw_id != HEVC_ID) {\r
 970                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
 971                                 dst[i] = src[i];\r
 972         } else {\r
 973             for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
 974                                 dst[i] = src[i];\r
 975             }\r
 976                 }\r
 977 \r
 978                 dsb();\r
 979 \r
 980                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
 981                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
 982                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
 983                 } else {\r
 984                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
 985                 }\r
 986 \r
 987         dsb();\r
 988         dmb();\r
 989 \r
 990 #if VPU_SERVICE_SHOW_TIME\r
 991                 do_gettimeofday(&dec_start);\r
 992 #endif\r
 993 \r
 994         } break;\r
 995         case VPU_PP : {\r
 996                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
 997                 pservice->reg_pproc = reg;\r
 998 \r
 999                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1000 \r
1001                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1002                         dst[i] = src[i];\r
1003 \r
1004                 dsb();\r
1005 \r
1006                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1007 \r
1008 #if VPU_SERVICE_SHOW_TIME\r
1009                 do_gettimeofday(&pp_start);\r
1010 #endif\r
1011 \r
1012         } break;\r
1013         case VPU_DEC_PP : {\r
1014                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1015                 pservice->reg_codec = reg;\r
1016                 pservice->reg_pproc = reg;\r
1017 \r
1018                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1019                         dst[i] = src[i];\r
1020 \r
1021                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1022                 dsb();\r
1023 \r
1024                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1025                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1026                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1027 \r
1028 #if VPU_SERVICE_SHOW_TIME\r
1029                 do_gettimeofday(&dec_start);\r
1030 #endif\r
1031 \r
1032         } break;\r
1033         default : {\r
1034                 pr_err("error: unsupport session type %d", reg->type);\r
1035                 atomic_sub(1, &pservice->total_running);\r
1036                 atomic_sub(1, &reg->session->task_running);\r
1037                 break;\r
1038         }\r
1039         }\r
1040 \r
1041 #if HEVC_SIM_ENABLE\r
1042     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1043         simulate_start(pservice);\r
1044     }\r
1045 #endif\r
1046 }\r
1047 \r
1048 static void try_set_reg(struct vpu_service_info *pservice)\r
1049 {\r
1050         // first get reg from reg list\r
1051         if (!list_empty(&pservice->waiting)) {\r
1052                 int can_set = 0;\r
1053                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1054 \r
1055                 vpu_service_power_on(pservice);\r
1056 \r
1057                 switch (reg->type) {\r
1058                 case VPU_ENC : {\r
1059                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1060                                 can_set = 1;\r
1061                 } break;\r
1062                 case VPU_DEC : {\r
1063                         if (NULL == pservice->reg_codec)\r
1064                                 can_set = 1;\r
1065                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1066                                 can_set = 0;\r
1067                         }\r
1068                 } break;\r
1069                 case VPU_PP : {\r
1070                         if (NULL == pservice->reg_codec) {\r
1071                                 if (NULL == pservice->reg_pproc)\r
1072                                         can_set = 1;\r
1073                         } else {\r
1074                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1075                                         can_set = 1;\r
1076                                 // can not charge frequency when vpu is working\r
1077                                 if (pservice->auto_freq) {\r
1078                                         can_set = 0;\r
1079                                 }\r
1080                         }\r
1081                 } break;\r
1082                 case VPU_DEC_PP : {\r
1083                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1084                                 can_set = 1;\r
1085                         } break;\r
1086                 default : {\r
1087                         printk("undefined reg type %d\n", reg->type);\r
1088                 } break;\r
1089                 }\r
1090                 if (can_set) {\r
1091                         reg_from_wait_to_run(pservice, reg);\r
1092                         reg_copy_to_hw(pservice, reg);\r
1093                 }\r
1094         }\r
1095 }\r
1096 \r
1097 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1098 {\r
1099         int ret = 0;\r
1100         switch (reg->type) {\r
1101         case VPU_ENC : {\r
1102                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1103                         ret = -EFAULT;\r
1104                 break;\r
1105         }\r
1106         case VPU_DEC : {\r
1107         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1108                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1109                         ret = -EFAULT;\r
1110                 break;\r
1111         }\r
1112         case VPU_PP : {\r
1113                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1114                         ret = -EFAULT;\r
1115                 break;\r
1116         }\r
1117         case VPU_DEC_PP : {\r
1118                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1119                         ret = -EFAULT;\r
1120                 break;\r
1121         }\r
1122         default : {\r
1123                 ret = -EFAULT;\r
1124                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1125                 break;\r
1126         }\r
1127         }\r
1128         reg_deinit(pservice, reg);\r
1129         return ret;\r
1130 }\r
1131 \r
1132 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1133 {\r
1134     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1135         vpu_session *session = (vpu_session *)filp->private_data;\r
1136         if (NULL == session) {\r
1137                 return -EINVAL;\r
1138         }\r
1139 \r
1140         switch (cmd) {\r
1141         case VPU_IOC_SET_CLIENT_TYPE : {\r
1142                 session->type = (VPU_CLIENT_TYPE)arg;\r
1143                 break;\r
1144         }\r
1145         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1146                 vpu_request req;\r
1147                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1148                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1149                         return -EFAULT;\r
1150                 } else {\r
1151                         if (VPU_ENC != session->type) {\r
1152                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1153                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1154                                         return -EFAULT;\r
1155                                 }\r
1156                         } else {\r
1157                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1158                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1159                                         return -EFAULT;\r
1160                                 }\r
1161                         }\r
1162                 }\r
1163 \r
1164                 break;\r
1165         }\r
1166         case VPU_IOC_SET_REG : {\r
1167                 vpu_request req;\r
1168                 vpu_reg *reg;\r
1169                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1170                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1171                         return -EFAULT;\r
1172                 }\r
1173                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1174                 if (NULL == reg) {\r
1175                         return -EFAULT;\r
1176                 } else {\r
1177                         mutex_lock(&pservice->lock);\r
1178                         try_set_reg(pservice);\r
1179                         mutex_unlock(&pservice->lock);\r
1180                 }\r
1181 \r
1182                 break;\r
1183         }\r
1184         case VPU_IOC_GET_REG : {\r
1185                 vpu_request req;\r
1186                 vpu_reg *reg;\r
1187                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1188                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1189                         return -EFAULT;\r
1190                 } else {\r
1191                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1192                         if (!list_empty(&session->done)) {\r
1193                                 if (ret < 0) {\r
1194                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1195                                 }\r
1196                                 ret = 0;\r
1197                         } else {\r
1198                                 if (unlikely(ret < 0)) {\r
1199                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1200                                 } else if (0 == ret) {\r
1201                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1202                                         ret = -ETIMEDOUT;\r
1203                                 }\r
1204                         }\r
1205                         if (ret < 0) {\r
1206                                 int task_running = atomic_read(&session->task_running);\r
1207                                 mutex_lock(&pservice->lock);\r
1208                                 vpu_service_dump(pservice);\r
1209                                 if (task_running) {\r
1210                                         atomic_set(&session->task_running, 0);\r
1211                                         atomic_sub(task_running, &pservice->total_running);\r
1212                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1213                                         vpu_reset(pservice);\r
1214                                         printk("done\n");\r
1215                                 }\r
1216                                 vpu_service_session_clear(pservice, session);\r
1217                                 mutex_unlock(&pservice->lock);\r
1218                                 return ret;\r
1219                         }\r
1220                 }\r
1221                 mutex_lock(&pservice->lock);\r
1222                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1223                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1224                 mutex_unlock(&pservice->lock);\r
1225                 break;\r
1226         }\r
1227         default : {\r
1228                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1229                 break;\r
1230         }\r
1231         }\r
1232 \r
1233         return 0;\r
1234 }\r
1235 \r
1236 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1237 {\r
1238         int ret = -EINVAL, i = 0;\r
1239         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1240         u32 enc_id = *tmp;\r
1241 \r
1242 #if HEVC_SIM_ENABLE\r
1243     /// temporary, hevc driver test.\r
1244     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1245         p->hw_info = &vpu_hw_set[2];\r
1246         return 0;\r
1247     }\r
1248 #endif\r
1249 \r
1250         enc_id = (enc_id >> 16) & 0xFFFF;\r
1251         pr_info("checking hw id %x\n", enc_id);\r
1252     p->hw_info = NULL;\r
1253         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1254                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1255                         p->hw_info = &vpu_hw_set[i];\r
1256                         ret = 0;\r
1257                         break;\r
1258                 }\r
1259         }\r
1260         iounmap((void *)tmp);\r
1261         return ret;\r
1262 }\r
1263 \r
1264 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1265 {\r
1266     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1267         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1268         if (NULL == session) {\r
1269                 pr_err("error: unable to allocate memory for vpu_session.");\r
1270                 return -ENOMEM;\r
1271         }\r
1272 \r
1273         session->type   = VPU_TYPE_BUTT;\r
1274         session->pid    = current->pid;\r
1275         INIT_LIST_HEAD(&session->waiting);\r
1276         INIT_LIST_HEAD(&session->running);\r
1277         INIT_LIST_HEAD(&session->done);\r
1278         INIT_LIST_HEAD(&session->list_session);\r
1279         init_waitqueue_head(&session->wait);\r
1280         atomic_set(&session->task_running, 0);\r
1281         mutex_lock(&pservice->lock);\r
1282         list_add_tail(&session->list_session, &pservice->session);\r
1283         filp->private_data = (void *)session;\r
1284         mutex_unlock(&pservice->lock);\r
1285 \r
1286         pr_debug("dev opened\n");\r
1287         return nonseekable_open(inode, filp);\r
1288 }\r
1289 \r
1290 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1291 {\r
1292     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1293         int task_running;\r
1294         vpu_session *session = (vpu_session *)filp->private_data;\r
1295         if (NULL == session)\r
1296                 return -EINVAL;\r
1297 \r
1298         task_running = atomic_read(&session->task_running);\r
1299         if (task_running) {\r
1300                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1301                 msleep(50);\r
1302         }\r
1303         wake_up(&session->wait);\r
1304 \r
1305         mutex_lock(&pservice->lock);\r
1306         /* remove this filp from the asynchronusly notified filp's */\r
1307         list_del_init(&session->list_session);\r
1308         vpu_service_session_clear(pservice, session);\r
1309         kfree(session);\r
1310         filp->private_data = NULL;\r
1311         mutex_unlock(&pservice->lock);\r
1312 \r
1313     pr_debug("dev closed\n");\r
1314         return 0;\r
1315 }\r
1316 \r
1317 static const struct file_operations vpu_service_fops = {\r
1318         .unlocked_ioctl = vpu_service_ioctl,\r
1319         .open           = vpu_service_open,\r
1320         .release        = vpu_service_release,\r
1321         //.fasync       = vpu_service_fasync,\r
1322 };\r
1323 \r
1324 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1325 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1326 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1327 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1328 static void get_hw_info(struct vpu_service_info *pservice);\r
1329 \r
1330 #if HEVC_SIM_ENABLE\r
1331 static void simulate_work(struct work_struct *work_s)\r
1332 {\r
1333     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1334     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1335     vpu_device *dev = &pservice->dec_dev;\r
1336 \r
1337     if (!list_empty(&pservice->running)) {\r
1338         atomic_add(1, &dev->irq_count_codec);\r
1339         vdpu_isr(0, (void*)pservice);\r
1340     } else {\r
1341         //simulate_start(pservice);\r
1342         pr_err("empty running queue\n");\r
1343     }\r
1344 }\r
1345 \r
1346 static void simulate_init(struct vpu_service_info *pservice)\r
1347 {\r
1348     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1349 }\r
1350 \r
1351 static void simulate_start(struct vpu_service_info *pservice)\r
1352 {\r
1353     cancel_delayed_work_sync(&pservice->power_off_work);\r
1354     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1355 }\r
1356 #endif\r
1357 \r
1358 #if HEVC_TEST_ENABLE\r
1359 static int hevc_test_case0(vpu_service_info *pservice);\r
1360 #endif\r
1361 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1362 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1363 #endif\r
1364 static int vcodec_probe(struct platform_device *pdev)\r
1365 {\r
1366     int ret = 0;\r
1367     struct resource *res = NULL;\r
1368     struct device *dev = &pdev->dev;\r
1369     void __iomem *regs = NULL;\r
1370     struct device_node *np = pdev->dev.of_node;\r
1371     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1372     char *prop = (char*)dev_name(dev);\r
1373 #if defined(CONFIG_VCODEC_MMU)\r
1374     struct device *mmu_dev = NULL;\r
1375     char mmu_dev_dts_name[40];\r
1376 #endif\r
1377 \r
1378     pr_info("probe device %s\n", dev_name(dev));\r
1379 \r
1380     of_property_read_string(np, "name", (const char**)&prop);\r
1381     dev_set_name(dev, prop);\r
1382 \r
1383     if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1384         pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1385     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1386         pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1387     } else {\r
1388         dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1389         return -1;\r
1390     }\r
1391 \r
1392     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1393     INIT_LIST_HEAD(&pservice->waiting);\r
1394     INIT_LIST_HEAD(&pservice->running);\r
1395     INIT_LIST_HEAD(&pservice->done);\r
1396     INIT_LIST_HEAD(&pservice->session);\r
1397     mutex_init(&pservice->lock);\r
1398     pservice->reg_codec = NULL;\r
1399     pservice->reg_pproc = NULL;\r
1400     atomic_set(&pservice->total_running, 0);\r
1401     pservice->enabled = false;\r
1402 \r
1403     pservice->dev = dev;\r
1404 \r
1405     vpu_get_clk(pservice);\r
1406 \r
1407     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1408 \r
1409     vpu_service_power_on(pservice);\r
1410 \r
1411     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1412 \r
1413     regs = devm_ioremap_resource(pservice->dev, res);\r
1414     if (IS_ERR(regs)) {\r
1415         ret = PTR_ERR(regs);\r
1416         goto err;\r
1417     }\r
1418 \r
1419     ret = vpu_service_check_hw(pservice, res->start);\r
1420     if (ret < 0) {\r
1421         pr_err("error: hw info check faild\n");\r
1422         goto err;\r
1423     }\r
1424 \r
1425     /// define regs address.\r
1426     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1427     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1428 \r
1429     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1430 \r
1431     pservice->reg_size   = pservice->dec_dev.iosize;\r
1432 \r
1433     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1434         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1435         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1436 \r
1437         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1438 \r
1439         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1440 \r
1441         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1442         if (pservice->irq_enc < 0) {\r
1443             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1444             ret = -ENXIO;\r
1445             goto err;\r
1446         }\r
1447 \r
1448         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1449         if (ret) {\r
1450             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1451             goto err;\r
1452         }\r
1453     }\r
1454 \r
1455     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1456     if (pservice->irq_dec < 0) {\r
1457         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1458         ret = -ENXIO;\r
1459         goto err;\r
1460     }\r
1461 \r
1462     /* get the IRQ line */\r
1463     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1464     if (ret) {\r
1465         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1466         goto err;\r
1467     }\r
1468 \r
1469     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1470     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1471     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1472     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1473 \r
1474     /// create device\r
1475     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1476     if (ret) {\r
1477         dev_err(dev, "alloc dev_t failed\n");\r
1478         goto err;\r
1479     }\r
1480 \r
1481     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1482 \r
1483     pservice->cdev.owner = THIS_MODULE;\r
1484     pservice->cdev.ops = &vpu_service_fops;\r
1485 \r
1486     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1487 \r
1488     if (ret) {\r
1489         dev_err(dev, "add dev_t failed\n");\r
1490         goto err;\r
1491     }\r
1492 \r
1493     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1494 \r
1495     if (IS_ERR(pservice->cls)) {\r
1496         ret = PTR_ERR(pservice->cls);\r
1497         dev_err(dev, "class_create err:%d\n", ret);\r
1498         goto err;\r
1499     }\r
1500 \r
1501     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1502 \r
1503     platform_set_drvdata(pdev, pservice);\r
1504 \r
1505     get_hw_info(pservice);\r
1506 \r
1507 \r
1508 #ifdef CONFIG_DEBUG_FS\r
1509     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1510     \r
1511     if (pservice->debugfs_dir == NULL) {\r
1512         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1513     }\r
1514 \r
1515     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1516                     pservice->debugfs_dir, pservice,\r
1517                     &debug_vcodec_fops);\r
1518 #endif\r
1519 \r
1520     vpu_service_power_off(pservice);\r
1521     pr_info("init success\n");\r
1522 \r
1523 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1524     pservice->ion_client = rockchip_ion_client_create("vpu");\r
1525     if (IS_ERR(pservice->ion_client)) {\r
1526         dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1527         return PTR_ERR(pservice->ion_client);\r
1528     } else {\r
1529         dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1530     }\r
1531     \r
1532     sprintf(mmu_dev_dts_name, "iommu,%s", dev_name(dev));\r
1533     \r
1534     mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1535     platform_set_sysmmu(mmu_dev, pservice->dev);\r
1536     \r
1537     iovmm_activate(pservice->dev);\r
1538 #endif\r
1539 \r
1540 #if HEVC_SIM_ENABLE\r
1541     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1542         simulate_init(pservice);\r
1543     }\r
1544 #endif\r
1545 \r
1546 #if HEVC_TEST_ENABLE\r
1547     hevc_test_case0(pservice);\r
1548 #endif\r
1549 \r
1550     return 0;\r
1551 \r
1552 err:\r
1553     pr_info("init failed\n");\r
1554     vpu_service_power_off(pservice);\r
1555     vpu_put_clk(pservice);\r
1556     wake_lock_destroy(&pservice->wake_lock);\r
1557 \r
1558     if (res) {\r
1559         if (regs) {\r
1560             devm_ioremap_release(&pdev->dev, res);\r
1561         }\r
1562         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1563     }\r
1564 \r
1565     if (pservice->irq_enc > 0) {\r
1566         free_irq(pservice->irq_enc, (void *)pservice);\r
1567     }\r
1568 \r
1569     if (pservice->irq_dec > 0) {\r
1570         free_irq(pservice->irq_dec, (void *)pservice);\r
1571     }\r
1572 \r
1573     if (pservice->child_dev) {\r
1574         device_destroy(pservice->cls, pservice->dev_t);\r
1575         cdev_del(&pservice->cdev);\r
1576         unregister_chrdev_region(pservice->dev_t, 1);\r
1577     }\r
1578 \r
1579     if (pservice->cls) {\r
1580         class_destroy(pservice->cls);\r
1581     }\r
1582 \r
1583     return ret;\r
1584 }\r
1585 \r
1586 static int vcodec_remove(struct platform_device *pdev)\r
1587 {\r
1588     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1589     struct resource *res;\r
1590 \r
1591     device_destroy(pservice->cls, pservice->dev_t);\r
1592     class_destroy(pservice->cls);\r
1593     cdev_del(&pservice->cdev);\r
1594     unregister_chrdev_region(pservice->dev_t, 1);\r
1595 \r
1596     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1597     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1598     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1599     devm_ioremap_release(&pdev->dev, res);\r
1600     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1601     vpu_put_clk(pservice);\r
1602     wake_lock_destroy(&pservice->wake_lock);\r
1603     \r
1604 #ifdef CONFIG_DEBUG_FS\r
1605     if (pservice->debugfs_file_regs) {\r
1606         debugfs_remove(pservice->debugfs_file_regs);\r
1607     }\r
1608 \r
1609     if (pservice->debugfs_dir) {\r
1610         debugfs_remove(pservice->debugfs_dir);\r
1611     }\r
1612 #endif\r
1613 \r
1614     return 0;\r
1615 }\r
1616 \r
1617 #if defined(CONFIG_OF)\r
1618 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1619     {.compatible = "vpu_service",},\r
1620     {.compatible = "rockchip,hevc_service",},\r
1621     {},\r
1622 };\r
1623 #endif\r
1624 \r
1625 static struct platform_driver vcodec_driver = {\r
1626     .probe     = vcodec_probe,\r
1627     .remove        = vcodec_remove,\r
1628     .driver = {\r
1629         .name = "vcodec",\r
1630         .owner = THIS_MODULE,\r
1631 #if defined(CONFIG_OF)\r
1632         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1633 #endif\r
1634     },\r
1635 };\r
1636 \r
1637 static void get_hw_info(struct vpu_service_info *pservice)\r
1638 {\r
1639     VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1640     VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1641 \r
1642     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {             \r
1643         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1644         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1645     \r
1646         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1647         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1648         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1649             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1650         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1651         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1652         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1653         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1654         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1655         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1656     \r
1657         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1658             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1659         } else {\r
1660             dec->maxDecPicWidth = 4096;\r
1661         }\r
1662     \r
1663         /* 2nd Config register */\r
1664         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1665         if (dec->refBufSupport) {\r
1666             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1667                 dec->refBufSupport |= 2;\r
1668             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1669                 dec->refBufSupport |= 4;\r
1670         }\r
1671         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1672         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1673         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1674         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1675     \r
1676         /* JPEG xtensions */\r
1677         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1678             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1679         } else {\r
1680             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1681         }\r
1682     \r
1683         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1684             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1685         } else {\r
1686             dec->rvSupport = RV_NOT_SUPPORTED;\r
1687         }\r
1688     \r
1689         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1690     \r
1691         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1692             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1693         }\r
1694     \r
1695         /// invalidate fuse register value in rk319x vpu and following.\r
1696         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1697             VPUHwFuseStatus_t hwFuseSts;\r
1698             /* Decoder fuse configuration */\r
1699             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1700     \r
1701             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1702             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1703             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1704             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1705             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1706             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1707             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1708             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1709             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1710             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1711             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1712             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1713             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1714             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1715     \r
1716             /* check max. decoder output width */\r
1717     \r
1718             if (fuseReg & 0x8000U)\r
1719                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1720             else if (fuseReg & 0x4000U)\r
1721                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1722             else if (fuseReg & 0x2000U)\r
1723                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1724             else if (fuseReg & 0x1000U)\r
1725                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1726             else    /* remove warning */\r
1727                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1728     \r
1729             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1730     \r
1731             /* Pp configuration */\r
1732             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1733     \r
1734             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1735                 dec->ppSupport = 1;\r
1736                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1737                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1738                 dec->ppConfig = configReg;\r
1739             } else {\r
1740                 dec->ppSupport = 0;\r
1741                 dec->maxPpOutPicWidth = 0;\r
1742                 dec->ppConfig = 0;\r
1743             }\r
1744     \r
1745             /* check the HW versio */\r
1746             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1747                 /* Pp configuration */\r
1748                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1749     \r
1750                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1751                     /* Pp fuse configuration */\r
1752                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1753     \r
1754                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1755                         hwFuseSts.ppSupportFuse = 1;\r
1756                         /* check max. pp output width */\r
1757                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1758                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1759                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1760                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1761                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1762                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1763                     } else {\r
1764                         hwFuseSts.ppSupportFuse = 0;\r
1765                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1766                         hwFuseSts.ppConfigFuse = 0;\r
1767                     }\r
1768                 } else {\r
1769                     hwFuseSts.ppSupportFuse = 0;\r
1770                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1771                     hwFuseSts.ppConfigFuse = 0;\r
1772                 }\r
1773     \r
1774                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1775                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1776                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1777                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1778                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1779                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1780                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1781                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1782                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1783                     dec->jpegSupport = JPEG_BASELINE;\r
1784                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1785                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1786                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1787                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1788                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1789                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1790     \r
1791                 /* check the pp config vs fuse status */\r
1792                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1793                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1794                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1795                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1796                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1797     \r
1798                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1799                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1800                 }\r
1801                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1802                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1803                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1804                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1805                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1806             }\r
1807         }\r
1808     \r
1809         configReg = pservice->enc_dev.hwregs[63];\r
1810         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1811         enc->h264Enabled = (configReg >> 27) & 1;\r
1812         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1813         enc->jpegEnabled = (configReg >> 25) & 1;\r
1814         enc->vsEnabled = (configReg >> 24) & 1;\r
1815         enc->rgbEnabled = (configReg >> 28) & 1;\r
1816         //enc->busType = (configReg >> 20) & 15;\r
1817         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1818         //enc->busWidth = (configReg >> 12) & 15;\r
1819         enc->reg_size = pservice->reg_size;\r
1820         enc->reserv[0] = enc->reserv[1] = 0;\r
1821     \r
1822         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
1823         if (pservice->auto_freq) {\r
1824             pr_info("vpu_service set to auto frequency mode\n");\r
1825             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1826         }\r
1827         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1828         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1829     } else {\r
1830         // disable frequency switch in hevc.\r
1831         pservice->auto_freq = false;\r
1832     }\r
1833 }\r
1834 \r
1835 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1836 {\r
1837     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1838     vpu_device *dev = &pservice->dec_dev;\r
1839     u32 raw_status;\r
1840     u32 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1841 \r
1842         pr_debug("dec_irq\n");\r
1843 \r
1844         if (irq_status & DEC_INTERRUPT_BIT) {\r
1845                 pr_debug("dec_isr dec %x\n", irq_status);\r
1846                 if ((irq_status & 0x40001) == 0x40001)\r
1847                 {\r
1848                         do {\r
1849                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1850                         } while ((irq_status & 0x40001) == 0x40001);\r
1851                 }\r
1852 \r
1853                 /* clear dec IRQ */\r
1854         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1855             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1856         } else {\r
1857             /*writel(irq_status \r
1858               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1859                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1860 \r
1861             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1862         }\r
1863                 atomic_add(1, &dev->irq_count_codec);\r
1864         }\r
1865 \r
1866     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1867         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1868         if (irq_status & PP_INTERRUPT_BIT) {\r
1869             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1870             /* clear pp IRQ */\r
1871             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1872             atomic_add(1, &dev->irq_count_pp);\r
1873         }\r
1874     }\r
1875 \r
1876     pservice->irq_status = raw_status;\r
1877 \r
1878         return IRQ_WAKE_THREAD;\r
1879 }\r
1880 \r
1881 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1882 {\r
1883     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1884     vpu_device *dev = &pservice->dec_dev;\r
1885 \r
1886         mutex_lock(&pservice->lock);\r
1887         if (atomic_read(&dev->irq_count_codec)) {\r
1888 #if VPU_SERVICE_SHOW_TIME\r
1889                 do_gettimeofday(&dec_end);\r
1890                 pr_info("dec task: %ld ms\n",\r
1891                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1892                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1893 #endif\r
1894                 atomic_sub(1, &dev->irq_count_codec);\r
1895                 if (NULL == pservice->reg_codec) {\r
1896                         pr_err("error: dec isr with no task waiting\n");\r
1897                 } else {\r
1898                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1899                 }\r
1900         }\r
1901 \r
1902         if (atomic_read(&dev->irq_count_pp)) {\r
1903 \r
1904 #if VPU_SERVICE_SHOW_TIME\r
1905                 do_gettimeofday(&pp_end);\r
1906                 printk("pp  task: %ld ms\n",\r
1907                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1908                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1909 #endif\r
1910 \r
1911                 atomic_sub(1, &dev->irq_count_pp);\r
1912                 if (NULL == pservice->reg_pproc) {\r
1913                         pr_err("error: pp isr with no task waiting\n");\r
1914                 } else {\r
1915                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1916                 }\r
1917         }\r
1918         try_set_reg(pservice);\r
1919         mutex_unlock(&pservice->lock);\r
1920         return IRQ_HANDLED;\r
1921 }\r
1922 \r
1923 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1924 {\r
1925         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1926     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1927     vpu_device *dev = &pservice->enc_dev;\r
1928         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1929 \r
1930         pr_debug("vepu_irq irq status %x\n", irq_status);\r
1931 \r
1932 #if VPU_SERVICE_SHOW_TIME\r
1933         do_gettimeofday(&enc_end);\r
1934         pr_info("enc task: %ld ms\n",\r
1935                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
1936                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
1937 #endif\r
1938     \r
1939         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
1940                 /* clear enc IRQ */\r
1941                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1942                 atomic_add(1, &dev->irq_count_codec);\r
1943         }\r
1944     \r
1945     pservice->irq_status = irq_status;\r
1946 \r
1947         return IRQ_WAKE_THREAD;\r
1948 }\r
1949 \r
1950 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
1951 {\r
1952         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1953     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1954     vpu_device *dev = &pservice->enc_dev;\r
1955 \r
1956         mutex_lock(&pservice->lock);\r
1957         if (atomic_read(&dev->irq_count_codec)) {\r
1958                 atomic_sub(1, &dev->irq_count_codec);\r
1959                 if (NULL == pservice->reg_codec) {\r
1960                         pr_err("error: enc isr with no task waiting\n");\r
1961                 } else {\r
1962                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1963                 }\r
1964         }\r
1965         try_set_reg(pservice);\r
1966         mutex_unlock(&pservice->lock);\r
1967         return IRQ_HANDLED;\r
1968 }\r
1969 \r
1970 static int __init vcodec_service_init(void)\r
1971 {\r
1972     int ret;\r
1973 \r
1974     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
1975         pr_err("Platform device register failed (%d).\n", ret);\r
1976         return ret;\r
1977     }\r
1978 \r
1979 #ifdef CONFIG_DEBUG_FS\r
1980     vcodec_debugfs_init();\r
1981 #endif\r
1982 \r
1983     return ret;\r
1984 }\r
1985 \r
1986 static void __exit vcodec_service_exit(void)\r
1987 {\r
1988 #ifdef CONFIG_DEBUG_FS\r
1989     vcodec_debugfs_exit();\r
1990 #endif\r
1991 \r
1992         platform_driver_unregister(&vcodec_driver);\r
1993 }\r
1994 \r
1995 module_init(vcodec_service_init);\r
1996 module_exit(vcodec_service_exit);\r
1997 \r
1998 #ifdef CONFIG_DEBUG_FS\r
1999 #include <linux/seq_file.h>\r
2000 \r
2001 static int vcodec_debugfs_init()\r
2002 {\r
2003     parent = debugfs_create_dir("vcodec", NULL);\r
2004     if (!parent)\r
2005         return -1;\r
2006 \r
2007     return 0;\r
2008 }\r
2009 \r
2010 static void vcodec_debugfs_exit()\r
2011 {\r
2012     debugfs_remove(parent);\r
2013 }\r
2014 \r
2015 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2016 {\r
2017     return debugfs_create_dir(dirname, parent);\r
2018 }\r
2019 \r
2020 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2021 {\r
2022         struct vpu_service_info *pservice = s->private;\r
2023     unsigned int i, n;\r
2024         vpu_reg *reg, *reg_tmp;\r
2025         vpu_session *session, *session_tmp;\r
2026 \r
2027         mutex_lock(&pservice->lock);\r
2028         vpu_service_power_on(pservice);\r
2029     if (pservice->hw_info->hw_id != HEVC_ID) {\r
2030         seq_printf(s, "\nENC Registers:\n");\r
2031         n = pservice->enc_dev.iosize >> 2;\r
2032         for (i = 0; i < n; i++) {\r
2033             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2034         }\r
2035     }\r
2036         seq_printf(s, "\nDEC Registers:\n");\r
2037         n = pservice->dec_dev.iosize >> 2;\r
2038         for (i = 0; i < n; i++) {\r
2039                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2040         }\r
2041 \r
2042         seq_printf(s, "\nvpu service status:\n");\r
2043         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2044                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2045                 //seq_printf(s, "waiting reg set %d\n");\r
2046                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2047                         seq_printf(s, "waiting register set\n");\r
2048                 }\r
2049                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2050                         seq_printf(s, "running register set\n");\r
2051                 }\r
2052                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2053                         seq_printf(s, "done    register set\n");\r
2054                 }\r
2055         }\r
2056         mutex_unlock(&pservice->lock);\r
2057 \r
2058     return 0;\r
2059 }\r
2060 \r
2061 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2062 {\r
2063         return single_open(file, debug_vcodec_show, inode->i_private);\r
2064 }\r
2065 \r
2066 #endif\r
2067 \r
2068 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2069 #include "hevc_test_inc/pps_00.h"\r
2070 #include "hevc_test_inc/register_00.h"\r
2071 #include "hevc_test_inc/rps_00.h"\r
2072 #include "hevc_test_inc/scaling_list_00.h"\r
2073 #include "hevc_test_inc/stream_00.h"\r
2074 \r
2075 #include "hevc_test_inc/pps_01.h"\r
2076 #include "hevc_test_inc/register_01.h"\r
2077 #include "hevc_test_inc/rps_01.h"\r
2078 #include "hevc_test_inc/scaling_list_01.h"\r
2079 #include "hevc_test_inc/stream_01.h"\r
2080 \r
2081 #include "hevc_test_inc/cabac.h"\r
2082 \r
2083 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2084 \r
2085 static struct ion_client *ion_client = NULL;\r
2086 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2087 {\r
2088         int size = (len+15) & (~15);\r
2089     struct ion_handle *handle;\r
2090         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2091 \r
2092     if (ion_client == NULL) {\r
2093         ion_client = rockchip_ion_client_create("vcodec");\r
2094     }\r
2095 \r
2096     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2097 \r
2098     ptr = ion_map_kernel(ion_client, handle);\r
2099 \r
2100     ion_phys(ion_client, handle, phy, &size);\r
2101 \r
2102         memcpy(ptr, tbl, len);\r
2103 \r
2104         return ptr;\r
2105 }\r
2106 \r
2107 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2108 {\r
2109         int size = (len+15) & (~15);\r
2110     struct ion_handle *handle;\r
2111         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2112 \r
2113     if (ion_client == NULL) {\r
2114         ion_client = rockchip_ion_client_create("vcodec");\r
2115     }\r
2116 \r
2117     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2118 \r
2119     ptr = ion_map_kernel(ion_client, handle);\r
2120 \r
2121     ion_phys(ion_client, handle, phy, &size);\r
2122 \r
2123         return ptr;\r
2124 }\r
2125 \r
2126 #define TEST_CNT    2\r
2127 static int hevc_test_case0(vpu_service_info *pservice)\r
2128 {\r
2129     vpu_session session;\r
2130     vpu_reg *reg; \r
2131     unsigned long size = 272;//sizeof(register_00); // registers array length\r
2132     int testidx = 0;\r
2133     int ret = 0;\r
2134 \r
2135     u8 *pps_tbl[TEST_CNT];\r
2136     u8 *register_tbl[TEST_CNT];\r
2137     u8 *rps_tbl[TEST_CNT];\r
2138     u8 *scaling_list_tbl[TEST_CNT];\r
2139     u8 *stream_tbl[TEST_CNT];\r
2140 \r
2141         int stream_size[2];\r
2142         int pps_size[2];\r
2143         int rps_size[2];\r
2144         int scl_size[2];\r
2145         int cabac_size[2];\r
2146         \r
2147     u32 phy_pps;\r
2148     u32 phy_rps;\r
2149     u32 phy_scl;\r
2150     u32 phy_str;\r
2151     u32 phy_yuv;\r
2152     u32 phy_ref;\r
2153     u32 phy_cabac;\r
2154 \r
2155         volatile u8 *stream_buf;\r
2156         volatile u8 *pps_buf;\r
2157         volatile u8 *rps_buf;\r
2158         volatile u8 *scl_buf;\r
2159         volatile u8 *yuv_buf;\r
2160         volatile u8 *cabac_buf;\r
2161         volatile u8 *ref_buf;\r
2162 \r
2163     u8 *pps;\r
2164     u8 *yuv[2];\r
2165     int i;\r
2166     \r
2167     pps_tbl[0] = pps_00;\r
2168     pps_tbl[1] = pps_01;\r
2169 \r
2170     register_tbl[0] = register_00;\r
2171     register_tbl[1] = register_01;\r
2172     \r
2173     rps_tbl[0] = rps_00;\r
2174     rps_tbl[1] = rps_01;\r
2175     \r
2176     scaling_list_tbl[0] = scaling_list_00;\r
2177     scaling_list_tbl[1] = scaling_list_01;\r
2178 \r
2179     stream_tbl[0] = stream_00;\r
2180     stream_tbl[1] = stream_01;\r
2181 \r
2182     stream_size[0] = sizeof(stream_00);\r
2183     stream_size[1] = sizeof(stream_01);\r
2184 \r
2185         pps_size[0] = sizeof(pps_00);\r
2186         pps_size[1] = sizeof(pps_01);\r
2187 \r
2188         rps_size[0] = sizeof(rps_00);\r
2189         rps_size[1] = sizeof(rps_01);\r
2190 \r
2191         scl_size[0] = sizeof(scaling_list_00);\r
2192         scl_size[1] = sizeof(scaling_list_01);\r
2193         \r
2194         cabac_size[0] = sizeof(Cabac_table);\r
2195         cabac_size[1] = sizeof(Cabac_table);\r
2196 \r
2197     // create session\r
2198     session.pid = current->pid;\r
2199     session.type = VPU_DEC;\r
2200     INIT_LIST_HEAD(&session.waiting);\r
2201         INIT_LIST_HEAD(&session.running);\r
2202         INIT_LIST_HEAD(&session.done);\r
2203         INIT_LIST_HEAD(&session.list_session);\r
2204         init_waitqueue_head(&session.wait);\r
2205         atomic_set(&session.task_running, 0);\r
2206         list_add_tail(&session.list_session, &pservice->session);\r
2207 \r
2208     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2209     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2210 \r
2211         while (testidx < TEST_CNT) {\r
2212         \r
2213         // create registers\r
2214         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2215         if (NULL == reg) {\r
2216             pr_err("error: kmalloc fail in reg_init\n");\r
2217             return -1;\r
2218         }\r
2219 \r
2220 \r
2221         if (size > pservice->reg_size) {\r
2222             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2223             size = pservice->reg_size;\r
2224         }\r
2225         reg->session = &session;\r
2226         reg->type = session.type;\r
2227         reg->size = size;\r
2228         reg->freq = VPU_FREQ_DEFAULT;\r
2229         reg->reg = (unsigned long *)&reg[1];\r
2230         INIT_LIST_HEAD(&reg->session_link);\r
2231         INIT_LIST_HEAD(&reg->status_link);\r
2232 \r
2233         // TODO: stuff registers\r
2234         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2235 \r
2236                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2237                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2238                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2239                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2240                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2241 \r
2242                 pps = pps_buf;\r
2243 \r
2244         // TODO: replace reigster address\r
2245 \r
2246         for (i=0; i<64; i++) {\r
2247             u32 scaling_offset;\r
2248             u32 tmp;\r
2249 \r
2250             scaling_offset = (u32)pps[i*80+74];\r
2251             scaling_offset += (u32)pps[i*80+75] << 8;\r
2252             scaling_offset += (u32)pps[i*80+76] << 16;\r
2253             scaling_offset += (u32)pps[i*80+77] << 24;\r
2254 \r
2255             tmp = phy_scl + scaling_offset;\r
2256 \r
2257             pps[i*80+74] = tmp & 0xff;\r
2258             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2259             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2260             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2261         }\r
2262 \r
2263         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2264 \r
2265         reg->reg[1] = 0x21;\r
2266         reg->reg[4] = phy_str;\r
2267         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2268         reg->reg[6] = phy_cabac;\r
2269         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2270         reg->reg[42] = phy_pps;\r
2271         reg->reg[43] = phy_rps;\r
2272         for (i = 10; i <= 24; i++) {\r
2273             reg->reg[i] = phy_yuv;\r
2274         }\r
2275 \r
2276         mutex_lock(&pservice->lock);\r
2277         list_add_tail(&reg->status_link, &pservice->waiting);\r
2278         list_add_tail(&reg->session_link, &session.waiting);\r
2279         mutex_unlock(&pservice->lock);\r
2280 \r
2281         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2282 \r
2283         // stuff hardware\r
2284         try_set_reg(pservice);\r
2285 \r
2286         // wait for result\r
2287         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2288         if (!list_empty(&session.done)) {\r
2289             if (ret < 0) {\r
2290                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2291             }\r
2292             ret = 0;\r
2293         } else {\r
2294             if (unlikely(ret < 0)) {\r
2295                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2296             } else if (0 == ret) {\r
2297                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2298                 ret = -ETIMEDOUT;\r
2299             }\r
2300         }\r
2301         if (ret < 0) {\r
2302             int task_running = atomic_read(&session.task_running);\r
2303             int n;\r
2304             mutex_lock(&pservice->lock);\r
2305             vpu_service_dump(pservice);\r
2306             if (task_running) {\r
2307                 atomic_set(&session.task_running, 0);\r
2308                 atomic_sub(task_running, &pservice->total_running);\r
2309                 printk("%d task is running but not return, reset hardware...", task_running);\r
2310                 vpu_reset(pservice);\r
2311                 printk("done\n");\r
2312             }\r
2313             vpu_service_session_clear(pservice, &session);\r
2314             mutex_unlock(&pservice->lock);\r
2315 \r
2316             printk("\nDEC Registers:\n");\r
2317                 n = pservice->dec_dev.iosize >> 2;\r
2318                 for (i=0; i<n; i++) {\r
2319                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2320                 }\r
2321 \r
2322             pr_err("test index %d failed\n", testidx);\r
2323             break;\r
2324         } else {\r
2325             pr_info("test index %d success\n", testidx);\r
2326 \r
2327             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2328 \r
2329             for (i=0; i<68; i++) {\r
2330                 if (i % 4 == 0) {\r
2331                     printk("%02d: ", i);\r
2332                 }\r
2333                 printk("%08x ", reg->reg[i]);\r
2334                 if ((i+1) % 4 == 0) {\r
2335                     printk("\n");\r
2336                 }\r
2337             }\r
2338 \r
2339             testidx++;\r
2340         }\r
2341 \r
2342         reg_deinit(pservice, reg);\r
2343     }\r
2344 \r
2345     return 0;\r
2346 }\r
2347 \r
2348 #endif\r
2349 \r