arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/clk.h>
  20 #include <linux/compat.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/fs.h>
  28 #include <linux/ioport.h>
  29 #include <linux/miscdevice.h>
  30 #include <linux/mm.h>
  31 #include <linux/poll.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/reset.h>
  34 #include <linux/sched.h>
  35 #include <linux/slab.h>
  36 #include <linux/wakelock.h>
  37 #include <linux/cdev.h>
  38 #include <linux/of.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/of_irq.h>
  41 #include <linux/rockchip/cpu.h>
  42 #include <linux/rockchip/cru.h>
  43 #include <linux/rockchip/pmu.h>
  44 #ifdef CONFIG_MFD_SYSCON
  45 #include <linux/regmap.h>
  46 #endif
  47 #include <linux/mfd/syscon.h>
  48
  49 #include <asm/cacheflush.h>
  50 #include <linux/uaccess.h>
  51 #include <linux/rockchip/grf.h>
  52
  53 #if defined(CONFIG_ION_ROCKCHIP)
  54 #include <linux/rockchip_ion.h>
  55 #endif
  56
  57 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  58 #define CONFIG_VCODEC_MMU
  59 #endif
  60
  61 #ifdef CONFIG_VCODEC_MMU
  62 #include <linux/rockchip-iovmm.h>
  63 #include <linux/dma-buf.h>
  64 #endif
  65
  66 #ifdef CONFIG_DEBUG_FS
  67 #include <linux/debugfs.h>
  68 #endif
  69
  70 #if defined(CONFIG_ARCH_RK319X)
  71 #include <mach/grf.h>
  72 #endif
  73
  74 #include "vcodec_service.h"
  75
  76 /*
  77  * debug flag usage:
  78  * +------+-------------------+
  79  * | 8bit |      24bit        |
  80  * +------+-------------------+
  81  *  0~23 bit is for different information type
  82  * 24~31 bit is for information print format
  83  */
  84
  85 #define DEBUG_POWER                             0x00000001
  86 #define DEBUG_CLOCK                             0x00000002
  87 #define DEBUG_IRQ_STATUS                        0x00000004
  88 #define DEBUG_IOMMU                             0x00000008
  89 #define DEBUG_IOCTL                             0x00000010
  90 #define DEBUG_FUNCTION                          0x00000020
  91 #define DEBUG_REGISTER                          0x00000040
  92 #define DEBUG_EXTRA_INFO                        0x00000080
  93 #define DEBUG_TIMING                            0x00000100
  94
  95 #define PRINT_FUNCTION                          0x80000000
  96 #define PRINT_LINE                              0x40000000
  97
  98 static int debug;
  99 module_param(debug, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(debug,
 101                  "Debug level - higher value produces more verbose messages");
 102
 103 #define HEVC_TEST_ENABLE        0
 104 #define VCODEC_CLOCK_ENABLE     1
 105
 106 typedef enum {
 107         VPU_DEC_ID_9190         = 0x6731,
 108         VPU_ID_8270             = 0x8270,
 109         VPU_ID_4831             = 0x4831,
 110         HEVC_ID                 = 0x6867,
 111 } VPU_HW_ID;
 112
 113 enum VPU_HW_SPEC {
 114         VPU_TYPE_VPU,
 115         VPU_TYPE_HEVC,
 116         VPU_TYPE_COMBO_NOENC,
 117         VPU_TYPE_COMBO
 118 };
 119
 120 typedef enum {
 121         VPU_DEC_TYPE_9190       = 0,
 122         VPU_ENC_TYPE_8270       = 0x100,
 123         VPU_ENC_TYPE_4831       ,
 124 } VPU_HW_TYPE_E;
 125
 126 typedef enum VPU_FREQ {
 127         VPU_FREQ_200M,
 128         VPU_FREQ_266M,
 129         VPU_FREQ_300M,
 130         VPU_FREQ_400M,
 131         VPU_FREQ_500M,
 132         VPU_FREQ_600M,
 133         VPU_FREQ_DEFAULT,
 134         VPU_FREQ_BUT,
 135 } VPU_FREQ;
 136
 137 typedef struct {
 138         VPU_HW_ID               hw_id;
 139         unsigned long           hw_addr;
 140         unsigned long           enc_offset;
 141         unsigned long           enc_reg_num;
 142         unsigned long           enc_io_size;
 143         unsigned long           dec_offset;
 144         unsigned long           dec_reg_num;
 145         unsigned long           dec_io_size;
 146 } VPU_HW_INFO_E;
 147
 148 struct extra_info_elem {
 149         u32 index;
 150         u32 offset;
 151 };
 152
 153 #define EXTRA_INFO_MAGIC        0x4C4A46
 154
 155 struct extra_info_for_iommu {
 156         u32 magic;
 157         u32 cnt;
 158         struct extra_info_elem elem[20];
 159 };
 160
 161 #define MHZ                                     (1000*1000)
 162
 163 #define REG_NUM_9190_DEC                        (60)
 164 #define REG_NUM_9190_PP                         (41)
 165 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 166
 167 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 168
 169 #define REG_NUM_ENC_8270                        (96)
 170 #define REG_SIZE_ENC_8270                       (0x200)
 171 #define REG_NUM_ENC_4831                        (164)
 172 #define REG_SIZE_ENC_4831                       (0x400)
 173
 174 #define REG_NUM_HEVC_DEC                        (68)
 175
 176 #define SIZE_REG(reg)                           ((reg)*4)
 177
 178 static VPU_HW_INFO_E vpu_hw_set[] = {
 179         [0] = {
 180                 .hw_id          = VPU_ID_8270,
 181                 .hw_addr        = 0,
 182                 .enc_offset     = 0x0,
 183                 .enc_reg_num    = REG_NUM_ENC_8270,
 184                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 185                 .dec_offset     = REG_SIZE_ENC_8270,
 186                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 187                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 188         },
 189         [1] = {
 190                 .hw_id          = VPU_ID_4831,
 191                 .hw_addr        = 0,
 192                 .enc_offset     = 0x0,
 193                 .enc_reg_num    = REG_NUM_ENC_4831,
 194                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 195                 .dec_offset     = REG_SIZE_ENC_4831,
 196                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 197                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 198         },
 199         [2] = {
 200                 .hw_id          = HEVC_ID,
 201                 .hw_addr        = 0,
 202                 .dec_offset     = 0x0,
 203                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 204                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 205         },
 206         [3] = {
 207                 .hw_id          = VPU_DEC_ID_9190,
 208                 .hw_addr        = 0,
 209                 .enc_offset     = 0x0,
 210                 .enc_reg_num    = 0,
 211                 .enc_io_size    = 0,
 212                 .dec_offset     = 0,
 213                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 214                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 215         },
 216 };
 217
 218 #ifndef BIT
 219 #define BIT(x)                                  (1<<(x))
 220 #endif
 221
 222 // interrupt and error status register
 223 #define DEC_INTERRUPT_REGISTER                  1
 224 #define DEC_INTERRUPT_BIT                       BIT(8)
 225 #define DEC_READY_BIT                           BIT(12)
 226 #define DEC_BUS_ERROR_BIT                       BIT(13)
 227 #define DEC_BUFFER_EMPTY_BIT                    BIT(14)
 228 #define DEC_ASO_ERROR_BIT                       BIT(15)
 229 #define DEC_STREAM_ERROR_BIT                    BIT(16)
 230 #define DEC_SLICE_DONE_BIT                      BIT(17)
 231 #define DEC_TIMEOUT_BIT                         BIT(18)
 232 #define DEC_ERR_MASK                            DEC_BUS_ERROR_BIT \
 233                                                 |DEC_BUFFER_EMPTY_BIT \
 234                                                 |DEC_STREAM_ERROR_BIT \
 235                                                 |DEC_TIMEOUT_BIT
 236
 237 #define PP_INTERRUPT_REGISTER                   60
 238 #define PP_INTERRUPT_BIT                        BIT(8)
 239 #define PP_READY_BIT                            BIT(12)
 240 #define PP_BUS_ERROR_BIT                        BIT(13)
 241 #define PP_ERR_MASK                             PP_BUS_ERROR_BIT
 242
 243 #define ENC_INTERRUPT_REGISTER                  1
 244 #define ENC_INTERRUPT_BIT                       BIT(0)
 245 #define ENC_READY_BIT                           BIT(2)
 246 #define ENC_BUS_ERROR_BIT                       BIT(3)
 247 #define ENC_BUFFER_FULL_BIT                     BIT(5)
 248 #define ENC_TIMEOUT_BIT                         BIT(6)
 249 #define ENC_ERR_MASK                            ENC_BUS_ERROR_BIT \
 250                                                 |ENC_BUFFER_FULL_BIT \
 251                                                 |ENC_TIMEOUT_BIT
 252
 253 #define HEVC_INTERRUPT_REGISTER                 1
 254 #define HEVC_DEC_INT_RAW_BIT                    BIT(9)
 255 #define HEVC_DEC_BUS_ERROR_BIT                  BIT(13)
 256 #define HEVC_DEC_STR_ERROR_BIT                  BIT(14)
 257 #define HEVC_DEC_TIMEOUT_BIT                    BIT(15)
 258 #define HEVC_DEC_BUFFER_EMPTY_BIT               BIT(16)
 259 #define HEVC_DEC_COLMV_ERROR_BIT                BIT(17)
 260 #define HEVC_DEC_ERR_MASK                       HEVC_DEC_BUS_ERROR_BIT \
 261                                                 |HEVC_DEC_STR_ERROR_BIT \
 262                                                 |HEVC_DEC_TIMEOUT_BIT \
 263                                                 |HEVC_DEC_BUFFER_EMPTY_BIT \
 264                                                 |HEVC_DEC_COLMV_ERROR_BIT
 265
 266
 267 // gating configuration set
 268 #define VPU_REG_EN_ENC                          14
 269 #define VPU_REG_ENC_GATE                        2
 270 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 271
 272 #define VPU_REG_EN_DEC                          1
 273 #define VPU_REG_DEC_GATE                        2
 274 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 275 #define VPU_REG_EN_PP                           0
 276 #define VPU_REG_PP_GATE                         1
 277 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 278 #define VPU_REG_EN_DEC_PP                       1
 279 #define VPU_REG_DEC_PP_GATE                     61
 280 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 281
 282 #define DEBUG
 283 #ifdef DEBUG
 284 #define vpu_debug_func(type, fmt, args...)                      \
 285         do {                                                    \
 286                 if (unlikely(debug & type)) {                   \
 287                         pr_info("%s:%d: " fmt,                  \
 288                                  __func__, __LINE__, ##args);   \
 289                 }                                               \
 290         } while (0)
 291 #define vpu_debug(type, fmt, args...)                           \
 292         do {                                                    \
 293                 if (unlikely(debug & type)) {                   \
 294                         pr_info(fmt, ##args);                   \
 295                 }                                               \
 296         } while (0)
 297 #else
 298 #define vpu_debug_func(level, fmt, args...)
 299 #define vpu_debug(level, fmt, args...)
 300 #endif
 301
 302 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
 303 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
 304
 305 #define vpu_err(fmt, args...)                           \
 306                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 307
 308 #if defined(CONFIG_VCODEC_MMU)
 309 static u8 addr_tbl_vpu_h264dec[] = {
 310         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 311         25, 26, 27, 28, 29, 40, 41
 312 };
 313
 314 static u8 addr_tbl_vpu_vp8dec[] = {
 315         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 316 };
 317
 318 static u8 addr_tbl_vpu_vp6dec[] = {
 319         12, 13, 14, 18, 27, 40
 320 };
 321
 322 static u8 addr_tbl_vpu_vc1dec[] = {
 323         12, 13, 14, 15, 16, 17, 27, 41
 324 };
 325
 326 static u8 addr_tbl_vpu_jpegdec[] = {
 327         12, 40, 66, 67
 328 };
 329
 330 static u8 addr_tbl_vpu_defaultdec[] = {
 331         12, 13, 14, 15, 16, 17, 40, 41
 332 };
 333
 334 static u8 addr_tbl_vpu_enc[] = {
 335         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 336 };
 337
 338 static u8 addr_tbl_hevc_dec[] = {
 339         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 340         21, 22, 23, 24, 42, 43
 341 };
 342 #endif
 343
 344 enum VPU_DEC_FMT {
 345         VPU_DEC_FMT_H264,
 346         VPU_DEC_FMT_MPEG4,
 347         VPU_DEC_FMT_H263,
 348         VPU_DEC_FMT_JPEG,
 349         VPU_DEC_FMT_VC1,
 350         VPU_DEC_FMT_MPEG2,
 351         VPU_DEC_FMT_MPEG1,
 352         VPU_DEC_FMT_VP6,
 353         VPU_DEC_FMT_RV,
 354         VPU_DEC_FMT_VP7,
 355         VPU_DEC_FMT_VP8,
 356         VPU_DEC_FMT_AVS,
 357         VPU_DEC_FMT_SVC,
 358         VPU_DEC_FMT_VC2,
 359         VPU_DEC_FMT_MVC,
 360         VPU_DEC_FMT_THEORA,
 361         VPU_DEC_FMT_RES
 362 };
 363
 364 /**
 365  * struct for process session which connect to vpu
 366  *
 367  * @author ChenHengming (2011-5-3)
 368  */
 369 typedef struct vpu_session {
 370         enum VPU_CLIENT_TYPE type;
 371         /* a linked list of data so we can access them for debugging */
 372         struct list_head list_session;
 373         /* a linked list of register data waiting for process */
 374         struct list_head waiting;
 375         /* a linked list of register data in processing */
 376         struct list_head running;
 377         /* a linked list of register data processed */
 378         struct list_head done;
 379         wait_queue_head_t wait;
 380         pid_t pid;
 381         atomic_t task_running;
 382 } vpu_session;
 383
 384 /**
 385  * struct for process register set
 386  *
 387  * @author ChenHengming (2011-5-4)
 388  */
 389 typedef struct vpu_reg {
 390         enum VPU_CLIENT_TYPE type;
 391         VPU_FREQ freq;
 392         vpu_session *session;
 393         struct vpu_subdev_data *data;
 394         struct list_head session_link;          /* link to vpu service session */
 395         struct list_head status_link;           /* link to register set list */
 396         unsigned long size;
 397 #if defined(CONFIG_VCODEC_MMU)
 398         struct list_head mem_region_list;
 399         u32 dec_base;
 400 #endif
 401         u32 *reg;
 402 } vpu_reg;
 403
 404 typedef struct vpu_device {
 405         atomic_t                irq_count_codec;
 406         atomic_t                irq_count_pp;
 407         unsigned long           iobaseaddr;
 408         unsigned int            iosize;
 409         volatile u32            *hwregs;
 410 } vpu_device;
 411
 412 enum vcodec_device_id {
 413         VCODEC_DEVICE_ID_VPU,
 414         VCODEC_DEVICE_ID_HEVC,
 415         VCODEC_DEVICE_ID_COMBO
 416 };
 417
 418 enum VCODEC_RUNNING_MODE {
 419         VCODEC_RUNNING_MODE_NONE = -1,
 420         VCODEC_RUNNING_MODE_VPU,
 421         VCODEC_RUNNING_MODE_HEVC,
 422 };
 423
 424 struct vcodec_mem_region {
 425         struct list_head srv_lnk;
 426         struct list_head reg_lnk;
 427         struct list_head session_lnk;
 428         unsigned long iova;     /* virtual address for iommu */
 429         unsigned long len;
 430         u32 reg_idx;
 431         struct ion_handle *hdl;
 432 };
 433
 434 enum vpu_ctx_state {
 435         MMU_ACTIVATED   = BIT(0)
 436 };
 437
 438 struct vpu_subdev_data {
 439         struct cdev cdev;
 440         dev_t dev_t;
 441         struct class *cls;
 442         struct device *child_dev;
 443
 444         int irq_enc;
 445         int irq_dec;
 446         struct vpu_service_info *pservice;
 447
 448         u32 *regs;
 449         enum VCODEC_RUNNING_MODE mode;
 450         struct list_head lnk_service;
 451
 452         struct device *dev;
 453
 454         vpu_device enc_dev;
 455         vpu_device dec_dev;
 456         VPU_HW_INFO_E *hw_info;
 457
 458         u32 reg_size;
 459         unsigned long state;
 460
 461 #ifdef CONFIG_DEBUG_FS
 462         struct dentry *debugfs_dir;
 463         struct dentry *debugfs_file_regs;
 464 #endif
 465
 466 #if defined(CONFIG_VCODEC_MMU)
 467         struct device *mmu_dev;
 468 #endif
 469 };
 470
 471 typedef struct vpu_service_info {
 472         struct wake_lock wake_lock;
 473         struct delayed_work power_off_work;
 474         struct mutex lock;
 475         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 476         struct list_head running;               /* link to link_reg in struct vpu_reg */
 477         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 478         struct list_head session;               /* link to list_session in struct vpu_session */
 479         atomic_t total_running;
 480         atomic_t enabled;
 481         atomic_t power_on_cnt;
 482         atomic_t power_off_cnt;
 483         vpu_reg *reg_codec;
 484         vpu_reg *reg_pproc;
 485         vpu_reg *reg_resev;
 486         struct vpu_dec_config dec_config;
 487         struct vpu_enc_config enc_config;
 488
 489         bool auto_freq;
 490         bool bug_dec_addr;
 491         atomic_t freq_status;
 492
 493         struct clk *aclk_vcodec;
 494         struct clk *hclk_vcodec;
 495         struct clk *clk_core;
 496         struct clk *clk_cabac;
 497         struct clk *pd_video;
 498
 499 #ifdef CONFIG_RESET_CONTROLLER
 500         struct reset_control *rst_a;
 501         struct reset_control *rst_h;
 502         struct reset_control *rst_v;
 503 #endif
 504         struct device *dev;
 505
 506         u32 irq_status;
 507         atomic_t reset_request;
 508 #if defined(CONFIG_VCODEC_MMU)
 509         struct ion_client *ion_client;
 510         struct list_head mem_region_list;
 511 #endif
 512
 513         enum vcodec_device_id dev_id;
 514
 515         enum VCODEC_RUNNING_MODE curr_mode;
 516         u32 prev_mode;
 517
 518         struct delayed_work simulate_work;
 519
 520         u32 mode_bit;
 521         u32 mode_ctrl;
 522         u32 *reg_base;
 523         u32 ioaddr;
 524 #ifdef CONFIG_MFD_SYSCON
 525         struct regmap *grf_base;
 526 #else
 527         u32 *grf_base;
 528 #endif
 529         char *name;
 530
 531         u32 subcnt;
 532         struct list_head subdev_list;
 533 } vpu_service_info;
 534
 535 struct vcodec_combo {
 536         struct vpu_service_info *vpu_srv;
 537         struct vpu_service_info *hevc_srv;
 538         struct list_head waiting;
 539         struct list_head running;
 540         struct mutex run_lock;
 541         vpu_reg *reg_codec;
 542         enum vcodec_device_id current_hw_mode;
 543 };
 544
 545 struct vpu_request {
 546         u32 *req;
 547         u32 size;
 548 };
 549
 550 #ifdef CONFIG_COMPAT
 551 struct compat_vpu_request {
 552         compat_uptr_t req;
 553         u32 size;
 554 };
 555 #endif
 556
 557 /* debugfs root directory for all device (vpu, hevc).*/
 558 static struct dentry *parent;
 559
 560 #ifdef CONFIG_DEBUG_FS
 561 static int vcodec_debugfs_init(void);
 562 static void vcodec_debugfs_exit(void);
 563 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 564 static int debug_vcodec_open(struct inode *inode, struct file *file);
 565
 566 static const struct file_operations debug_vcodec_fops = {
 567         .open = debug_vcodec_open,
 568         .read = seq_read,
 569         .llseek = seq_lseek,
 570         .release = single_release,
 571 };
 572 #endif
 573
 574 #define VDPU_SOFT_RESET_REG     101
 575 #define VDPU_CLEAN_CACHE_REG    516
 576 #define VEPU_CLEAN_CACHE_REG    772
 577 #define HEVC_CLEAN_CACHE_REG    260
 578
 579 #define VPU_REG_ENABLE(base, reg)       do { \
 580                                                 base[reg] = 1; \
 581                                         } while (0)
 582
 583 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 584 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 585 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 586 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 587
 588 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 589 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 590
 591 typedef struct {
 592         char *name;
 593         struct timeval start;
 594         struct timeval end;
 595         u32 error_mask;
 596 } task_info;
 597
 598 typedef enum {
 599         TASK_VPU_ENC,
 600         TASK_VPU_DEC,
 601         TASK_VPU_PP,
 602         TASK_RKDEC_HEVC,
 603         TASK_TYPE_BUTT,
 604 } TASK_TYPE;
 605
 606 task_info tasks[TASK_TYPE_BUTT] = {
 607         {
 608                 .name = "enc",
 609                 .error_mask = ENC_ERR_MASK
 610         },
 611         {
 612                 .name = "dec",
 613                 .error_mask = DEC_ERR_MASK
 614         },
 615         {
 616                 .name = "pp",
 617                 .error_mask = PP_ERR_MASK
 618         },
 619         {
 620                 .name = "hevc",
 621                 .error_mask = HEVC_DEC_ERR_MASK
 622         },
 623 };
 624
 625 static void time_record(task_info *task, int is_end)
 626 {
 627         if (unlikely(debug & DEBUG_TIMING)) {
 628                 do_gettimeofday((is_end)?(&task->end):(&task->start));
 629         }
 630 }
 631
 632 static void time_diff(task_info *task)
 633 {
 634         vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
 635                         (task->end.tv_sec  - task->start.tv_sec)  * 1000 +
 636                         (task->end.tv_usec - task->start.tv_usec) / 1000);
 637 }
 638
 639 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 640 {
 641         int bits;
 642         u32 raw = 0;
 643         struct vpu_service_info *pservice = data->pservice;
 644         struct vpu_subdev_data *subdata, *n;
 645         if (pservice->subcnt < 2) {
 646 #if defined(CONFIG_VCODEC_MMU)
 647                 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 648                         set_bit(MMU_ACTIVATED, &data->state);
 649                         if (atomic_read(&pservice->enabled))
 650                                 rockchip_iovmm_activate(data->dev);
 651                         else
 652                                 BUG_ON(!atomic_read(&pservice->enabled));
 653                 }
 654 #endif
 655                 return;
 656         }
 657
 658         if (pservice->curr_mode == data->mode)
 659                 return;
 660
 661         vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
 662 #if defined(CONFIG_VCODEC_MMU)
 663         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 664                 if (data != subdata && subdata->mmu_dev &&
 665                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 666                         clear_bit(MMU_ACTIVATED, &subdata->state);
 667                         rockchip_iovmm_deactivate(subdata->dev);
 668                 }
 669         }
 670 #endif
 671         bits = 1 << pservice->mode_bit;
 672 #ifdef CONFIG_MFD_SYSCON
 673         regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
 674
 675         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 676                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 677                         raw | bits | (bits << 16));
 678         else
 679                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 680                         (raw & (~bits)) | (bits << 16));
 681 #else
 682         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 683         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 684                 writel_relaxed(raw | bits | (bits << 16),
 685                         pservice->grf_base + pservice->mode_ctrl / 4);
 686         else
 687                 writel_relaxed((raw & (~bits)) | (bits << 16),
 688                         pservice->grf_base + pservice->mode_ctrl / 4);
 689 #endif
 690 #if defined(CONFIG_VCODEC_MMU)
 691         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 692                 set_bit(MMU_ACTIVATED, &data->state);
 693                 if (atomic_read(&pservice->enabled))
 694                         rockchip_iovmm_activate(data->dev);
 695                 else
 696                         BUG_ON(!atomic_read(&pservice->enabled));
 697         }
 698 #endif
 699         pservice->prev_mode = pservice->curr_mode;
 700         pservice->curr_mode = data->mode;
 701 }
 702
 703 static void vcodec_exit_mode(struct vpu_subdev_data *data)
 704 {
 705         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 706                 clear_bit(MMU_ACTIVATED, &data->state);
 707                 rockchip_iovmm_deactivate(data->dev);
 708                 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 709         }
 710 }
 711
 712 static int vpu_get_clk(struct vpu_service_info *pservice)
 713 {
 714 #if VCODEC_CLOCK_ENABLE
 715         switch (pservice->dev_id) {
 716         case VCODEC_DEVICE_ID_HEVC:
 717                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 718                 if (IS_ERR(pservice->pd_video)) {
 719                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 720                         return -1;
 721                 }
 722         case VCODEC_DEVICE_ID_COMBO:
 723                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 724                 if (IS_ERR(pservice->clk_cabac)) {
 725                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 726                         pservice->clk_cabac = NULL;
 727                 }
 728                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 729                 if (IS_ERR(pservice->clk_core)) {
 730                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 731                         return -1;
 732                 }
 733         case VCODEC_DEVICE_ID_VPU:
 734                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 735                 if (IS_ERR(pservice->aclk_vcodec)) {
 736                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 737                         return -1;
 738                 }
 739
 740                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 741                 if (IS_ERR(pservice->hclk_vcodec)) {
 742                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 743                         return -1;
 744                 }
 745                 if (pservice->pd_video == NULL) {
 746                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 747                         if (IS_ERR(pservice->pd_video)) {
 748                                 pservice->pd_video = NULL;
 749                                 dev_info(pservice->dev, "do not have pd_video\n");
 750                         }
 751                 }
 752                 break;
 753         default:
 754                 ;
 755         }
 756
 757         return 0;
 758 #else
 759         return 0;
 760 #endif
 761 }
 762
 763 static void vpu_put_clk(struct vpu_service_info *pservice)
 764 {
 765 #if VCODEC_CLOCK_ENABLE
 766         if (pservice->pd_video)
 767                 devm_clk_put(pservice->dev, pservice->pd_video);
 768         if (pservice->aclk_vcodec)
 769                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 770         if (pservice->hclk_vcodec)
 771                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 772         if (pservice->clk_core)
 773                 devm_clk_put(pservice->dev, pservice->clk_core);
 774         if (pservice->clk_cabac)
 775                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 776 #endif
 777 }
 778
 779 static void vpu_reset(struct vpu_subdev_data *data)
 780 {
 781         struct vpu_service_info *pservice = data->pservice;
 782         enum pmu_idle_req type = IDLE_REQ_VIDEO;
 783
 784         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC)
 785                 type = IDLE_REQ_HEVC;
 786
 787         pr_info("%s: resetting...", dev_name(pservice->dev));
 788
 789 #if defined(CONFIG_ARCH_RK29)
 790         clk_disable(aclk_ddr_vepu);
 791         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 792         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 793         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 794         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 795         mdelay(10);
 796         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 797         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 798         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 799         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 800         clk_enable(aclk_ddr_vepu);
 801 #elif defined(CONFIG_ARCH_RK30)
 802         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 803         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 804         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 805         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 806         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 807         mdelay(1);
 808         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 809         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 810         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 811         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 812         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 813 #else
 814 #endif
 815         WARN_ON(pservice->reg_codec != NULL);
 816         WARN_ON(pservice->reg_pproc != NULL);
 817         WARN_ON(pservice->reg_resev != NULL);
 818         pservice->reg_codec = NULL;
 819         pservice->reg_pproc = NULL;
 820         pservice->reg_resev = NULL;
 821
 822         pr_info("for 3288/3368...");
 823 #ifdef CONFIG_RESET_CONTROLLER
 824         if (pservice->rst_a && pservice->rst_h) {
 825                 if (rockchip_pmu_ops.set_idle_request)
 826                         rockchip_pmu_ops.set_idle_request(type, true);
 827                 pr_info("reset in\n");
 828                 if (pservice->rst_v)
 829                         reset_control_assert(pservice->rst_v);
 830                 reset_control_assert(pservice->rst_a);
 831                 reset_control_assert(pservice->rst_h);
 832                 usleep_range(10, 20);
 833                 reset_control_deassert(pservice->rst_h);
 834                 reset_control_deassert(pservice->rst_a);
 835                 if (pservice->rst_v)
 836                         reset_control_deassert(pservice->rst_v);
 837                 if (rockchip_pmu_ops.set_idle_request)
 838                         rockchip_pmu_ops.set_idle_request(type, false);
 839         }
 840 #endif
 841
 842 #if defined(CONFIG_VCODEC_MMU)
 843         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 844                 clear_bit(MMU_ACTIVATED, &data->state);
 845                 if (atomic_read(&pservice->enabled))
 846                         rockchip_iovmm_deactivate(data->dev);
 847                 else
 848                         BUG_ON(!atomic_read(&pservice->enabled));
 849         }
 850 #endif
 851         atomic_set(&pservice->reset_request, 0);
 852         pr_info("done\n");
 853 }
 854
 855 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 856 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 857 {
 858         vpu_reg *reg, *n;
 859         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 860                 reg_deinit(data, reg);
 861         }
 862         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 863                 reg_deinit(data, reg);
 864         }
 865         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 866                 reg_deinit(data, reg);
 867         }
 868 }
 869
 870 static void vpu_service_dump(struct vpu_service_info *pservice)
 871 {
 872 }
 873
 874 static void vpu_service_power_off(struct vpu_service_info *pservice)
 875 {
 876         int total_running;
 877         struct vpu_subdev_data *data = NULL, *n;
 878         int ret = atomic_add_unless(&pservice->enabled, -1, 0);
 879         if (!ret)
 880                 return;
 881
 882         total_running = atomic_read(&pservice->total_running);
 883         if (total_running) {
 884                 pr_alert("alert: power off when %d task running!!\n", total_running);
 885                 mdelay(50);
 886                 pr_alert("alert: delay 50 ms for running task\n");
 887                 vpu_service_dump(pservice);
 888         }
 889
 890         pr_info("%s: power off...", dev_name(pservice->dev));
 891         udelay(10);
 892 #if defined(CONFIG_VCODEC_MMU)
 893         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 894                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 895                         clear_bit(MMU_ACTIVATED, &data->state);
 896                         rockchip_iovmm_deactivate(data->dev);
 897                 }
 898         }
 899         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 900 #endif
 901
 902 #if VCODEC_CLOCK_ENABLE
 903         if (pservice->pd_video)
 904                 clk_disable_unprepare(pservice->pd_video);
 905         if (pservice->hclk_vcodec)
 906                 clk_disable_unprepare(pservice->hclk_vcodec);
 907         if (pservice->aclk_vcodec)
 908                 clk_disable_unprepare(pservice->aclk_vcodec);
 909         if (pservice->clk_core)
 910                 clk_disable_unprepare(pservice->clk_core);
 911         if (pservice->clk_cabac)
 912                 clk_disable_unprepare(pservice->clk_cabac);
 913 #endif
 914
 915         atomic_add(1, &pservice->power_off_cnt);
 916         wake_unlock(&pservice->wake_lock);
 917         pr_info("done\n");
 918 }
 919
 920 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 921 {
 922         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 923 }
 924
 925 static void vpu_power_off_work(struct work_struct *work_s)
 926 {
 927         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 928         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 929
 930         if (mutex_trylock(&pservice->lock)) {
 931                 vpu_service_power_off(pservice);
 932                 mutex_unlock(&pservice->lock);
 933         } else {
 934                 /* Come back later if the device is busy... */
 935                 vpu_queue_power_off_work(pservice);
 936         }
 937 }
 938
 939 static void vpu_service_power_on(struct vpu_service_info *pservice)
 940 {
 941         int ret;
 942         static ktime_t last;
 943         ktime_t now = ktime_get();
 944         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 945                 cancel_delayed_work_sync(&pservice->power_off_work);
 946                 vpu_queue_power_off_work(pservice);
 947                 last = now;
 948         }
 949         ret = atomic_add_unless(&pservice->enabled, 1, 1);
 950         if (!ret)
 951                 return ;
 952
 953         pr_info("%s: power on\n", dev_name(pservice->dev));
 954
 955 #define BIT_VCODEC_CLK_SEL      (1<<10)
 956         if (cpu_is_rk312x())
 957                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 958                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 959                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 960
 961 #if VCODEC_CLOCK_ENABLE
 962         if (pservice->aclk_vcodec)
 963                 clk_prepare_enable(pservice->aclk_vcodec);
 964         if (pservice->hclk_vcodec)
 965                 clk_prepare_enable(pservice->hclk_vcodec);
 966         if (pservice->clk_core)
 967                 clk_prepare_enable(pservice->clk_core);
 968         if (pservice->clk_cabac)
 969                 clk_prepare_enable(pservice->clk_cabac);
 970         if (pservice->pd_video)
 971                 clk_prepare_enable(pservice->pd_video);
 972 #endif
 973
 974         udelay(10);
 975         atomic_add(1, &pservice->power_on_cnt);
 976         wake_lock(&pservice->wake_lock);
 977 }
 978
 979 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 980 {
 981         u32 type = (reg->reg[3] & 0xF0000000) >> 28;
 982         return ((type == 8) || (type == 4));
 983 }
 984
 985 static inline bool reg_check_interlace(vpu_reg *reg)
 986 {
 987         u32 type = (reg->reg[3] & (1 << 23));
 988         return (type > 0);
 989 }
 990
 991 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 992 {
 993         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 994         return type;
 995 }
 996
 997 static inline int reg_probe_width(vpu_reg *reg)
 998 {
 999         int width_in_mb = reg->reg[4] >> 23;
1000         return width_in_mb * 16;
1001 }
1002
1003 static inline int reg_probe_hevc_y_stride(vpu_reg *reg)
1004 {
1005         int y_virstride = reg->reg[8];
1006         return y_virstride;
1007 }
1008
1009 #if defined(CONFIG_VCODEC_MMU)
1010 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
1011 {
1012         struct vpu_service_info *pservice = data->pservice;
1013         struct ion_handle *hdl;
1014         int ret = 0;
1015         struct vcodec_mem_region *mem_region;
1016
1017         hdl = ion_import_dma_buf(pservice->ion_client, fd);
1018         if (IS_ERR(hdl)) {
1019                 vpu_err("import dma-buf from fd %d failed\n", fd);
1020                 return PTR_ERR(hdl);
1021         }
1022         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1023
1024         if (mem_region == NULL) {
1025                 vpu_err("allocate memory for iommu memory region failed\n");
1026                 ion_free(pservice->ion_client, hdl);
1027                 return -1;
1028         }
1029
1030         mem_region->hdl = hdl;
1031         ret = ion_map_iommu(data->dev, pservice->ion_client,
1032                 mem_region->hdl, &mem_region->iova, &mem_region->len);
1033
1034         if (ret < 0) {
1035                 vpu_err("ion map iommu failed\n");
1036                 kfree(mem_region);
1037                 ion_free(pservice->ion_client, hdl);
1038                 return ret;
1039         }
1040         INIT_LIST_HEAD(&mem_region->reg_lnk);
1041         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1042         return mem_region->iova;
1043 }
1044
1045 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
1046                                 int size, vpu_reg *reg,
1047                                 struct extra_info_for_iommu *ext_inf)
1048 {
1049         struct vpu_service_info *pservice = data->pservice;
1050         int i;
1051         int usr_fd = 0;
1052         int offset = 0;
1053
1054         if (tbl == NULL || size <= 0) {
1055                 dev_err(pservice->dev, "input arguments invalidate\n");
1056                 return -1;
1057         }
1058
1059         for (i = 0; i < size; i++) {
1060                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
1061
1062                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
1063                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
1064                         /* special for vpu dec num 41 regitster */
1065                         offset = reg->reg[tbl[i]] >> 10 << 4;
1066                 else
1067                         offset = reg->reg[tbl[i]] >> 10;
1068
1069                 if (usr_fd != 0) {
1070                         struct ion_handle *hdl;
1071                         int ret = 0;
1072                         struct vcodec_mem_region *mem_region;
1073
1074                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
1075                         if (IS_ERR(hdl)) {
1076                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
1077                                 return PTR_ERR(hdl);
1078                         }
1079
1080                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
1081                                 int i = 0;
1082                                 char *pps;
1083                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
1084                                 for (i=0; i<64; i++) {
1085                                         u32 scaling_offset;
1086                                         u32 tmp;
1087                                         int scaling_fd= 0;
1088                                         scaling_offset = (u32)pps[i*80+74];
1089                                         scaling_offset += (u32)pps[i*80+75] << 8;
1090                                         scaling_offset += (u32)pps[i*80+76] << 16;
1091                                         scaling_offset += (u32)pps[i*80+77] << 24;
1092                                         scaling_fd = scaling_offset&0x3ff;
1093                                         scaling_offset = scaling_offset >> 10;
1094                                         if(scaling_fd > 0) {
1095                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
1096                                                 tmp += scaling_offset;
1097                                                 pps[i*80+74] = tmp & 0xff;
1098                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
1099                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
1100                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
1101                                         }
1102                                 }
1103                         }
1104
1105                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1106
1107                         if (mem_region == NULL) {
1108                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
1109                                 ion_free(pservice->ion_client, hdl);
1110                                 return -1;
1111                         }
1112
1113                         mem_region->hdl = hdl;
1114                         mem_region->reg_idx = tbl[i];
1115                         ret = ion_map_iommu(data->dev,
1116                                             pservice->ion_client,
1117                                             mem_region->hdl,
1118                                             &mem_region->iova,
1119                                             &mem_region->len);
1120
1121                         if (ret < 0) {
1122                                 dev_err(pservice->dev, "ion map iommu failed\n");
1123                                 kfree(mem_region);
1124                                 ion_free(pservice->ion_client, hdl);
1125                                 return ret;
1126                         }
1127
1128                         /* special for vpu dec num 12: record decoded length
1129                            hacking for decoded length
1130                            NOTE: not a perfect fix, the fd is not recorded */
1131                         if (tbl[i] == 12 && data->hw_info->hw_id != HEVC_ID &&
1132                                         (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {
1133                                 reg->dec_base = mem_region->iova + offset;
1134                                 vpu_debug(DEBUG_REGISTER, "dec_set %08x\n", reg->dec_base);
1135                         }
1136
1137                         reg->reg[tbl[i]] = mem_region->iova + offset;
1138                         INIT_LIST_HEAD(&mem_region->reg_lnk);
1139                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1140                 }
1141         }
1142
1143         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1144                 for (i=0; i<ext_inf->cnt; i++) {
1145                         vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1146                                   ext_inf->elem[i].index,
1147                                   ext_inf->elem[i].offset);
1148                         reg->reg[ext_inf->elem[i].index] +=
1149                                 ext_inf->elem[i].offset;
1150                 }
1151         }
1152
1153         return 0;
1154 }
1155
1156 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1157                                         vpu_reg *reg,
1158                                         struct extra_info_for_iommu *ext_inf)
1159 {
1160         VPU_HW_ID hw_id;
1161         u8 *tbl;
1162         int size = 0;
1163
1164         hw_id = data->hw_info->hw_id;
1165
1166         if (hw_id == HEVC_ID) {
1167                 tbl = addr_tbl_hevc_dec;
1168                 size = sizeof(addr_tbl_hevc_dec);
1169         } else {
1170                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1171                         switch (reg_check_fmt(reg)) {
1172                         case VPU_DEC_FMT_H264:
1173                                 {
1174                                         tbl = addr_tbl_vpu_h264dec;
1175                                         size = sizeof(addr_tbl_vpu_h264dec);
1176                                         break;
1177                                 }
1178                         case VPU_DEC_FMT_VP8:
1179                         case VPU_DEC_FMT_VP7:
1180                                 {
1181                                         tbl = addr_tbl_vpu_vp8dec;
1182                                         size = sizeof(addr_tbl_vpu_vp8dec);
1183                                         break;
1184                                 }
1185
1186                         case VPU_DEC_FMT_VP6:
1187                                 {
1188                                         tbl = addr_tbl_vpu_vp6dec;
1189                                         size = sizeof(addr_tbl_vpu_vp6dec);
1190                                         break;
1191                                 }
1192                         case VPU_DEC_FMT_VC1:
1193                                 {
1194                                         tbl = addr_tbl_vpu_vc1dec;
1195                                         size = sizeof(addr_tbl_vpu_vc1dec);
1196                                         break;
1197                                 }
1198
1199                         case VPU_DEC_FMT_JPEG:
1200                                 {
1201                                         tbl = addr_tbl_vpu_jpegdec;
1202                                         size = sizeof(addr_tbl_vpu_jpegdec);
1203                                         break;
1204                                 }
1205                         default:
1206                                 tbl = addr_tbl_vpu_defaultdec;
1207                                 size = sizeof(addr_tbl_vpu_defaultdec);
1208                                 break;
1209                         }
1210                 } else if (reg->type == VPU_ENC) {
1211                         tbl = addr_tbl_vpu_enc;
1212                         size = sizeof(addr_tbl_vpu_enc);
1213                 }
1214         }
1215
1216         if (size != 0) {
1217                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1218         } else {
1219                 return -1;
1220         }
1221 }
1222 #endif
1223
1224 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1225         vpu_session *session, void __user *src, u32 size)
1226 {
1227         struct vpu_service_info *pservice = data->pservice;
1228         int extra_size = 0;
1229         struct extra_info_for_iommu extra_info;
1230         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1231
1232         vpu_debug_enter();
1233
1234         if (NULL == reg) {
1235                 vpu_err("error: kmalloc fail in reg_init\n");
1236                 return NULL;
1237         }
1238
1239         if (size > data->reg_size) {
1240                 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1241                   size, data->reg_size);*/
1242                 extra_size = size - data->reg_size;
1243                 size = data->reg_size;
1244         }
1245         reg->session = session;
1246         reg->data = data;
1247         reg->type = session->type;
1248         reg->size = size;
1249         reg->freq = VPU_FREQ_DEFAULT;
1250         reg->reg = (u32 *)&reg[1];
1251         INIT_LIST_HEAD(&reg->session_link);
1252         INIT_LIST_HEAD(&reg->status_link);
1253
1254 #if defined(CONFIG_VCODEC_MMU)
1255         if (data->mmu_dev)
1256                 INIT_LIST_HEAD(&reg->mem_region_list);
1257 #endif
1258
1259         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1260                 vpu_err("error: copy_from_user failed in reg_init\n");
1261                 kfree(reg);
1262                 return NULL;
1263         }
1264
1265         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1266                 vpu_err("error: copy_from_user failed in reg_init\n");
1267                 kfree(reg);
1268                 return NULL;
1269         }
1270
1271 #if defined(CONFIG_VCODEC_MMU)
1272         if (data->mmu_dev &&
1273             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1274                 vpu_err("error: translate reg address failed\n");
1275                 kfree(reg);
1276                 return NULL;
1277         }
1278 #endif
1279
1280         mutex_lock(&pservice->lock);
1281         list_add_tail(&reg->status_link, &pservice->waiting);
1282         list_add_tail(&reg->session_link, &session->waiting);
1283         mutex_unlock(&pservice->lock);
1284
1285         if (pservice->auto_freq) {
1286                 if (!soc_is_rk2928g()) {
1287                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1288                                 if (reg_check_rmvb_wmv(reg)) {
1289                                         reg->freq = VPU_FREQ_200M;
1290                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1291                                         if (reg_probe_width(reg) > 3200) {
1292                                                 /*raise frequency for 4k avc.*/
1293                                                 reg->freq = VPU_FREQ_600M;
1294                                         }
1295                                 } else {
1296                                         if (reg_check_interlace(reg)) {
1297                                                 reg->freq = VPU_FREQ_400M;
1298                                         }
1299                                 }
1300                         }
1301                         if (data->hw_info->hw_id == HEVC_ID) {
1302                                 if (reg_probe_hevc_y_stride(reg) > 60000)
1303                                         reg->freq = VPU_FREQ_400M;
1304                         }
1305                         if (reg->type == VPU_PP) {
1306                                 reg->freq = VPU_FREQ_400M;
1307                         }
1308                 }
1309         }
1310         vpu_debug_leave();
1311         return reg;
1312 }
1313
1314 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1315 {
1316         struct vpu_service_info *pservice = data->pservice;
1317 #if defined(CONFIG_VCODEC_MMU)
1318         struct vcodec_mem_region *mem_region = NULL, *n;
1319 #endif
1320
1321         list_del_init(&reg->session_link);
1322         list_del_init(&reg->status_link);
1323         if (reg == pservice->reg_codec)
1324                 pservice->reg_codec = NULL;
1325         if (reg == pservice->reg_pproc)
1326                 pservice->reg_pproc = NULL;
1327
1328 #if defined(CONFIG_VCODEC_MMU)
1329         /* release memory region attach to this registers table. */
1330         if (data->mmu_dev) {
1331                 list_for_each_entry_safe(mem_region, n,
1332                         &reg->mem_region_list, reg_lnk) {
1333                         /* do not unmap iommu manually,
1334                            unmap will proccess when memory release */
1335                         /*vcodec_enter_mode(data);
1336                         ion_unmap_iommu(data->dev,
1337                                         pservice->ion_client,
1338                                         mem_region->hdl);
1339                         vcodec_exit_mode();*/
1340                         ion_free(pservice->ion_client, mem_region->hdl);
1341                         list_del_init(&mem_region->reg_lnk);
1342                         kfree(mem_region);
1343                 }
1344         }
1345 #endif
1346
1347         kfree(reg);
1348 }
1349
1350 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1351 {
1352         vpu_debug_enter();
1353         list_del_init(&reg->status_link);
1354         list_add_tail(&reg->status_link, &pservice->running);
1355
1356         list_del_init(&reg->session_link);
1357         list_add_tail(&reg->session_link, &reg->session->running);
1358         vpu_debug_leave();
1359 }
1360
1361 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1362 {
1363         int i;
1364         u32 *dst = (u32 *)&reg->reg[0];
1365         vpu_debug_enter();
1366         for (i = 0; i < count; i++)
1367                 *dst++ = *src++;
1368         vpu_debug_leave();
1369 }
1370
1371 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1372         vpu_reg *reg)
1373 {
1374         struct vpu_service_info *pservice = data->pservice;
1375         int irq_reg = -1;
1376
1377         vpu_debug_enter();
1378
1379         list_del_init(&reg->status_link);
1380         list_add_tail(&reg->status_link, &pservice->done);
1381
1382         list_del_init(&reg->session_link);
1383         list_add_tail(&reg->session_link, &reg->session->done);
1384
1385         /*vcodec_enter_mode(data);*/
1386         switch (reg->type) {
1387         case VPU_ENC : {
1388                 pservice->reg_codec = NULL;
1389                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1390                 irq_reg = ENC_INTERRUPT_REGISTER;
1391                 break;
1392         }
1393         case VPU_DEC : {
1394                 int reg_len = REG_NUM_9190_DEC;
1395                 pservice->reg_codec = NULL;
1396                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1397 #if defined(CONFIG_VCODEC_MMU)
1398                 /* revert hack for decoded length */
1399                 if (data->hw_info->hw_id != HEVC_ID) {
1400                         u32 dec_get = reg->reg[12];
1401                         s32 dec_length = dec_get - reg->dec_base;
1402                         vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1403                         reg->reg[12] = dec_length << 10;
1404                 }
1405 #endif
1406                 irq_reg = DEC_INTERRUPT_REGISTER;
1407                 break;
1408         }
1409         case VPU_PP : {
1410                 pservice->reg_pproc = NULL;
1411                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1412                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1413                 break;
1414         }
1415         case VPU_DEC_PP : {
1416                 pservice->reg_codec = NULL;
1417                 pservice->reg_pproc = NULL;
1418                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1419                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1420 #if defined(CONFIG_VCODEC_MMU)
1421                 /* revert hack for decoded length */
1422                 if (data->hw_info->hw_id != HEVC_ID) {
1423                         u32 dec_get = reg->reg[12];
1424                         s32 dec_length = dec_get - reg->dec_base;
1425                         vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1426                         reg->reg[12] = dec_length << 10;
1427                 }
1428 #endif
1429                 break;
1430         }
1431         default : {
1432                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1433                 break;
1434         }
1435         }
1436         vcodec_exit_mode(data);
1437
1438         if (irq_reg != -1)
1439                 reg->reg[irq_reg] = pservice->irq_status;
1440
1441         atomic_sub(1, &reg->session->task_running);
1442         atomic_sub(1, &pservice->total_running);
1443         wake_up(&reg->session->wait);
1444
1445         vpu_debug_leave();
1446 }
1447
1448 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1449 {
1450         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1451         if (curr == reg->freq)
1452                 return;
1453         atomic_set(&pservice->freq_status, reg->freq);
1454         switch (reg->freq) {
1455         case VPU_FREQ_200M : {
1456                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1457         } break;
1458         case VPU_FREQ_266M : {
1459                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1460         } break;
1461         case VPU_FREQ_300M : {
1462                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1463         } break;
1464         case VPU_FREQ_400M : {
1465                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1466         } break;
1467         case VPU_FREQ_500M : {
1468                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1469         } break;
1470         case VPU_FREQ_600M : {
1471                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1472         } break;
1473         default : {
1474                 if (soc_is_rk2928g())
1475                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1476                 else
1477                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1478         } break;
1479         }
1480 }
1481
1482 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1483 {
1484         struct vpu_service_info *pservice = data->pservice;
1485         int i;
1486         u32 *src = (u32 *)&reg->reg[0];
1487         vpu_debug_enter();
1488
1489         atomic_add(1, &pservice->total_running);
1490         atomic_add(1, &reg->session->task_running);
1491         if (pservice->auto_freq)
1492                 vpu_service_set_freq(pservice, reg);
1493
1494         vcodec_enter_mode(data);
1495
1496         switch (reg->type) {
1497         case VPU_ENC : {
1498                 int enc_count = data->hw_info->enc_reg_num;
1499                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1500
1501                 pservice->reg_codec = reg;
1502
1503                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1504
1505                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1506                         dst[i] = src[i];
1507
1508                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1509                         dst[i] = src[i];
1510
1511                 VEPU_CLEAN_CACHE(dst);
1512
1513                 dsb(sy);
1514
1515                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1516                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1517
1518                 time_record(&tasks[TASK_VPU_ENC], 0);
1519         } break;
1520         case VPU_DEC : {
1521                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1522
1523                 pservice->reg_codec = reg;
1524
1525                 if (data->hw_info->hw_id != HEVC_ID) {
1526                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1527                                 dst[i] = src[i];
1528                         VDPU_CLEAN_CACHE(dst);
1529                 } else {
1530                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1531                                 dst[i] = src[i];
1532                         HEVC_CLEAN_CACHE(dst);
1533                 }
1534
1535                 dsb(sy);
1536
1537                 if (data->hw_info->hw_id != HEVC_ID) {
1538                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1539                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1540                 } else {
1541                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1542                 }
1543                 dsb(sy);
1544                 dmb(sy);
1545
1546                 time_record(&tasks[TASK_VPU_DEC], 0);
1547         } break;
1548         case VPU_PP : {
1549                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1550                 pservice->reg_pproc = reg;
1551
1552                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1553
1554                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1555                         dst[i] = src[i];
1556
1557                 dsb(sy);
1558
1559                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1560
1561                 time_record(&tasks[TASK_VPU_PP], 0);
1562         } break;
1563         case VPU_DEC_PP : {
1564                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1565                 pservice->reg_codec = reg;
1566                 pservice->reg_pproc = reg;
1567
1568                 VDPU_SOFT_RESET(dst);
1569                 VDPU_CLEAN_CACHE(dst);
1570
1571                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1572                         dst[i] = src[i];
1573
1574                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1575                 dsb(sy);
1576
1577                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1578                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1579                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1580
1581                 time_record(&tasks[TASK_VPU_DEC], 0);
1582         } break;
1583         default : {
1584                 vpu_err("error: unsupport session type %d", reg->type);
1585                 atomic_sub(1, &pservice->total_running);
1586                 atomic_sub(1, &reg->session->task_running);
1587         } break;
1588         }
1589
1590         /*vcodec_exit_mode(data);*/
1591         vpu_debug_leave();
1592 }
1593
1594 static void try_set_reg(struct vpu_subdev_data *data)
1595 {
1596         struct vpu_service_info *pservice = data->pservice;
1597         vpu_debug_enter();
1598         if (!list_empty(&pservice->waiting)) {
1599                 int can_set = 0;
1600                 bool change_able = (NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc);
1601                 int reset_request = atomic_read(&pservice->reset_request);
1602                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1603
1604                 vpu_service_power_on(pservice);
1605
1606                 // first check can_set flag
1607                 if (change_able || !reset_request) {
1608                         switch (reg->type) {
1609                         case VPU_ENC : {
1610                                 if (change_able)
1611                                         can_set = 1;
1612                         } break;
1613                         case VPU_DEC : {
1614                                 if (NULL == pservice->reg_codec)
1615                                         can_set = 1;
1616                                 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1617                                         can_set = 0;
1618                         } break;
1619                         case VPU_PP : {
1620                                 if (NULL == pservice->reg_codec) {
1621                                         if (NULL == pservice->reg_pproc)
1622                                                 can_set = 1;
1623                                 } else {
1624                                         if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1625                                                 can_set = 1;
1626                                         /* can not charge frequency when vpu is working */
1627                                         if (pservice->auto_freq)
1628                                                 can_set = 0;
1629                                 }
1630                         } break;
1631                         case VPU_DEC_PP : {
1632                                 if (change_able)
1633                                         can_set = 1;
1634                                 } break;
1635                         default : {
1636                                 printk("undefined reg type %d\n", reg->type);
1637                         } break;
1638                         }
1639                 }
1640
1641                 // then check reset request
1642                 if (reset_request && !change_able)
1643                         reset_request = 0;
1644
1645                 // do reset before setting registers
1646                 if (reset_request)
1647                         vpu_reset(data);
1648
1649                 if (can_set) {
1650                         reg_from_wait_to_run(pservice, reg);
1651                         reg_copy_to_hw(reg->data, reg);
1652                 }
1653         }
1654         vpu_debug_leave();
1655 }
1656
1657 static int return_reg(struct vpu_subdev_data *data,
1658         vpu_reg *reg, u32 __user *dst)
1659 {
1660         int ret = 0;
1661         vpu_debug_enter();
1662         switch (reg->type) {
1663         case VPU_ENC : {
1664                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1665                         ret = -EFAULT;
1666                 break;
1667         }
1668         case VPU_DEC : {
1669                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1670                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1671                         ret = -EFAULT;
1672                 break;
1673         }
1674         case VPU_PP : {
1675                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1676                         ret = -EFAULT;
1677                 break;
1678         }
1679         case VPU_DEC_PP : {
1680                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1681                         ret = -EFAULT;
1682                 break;
1683         }
1684         default : {
1685                 ret = -EFAULT;
1686                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1687                 break;
1688         }
1689         }
1690         reg_deinit(data, reg);
1691         vpu_debug_leave();
1692         return ret;
1693 }
1694
1695 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1696         unsigned long arg)
1697 {
1698         struct vpu_subdev_data *data =
1699                 container_of(filp->f_dentry->d_inode->i_cdev,
1700                         struct vpu_subdev_data, cdev);
1701         struct vpu_service_info *pservice = data->pservice;
1702         vpu_session *session = (vpu_session *)filp->private_data;
1703         vpu_debug_enter();
1704         if (NULL == session)
1705                 return -EINVAL;
1706
1707         switch (cmd) {
1708         case VPU_IOC_SET_CLIENT_TYPE : {
1709                 session->type = (enum VPU_CLIENT_TYPE)arg;
1710                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1711                 break;
1712         }
1713         case VPU_IOC_GET_HW_FUSE_STATUS : {
1714                 struct vpu_request req;
1715                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1716                 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1717                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1718                         return -EFAULT;
1719                 } else {
1720                         if (VPU_ENC != session->type) {
1721                                 if (copy_to_user((void __user *)req.req,
1722                                         &pservice->dec_config,
1723                                         sizeof(struct vpu_dec_config))) {
1724                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1725                                                 session->type);
1726                                         return -EFAULT;
1727                                 }
1728                         } else {
1729                                 if (copy_to_user((void __user *)req.req,
1730                                         &pservice->enc_config,
1731                                         sizeof(struct vpu_enc_config ))) {
1732                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1733                                                 session->type);
1734                                         return -EFAULT;
1735                                 }
1736                         }
1737                 }
1738
1739                 break;
1740         }
1741         case VPU_IOC_SET_REG : {
1742                 struct vpu_request req;
1743                 vpu_reg *reg;
1744                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1745                 if (copy_from_user(&req, (void __user *)arg,
1746                         sizeof(struct vpu_request))) {
1747                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1748                         return -EFAULT;
1749                 }
1750                 reg = reg_init(data, session,
1751                         (void __user *)req.req, req.size);
1752                 if (NULL == reg) {
1753                         return -EFAULT;
1754                 } else {
1755                         mutex_lock(&pservice->lock);
1756                         try_set_reg(data);
1757                         mutex_unlock(&pservice->lock);
1758                 }
1759
1760                 break;
1761         }
1762         case VPU_IOC_GET_REG : {
1763                 struct vpu_request req;
1764                 vpu_reg *reg;
1765                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1766                 if (copy_from_user(&req, (void __user *)arg,
1767                         sizeof(struct vpu_request))) {
1768                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1769                         return -EFAULT;
1770                 } else {
1771                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1772                         if (!list_empty(&session->done)) {
1773                                 if (ret < 0) {
1774                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1775                                 }
1776                                 ret = 0;
1777                         } else {
1778                                 if (unlikely(ret < 0)) {
1779                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1780                                 } else if (0 == ret) {
1781                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1782                                         ret = -ETIMEDOUT;
1783                                 }
1784                         }
1785                         if (ret < 0) {
1786                                 int task_running = atomic_read(&session->task_running);
1787                                 mutex_lock(&pservice->lock);
1788                                 vpu_service_dump(pservice);
1789                                 if (task_running) {
1790                                         atomic_set(&session->task_running, 0);
1791                                         atomic_sub(task_running, &pservice->total_running);
1792                                         printk("%d task is running but not return, reset hardware...", task_running);
1793                                         vpu_reset(data);
1794                                         printk("done\n");
1795                                 }
1796                                 vpu_service_session_clear(data, session);
1797                                 mutex_unlock(&pservice->lock);
1798                                 return ret;
1799                         }
1800                 }
1801                 mutex_lock(&pservice->lock);
1802                 reg = list_entry(session->done.next, vpu_reg, session_link);
1803                 return_reg(data, reg, (u32 __user *)req.req);
1804                 mutex_unlock(&pservice->lock);
1805                 break;
1806         }
1807         case VPU_IOC_PROBE_IOMMU_STATUS: {
1808                 int iommu_enable = 0;
1809
1810                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1811
1812 #if defined(CONFIG_VCODEC_MMU)
1813                 iommu_enable = data->mmu_dev ? 1 : 0;
1814 #endif
1815
1816                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1817                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1818                         return -EFAULT;
1819                 }
1820                 break;
1821         }
1822         default : {
1823                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1824                 break;
1825         }
1826         }
1827         vpu_debug_leave();
1828         return 0;
1829 }
1830
1831 #ifdef CONFIG_COMPAT
1832 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1833         unsigned long arg)
1834 {
1835         struct vpu_subdev_data *data =
1836                 container_of(filp->f_dentry->d_inode->i_cdev,
1837                         struct vpu_subdev_data, cdev);
1838         struct vpu_service_info *pservice = data->pservice;
1839         vpu_session *session = (vpu_session *)filp->private_data;
1840         vpu_debug_enter();
1841         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1842                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1843         if (NULL == session)
1844                 return -EINVAL;
1845
1846         switch (cmd) {
1847         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1848                 session->type = (enum VPU_CLIENT_TYPE)arg;
1849                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1850                 break;
1851         }
1852         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1853                 struct compat_vpu_request req;
1854                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1855                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1856                                    sizeof(struct compat_vpu_request))) {
1857                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1858                                 " copy_from_user failed\n");
1859                         return -EFAULT;
1860                 } else {
1861                         if (VPU_ENC != session->type) {
1862                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1863                                                  &pservice->dec_config,
1864                                                  sizeof(struct vpu_dec_config))) {
1865                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1866                                                 "copy_to_user failed type %d\n",
1867                                                 session->type);
1868                                         return -EFAULT;
1869                                 }
1870                         } else {
1871                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1872                                                  &pservice->enc_config,
1873                                                  sizeof(struct vpu_enc_config ))) {
1874                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1875                                                 " copy_to_user failed type %d\n",
1876                                                 session->type);
1877                                         return -EFAULT;
1878                                 }
1879                         }
1880                 }
1881
1882                 break;
1883         }
1884         case COMPAT_VPU_IOC_SET_REG : {
1885                 struct compat_vpu_request req;
1886                 vpu_reg *reg;
1887                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1888                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1889                                    sizeof(struct compat_vpu_request))) {
1890                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1891                         return -EFAULT;
1892                 }
1893                 reg = reg_init(data, session,
1894                                compat_ptr((compat_uptr_t)req.req), req.size);
1895                 if (NULL == reg) {
1896                         return -EFAULT;
1897                 } else {
1898                         mutex_lock(&pservice->lock);
1899                         try_set_reg(data);
1900                         mutex_unlock(&pservice->lock);
1901                 }
1902
1903                 break;
1904         }
1905         case COMPAT_VPU_IOC_GET_REG : {
1906                 struct compat_vpu_request req;
1907                 vpu_reg *reg;
1908                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1909                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1910                                    sizeof(struct compat_vpu_request))) {
1911                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1912                         return -EFAULT;
1913                 } else {
1914                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1915                         if (!list_empty(&session->done)) {
1916                                 if (ret < 0) {
1917                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1918                                 }
1919                                 ret = 0;
1920                         } else {
1921                                 if (unlikely(ret < 0)) {
1922                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1923                                 } else if (0 == ret) {
1924                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1925                                         ret = -ETIMEDOUT;
1926                                 }
1927                         }
1928                         if (ret < 0) {
1929                                 int task_running = atomic_read(&session->task_running);
1930                                 mutex_lock(&pservice->lock);
1931                                 vpu_service_dump(pservice);
1932                                 if (task_running) {
1933                                         atomic_set(&session->task_running, 0);
1934                                         atomic_sub(task_running, &pservice->total_running);
1935                                         printk("%d task is running but not return, reset hardware...", task_running);
1936                                         vpu_reset(data);
1937                                         printk("done\n");
1938                                 }
1939                                 vpu_service_session_clear(data, session);
1940                                 mutex_unlock(&pservice->lock);
1941                                 return ret;
1942                         }
1943                 }
1944                 mutex_lock(&pservice->lock);
1945                 reg = list_entry(session->done.next, vpu_reg, session_link);
1946                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1947                 mutex_unlock(&pservice->lock);
1948                 break;
1949         }
1950         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1951                 int iommu_enable = 0;
1952
1953                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1954 #if defined(CONFIG_VCODEC_MMU)
1955                 iommu_enable = data->mmu_dev ? 1 : 0;
1956 #endif
1957
1958                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1959                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1960                         return -EFAULT;
1961                 }
1962                 break;
1963         }
1964         default : {
1965                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1966                 break;
1967         }
1968         }
1969         vpu_debug_leave();
1970         return 0;
1971 }
1972 #endif
1973
1974 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1975 {
1976         int ret = -EINVAL, i = 0;
1977         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1978         u32 enc_id = *tmp;
1979
1980         enc_id = (enc_id >> 16) & 0xFFFF;
1981         pr_info("checking hw id %x\n", enc_id);
1982         data->hw_info = NULL;
1983         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1984                 if (enc_id == vpu_hw_set[i].hw_id) {
1985                         data->hw_info = &vpu_hw_set[i];
1986                         ret = 0;
1987                         break;
1988                 }
1989         }
1990         iounmap((void *)tmp);
1991         return ret;
1992 }
1993
1994 static int vpu_service_open(struct inode *inode, struct file *filp)
1995 {
1996         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1997         struct vpu_service_info *pservice = data->pservice;
1998         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1999
2000         vpu_debug_enter();
2001
2002         if (NULL == session) {
2003                 vpu_err("error: unable to allocate memory for vpu_session.");
2004                 return -ENOMEM;
2005         }
2006
2007         session->type   = VPU_TYPE_BUTT;
2008         session->pid    = current->pid;
2009         INIT_LIST_HEAD(&session->waiting);
2010         INIT_LIST_HEAD(&session->running);
2011         INIT_LIST_HEAD(&session->done);
2012         INIT_LIST_HEAD(&session->list_session);
2013         init_waitqueue_head(&session->wait);
2014         atomic_set(&session->task_running, 0);
2015         mutex_lock(&pservice->lock);
2016         list_add_tail(&session->list_session, &pservice->session);
2017         filp->private_data = (void *)session;
2018         mutex_unlock(&pservice->lock);
2019
2020         pr_debug("dev opened\n");
2021         vpu_debug_leave();
2022         return nonseekable_open(inode, filp);
2023 }
2024
2025 static int vpu_service_release(struct inode *inode, struct file *filp)
2026 {
2027         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
2028         struct vpu_service_info *pservice = data->pservice;
2029         int task_running;
2030         vpu_session *session = (vpu_session *)filp->private_data;
2031         vpu_debug_enter();
2032         if (NULL == session)
2033                 return -EINVAL;
2034
2035         task_running = atomic_read(&session->task_running);
2036         if (task_running) {
2037                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
2038                 msleep(50);
2039         }
2040         wake_up(&session->wait);
2041
2042         mutex_lock(&pservice->lock);
2043         /* remove this filp from the asynchronusly notified filp's */
2044         list_del_init(&session->list_session);
2045         vpu_service_session_clear(data, session);
2046         kfree(session);
2047         filp->private_data = NULL;
2048         mutex_unlock(&pservice->lock);
2049
2050         pr_debug("dev closed\n");
2051         vpu_debug_leave();
2052         return 0;
2053 }
2054
2055 static const struct file_operations vpu_service_fops = {
2056         .unlocked_ioctl = vpu_service_ioctl,
2057         .open           = vpu_service_open,
2058         .release        = vpu_service_release,
2059 #ifdef CONFIG_COMPAT
2060         .compat_ioctl   = compat_vpu_service_ioctl,
2061 #endif
2062 };
2063
2064 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2065 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2066 static irqreturn_t vepu_irq(int irq, void *dev_id);
2067 static irqreturn_t vepu_isr(int irq, void *dev_id);
2068 static void get_hw_info(struct vpu_subdev_data *data);
2069
2070 #ifdef CONFIG_VCODEC_MMU
2071 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2072 {
2073         struct device_node *dn = NULL;
2074         struct platform_device *pd = NULL;
2075         struct device *ret = NULL ;
2076
2077         dn = of_find_compatible_node(NULL,NULL,compt);
2078         if(!dn) {
2079                 printk("can't find device node %s \r\n",compt);
2080                 return NULL;
2081         }
2082
2083         pd = of_find_device_by_node(dn);
2084         if(!pd) {
2085                 printk("can't find platform device in device node %s\n",compt);
2086                 return  NULL;
2087         }
2088         ret = &pd->dev;
2089
2090         return ret;
2091
2092 }
2093 #ifdef CONFIG_IOMMU_API
2094 static inline void platform_set_sysmmu(struct device *iommu,
2095         struct device *dev)
2096 {
2097         dev->archdata.iommu = iommu;
2098 }
2099 #else
2100 static inline void platform_set_sysmmu(struct device *iommu,
2101         struct device *dev)
2102 {
2103 }
2104 #endif
2105
2106 int vcodec_sysmmu_fault_hdl(struct device *dev,
2107                                 enum rk_iommu_inttype itype,
2108                                 unsigned long pgtable_base,
2109                                 unsigned long fault_addr, unsigned int status)
2110 {
2111         struct platform_device *pdev;
2112         struct vpu_subdev_data *data;
2113         struct vpu_service_info *pservice;
2114
2115         vpu_debug_enter();
2116
2117         pdev = container_of(dev, struct platform_device, dev);
2118
2119         data = platform_get_drvdata(pdev);
2120         pservice = data->pservice;
2121
2122         if (pservice->reg_codec) {
2123                 struct vcodec_mem_region *mem, *n;
2124                 int i = 0;
2125                 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
2126                 list_for_each_entry_safe(mem, n,
2127                                          &pservice->reg_codec->mem_region_list,
2128                                          reg_lnk) {
2129                         vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
2130                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
2131                         i++;
2132                 }
2133
2134                 pr_alert("vcodec, page fault occur, reset hw\n");
2135                 pservice->reg_codec->reg[101] = 1;
2136                 vpu_reset(data);
2137         }
2138
2139         return 0;
2140 }
2141 #endif
2142
2143 #if HEVC_TEST_ENABLE
2144 static int hevc_test_case0(vpu_service_info *pservice);
2145 #endif
2146 #if defined(CONFIG_ION_ROCKCHIP)
2147 extern struct ion_client *rockchip_ion_client_create(const char * name);
2148 #endif
2149
2150 static int vcodec_subdev_probe(struct platform_device *pdev,
2151         struct vpu_service_info *pservice)
2152 {
2153         int ret = 0;
2154         struct resource *res = NULL;
2155         u32 ioaddr = 0;
2156         struct device *dev = &pdev->dev;
2157         char *name = (char*)dev_name(dev);
2158         struct device_node *np = pdev->dev.of_node;
2159         struct vpu_subdev_data *data =
2160                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2161 #if defined(CONFIG_VCODEC_MMU)
2162         u32 iommu_en = 0;
2163         char mmu_dev_dts_name[40];
2164         of_property_read_u32(np, "iommu_enabled", &iommu_en);
2165 #endif
2166         pr_info("probe device %s\n", dev_name(dev));
2167
2168         data->pservice = pservice;
2169         data->dev = dev;
2170
2171         of_property_read_string(np, "name", (const char**)&name);
2172         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2173         /*dev_set_name(dev, name);*/
2174
2175         if (pservice->reg_base == 0) {
2176                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2177                 data->regs = devm_ioremap_resource(dev, res);
2178                 if (IS_ERR(data->regs)) {
2179                         ret = PTR_ERR(data->regs);
2180                         goto err;
2181                 }
2182                 ioaddr = res->start;
2183         } else {
2184                 data->regs = pservice->reg_base;
2185                 ioaddr = pservice->ioaddr;
2186         }
2187
2188         clear_bit(MMU_ACTIVATED, &data->state);
2189         vcodec_enter_mode(data);
2190         ret = vpu_service_check_hw(data, ioaddr);
2191         if (ret < 0) {
2192                 vpu_err("error: hw info check faild\n");
2193                 goto err;
2194         }
2195
2196         data->dec_dev.iosize = data->hw_info->dec_io_size;
2197         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2198         data->reg_size = data->dec_dev.iosize;
2199
2200         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2201                 data->enc_dev.iosize = data->hw_info->enc_io_size;
2202                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2203                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2204         }
2205
2206         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2207         if (data->irq_enc > 0) {
2208                 ret = devm_request_threaded_irq(dev,
2209                         data->irq_enc, vepu_irq, vepu_isr,
2210                         IRQF_SHARED, dev_name(dev),
2211                         (void *)data);
2212                 if (ret) {
2213                         dev_err(dev,
2214                                 "error: can't request vepu irq %d\n",
2215                                 data->irq_enc);
2216                         goto err;
2217                 }
2218         }
2219         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2220         if (data->irq_dec > 0) {
2221                 ret = devm_request_threaded_irq(dev,
2222                         data->irq_dec, vdpu_irq, vdpu_isr,
2223                         IRQF_SHARED, dev_name(dev),
2224                         (void *)data);
2225                 if (ret) {
2226                         dev_err(dev,
2227                                 "error: can't request vdpu irq %d\n",
2228                                 data->irq_dec);
2229                         goto err;
2230                 }
2231         }
2232         atomic_set(&data->dec_dev.irq_count_codec, 0);
2233         atomic_set(&data->dec_dev.irq_count_pp, 0);
2234         atomic_set(&data->enc_dev.irq_count_codec, 0);
2235         atomic_set(&data->enc_dev.irq_count_pp, 0);
2236 #if defined(CONFIG_VCODEC_MMU)
2237         if (iommu_en) {
2238                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2239                         sprintf(mmu_dev_dts_name,
2240                                 HEVC_IOMMU_COMPATIBLE_NAME);
2241                 else
2242                         sprintf(mmu_dev_dts_name,
2243                                 VPU_IOMMU_COMPATIBLE_NAME);
2244
2245                 data->mmu_dev =
2246                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2247
2248                 if (data->mmu_dev)
2249                         platform_set_sysmmu(data->mmu_dev, dev);
2250
2251                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2252         }
2253 #endif
2254         get_hw_info(data);
2255         pservice->auto_freq = true;
2256
2257         vcodec_exit_mode(data);
2258         /* create device node */
2259         ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2260         if (ret) {
2261                 dev_err(dev, "alloc dev_t failed\n");
2262                 goto err;
2263         }
2264
2265         cdev_init(&data->cdev, &vpu_service_fops);
2266
2267         data->cdev.owner = THIS_MODULE;
2268         data->cdev.ops = &vpu_service_fops;
2269
2270         ret = cdev_add(&data->cdev, data->dev_t, 1);
2271
2272         if (ret) {
2273                 dev_err(dev, "add dev_t failed\n");
2274                 goto err;
2275         }
2276
2277         data->cls = class_create(THIS_MODULE, name);
2278
2279         if (IS_ERR(data->cls)) {
2280                 ret = PTR_ERR(data->cls);
2281                 dev_err(dev, "class_create err:%d\n", ret);
2282                 goto err;
2283         }
2284
2285         data->child_dev = device_create(data->cls, dev,
2286                 data->dev_t, NULL, name);
2287
2288         platform_set_drvdata(pdev, data);
2289
2290         INIT_LIST_HEAD(&data->lnk_service);
2291         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2292
2293 #ifdef CONFIG_DEBUG_FS
2294         data->debugfs_dir =
2295                 vcodec_debugfs_create_device_dir((char*)name, parent);
2296         if (data->debugfs_dir == NULL)
2297                 vpu_err("create debugfs dir %s failed\n", name);
2298
2299         data->debugfs_file_regs =
2300                 debugfs_create_file("regs", 0664,
2301                                     data->debugfs_dir, data,
2302                                     &debug_vcodec_fops);
2303 #endif
2304         return 0;
2305 err:
2306         if (data->irq_enc > 0)
2307                 free_irq(data->irq_enc, (void *)data);
2308         if (data->irq_dec > 0)
2309                 free_irq(data->irq_dec, (void *)data);
2310
2311         if (data->child_dev) {
2312                 device_destroy(data->cls, data->dev_t);
2313                 cdev_del(&data->cdev);
2314                 unregister_chrdev_region(data->dev_t, 1);
2315         }
2316
2317         if (data->cls)
2318                 class_destroy(data->cls);
2319         return -1;
2320 }
2321
2322 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2323 {
2324         device_destroy(data->cls, data->dev_t);
2325         class_destroy(data->cls);
2326         cdev_del(&data->cdev);
2327         unregister_chrdev_region(data->dev_t, 1);
2328
2329         free_irq(data->irq_enc, (void *)&data);
2330         free_irq(data->irq_dec, (void *)&data);
2331
2332 #ifdef CONFIG_DEBUG_FS
2333         debugfs_remove_recursive(data->debugfs_dir);
2334 #endif
2335 }
2336
2337 static void vcodec_read_property(struct device_node *np,
2338         struct vpu_service_info *pservice)
2339 {
2340         pservice->mode_bit = 0;
2341         pservice->mode_ctrl = 0;
2342         pservice->subcnt = 0;
2343
2344         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2345
2346         if (pservice->subcnt > 1) {
2347                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2348                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2349         }
2350 #ifdef CONFIG_MFD_SYSCON
2351         pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2352 #else
2353         pservice->grf_base = (u32*)RK_GRF_VIRT;
2354 #endif
2355         if (IS_ERR(pservice->grf_base)) {
2356 #ifdef CONFIG_ARM
2357                 pservice->grf_base = RK_GRF_VIRT;
2358 #else
2359                 vpu_err("can't find vpu grf property\n");
2360                 return;
2361 #endif
2362         }
2363
2364 #ifdef CONFIG_RESET_CONTROLLER
2365         pservice->rst_a = devm_reset_control_get(pservice->dev, "video_a");
2366         pservice->rst_h = devm_reset_control_get(pservice->dev, "video_h");
2367         pservice->rst_v = devm_reset_control_get(pservice->dev, "video");
2368
2369         if (IS_ERR_OR_NULL(pservice->rst_a)) {
2370                 pr_warn("No reset resource define\n");
2371                 pservice->rst_a = NULL;
2372         }
2373
2374         if (IS_ERR_OR_NULL(pservice->rst_h)) {
2375                 pr_warn("No reset resource define\n");
2376                 pservice->rst_h = NULL;
2377         }
2378
2379         if (IS_ERR_OR_NULL(pservice->rst_v)) {
2380                 pr_warn("No reset resource define\n");
2381                 pservice->rst_v = NULL;
2382         }
2383 #endif
2384
2385         of_property_read_string(np, "name", (const char**)&pservice->name);
2386 }
2387
2388 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2389 {
2390         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2391         pservice->curr_mode = -1;
2392
2393         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2394         INIT_LIST_HEAD(&pservice->waiting);
2395         INIT_LIST_HEAD(&pservice->running);
2396         mutex_init(&pservice->lock);
2397
2398         INIT_LIST_HEAD(&pservice->done);
2399         INIT_LIST_HEAD(&pservice->session);
2400         INIT_LIST_HEAD(&pservice->subdev_list);
2401
2402         pservice->reg_pproc     = NULL;
2403         atomic_set(&pservice->total_running, 0);
2404         atomic_set(&pservice->enabled,       0);
2405         atomic_set(&pservice->power_on_cnt,  0);
2406         atomic_set(&pservice->power_off_cnt, 0);
2407         atomic_set(&pservice->reset_request, 0);
2408
2409         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2410
2411         pservice->ion_client = rockchip_ion_client_create("vpu");
2412         if (IS_ERR(pservice->ion_client)) {
2413                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2414                         PTR_ERR(pservice->ion_client));
2415         } else {
2416                 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2417         }
2418 }
2419
2420 static int vcodec_probe(struct platform_device *pdev)
2421 {
2422         int i;
2423         int ret = 0;
2424         struct resource *res = NULL;
2425         struct device *dev = &pdev->dev;
2426         struct device_node *np = pdev->dev.of_node;
2427         struct vpu_service_info *pservice =
2428                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2429
2430         pr_info("probe device %s\n", dev_name(dev));
2431
2432         pservice->dev = dev;
2433
2434         vcodec_read_property(np, pservice);
2435         vcodec_init_drvdata(pservice);
2436
2437         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2438                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2439         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2440                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2441         else
2442                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2443
2444         if (0 > vpu_get_clk(pservice))
2445                 goto err;
2446
2447         vpu_service_power_on(pservice);
2448
2449         if (of_property_read_bool(np, "reg")) {
2450                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2451
2452                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2453                 if (IS_ERR(pservice->reg_base)) {
2454                         vpu_err("ioremap registers base failed\n");
2455                         ret = PTR_ERR(pservice->reg_base);
2456                         goto err;
2457                 }
2458                 pservice->ioaddr = res->start;
2459         } else {
2460                 pservice->reg_base = 0;
2461         }
2462
2463         if (of_property_read_bool(np, "subcnt")) {
2464                 for (i = 0; i<pservice->subcnt; i++) {
2465                         struct device_node *sub_np;
2466                         struct platform_device *sub_pdev;
2467                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2468                         sub_pdev = of_find_device_by_node(sub_np);
2469
2470                         vcodec_subdev_probe(sub_pdev, pservice);
2471                 }
2472         } else {
2473                 vcodec_subdev_probe(pdev, pservice);
2474         }
2475         platform_set_drvdata(pdev, pservice);
2476
2477         vpu_service_power_off(pservice);
2478
2479         pr_info("init success\n");
2480
2481         return 0;
2482
2483 err:
2484         pr_info("init failed\n");
2485         vpu_service_power_off(pservice);
2486         vpu_put_clk(pservice);
2487         wake_lock_destroy(&pservice->wake_lock);
2488
2489         if (res)
2490                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2491
2492         return ret;
2493 }
2494
2495 static int vcodec_remove(struct platform_device *pdev)
2496 {
2497         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2498         struct resource *res;
2499         struct vpu_subdev_data *data, *n;
2500
2501         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2502                 vcodec_subdev_remove(data);
2503         }
2504
2505         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2506         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2507         vpu_put_clk(pservice);
2508         wake_lock_destroy(&pservice->wake_lock);
2509
2510         return 0;
2511 }
2512
2513 #if defined(CONFIG_OF)
2514 static const struct of_device_id vcodec_service_dt_ids[] = {
2515         {.compatible = "vpu_service",},
2516         {.compatible = "rockchip,hevc_service",},
2517         {.compatible = "rockchip,vpu_combo",},
2518         {},
2519 };
2520 #endif
2521
2522 static struct platform_driver vcodec_driver = {
2523         .probe = vcodec_probe,
2524         .remove = vcodec_remove,
2525         .driver = {
2526                 .name = "vcodec",
2527                 .owner = THIS_MODULE,
2528 #if defined(CONFIG_OF)
2529                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2530 #endif
2531         },
2532 };
2533
2534 static void get_hw_info(struct vpu_subdev_data *data)
2535 {
2536         struct vpu_service_info *pservice = data->pservice;
2537         struct vpu_dec_config *dec = &pservice->dec_config;
2538         struct vpu_enc_config *enc = &pservice->enc_config;
2539         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2540                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2541                 u32 asicID      = data->dec_dev.hwregs[0];
2542
2543                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2544                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2545                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2546                         dec->jpegSupport = JPEG_PROGRESSIVE;
2547                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2548                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2549                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2550                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2551                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2552                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2553
2554                 dec->maxDecPicWidth = 4096;
2555
2556                 /* 2nd Config register */
2557                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2558                 if (dec->refBufSupport) {
2559                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2560                                 dec->refBufSupport |= 2;
2561                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2562                                 dec->refBufSupport |= 4;
2563                 }
2564                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2565                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2566                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2567                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2568
2569                 /* JPEG xtensions */
2570                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2571                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2572                 else
2573                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2574
2575                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2576                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2577                 else
2578                         dec->rvSupport = RV_NOT_SUPPORTED;
2579                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2580
2581                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2582                         dec->refBufSupport |= 8; /* enable HW support for offset */
2583
2584                 if (!cpu_is_rk3036()) {
2585                         configReg = data->enc_dev.hwregs[63];
2586                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2587                         enc->h264Enabled = (configReg >> 27) & 1;
2588                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2589                         enc->jpegEnabled = (configReg >> 25) & 1;
2590                         enc->vsEnabled = (configReg >> 24) & 1;
2591                         enc->rgbEnabled = (configReg >> 28) & 1;
2592                         enc->reg_size = data->reg_size;
2593                         enc->reserv[0] = enc->reserv[1] = 0;
2594                 }
2595                 pservice->auto_freq = true;
2596                 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2597                 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2598
2599                 pservice->bug_dec_addr = cpu_is_rk30xx();
2600         } else {
2601                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2602                         dec->maxDecPicWidth = 1920;
2603                 else
2604                         dec->maxDecPicWidth = 4096;
2605                 /* disable frequency switch in hevc.*/
2606                 pservice->auto_freq = false;
2607         }
2608 }
2609
2610 static bool check_irq_err(task_info *task, u32 irq_status)
2611 {
2612         return (task->error_mask & irq_status) ? true : false;
2613 }
2614
2615 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2616 {
2617         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2618         struct vpu_service_info *pservice = data->pservice;
2619         vpu_device *dev = &data->dec_dev;
2620         u32 raw_status;
2621         u32 dec_status;
2622
2623         /*vcodec_enter_mode(data);*/
2624
2625         dec_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2626
2627         if (dec_status & DEC_INTERRUPT_BIT) {
2628                 time_record(&tasks[TASK_VPU_DEC], 1);
2629                 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", dec_status);
2630                 if ((dec_status & 0x40001) == 0x40001) {
2631                         do {
2632                                 dec_status =
2633                                         readl(dev->hwregs +
2634                                                 DEC_INTERRUPT_REGISTER);
2635                         } while ((dec_status & 0x40001) == 0x40001);
2636                 }
2637
2638                 if (check_irq_err((data->hw_info->hw_id == HEVC_ID)?
2639                                         (&tasks[TASK_RKDEC_HEVC]) : (&tasks[TASK_VPU_DEC]),
2640                                         dec_status)) {
2641                         atomic_add(1, &pservice->reset_request);
2642                 }
2643
2644                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2645                 atomic_add(1, &dev->irq_count_codec);
2646                 time_diff(&tasks[TASK_VPU_DEC]);
2647         }
2648
2649         if (data->hw_info->hw_id != HEVC_ID) {
2650                 u32 pp_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2651                 if (pp_status & PP_INTERRUPT_BIT) {
2652                         time_record(&tasks[TASK_VPU_PP], 1);
2653                         vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", pp_status);
2654
2655                         if (check_irq_err(&tasks[TASK_VPU_PP], dec_status))
2656                                 atomic_add(1, &pservice->reset_request);
2657
2658                         /* clear pp IRQ */
2659                         writel(pp_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2660                         atomic_add(1, &dev->irq_count_pp);
2661                         time_diff(&tasks[TASK_VPU_PP]);
2662                 }
2663         }
2664
2665         pservice->irq_status = raw_status;
2666
2667         /*vcodec_exit_mode(pservice);*/
2668
2669         if (atomic_read(&dev->irq_count_pp) ||
2670             atomic_read(&dev->irq_count_codec))
2671                 return IRQ_WAKE_THREAD;
2672         else
2673                 return IRQ_NONE;
2674 }
2675
2676 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2677 {
2678         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2679         struct vpu_service_info *pservice = data->pservice;
2680         vpu_device *dev = &data->dec_dev;
2681
2682         mutex_lock(&pservice->lock);
2683         if (atomic_read(&dev->irq_count_codec)) {
2684                 atomic_sub(1, &dev->irq_count_codec);
2685                 if (NULL == pservice->reg_codec) {
2686                         vpu_err("error: dec isr with no task waiting\n");
2687                 } else {
2688                         reg_from_run_to_done(data, pservice->reg_codec);
2689                         /* avoid vpu timeout and can't recover problem */
2690                         VDPU_SOFT_RESET(data->regs);
2691                 }
2692         }
2693
2694         if (atomic_read(&dev->irq_count_pp)) {
2695                 atomic_sub(1, &dev->irq_count_pp);
2696                 if (NULL == pservice->reg_pproc) {
2697                         vpu_err("error: pp isr with no task waiting\n");
2698                 } else {
2699                         reg_from_run_to_done(data, pservice->reg_pproc);
2700                 }
2701         }
2702         try_set_reg(data);
2703         mutex_unlock(&pservice->lock);
2704         return IRQ_HANDLED;
2705 }
2706
2707 static irqreturn_t vepu_irq(int irq, void *dev_id)
2708 {
2709         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2710         struct vpu_service_info *pservice = data->pservice;
2711         vpu_device *dev = &data->enc_dev;
2712         u32 irq_status;
2713
2714         /*vcodec_enter_mode(data);*/
2715         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2716
2717         vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2718
2719         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2720                 time_record(&tasks[TASK_VPU_ENC], 1);
2721
2722                 if (check_irq_err(&tasks[TASK_VPU_ENC], irq_status))
2723                         atomic_add(1, &pservice->reset_request);
2724
2725                 /* clear enc IRQ */
2726                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2727                 atomic_add(1, &dev->irq_count_codec);
2728                 time_diff(&tasks[TASK_VPU_ENC]);
2729         }
2730
2731         pservice->irq_status = irq_status;
2732
2733         /*vcodec_exit_mode(pservice);*/
2734
2735         if (atomic_read(&dev->irq_count_codec))
2736                 return IRQ_WAKE_THREAD;
2737         else
2738                 return IRQ_NONE;
2739 }
2740
2741 static irqreturn_t vepu_isr(int irq, void *dev_id)
2742 {
2743         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2744         struct vpu_service_info *pservice = data->pservice;
2745         vpu_device *dev = &data->enc_dev;
2746
2747         mutex_lock(&pservice->lock);
2748         if (atomic_read(&dev->irq_count_codec)) {
2749                 atomic_sub(1, &dev->irq_count_codec);
2750                 if (NULL == pservice->reg_codec) {
2751                         vpu_err("error: enc isr with no task waiting\n");
2752                 } else {
2753                         reg_from_run_to_done(data, pservice->reg_codec);
2754                 }
2755         }
2756         try_set_reg(data);
2757         mutex_unlock(&pservice->lock);
2758         return IRQ_HANDLED;
2759 }
2760
2761 static int __init vcodec_service_init(void)
2762 {
2763         int ret;
2764
2765         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2766                 vpu_err("Platform device register failed (%d).\n", ret);
2767                 return ret;
2768         }
2769
2770 #ifdef CONFIG_DEBUG_FS
2771         vcodec_debugfs_init();
2772 #endif
2773
2774         return ret;
2775 }
2776
2777 static void __exit vcodec_service_exit(void)
2778 {
2779 #ifdef CONFIG_DEBUG_FS
2780         vcodec_debugfs_exit();
2781 #endif
2782
2783         platform_driver_unregister(&vcodec_driver);
2784 }
2785
2786 module_init(vcodec_service_init);
2787 module_exit(vcodec_service_exit);
2788
2789 #ifdef CONFIG_DEBUG_FS
2790 #include <linux/seq_file.h>
2791
2792 static int vcodec_debugfs_init()
2793 {
2794         parent = debugfs_create_dir("vcodec", NULL);
2795         if (!parent)
2796                 return -1;
2797
2798         return 0;
2799 }
2800
2801 static void vcodec_debugfs_exit()
2802 {
2803         debugfs_remove(parent);
2804 }
2805
2806 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2807 {
2808         return debugfs_create_dir(dirname, parent);
2809 }
2810
2811 static int debug_vcodec_show(struct seq_file *s, void *unused)
2812 {
2813         struct vpu_subdev_data *data = s->private;
2814         struct vpu_service_info *pservice = data->pservice;
2815         unsigned int i, n;
2816         vpu_reg *reg, *reg_tmp;
2817         vpu_session *session, *session_tmp;
2818
2819         mutex_lock(&pservice->lock);
2820         vpu_service_power_on(pservice);
2821         if (data->hw_info->hw_id != HEVC_ID) {
2822                 seq_printf(s, "\nENC Registers:\n");
2823                 n = data->enc_dev.iosize >> 2;
2824                 for (i = 0; i < n; i++)
2825                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2826         }
2827         seq_printf(s, "\nDEC Registers:\n");
2828         n = data->dec_dev.iosize >> 2;
2829         for (i = 0; i < n; i++)
2830                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2831
2832         seq_printf(s, "\nvpu service status:\n");
2833         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2834                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2835                 /*seq_printf(s, "waiting reg set %d\n");*/
2836                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2837                         seq_printf(s, "waiting register set\n");
2838                 }
2839                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2840                         seq_printf(s, "running register set\n");
2841                 }
2842                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2843                         seq_printf(s, "done    register set\n");
2844                 }
2845         }
2846
2847         seq_printf(s, "\npower counter: on %d off %d\n",
2848                         atomic_read(&pservice->power_on_cnt),
2849                         atomic_read(&pservice->power_off_cnt));
2850         mutex_unlock(&pservice->lock);
2851         vpu_service_power_off(pservice);
2852
2853         return 0;
2854 }
2855
2856 static int debug_vcodec_open(struct inode *inode, struct file *file)
2857 {
2858         return single_open(file, debug_vcodec_show, inode->i_private);
2859 }
2860
2861 #endif
2862
2863 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2864 #include "hevc_test_inc/pps_00.h"
2865 #include "hevc_test_inc/register_00.h"
2866 #include "hevc_test_inc/rps_00.h"
2867 #include "hevc_test_inc/scaling_list_00.h"
2868 #include "hevc_test_inc/stream_00.h"
2869
2870 #include "hevc_test_inc/pps_01.h"
2871 #include "hevc_test_inc/register_01.h"
2872 #include "hevc_test_inc/rps_01.h"
2873 #include "hevc_test_inc/scaling_list_01.h"
2874 #include "hevc_test_inc/stream_01.h"
2875
2876 #include "hevc_test_inc/cabac.h"
2877
2878 extern struct ion_client *rockchip_ion_client_create(const char * name);
2879
2880 static struct ion_client *ion_client = NULL;
2881 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2882 {
2883         int size = (len+15) & (~15);
2884         struct ion_handle *handle;
2885         u8 *ptr;
2886
2887         if (ion_client == NULL)
2888                 ion_client = rockchip_ion_client_create("vcodec");
2889
2890         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2891
2892         ptr = ion_map_kernel(ion_client, handle);
2893
2894         ion_phys(ion_client, handle, phy, &size);
2895
2896         memcpy(ptr, tbl, len);
2897
2898         return ptr;
2899 }
2900
2901 u8* get_align_ptr_no_copy(int len, u32 *phy)
2902 {
2903         int size = (len+15) & (~15);
2904         struct ion_handle *handle;
2905         u8 *ptr;
2906
2907         if (ion_client == NULL)
2908                 ion_client = rockchip_ion_client_create("vcodec");
2909
2910         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2911
2912         ptr = ion_map_kernel(ion_client, handle);
2913
2914         ion_phys(ion_client, handle, phy, &size);
2915
2916         return ptr;
2917 }
2918
2919 #define TEST_CNT    2
2920 static int hevc_test_case0(vpu_service_info *pservice)
2921 {
2922         vpu_session session;
2923         vpu_reg *reg;
2924         unsigned long size = 272;
2925         int testidx = 0;
2926         int ret = 0;
2927         u8 *pps_tbl[TEST_CNT];
2928         u8 *register_tbl[TEST_CNT];
2929         u8 *rps_tbl[TEST_CNT];
2930         u8 *scaling_list_tbl[TEST_CNT];
2931         u8 *stream_tbl[TEST_CNT];
2932
2933         int stream_size[2];
2934         int pps_size[2];
2935         int rps_size[2];
2936         int scl_size[2];
2937         int cabac_size[2];
2938
2939         u32 phy_pps;
2940         u32 phy_rps;
2941         u32 phy_scl;
2942         u32 phy_str;
2943         u32 phy_yuv;
2944         u32 phy_ref;
2945         u32 phy_cabac;
2946
2947         volatile u8 *stream_buf;
2948         volatile u8 *pps_buf;
2949         volatile u8 *rps_buf;
2950         volatile u8 *scl_buf;
2951         volatile u8 *yuv_buf;
2952         volatile u8 *cabac_buf;
2953         volatile u8 *ref_buf;
2954
2955         u8 *pps;
2956         u8 *yuv[2];
2957         int i;
2958
2959         pps_tbl[0] = pps_00;
2960         pps_tbl[1] = pps_01;
2961
2962         register_tbl[0] = register_00;
2963         register_tbl[1] = register_01;
2964
2965         rps_tbl[0] = rps_00;
2966         rps_tbl[1] = rps_01;
2967
2968         scaling_list_tbl[0] = scaling_list_00;
2969         scaling_list_tbl[1] = scaling_list_01;
2970
2971         stream_tbl[0] = stream_00;
2972         stream_tbl[1] = stream_01;
2973
2974         stream_size[0] = sizeof(stream_00);
2975         stream_size[1] = sizeof(stream_01);
2976
2977         pps_size[0] = sizeof(pps_00);
2978         pps_size[1] = sizeof(pps_01);
2979
2980         rps_size[0] = sizeof(rps_00);
2981         rps_size[1] = sizeof(rps_01);
2982
2983         scl_size[0] = sizeof(scaling_list_00);
2984         scl_size[1] = sizeof(scaling_list_01);
2985
2986         cabac_size[0] = sizeof(Cabac_table);
2987         cabac_size[1] = sizeof(Cabac_table);
2988
2989         /* create session */
2990         session.pid = current->pid;
2991         session.type = VPU_DEC;
2992         INIT_LIST_HEAD(&session.waiting);
2993         INIT_LIST_HEAD(&session.running);
2994         INIT_LIST_HEAD(&session.done);
2995         INIT_LIST_HEAD(&session.list_session);
2996         init_waitqueue_head(&session.wait);
2997         atomic_set(&session.task_running, 0);
2998         list_add_tail(&session.list_session, &pservice->session);
2999
3000         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
3001         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
3002
3003         while (testidx < TEST_CNT) {
3004                 /* create registers */
3005                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
3006                 if (NULL == reg) {
3007                         vpu_err("error: kmalloc fail in reg_init\n");
3008                         return -1;
3009                 }
3010
3011                 if (size > pservice->reg_size) {
3012                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
3013                         size = pservice->reg_size;
3014                 }
3015                 reg->session = &session;
3016                 reg->type = session.type;
3017                 reg->size = size;
3018                 reg->freq = VPU_FREQ_DEFAULT;
3019                 reg->reg = (unsigned long *)&reg[1];
3020                 INIT_LIST_HEAD(&reg->session_link);
3021                 INIT_LIST_HEAD(&reg->status_link);
3022
3023                 /* TODO: stuff registers */
3024                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
3025
3026                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
3027                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
3028                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
3029                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
3030                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
3031
3032                 pps = pps_buf;
3033
3034                 /* TODO: replace reigster address */
3035                 for (i=0; i<64; i++) {
3036                         u32 scaling_offset;
3037                         u32 tmp;
3038
3039                         scaling_offset = (u32)pps[i*80+74];
3040                         scaling_offset += (u32)pps[i*80+75] << 8;
3041                         scaling_offset += (u32)pps[i*80+76] << 16;
3042                         scaling_offset += (u32)pps[i*80+77] << 24;
3043
3044                         tmp = phy_scl + scaling_offset;
3045
3046                         pps[i*80+74] = tmp & 0xff;
3047                         pps[i*80+75] = (tmp >> 8) & 0xff;
3048                         pps[i*80+76] = (tmp >> 16) & 0xff;
3049                         pps[i*80+77] = (tmp >> 24) & 0xff;
3050                 }
3051
3052                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
3053                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
3054
3055                 reg->reg[1] = 0x21;
3056                 reg->reg[4] = phy_str;
3057                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
3058                 reg->reg[6] = phy_cabac;
3059                 reg->reg[7] = testidx?phy_ref:phy_yuv;
3060                 reg->reg[42] = phy_pps;
3061                 reg->reg[43] = phy_rps;
3062                 for (i = 10; i <= 24; i++)
3063                         reg->reg[i] = phy_yuv;
3064
3065                 mutex_lock(pservice->lock);
3066                 list_add_tail(&reg->status_link, &pservice->waiting);
3067                 list_add_tail(&reg->session_link, &session.waiting);
3068                 mutex_unlock(pservice->lock);
3069
3070                 /* stuff hardware */
3071                 try_set_reg(data);
3072
3073                 /* wait for result */
3074                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
3075                 if (!list_empty(&session.done)) {
3076                         if (ret < 0)
3077                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
3078                         ret = 0;
3079                 } else {
3080                         if (unlikely(ret < 0)) {
3081                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
3082                         } else if (0 == ret) {
3083                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
3084                                 ret = -ETIMEDOUT;
3085                         }
3086                 }
3087                 if (ret < 0) {
3088                         int task_running = atomic_read(&session.task_running);
3089                         int n;
3090                         mutex_lock(pservice->lock);
3091                         vpu_service_dump(pservice);
3092                         if (task_running) {
3093                                 atomic_set(&session.task_running, 0);
3094                                 atomic_sub(task_running, &pservice->total_running);
3095                                 printk("%d task is running but not return, reset hardware...", task_running);
3096                                 vpu_reset(data);
3097                                 printk("done\n");
3098                         }
3099                         vpu_service_session_clear(pservice, &session);
3100                         mutex_unlock(pservice->lock);
3101
3102                         printk("\nDEC Registers:\n");
3103                         n = data->dec_dev.iosize >> 2;
3104                         for (i=0; i<n; i++)
3105                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
3106
3107                         vpu_err("test index %d failed\n", testidx);
3108                         break;
3109                 } else {
3110                         vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
3111
3112                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
3113
3114                         for (i=0; i<68; i++) {
3115                                 if (i % 4 == 0)
3116                                         printk("%02d: ", i);
3117                                 printk("%08x ", reg->reg[i]);
3118                                 if ((i+1) % 4 == 0)
3119                                         printk("\n");
3120                         }
3121
3122                         testidx++;
3123                 }
3124
3125                 reg_deinit(data, reg);
3126         }
3127
3128         return 0;
3129 }
3130
3131 #endif
3132