arch/arm/mach-rockchip/vcodec_service.c

   1
   2 /* arch/arm/mach-rk29/vpu.c
   3  *
   4  * Copyright (C) 2010 ROCKCHIP, Inc.
   5  * author: chenhengming chm@rock-chips.com
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/fs.h>
  26 #include <linux/ioport.h>
  27 #include <linux/miscdevice.h>
  28 #include <linux/mm.h>
  29 #include <linux/poll.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/sched.h>
  32 #include <linux/slab.h>
  33 #include <linux/wakelock.h>
  34 #include <linux/cdev.h>
  35 #include <linux/of.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39
  40 #include <asm/cacheflush.h>
  41 #include <linux/uaccess.h>
  42 #include <linux/rockchip/grf.h>
  43
  44 #if defined(CONFIG_ION_ROCKCHIP)
  45 #include <linux/rockchip_ion.h>
  46 #endif
  47
  48 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  49 #define CONFIG_VCODEC_MMU
  50 #endif
  51
  52 #ifdef CONFIG_VCODEC_MMU
  53 #include <linux/rockchip-iovmm.h>
  54 #include <linux/dma-buf.h>
  55 #endif
  56
  57 #ifdef CONFIG_DEBUG_FS
  58 #include <linux/debugfs.h>
  59 #endif
  60
  61 #if defined(CONFIG_ARCH_RK319X)
  62 #include <mach/grf.h>
  63 #endif
  64
  65 #include "vcodec_service.h"
  66
  67 #define HEVC_TEST_ENABLE        0
  68 #define HEVC_SIM_ENABLE         0
  69 #define VCODEC_CLOCK_ENABLE     1
  70
  71 typedef enum {
  72         VPU_DEC_ID_9190         = 0x6731,
  73         VPU_ID_8270             = 0x8270,
  74         VPU_ID_4831             = 0x4831,
  75         HEVC_ID                 = 0x6867,
  76 } VPU_HW_ID;
  77
  78 typedef enum {
  79         VPU_DEC_TYPE_9190       = 0,
  80         VPU_ENC_TYPE_8270       = 0x100,
  81         VPU_ENC_TYPE_4831       ,
  82 } VPU_HW_TYPE_E;
  83
  84 typedef enum VPU_FREQ {
  85         VPU_FREQ_200M,
  86         VPU_FREQ_266M,
  87         VPU_FREQ_300M,
  88         VPU_FREQ_400M,
  89         VPU_FREQ_500M,
  90         VPU_FREQ_600M,
  91         VPU_FREQ_DEFAULT,
  92         VPU_FREQ_BUT,
  93 } VPU_FREQ;
  94
  95 typedef struct {
  96         VPU_HW_ID               hw_id;
  97         unsigned long           hw_addr;
  98         unsigned long           enc_offset;
  99         unsigned long           enc_reg_num;
 100         unsigned long           enc_io_size;
 101         unsigned long           dec_offset;
 102         unsigned long           dec_reg_num;
 103         unsigned long           dec_io_size;
 104 } VPU_HW_INFO_E;
 105
 106 struct extra_info_elem {
 107         u32 index;
 108         u32 offset;
 109 };
 110
 111 #define EXTRA_INFO_MAGIC        0x4C4A46
 112
 113 struct extra_info_for_iommu {
 114         u32 magic;
 115         u32 cnt;
 116         struct extra_info_elem elem[20];
 117 };
 118
 119 #define VPU_SERVICE_SHOW_TIME                   0
 120
 121 #if VPU_SERVICE_SHOW_TIME
 122 static struct timeval enc_start, enc_end;
 123 static struct timeval dec_start, dec_end;
 124 static struct timeval pp_start,  pp_end;
 125 #endif
 126
 127 #define MHZ                                     (1000*1000)
 128
 129 #define REG_NUM_9190_DEC                        (60)
 130 #define REG_NUM_9190_PP                         (41)
 131 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 132
 133 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 134
 135 #define REG_NUM_ENC_8270                        (96)
 136 #define REG_SIZE_ENC_8270                       (0x200)
 137 #define REG_NUM_ENC_4831                        (164)
 138 #define REG_SIZE_ENC_4831                       (0x400)
 139
 140 #define REG_NUM_HEVC_DEC                        (68)
 141
 142 #define SIZE_REG(reg)                           ((reg)*4)
 143
 144 static VPU_HW_INFO_E vpu_hw_set[] = {
 145         [0] = {
 146                 .hw_id          = VPU_ID_8270,
 147                 .hw_addr        = 0,
 148                 .enc_offset     = 0x0,
 149                 .enc_reg_num    = REG_NUM_ENC_8270,
 150                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 151                 .dec_offset     = REG_SIZE_ENC_8270,
 152                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 153                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 154         },
 155         [1] = {
 156                 .hw_id          = VPU_ID_4831,
 157                 .hw_addr        = 0,
 158                 .enc_offset     = 0x0,
 159                 .enc_reg_num    = REG_NUM_ENC_4831,
 160                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 161                 .dec_offset     = REG_SIZE_ENC_4831,
 162                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 163                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 164         },
 165         [2] = {
 166                 .hw_id          = HEVC_ID,
 167                 .hw_addr        = 0,
 168                 .dec_offset     = 0x0,
 169                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 170                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 171         },
 172         [3] = {
 173                 .hw_id          = VPU_DEC_ID_9190,
 174                 .hw_addr        = 0,
 175                 .enc_offset     = 0x0,
 176                 .enc_reg_num    = 0,
 177                 .enc_io_size    = 0,
 178                 .dec_offset     = REG_SIZE_ENC_4831,
 179                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 180                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 181         },
 182
 183 };
 184
 185
 186 #define DEC_INTERRUPT_REGISTER                  1
 187 #define PP_INTERRUPT_REGISTER                   60
 188 #define ENC_INTERRUPT_REGISTER                  1
 189
 190 #define DEC_INTERRUPT_BIT                       0x100
 191 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 192 #define PP_INTERRUPT_BIT                        0x100
 193 #define ENC_INTERRUPT_BIT                       0x1
 194
 195 #define HEVC_DEC_INT_RAW_BIT                    0x200
 196 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 197 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 198 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 199
 200 #define VPU_REG_EN_ENC                          14
 201 #define VPU_REG_ENC_GATE                        2
 202 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 203
 204 #define VPU_REG_EN_DEC                          1
 205 #define VPU_REG_DEC_GATE                        2
 206 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 207 #define VPU_REG_EN_PP                           0
 208 #define VPU_REG_PP_GATE                         1
 209 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 210 #define VPU_REG_EN_DEC_PP                       1
 211 #define VPU_REG_DEC_PP_GATE                     61
 212 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 213
 214 #if defined(CONFIG_VCODEC_MMU)
 215 static u8 addr_tbl_vpu_h264dec[] = {
 216         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 217         25, 26, 27, 28, 29, 40, 41
 218 };
 219
 220 static u8 addr_tbl_vpu_vp8dec[] = {
 221         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 222 };
 223
 224 static u8 addr_tbl_vpu_vp6dec[] = {
 225         12, 13, 14, 18, 27, 40
 226 };
 227
 228 static u8 addr_tbl_vpu_vc1dec[] = {
 229         12, 13, 14, 15, 16, 17, 27, 41
 230 };
 231
 232 static u8 addr_tbl_vpu_jpegdec[] = {
 233         12, 40, 66, 67
 234 };
 235
 236 static u8 addr_tbl_vpu_defaultdec[] = {
 237         12, 13, 14, 15, 16, 17, 40, 41
 238 };
 239
 240 static u8 addr_tbl_vpu_enc[] = {
 241         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 242 };
 243
 244 static u8 addr_tbl_hevc_dec[] = {
 245         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 246         21, 22, 23, 24, 42, 43
 247 };
 248 #endif
 249
 250 enum VPU_DEC_FMT {
 251         VPU_DEC_FMT_H264,
 252         VPU_DEC_FMT_MPEG4,
 253         VPU_DEC_FMT_H263,
 254         VPU_DEC_FMT_JPEG,
 255         VPU_DEC_FMT_VC1,
 256         VPU_DEC_FMT_MPEG2,
 257         VPU_DEC_FMT_MPEG1,
 258         VPU_DEC_FMT_VP6,
 259         VPU_DEC_FMT_RV,
 260         VPU_DEC_FMT_VP7,
 261         VPU_DEC_FMT_VP8,
 262         VPU_DEC_FMT_AVS,
 263         VPU_DEC_FMT_SVC,
 264         VPU_DEC_FMT_VC2,
 265         VPU_DEC_FMT_MVC,
 266         VPU_DEC_FMT_THEORA,
 267         VPU_DEC_FMT_RES
 268 };
 269
 270 /**
 271  * struct for process session which connect to vpu
 272  *
 273  * @author ChenHengming (2011-5-3)
 274  */
 275 typedef struct vpu_session {
 276         VPU_CLIENT_TYPE         type;
 277         /* a linked list of data so we can access them for debugging */
 278         struct list_head        list_session;
 279         /* a linked list of register data waiting for process */
 280         struct list_head        waiting;
 281         /* a linked list of register data in processing */
 282         struct list_head        running;
 283         /* a linked list of register data processed */
 284         struct list_head        done;
 285         wait_queue_head_t       wait;
 286         pid_t                   pid;
 287         atomic_t                task_running;
 288 } vpu_session;
 289
 290 /**
 291  * struct for process register set
 292  *
 293  * @author ChenHengming (2011-5-4)
 294  */
 295 typedef struct vpu_reg {
 296         VPU_CLIENT_TYPE         type;
 297         VPU_FREQ                freq;
 298         vpu_session             *session;
 299         struct list_head        session_link;           /* link to vpu service session */
 300         struct list_head        status_link;            /* link to register set list */
 301         unsigned long           size;
 302 #if defined(CONFIG_VCODEC_MMU)
 303         struct list_head        mem_region_list;
 304 #endif
 305         unsigned long           *reg;
 306 } vpu_reg;
 307
 308 typedef struct vpu_device {
 309         atomic_t                irq_count_codec;
 310         atomic_t                irq_count_pp;
 311         unsigned long           iobaseaddr;
 312         unsigned int            iosize;
 313         volatile u32            *hwregs;
 314 } vpu_device;
 315
 316 enum vcodec_device_id {
 317         VCODEC_DEVICE_ID_VPU,
 318         VCODEC_DEVICE_ID_HEVC
 319 };
 320
 321 struct vcodec_mem_region {
 322         struct list_head srv_lnk;
 323         struct list_head reg_lnk;
 324         struct list_head session_lnk;
 325         unsigned long iova;     /* virtual address for iommu */
 326         unsigned long len;
 327         u32 reg_idx;
 328         struct ion_handle *hdl;
 329 };
 330
 331 typedef struct vpu_service_info {
 332         struct wake_lock        wake_lock;
 333         struct delayed_work     power_off_work;
 334         struct mutex            *lock;
 335         struct list_head        *waiting;               /* link to link_reg in struct vpu_reg */
 336         struct list_head        *running;               /* link to link_reg in struct vpu_reg */
 337         struct list_head        done;                   /* link to link_reg in struct vpu_reg */
 338         struct list_head        session;                /* link to list_session in struct vpu_session */
 339         atomic_t                total_running;
 340         bool                    enabled;
 341         vpu_reg                 **reg_codec;
 342         vpu_reg                 *reg_pproc;
 343         vpu_reg                 *reg_resev;
 344         VPUHwDecConfig_t        dec_config;
 345         VPUHwEncConfig_t        enc_config;
 346         VPU_HW_INFO_E           *hw_info;
 347         unsigned long           reg_size;
 348         bool                    auto_freq;
 349         bool                    bug_dec_addr;
 350         atomic_t                freq_status;
 351
 352         struct clk              *aclk_vcodec;
 353         struct clk              *hclk_vcodec;
 354         struct clk              *clk_core;
 355         struct clk              *clk_cabac;
 356         struct clk              *pd_video;
 357
 358         int                     irq_dec;
 359         int                     irq_enc;
 360
 361         vpu_device              enc_dev;
 362         vpu_device              dec_dev;
 363
 364         struct device           *dev;
 365
 366         struct cdev             cdev;
 367         dev_t                   dev_t;
 368         struct class            *cls;
 369         struct device           *child_dev;
 370
 371         struct dentry           *debugfs_dir;
 372         struct dentry           *debugfs_file_regs;
 373
 374         u32 irq_status;
 375 #if defined(CONFIG_VCODEC_MMU)
 376         struct ion_client       *ion_client;
 377         struct list_head        mem_region_list;
 378         struct device           *mmu_dev;
 379 #endif
 380
 381         enum vcodec_device_id   dev_id;
 382
 383         u32                     reserved_mode;
 384
 385         struct delayed_work     simulate_work;
 386 } vpu_service_info;
 387
 388 struct vcodec_combo {
 389         struct vpu_service_info *vpu_srv;
 390         struct vpu_service_info *hevc_srv;
 391         struct list_head waiting;
 392         struct list_head running;
 393         struct mutex run_lock;
 394         vpu_reg *reg_codec;
 395         enum vcodec_device_id current_hw_mode;
 396 };
 397
 398 typedef struct vpu_request
 399 {
 400         unsigned long *req;
 401         unsigned long size;
 402 } vpu_request;
 403
 404 /// global variable
 405 //static struct clk *pd_video;
 406 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).
 407 /* mutex for selecting operation registers of vpu or hevc */
 408 static struct mutex g_mode_mutex;
 409 static struct vcodec_combo g_combo;
 410
 411 #ifdef CONFIG_DEBUG_FS
 412 static int vcodec_debugfs_init(void);
 413 static void vcodec_debugfs_exit(void);
 414 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 415 static int debug_vcodec_open(struct inode *inode, struct file *file);
 416
 417 static const struct file_operations debug_vcodec_fops = {
 418         .open = debug_vcodec_open,
 419         .read = seq_read,
 420         .llseek = seq_lseek,
 421         .release = single_release,
 422 };
 423 #endif
 424
 425 #define VDPU_SOFT_RESET_REG     101
 426 #define VDPU_CLEAR_CACHE_REG    516
 427 #define VEPU_CLEAR_CACHE_REG    772
 428 #define HEVC_CLEAR_CACHE_REG    260
 429
 430 #define VPU_REG_ENABLE(base, reg)       do { \
 431                                                 base[reg] = 1; \
 432                                         } while (0)
 433
 434 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 435 #define VDPU_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAR_CACHE_REG)
 436 #define VEPU_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAR_CACHE_REG)
 437 #define HEVC_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAR_CACHE_REG)
 438
 439 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 440 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 441 #define VPU_SIMULATE_DELAY              msecs_to_jiffies(15)
 442
 443 #define BIT_VCODEC_SEL_RK3036           (1<<3)
 444 #define BIT_VCODEC_SEL_RK312X           (1<<15)
 445 static void vcodec_enter_mode_nolock(enum vcodec_device_id id, u32 *reserved_mode)
 446 {
 447         if (cpu_is_rk3036() || cpu_is_rk312x()) {
 448                 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
 449                 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 450                 if (reserved_mode)
 451                         *reserved_mode = readl_relaxed(addr);
 452                 if (id == VCODEC_DEVICE_ID_HEVC)
 453                         writel_relaxed(readl_relaxed(addr) | (bits) | (bits << 16), addr);
 454                 else
 455                         writel_relaxed((readl_relaxed(addr) & (~bits)) | (bits << 16), addr);
 456         }
 457 }
 458
 459 static void vcodec_exit_mode_nolock(enum vcodec_device_id id, u32 reserved_mode)
 460 {
 461         if (cpu_is_rk3036() || cpu_is_rk312x()) {
 462                 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
 463                 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 464                 writel_relaxed(reserved_mode | (bits << 16), addr);
 465         }
 466 }
 467
 468 static void vcodec_enter_mode(enum vcodec_device_id id)
 469 {
 470         if (cpu_is_rk3036() || cpu_is_rk312x())
 471                 mutex_lock(&g_mode_mutex);
 472         vcodec_enter_mode_nolock(id, NULL);
 473 }
 474
 475 static void vcodec_exit_mode(void)
 476 {
 477         if (cpu_is_rk3036() || cpu_is_rk312x())
 478                 mutex_unlock(&g_mode_mutex);
 479 }
 480
 481 static int vpu_get_clk(struct vpu_service_info *pservice)
 482 {
 483 #if VCODEC_CLOCK_ENABLE
 484         do {
 485                 pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");
 486                 if (IS_ERR(pservice->aclk_vcodec)) {
 487                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 488                         break;
 489                 }
 490
 491                 pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");
 492                 if (IS_ERR(pservice->hclk_vcodec)) {
 493                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 494                         break;
 495                 }
 496
 497                 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 498                         pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 499                         if (IS_ERR(pservice->clk_core)) {
 500                                 dev_err(pservice->dev, "failed on clk_get clk_core\n");
 501                                 break;
 502                         }
 503
 504                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 505                                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 506                                 if (IS_ERR(pservice->clk_cabac)) {
 507                                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 508                                         break;
 509                                 }
 510                         } else {
 511                                 pservice->clk_cabac = NULL;
 512                         }
 513
 514                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 515                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 516                                 if (IS_ERR(pservice->pd_video)) {
 517                                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 518                                         break;
 519                                 }
 520                         } else {
 521                                 pservice->pd_video = NULL;
 522                         }
 523                 } else {
 524                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 525                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 526                                 if (IS_ERR(pservice->pd_video)) {
 527                                         dev_err(pservice->dev, "failed on clk_get pd_video\n");
 528                                         break;
 529                                 }
 530                         } else {
 531                                 pservice->pd_video = NULL;
 532                         }
 533                 }
 534
 535                 if (cpu_is_rk312x()) {
 536                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 537                         if (IS_ERR(pservice->pd_video)) {
 538                                 dev_err(pservice->dev, "failed on clk_get pd_video\n");
 539                                 break;
 540                         }
 541                 }
 542
 543                 return 0;
 544         } while (0);
 545
 546         return -1;
 547 #else
 548         return 0;
 549 #endif
 550 }
 551
 552 static void vpu_put_clk(struct vpu_service_info *pservice)
 553 {
 554 #if VCODEC_CLOCK_ENABLE
 555         if (pservice->pd_video) {
 556                 devm_clk_put(pservice->dev, pservice->pd_video);
 557         }
 558
 559         if (pservice->aclk_vcodec) {
 560                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 561         }
 562
 563         if (pservice->hclk_vcodec) {
 564                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 565         }
 566
 567         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 568                 if (pservice->clk_core) {
 569                         devm_clk_put(pservice->dev, pservice->clk_core);
 570                 }
 571
 572                 if (pservice->clk_cabac) {
 573                         devm_clk_put(pservice->dev, pservice->clk_cabac);
 574                 }
 575         }
 576 #endif
 577 }
 578
 579 static void vpu_reset(struct vpu_service_info *pservice)
 580 {
 581 #if defined(CONFIG_ARCH_RK29)
 582         clk_disable(aclk_ddr_vepu);
 583         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 584         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 585         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 586         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 587         mdelay(10);
 588         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 589         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 590         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 591         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 592         clk_enable(aclk_ddr_vepu);
 593 #elif defined(CONFIG_ARCH_RK30)
 594         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 595         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 596         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 597         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 598         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 599         mdelay(1);
 600         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 601         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 602         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 603         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 604         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 605 #endif
 606         *pservice->reg_codec = NULL;
 607         pservice->reg_pproc = NULL;
 608         pservice->reg_resev = NULL;
 609 }
 610
 611 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);
 612 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)
 613 {
 614         vpu_reg *reg, *n;
 615         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 616                 reg_deinit(pservice, reg);
 617         }
 618         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 619                 reg_deinit(pservice, reg);
 620         }
 621         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 622                 reg_deinit(pservice, reg);
 623         }
 624 }
 625
 626 static void vpu_service_dump(struct vpu_service_info *pservice)
 627 {
 628         int running;
 629         vpu_reg *reg, *reg_tmp;
 630         vpu_session *session, *session_tmp;
 631
 632         running = atomic_read(&pservice->total_running);
 633         printk("total_running %d\n", running);
 634
 635         printk("reg_codec 0x%.8x\n", (unsigned int)(*pservice->reg_codec));
 636         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);
 637         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);
 638
 639         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
 640                 printk("session pid %d type %d:\n", session->pid, session->type);
 641                 running = atomic_read(&session->task_running);
 642                 printk("task_running %d\n", running);
 643                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
 644                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);
 645                 }
 646                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
 647                         printk("running register set 0x%.8x\n", (unsigned int)reg);
 648                 }
 649                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
 650                         printk("done    register set 0x%.8x\n", (unsigned int)reg);
 651                 }
 652         }
 653 }
 654
 655 static void vpu_service_power_off(struct vpu_service_info *pservice)
 656 {
 657         int total_running;
 658         if (!pservice->enabled)
 659                 return;
 660
 661         pservice->enabled = false;
 662         total_running = atomic_read(&pservice->total_running);
 663         if (total_running) {
 664                 pr_alert("alert: power off when %d task running!!\n", total_running);
 665                 mdelay(50);
 666                 pr_alert("alert: delay 50 ms for running task\n");
 667                 vpu_service_dump(pservice);
 668         }
 669
 670         pr_info("%s: power off...", dev_name(pservice->dev));
 671         udelay(10);
 672
 673 #if defined(CONFIG_VCODEC_MMU)
 674         if (pservice->mmu_dev && !(cpu_is_rk3036() || cpu_is_rk312x())) {
 675                 vcodec_enter_mode(pservice->dev_id);
 676                 rockchip_iovmm_deactivate(pservice->dev);
 677                 vcodec_exit_mode();
 678         }
 679 #endif
 680
 681 #if VCODEC_CLOCK_ENABLE
 682         if (pservice->pd_video)
 683                 clk_disable_unprepare(pservice->pd_video);
 684         if (pservice->hclk_vcodec)
 685                 clk_disable_unprepare(pservice->hclk_vcodec);
 686         if (pservice->aclk_vcodec)
 687                 clk_disable_unprepare(pservice->aclk_vcodec);
 688         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 689                 if (pservice->clk_core)
 690                         clk_disable_unprepare(pservice->clk_core);
 691                 if (pservice->clk_cabac)
 692                         clk_disable_unprepare(pservice->clk_cabac);
 693         }
 694 #endif
 695
 696         wake_unlock(&pservice->wake_lock);
 697         pr_info("done\n");
 698 }
 699
 700 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 701 {
 702         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 703 }
 704
 705 static void vpu_power_off_work(struct work_struct *work_s)
 706 {
 707         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 708         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 709
 710         if (mutex_trylock(pservice->lock)) {
 711                 vpu_service_power_off(pservice);
 712                 mutex_unlock(pservice->lock);
 713         } else {
 714                 /* Come back later if the device is busy... */
 715                 vpu_queue_power_off_work(pservice);
 716         }
 717 }
 718
 719 static void vpu_service_power_on(struct vpu_service_info *pservice)
 720 {
 721         static ktime_t last;
 722         ktime_t now = ktime_get();
 723         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 724                 cancel_delayed_work_sync(&pservice->power_off_work);
 725                 vpu_queue_power_off_work(pservice);
 726                 last = now;
 727         }
 728         if (pservice->enabled)
 729                 return ;
 730
 731         pservice->enabled = true;
 732         printk("%s: power on\n", dev_name(pservice->dev));
 733
 734 #if VCODEC_CLOCK_ENABLE
 735         if (pservice->aclk_vcodec)
 736                 clk_prepare_enable(pservice->aclk_vcodec);
 737
 738         if (pservice->hclk_vcodec)
 739                 clk_prepare_enable(pservice->hclk_vcodec);
 740
 741         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 742                 if (pservice->clk_core)
 743                         clk_prepare_enable(pservice->clk_core);
 744         if (pservice->clk_cabac)
 745                 clk_prepare_enable(pservice->clk_cabac);
 746         }
 747
 748         if (pservice->pd_video)
 749                 clk_prepare_enable(pservice->pd_video);
 750 #endif
 751
 752 #if defined(CONFIG_ARCH_RK319X)
 753         /// select aclk_vepu as vcodec clock source.
 754 #define BIT_VCODEC_SEL  (1<<7)
 755         writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) |
 756                 (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),
 757                 RK319X_GRF_BASE + GRF_SOC_CON1);
 758 #endif
 759 #define BIT_VCODEC_CLK_SEL      (1<<10)
 760         if (cpu_is_rk312x())
 761                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 762                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 763                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 764
 765         udelay(10);
 766         wake_lock(&pservice->wake_lock);
 767
 768 #if defined(CONFIG_VCODEC_MMU)
 769         if (pservice->mmu_dev && !(cpu_is_rk3036() || cpu_is_rk312x())) {
 770                 vcodec_enter_mode(pservice->dev_id);
 771                 rockchip_iovmm_activate(pservice->dev);
 772                 vcodec_exit_mode();
 773         }
 774 #endif
 775 }
 776
 777 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 778 {
 779         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
 780         return ((type == 8) || (type == 4));
 781 }
 782
 783 static inline bool reg_check_interlace(vpu_reg *reg)
 784 {
 785         unsigned long type = (reg->reg[3] & (1 << 23));
 786         return (type > 0);
 787 }
 788
 789 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 790 {
 791         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 792         return type;
 793 }
 794
 795 static inline int reg_probe_width(vpu_reg *reg)
 796 {
 797         int width_in_mb = reg->reg[4] >> 23;
 798         return width_in_mb * 16;
 799 }
 800
 801 #if defined(CONFIG_VCODEC_MMU)
 802 static int vcodec_fd_to_iova(struct vpu_service_info *pservice, vpu_reg *reg,int fd)
 803 {
 804         struct ion_handle *hdl;
 805         int ret = 0;
 806         struct vcodec_mem_region *mem_region;
 807
 808         hdl = ion_import_dma_buf(pservice->ion_client, fd);
 809         if (IS_ERR(hdl)) {
 810                 dev_err(pservice->dev, "import dma-buf from fd %d failed\n", fd);
 811                 return PTR_ERR(hdl);
 812         }
 813         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 814
 815         if (mem_region == NULL) {
 816                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 817                 ion_free(pservice->ion_client, hdl);
 818                 return -1;
 819         }
 820
 821         mem_region->hdl = hdl;
 822         vcodec_enter_mode(pservice->dev_id);
 823         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);
 824         vcodec_exit_mode();
 825
 826         if (ret < 0) {
 827                 dev_err(pservice->dev, "ion map iommu failed\n");
 828                 kfree(mem_region);
 829                 ion_free(pservice->ion_client, hdl);
 830                 return ret;
 831         }
 832         INIT_LIST_HEAD(&mem_region->reg_lnk);
 833         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 834         return mem_region->iova;
 835 }
 836
 837 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl,
 838                                 int size, vpu_reg *reg,
 839                                 struct extra_info_for_iommu *ext_inf)
 840 {
 841         int i;
 842         int usr_fd = 0;
 843         int offset = 0;
 844
 845         if (tbl == NULL || size <= 0) {
 846                 dev_err(pservice->dev, "input arguments invalidate\n");
 847                 return -1;
 848         }
 849
 850         vpu_service_power_on(pservice);
 851
 852         for (i = 0; i < size; i++) {
 853                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 854
 855                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID &&
 856                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 857                         /* special for vpu dec num 41 regitster */
 858                         offset = reg->reg[tbl[i]] >> 10 << 4;
 859                 else
 860                         offset = reg->reg[tbl[i]] >> 10;
 861
 862                 if (usr_fd != 0) {
 863                         struct ion_handle *hdl;
 864                         int ret = 0;
 865                         struct vcodec_mem_region *mem_region;
 866
 867                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 868                         if (IS_ERR(hdl)) {
 869                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 870                                 return PTR_ERR(hdl);
 871                         }
 872
 873                         if (tbl[i] == 42 && pservice->hw_info->hw_id == HEVC_ID){
 874                                 int i = 0;
 875                                 char *pps;
 876                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
 877                                 for (i=0; i<64; i++) {
 878                                         u32 scaling_offset;
 879                                         u32 tmp;
 880                                         int scaling_fd= 0;
 881                                         scaling_offset = (u32)pps[i*80+74];
 882                                         scaling_offset += (u32)pps[i*80+75] << 8;
 883                                         scaling_offset += (u32)pps[i*80+76] << 16;
 884                                         scaling_offset += (u32)pps[i*80+77] << 24;
 885                                         scaling_fd = scaling_offset&0x3ff;
 886                                         scaling_offset = scaling_offset >> 10;
 887                                         if(scaling_fd > 0) {
 888                                                 tmp = vcodec_fd_to_iova(pservice,reg,scaling_fd);
 889                                                 tmp += scaling_offset;
 890                                                 pps[i*80+74] = tmp & 0xff;
 891                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
 892                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
 893                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
 894                                         }
 895                                 }
 896                         }
 897
 898                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 899
 900                         if (mem_region == NULL) {
 901                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 902                                 ion_free(pservice->ion_client, hdl);
 903                                 return -1;
 904                         }
 905
 906                         mem_region->hdl = hdl;
 907                         mem_region->reg_idx = tbl[i];
 908                         vcodec_enter_mode(pservice->dev_id);
 909                         ret = ion_map_iommu(pservice->dev,
 910                                             pservice->ion_client,
 911                                             mem_region->hdl,
 912                                             &mem_region->iova,
 913                                             &mem_region->len);
 914                         vcodec_exit_mode();
 915
 916                         if (ret < 0) {
 917                                 dev_err(pservice->dev, "ion map iommu failed\n");
 918                                 kfree(mem_region);
 919                                 ion_free(pservice->ion_client, hdl);
 920                                 return ret;
 921                         }
 922                         reg->reg[tbl[i]] = mem_region->iova + offset;
 923                         INIT_LIST_HEAD(&mem_region->reg_lnk);
 924                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 925                 }
 926         }
 927
 928         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
 929                 for (i=0; i<ext_inf->cnt; i++) {
 930                         pr_info("reg[%d] + offset %d\n", ext_inf->elem[i].index, ext_inf->elem[i].offset);
 931                         reg->reg[ext_inf->elem[i].index] += ext_inf->elem[i].offset;
 932                 }
 933         }
 934
 935         return 0;
 936 }
 937
 938 static int vcodec_reg_address_translate(struct vpu_service_info *pservice,
 939                                         vpu_reg *reg,
 940                                         struct extra_info_for_iommu *ext_inf)
 941 {
 942         VPU_HW_ID hw_id;
 943         u8 *tbl;
 944         int size = 0;
 945
 946         hw_id = pservice->hw_info->hw_id;
 947
 948         if (hw_id == HEVC_ID) {
 949                 tbl = addr_tbl_hevc_dec;
 950                 size = sizeof(addr_tbl_hevc_dec);
 951         } else {
 952                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 953                         switch (reg_check_fmt(reg)) {
 954                         case VPU_DEC_FMT_H264:
 955                                 {
 956                                         tbl = addr_tbl_vpu_h264dec;
 957                                         size = sizeof(addr_tbl_vpu_h264dec);
 958                                         break;
 959                                 }
 960                         case VPU_DEC_FMT_VP8:
 961                         case VPU_DEC_FMT_VP7:
 962                                 {
 963                                         tbl = addr_tbl_vpu_vp8dec;
 964                                         size = sizeof(addr_tbl_vpu_vp8dec);
 965                                         break;
 966                                 }
 967
 968                         case VPU_DEC_FMT_VP6:
 969                                 {
 970                                         tbl = addr_tbl_vpu_vp6dec;
 971                                         size = sizeof(addr_tbl_vpu_vp6dec);
 972                                         break;
 973                                 }
 974                         case VPU_DEC_FMT_VC1:
 975                                 {
 976                                         tbl = addr_tbl_vpu_vc1dec;
 977                                         size = sizeof(addr_tbl_vpu_vc1dec);
 978                                         break;
 979                                 }
 980
 981                         case VPU_DEC_FMT_JPEG:
 982                                 {
 983                                         tbl = addr_tbl_vpu_jpegdec;
 984                                         size = sizeof(addr_tbl_vpu_jpegdec);
 985                                         break;
 986                                 }
 987                         default:
 988                                 tbl = addr_tbl_vpu_defaultdec;
 989                                 size = sizeof(addr_tbl_vpu_defaultdec);
 990                                 break;
 991                         }
 992                 } else if (reg->type == VPU_ENC) {
 993                         tbl = addr_tbl_vpu_enc;
 994                         size = sizeof(addr_tbl_vpu_enc);
 995                 }
 996         }
 997
 998         if (size != 0) {
 999                 return vcodec_bufid_to_iova(pservice, tbl, size, reg, ext_inf);
1000         } else {
1001                 return -1;
1002         }
1003 }
1004 #endif
1005
1006 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)
1007 {
1008         int extra_size = 0;
1009         struct extra_info_for_iommu extra_info;
1010         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
1011         if (NULL == reg) {
1012                 pr_err("error: kmalloc fail in reg_init\n");
1013                 return NULL;
1014         }
1015
1016         if (size > pservice->reg_size) {
1017                 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
1018                 size = pservice->reg_size;*/
1019                 extra_size = size - pservice->reg_size;
1020                 size = pservice->reg_size;
1021         }
1022         reg->session = session;
1023         reg->type = session->type;
1024         reg->size = size;
1025         reg->freq = VPU_FREQ_DEFAULT;
1026         reg->reg = (unsigned long *)&reg[1];
1027         INIT_LIST_HEAD(&reg->session_link);
1028         INIT_LIST_HEAD(&reg->status_link);
1029
1030 #if defined(CONFIG_VCODEC_MMU)
1031         if (pservice->mmu_dev)
1032                 INIT_LIST_HEAD(&reg->mem_region_list);
1033 #endif
1034
1035         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1036                 pr_err("error: copy_from_user failed in reg_init\n");
1037                 kfree(reg);
1038                 return NULL;
1039         }
1040
1041         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1042                 pr_err("error: copy_from_user failed in reg_init\n");
1043                 kfree(reg);
1044                 return NULL;
1045         }
1046
1047 #if defined(CONFIG_VCODEC_MMU)
1048         if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg, &extra_info)) {
1049                 pr_err("error: translate reg address failed\n");
1050                 kfree(reg);
1051                 return NULL;
1052         }
1053 #endif
1054
1055         mutex_lock(pservice->lock);
1056         list_add_tail(&reg->status_link, pservice->waiting);
1057         list_add_tail(&reg->session_link, &session->waiting);
1058         mutex_unlock(pservice->lock);
1059
1060         if (pservice->auto_freq) {
1061                 if (!soc_is_rk2928g()) {
1062                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1063                                 if (reg_check_rmvb_wmv(reg)) {
1064                                         reg->freq = VPU_FREQ_200M;
1065                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1066                                         if (reg_probe_width(reg) > 3200) {
1067                                                 // raise frequency for 4k avc.
1068                                                 reg->freq = VPU_FREQ_500M;
1069                                         }
1070                                 } else {
1071                                         if (reg_check_interlace(reg)) {
1072                                                 reg->freq = VPU_FREQ_400M;
1073                                         }
1074                                 }
1075                         }
1076                         if (reg->type == VPU_PP) {
1077                                 reg->freq = VPU_FREQ_400M;
1078                         }
1079                 }
1080         }
1081
1082         /*reg->reg[2] &= (~0x800000L);*/
1083
1084         return reg;
1085 }
1086
1087 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)
1088 {
1089 #if defined(CONFIG_VCODEC_MMU)
1090         struct vcodec_mem_region *mem_region = NULL, *n;
1091 #endif
1092
1093         list_del_init(&reg->session_link);
1094         list_del_init(&reg->status_link);
1095         if (reg == (*pservice->reg_codec))
1096                 *pservice->reg_codec = NULL;
1097         if (reg == pservice->reg_pproc)
1098                 pservice->reg_pproc = NULL;
1099
1100 #if defined(CONFIG_VCODEC_MMU)
1101         // release memory region attach to this registers table.
1102         if (pservice->mmu_dev) {
1103                 list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {
1104                         /* do not unmap iommu manually,
1105                            unmap will proccess when memory release */
1106                         /*vcodec_enter_mode(pservice->dev_id);
1107                         ion_unmap_iommu(pservice->dev,
1108                                         pservice->ion_client,
1109                                         mem_region->hdl);
1110                         vcodec_exit_mode();*/
1111                         ion_free(pservice->ion_client, mem_region->hdl);
1112                         list_del_init(&mem_region->reg_lnk);
1113                         kfree(mem_region);
1114                 }
1115         }
1116 #endif
1117
1118         kfree(reg);
1119 }
1120
1121 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1122 {
1123         list_del_init(&reg->status_link);
1124         list_add_tail(&reg->status_link, pservice->running);
1125
1126         list_del_init(&reg->session_link);
1127         list_add_tail(&reg->session_link, &reg->session->running);
1128 }
1129
1130 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1131 {
1132         int i;
1133         u32 *dst = (u32 *)&reg->reg[0];
1134
1135         for (i = 0; i < count; i++)
1136                 *dst++ = *src++;
1137 }
1138
1139 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)
1140 {
1141         int irq_reg = -1;
1142         list_del_init(&reg->status_link);
1143         list_add_tail(&reg->status_link, &pservice->done);
1144
1145         list_del_init(&reg->session_link);
1146         list_add_tail(&reg->session_link, &reg->session->done);
1147
1148         vcodec_enter_mode(pservice->dev_id);
1149         switch (reg->type) {
1150         case VPU_ENC : {
1151                 *pservice->reg_codec = NULL;
1152                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);
1153                 irq_reg = ENC_INTERRUPT_REGISTER;
1154                 break;
1155         }
1156         case VPU_DEC : {
1157                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1158                 *pservice->reg_codec = NULL;
1159                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);
1160                 irq_reg = DEC_INTERRUPT_REGISTER;
1161                 break;
1162         }
1163         case VPU_PP : {
1164                 pservice->reg_pproc = NULL;
1165                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1166                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1167                 break;
1168         }
1169         case VPU_DEC_PP : {
1170                 *pservice->reg_codec = NULL;
1171                 pservice->reg_pproc = NULL;
1172                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1173                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1174                 break;
1175         }
1176         default : {
1177                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
1178                 break;
1179         }
1180         }
1181         if (cpu_is_rk3036() || cpu_is_rk312x())
1182                 rockchip_iovmm_deactivate(pservice->dev);
1183         vcodec_exit_mode();
1184
1185         if (irq_reg != -1) {
1186                 reg->reg[irq_reg] = pservice->irq_status;
1187         }
1188
1189         atomic_sub(1, &reg->session->task_running);
1190         atomic_sub(1, &pservice->total_running);
1191         wake_up(&reg->session->wait);
1192 }
1193
1194 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1195 {
1196         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1197         if (curr == reg->freq) {
1198                 return ;
1199         }
1200         atomic_set(&pservice->freq_status, reg->freq);
1201         switch (reg->freq) {
1202         case VPU_FREQ_200M : {
1203                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1204                 //printk("default: 200M\n");
1205         } break;
1206         case VPU_FREQ_266M : {
1207                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1208                 //printk("default: 266M\n");
1209         } break;
1210         case VPU_FREQ_300M : {
1211                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1212                 //printk("default: 300M\n");
1213         } break;
1214         case VPU_FREQ_400M : {
1215                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1216                 //printk("default: 400M\n");
1217         } break;
1218         case VPU_FREQ_500M : {
1219                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1220         } break;
1221         case VPU_FREQ_600M : {
1222                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1223         } break;
1224         default : {
1225                 if (soc_is_rk2928g()) {
1226                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1227                 } else {
1228                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1229                 }
1230                 //printk("default: 300M\n");
1231         } break;
1232         }
1233 }
1234
1235 #if HEVC_SIM_ENABLE
1236 static void simulate_start(struct vpu_service_info *pservice);
1237 #endif
1238 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)
1239 {
1240         int i;
1241         u32 *src = (u32 *)&reg->reg[0];
1242         atomic_add(1, &pservice->total_running);
1243         atomic_add(1, &reg->session->task_running);
1244         if (pservice->auto_freq) {
1245                 vpu_service_set_freq(pservice, reg);
1246         }
1247
1248         vcodec_enter_mode(pservice->dev_id);
1249
1250         if (cpu_is_rk3036() || cpu_is_rk312x())
1251                 rockchip_iovmm_activate(pservice->dev);
1252
1253         switch (reg->type) {
1254         case VPU_ENC : {
1255                 int enc_count = pservice->hw_info->enc_reg_num;
1256                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;
1257
1258                 *pservice->reg_codec = reg;
1259
1260                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1261
1262                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1263                         dst[i] = src[i];
1264
1265                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1266                         dst[i] = src[i];
1267
1268                 VEPU_CLEAR_CACHE(dst);
1269
1270                 dsb();
1271
1272                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1273                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1274
1275 #if VPU_SERVICE_SHOW_TIME
1276                 do_gettimeofday(&enc_start);
1277 #endif
1278
1279         } break;
1280         case VPU_DEC : {
1281                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1282
1283                 *pservice->reg_codec = reg;
1284
1285                 if (pservice->hw_info->hw_id != HEVC_ID) {
1286                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1287                                 dst[i] = src[i];
1288                         VDPU_CLEAR_CACHE(dst);
1289                 } else {
1290                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1291                                 dst[i] = src[i];
1292                         HEVC_CLEAR_CACHE(dst);
1293                 }
1294
1295                 dsb();
1296
1297                 if (pservice->hw_info->hw_id != HEVC_ID) {
1298                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1299                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];
1300                 } else {
1301                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1302                 }
1303
1304                 dsb();
1305                 dmb();
1306
1307 #if VPU_SERVICE_SHOW_TIME
1308                 do_gettimeofday(&dec_start);
1309 #endif
1310
1311         } break;
1312         case VPU_PP : {
1313                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1314                 pservice->reg_pproc = reg;
1315
1316                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1317
1318                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1319                         dst[i] = src[i];
1320
1321                 dsb();
1322
1323                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1324
1325 #if VPU_SERVICE_SHOW_TIME
1326                 do_gettimeofday(&pp_start);
1327 #endif
1328
1329         } break;
1330         case VPU_DEC_PP : {
1331                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1332                 *pservice->reg_codec = reg;
1333                 pservice->reg_pproc = reg;
1334
1335                 VDPU_SOFT_RESET(dst);
1336                 VDPU_CLEAR_CACHE(dst);
1337
1338                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1339                         dst[i] = src[i];
1340
1341                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1342                 dsb();
1343
1344                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1345                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1346                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1347
1348 #if VPU_SERVICE_SHOW_TIME
1349                 do_gettimeofday(&dec_start);
1350 #endif
1351
1352         } break;
1353         default : {
1354                 pr_err("error: unsupport session type %d", reg->type);
1355                 atomic_sub(1, &pservice->total_running);
1356                 atomic_sub(1, &reg->session->task_running);
1357                 break;
1358         }
1359         }
1360
1361         vcodec_exit_mode();
1362
1363 #if HEVC_SIM_ENABLE
1364         if (pservice->hw_info->hw_id == HEVC_ID) {
1365                 simulate_start(pservice);
1366         }
1367 #endif
1368 }
1369
1370 static void try_set_reg(struct vpu_service_info *pservice)
1371 {
1372         // first get reg from reg list
1373         if (!list_empty(pservice->waiting)) {
1374                 int can_set = 0;
1375                 vpu_reg *reg = list_entry(pservice->waiting->next, vpu_reg, status_link);
1376
1377                 vpu_service_power_on(pservice);
1378
1379                 switch (reg->type) {
1380                 case VPU_ENC : {
1381                         if ((NULL == *pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1382                                 can_set = 1;
1383                 } break;
1384                 case VPU_DEC : {
1385                         if (NULL == *pservice->reg_codec)
1386                                 can_set = 1;
1387                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {
1388                                 can_set = 0;
1389                         }
1390                 } break;
1391                 case VPU_PP : {
1392                         if (NULL == *pservice->reg_codec) {
1393                                 if (NULL == pservice->reg_pproc)
1394                                         can_set = 1;
1395                         } else {
1396                                 if ((VPU_DEC == (*pservice->reg_codec)->type) && (NULL == pservice->reg_pproc))
1397                                         can_set = 1;
1398                                 // can not charge frequency when vpu is working
1399                                 if (pservice->auto_freq) {
1400                                         can_set = 0;
1401                                 }
1402                         }
1403                 } break;
1404                 case VPU_DEC_PP : {
1405                         if ((NULL == *pservice->reg_codec) && (NULL == pservice->reg_pproc))
1406                                 can_set = 1;
1407                         } break;
1408                 default : {
1409                         printk("undefined reg type %d\n", reg->type);
1410                 } break;
1411                 }
1412                 if (can_set) {
1413                         reg_from_wait_to_run(pservice, reg);
1414                         reg_copy_to_hw(pservice, reg);
1415                 }
1416         }
1417 }
1418
1419 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)
1420 {
1421         int ret = 0;
1422         switch (reg->type) {
1423         case VPU_ENC : {
1424                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))
1425                         ret = -EFAULT;
1426                 break;
1427         }
1428         case VPU_DEC : {
1429                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1430                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1431                         ret = -EFAULT;
1432                 break;
1433         }
1434         case VPU_PP : {
1435                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1436                         ret = -EFAULT;
1437                 break;
1438         }
1439         case VPU_DEC_PP : {
1440                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1441                         ret = -EFAULT;
1442                 break;
1443         }
1444         default : {
1445                 ret = -EFAULT;
1446                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);
1447                 break;
1448         }
1449         }
1450         reg_deinit(pservice, reg);
1451         return ret;
1452 }
1453
1454 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1455 {
1456     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);
1457         vpu_session *session = (vpu_session *)filp->private_data;
1458         if (NULL == session) {
1459                 return -EINVAL;
1460         }
1461
1462         switch (cmd) {
1463         case VPU_IOC_SET_CLIENT_TYPE : {
1464                 session->type = (VPU_CLIENT_TYPE)arg;
1465                 break;
1466         }
1467         case VPU_IOC_GET_HW_FUSE_STATUS : {
1468                 vpu_request req;
1469                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1470                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1471                         return -EFAULT;
1472                 } else {
1473                         if (VPU_ENC != session->type) {
1474                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {
1475                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1476                                         return -EFAULT;
1477                                 }
1478                         } else {
1479                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {
1480                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1481                                         return -EFAULT;
1482                                 }
1483                         }
1484                 }
1485
1486                 break;
1487         }
1488         case VPU_IOC_SET_REG : {
1489                 vpu_request req;
1490                 vpu_reg *reg;
1491                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1492                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1493                         return -EFAULT;
1494                 }
1495                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);
1496                 if (NULL == reg) {
1497                         return -EFAULT;
1498                 } else {
1499                         mutex_lock(pservice->lock);
1500                         try_set_reg(pservice);
1501                         mutex_unlock(pservice->lock);
1502                 }
1503
1504                 break;
1505         }
1506         case VPU_IOC_GET_REG : {
1507                 vpu_request req;
1508                 vpu_reg *reg;
1509                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1510                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1511                         return -EFAULT;
1512                 } else {
1513                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1514                         if (!list_empty(&session->done)) {
1515                                 if (ret < 0) {
1516                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1517                                 }
1518                                 ret = 0;
1519                         } else {
1520                                 if (unlikely(ret < 0)) {
1521                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
1522                                 } else if (0 == ret) {
1523                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1524                                         ret = -ETIMEDOUT;
1525                                 }
1526                         }
1527                         if (ret < 0) {
1528                                 int task_running = atomic_read(&session->task_running);
1529                                 mutex_lock(pservice->lock);
1530                                 vpu_service_dump(pservice);
1531                                 if (task_running) {
1532                                         atomic_set(&session->task_running, 0);
1533                                         atomic_sub(task_running, &pservice->total_running);
1534                                         printk("%d task is running but not return, reset hardware...", task_running);
1535                                         vpu_reset(pservice);
1536                                         printk("done\n");
1537                                 }
1538                                 vpu_service_session_clear(pservice, session);
1539                                 mutex_unlock(pservice->lock);
1540                                 return ret;
1541                         }
1542                 }
1543                 mutex_lock(pservice->lock);
1544                 reg = list_entry(session->done.next, vpu_reg, session_link);
1545                 return_reg(pservice, reg, (u32 __user *)req.req);
1546                 mutex_unlock(pservice->lock);
1547                 break;
1548         }
1549         case VPU_IOC_PROBE_IOMMU_STATUS: {
1550                 int iommu_enable = 0;
1551
1552 #if defined(CONFIG_VCODEC_MMU)
1553                 iommu_enable = pservice->mmu_dev ? 1 : 0;
1554 #endif
1555
1556                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1557                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1558                         return -EFAULT;
1559                 }
1560                 break;
1561         }
1562         default : {
1563                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1564                 break;
1565         }
1566         }
1567
1568         return 0;
1569 }
1570
1571 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
1572 {
1573         int ret = -EINVAL, i = 0;
1574         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1575         u32 enc_id = *tmp;
1576
1577 #if HEVC_SIM_ENABLE
1578         /// temporary, hevc driver test.
1579         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {
1580                 p->hw_info = &vpu_hw_set[2];
1581                 return 0;
1582         }
1583 #endif
1584         enc_id = (enc_id >> 16) & 0xFFFF;
1585         pr_info("checking hw id %x\n", enc_id);
1586         p->hw_info = NULL;
1587         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1588                 if (enc_id == vpu_hw_set[i].hw_id) {
1589                         p->hw_info = &vpu_hw_set[i];
1590                         ret = 0;
1591                         break;
1592                 }
1593         }
1594         iounmap((void *)tmp);
1595         return ret;
1596 }
1597
1598 static int vpu_service_open(struct inode *inode, struct file *filp)
1599 {
1600         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1601         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1602         if (NULL == session) {
1603                 pr_err("error: unable to allocate memory for vpu_session.");
1604                 return -ENOMEM;
1605         }
1606
1607         session->type   = VPU_TYPE_BUTT;
1608         session->pid    = current->pid;
1609         INIT_LIST_HEAD(&session->waiting);
1610         INIT_LIST_HEAD(&session->running);
1611         INIT_LIST_HEAD(&session->done);
1612         INIT_LIST_HEAD(&session->list_session);
1613         init_waitqueue_head(&session->wait);
1614         atomic_set(&session->task_running, 0);
1615         mutex_lock(pservice->lock);
1616         list_add_tail(&session->list_session, &pservice->session);
1617         filp->private_data = (void *)session;
1618         mutex_unlock(pservice->lock);
1619
1620         pr_debug("dev opened\n");
1621         return nonseekable_open(inode, filp);
1622 }
1623
1624 static int vpu_service_release(struct inode *inode, struct file *filp)
1625 {
1626         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1627         int task_running;
1628         vpu_session *session = (vpu_session *)filp->private_data;
1629         if (NULL == session)
1630                 return -EINVAL;
1631
1632         task_running = atomic_read(&session->task_running);
1633         if (task_running) {
1634                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1635                 msleep(50);
1636         }
1637         wake_up(&session->wait);
1638
1639         mutex_lock(pservice->lock);
1640         /* remove this filp from the asynchronusly notified filp's */
1641         list_del_init(&session->list_session);
1642         vpu_service_session_clear(pservice, session);
1643         kfree(session);
1644         filp->private_data = NULL;
1645         mutex_unlock(pservice->lock);
1646
1647         pr_debug("dev closed\n");
1648         return 0;
1649 }
1650
1651 static const struct file_operations vpu_service_fops = {
1652         .unlocked_ioctl = vpu_service_ioctl,
1653         .open           = vpu_service_open,
1654         .release        = vpu_service_release,
1655         //.fasync       = vpu_service_fasync,
1656 };
1657
1658 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1659 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1660 static irqreturn_t vepu_irq(int irq, void *dev_id);
1661 static irqreturn_t vepu_isr(int irq, void *dev_id);
1662 static void get_hw_info(struct vpu_service_info *pservice);
1663
1664 #if HEVC_SIM_ENABLE
1665 static void simulate_work(struct work_struct *work_s)
1666 {
1667         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
1668         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);
1669         vpu_device *dev = &pservice->dec_dev;
1670
1671         if (!list_empty(&pservice->running)) {
1672                 atomic_add(1, &dev->irq_count_codec);
1673                 vdpu_isr(0, (void*)pservice);
1674         } else {
1675                 //simulate_start(pservice);
1676                 pr_err("empty running queue\n");
1677         }
1678 }
1679
1680 static void simulate_init(struct vpu_service_info *pservice)
1681 {
1682         INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);
1683 }
1684
1685 static void simulate_start(struct vpu_service_info *pservice)
1686 {
1687         cancel_delayed_work_sync(&pservice->power_off_work);
1688         queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);
1689 }
1690 #endif
1691
1692 #ifdef CONFIG_VCODEC_MMU
1693 static struct device *rockchip_get_sysmmu_device_by_compatible(const char *compt)
1694 {
1695         struct device_node *dn = NULL;
1696         struct platform_device *pd = NULL;
1697         struct device *ret = NULL ;
1698
1699         dn = of_find_compatible_node(NULL,NULL,compt);
1700         if(!dn) {
1701                 printk("can't find device node %s \r\n",compt);
1702                 return NULL;
1703         }
1704
1705         pd = of_find_device_by_node(dn);
1706         if(!pd) {
1707                 printk("can't find platform device in device node %s\n",compt);
1708                 return  NULL;
1709         }
1710         ret = &pd->dev;
1711
1712         return ret;
1713
1714 }
1715 #ifdef CONFIG_IOMMU_API
1716 static inline void platform_set_sysmmu(struct device *iommu,
1717         struct device *dev)
1718 {
1719         dev->archdata.iommu = iommu;
1720 }
1721 #else
1722 static inline void platform_set_sysmmu(struct device *iommu,
1723         struct device *dev)
1724 {
1725 }
1726 #endif
1727
1728 int vcodec_sysmmu_fault_handler(struct device *dev,
1729                                 enum rk_iommu_inttype itype,
1730                                 unsigned long pgtable_base,
1731                                 unsigned long fault_addr, unsigned int status)
1732 {
1733         struct platform_device *pdev;
1734         struct vpu_service_info *pservice;
1735
1736         pr_info("%s in\n", __func__);
1737
1738         pdev = container_of(dev, struct platform_device, dev);
1739
1740         pservice = platform_get_drvdata(pdev);
1741
1742         if (pservice->reg_codec) {
1743                 struct vcodec_mem_region *mem, *n;
1744                 int i = 0;
1745                 pr_info("vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1746                 list_for_each_entry_safe(mem, n,
1747                                          &(*pservice->reg_codec)->mem_region_list,
1748                                          reg_lnk) {
1749                         pr_info("vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1750                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
1751                         i++;
1752                 }
1753
1754                 pr_alert("vcodec, page fault occur, reset hw\n");
1755                 (*pservice->reg_codec)->reg[101] = 1;
1756                 vpu_reset(pservice);
1757         }
1758
1759         return 0;
1760 }
1761 #endif
1762
1763 #if HEVC_TEST_ENABLE
1764 static int hevc_test_case0(vpu_service_info *pservice);
1765 #endif
1766 #if defined(CONFIG_ION_ROCKCHIP)
1767 extern struct ion_client *rockchip_ion_client_create(const char * name);
1768 #endif
1769 static int vcodec_probe(struct platform_device *pdev)
1770 {
1771         int ret = 0;
1772         struct resource *res = NULL;
1773         struct device *dev = &pdev->dev;
1774         void __iomem *regs = NULL;
1775         struct device_node *np = pdev->dev.of_node;
1776         struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
1777         char *prop = (char*)dev_name(dev);
1778         u32 config;
1779 #if defined(CONFIG_VCODEC_MMU)
1780         u32 iommu_en = 0;
1781         char mmu_dev_dts_name[40];
1782         of_property_read_u32(np, "iommu_enabled", &iommu_en);
1783 #endif
1784
1785         pr_info("probe device %s\n", dev_name(dev));
1786
1787         of_property_read_string(np, "name", (const char**)&prop);
1788         dev_set_name(dev, prop);
1789
1790         if (strcmp(dev_name(dev), "hevc_service") == 0) {
1791                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
1792                 g_combo.hevc_srv = pservice;
1793         } else if (strcmp(dev_name(dev), "vpu_service") == 0) {
1794                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
1795                 g_combo.vpu_srv = pservice;
1796         } else {
1797                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));
1798                 return -1;
1799         }
1800
1801         mutex_init(&g_mode_mutex);
1802         vcodec_enter_mode_nolock(pservice->dev_id, &config);
1803
1804         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
1805         if (cpu_is_rk3036() || cpu_is_rk312x()) {
1806                 pservice->waiting = &g_combo.waiting;
1807                 pservice->running = &g_combo.running;
1808                 pservice->lock = &g_combo.run_lock;
1809                 pservice->reg_codec = &g_combo.reg_codec;
1810         } else {
1811                 pservice->waiting = kzalloc(sizeof(struct list_head), GFP_KERNEL);
1812                 pservice->running = kzalloc(sizeof(struct list_head), GFP_KERNEL);
1813                 pservice->lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
1814                 pservice->reg_codec = kzalloc(sizeof(vpu_reg*), GFP_KERNEL);
1815                 INIT_LIST_HEAD(pservice->waiting);
1816                 INIT_LIST_HEAD(pservice->running);
1817                 mutex_init(pservice->lock);
1818         }
1819         INIT_LIST_HEAD(&pservice->done);
1820         INIT_LIST_HEAD(&pservice->session);
1821
1822         pservice->reg_pproc     = NULL;
1823         atomic_set(&pservice->total_running, 0);
1824         pservice->enabled = false;
1825 #if defined(CONFIG_VCODEC_MMU)
1826         pservice->mmu_dev = NULL;
1827 #endif
1828         pservice->dev = dev;
1829
1830         if (0 > vpu_get_clk(pservice))
1831                 goto err;
1832
1833         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
1834
1835         vpu_service_power_on(pservice);
1836
1837         mdelay(1);
1838
1839         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1840
1841         res->flags &= ~IORESOURCE_CACHEABLE;
1842
1843         regs = devm_ioremap_resource(pservice->dev, res);
1844         if (IS_ERR(regs)) {
1845                 ret = PTR_ERR(regs);
1846                 goto err;
1847         }
1848
1849         {
1850                 u32 offset = res->start;
1851                 if (cpu_is_rk3036()) {
1852                         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)
1853                                 offset += 0x400;
1854                 }
1855                 ret = vpu_service_check_hw(pservice, offset);
1856                 if (ret < 0) {
1857                         pr_err("error: hw info check faild\n");
1858                         goto err;
1859                 }
1860         }
1861
1862         /// define regs address.
1863         pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;
1864         pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;
1865
1866         pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);
1867
1868         pservice->reg_size   = pservice->dec_dev.iosize;
1869
1870         if (pservice->hw_info->hw_id != HEVC_ID && !cpu_is_rk3036()) {
1871                 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;
1872                 pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;
1873
1874                 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;
1875
1876                 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);
1877
1878                 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1879                 if (pservice->irq_enc < 0) {
1880                         dev_err(pservice->dev, "cannot find IRQ encoder\n");
1881                         ret = -ENXIO;
1882                         goto err;
1883                 }
1884
1885                 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, IRQF_DISABLED, dev_name(pservice->dev), (void *)pservice);
1886                 if (ret) {
1887                         dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);
1888                         goto err;
1889                 }
1890         }
1891
1892         pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1893         if (pservice->irq_dec < 0) {
1894                 dev_err(pservice->dev, "cannot find IRQ decoder\n");
1895                 ret = -ENXIO;
1896                 goto err;
1897         }
1898
1899         /* get the IRQ line */
1900         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);
1901         if (ret) {
1902                 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);
1903                 goto err;
1904         }
1905
1906         atomic_set(&pservice->dec_dev.irq_count_codec, 0);
1907         atomic_set(&pservice->dec_dev.irq_count_pp, 0);
1908         atomic_set(&pservice->enc_dev.irq_count_codec, 0);
1909         atomic_set(&pservice->enc_dev.irq_count_pp, 0);
1910
1911         /// create device
1912         ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));
1913         if (ret) {
1914                 dev_err(dev, "alloc dev_t failed\n");
1915                 goto err;
1916         }
1917
1918         cdev_init(&pservice->cdev, &vpu_service_fops);
1919
1920         pservice->cdev.owner = THIS_MODULE;
1921         pservice->cdev.ops = &vpu_service_fops;
1922
1923         ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);
1924
1925         if (ret) {
1926                 dev_err(dev, "add dev_t failed\n");
1927                 goto err;
1928         }
1929
1930         pservice->cls = class_create(THIS_MODULE, dev_name(dev));
1931
1932         if (IS_ERR(pservice->cls)) {
1933                 ret = PTR_ERR(pservice->cls);
1934                 dev_err(dev, "class_create err:%d\n", ret);
1935                 goto err;
1936         }
1937
1938         pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));
1939
1940         platform_set_drvdata(pdev, pservice);
1941
1942         get_hw_info(pservice);
1943
1944
1945 #ifdef CONFIG_DEBUG_FS
1946         pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
1947         if (pservice->debugfs_dir == NULL)
1948                 pr_err("create debugfs dir %s failed\n", dev_name(dev));
1949
1950         pservice->debugfs_file_regs =
1951                 debugfs_create_file("regs", 0664,
1952                                     pservice->debugfs_dir, pservice,
1953                                     &debug_vcodec_fops);
1954 #endif
1955
1956 #if defined(CONFIG_VCODEC_MMU)
1957         if (iommu_en) {
1958                 pservice->ion_client = rockchip_ion_client_create("vpu");
1959                 if (IS_ERR(pservice->ion_client)) {
1960                         dev_err(&pdev->dev, "failed to create ion client for vcodec");
1961                         return PTR_ERR(pservice->ion_client);
1962                 } else {
1963                         dev_info(&pdev->dev, "vcodec ion client create success!\n");
1964                 }
1965
1966                 if (pservice->hw_info->hw_id == HEVC_ID)
1967                         sprintf(mmu_dev_dts_name, HEVC_IOMMU_COMPATIBLE_NAME);
1968                 else
1969                         sprintf(mmu_dev_dts_name, VPU_IOMMU_COMPATIBLE_NAME);
1970
1971                 pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);
1972
1973                 if (pservice->mmu_dev) {
1974                         platform_set_sysmmu(pservice->mmu_dev, pservice->dev);
1975                         /*rockchip_iovmm_activate(pservice->dev);*/
1976                 }
1977
1978                 rockchip_iovmm_set_fault_handler(pservice->dev, vcodec_sysmmu_fault_handler);
1979         }
1980 #endif
1981         vcodec_exit_mode_nolock(pservice->dev_id, config);
1982         vpu_service_power_off(pservice);
1983
1984         pr_info("init success\n");
1985
1986 #if HEVC_SIM_ENABLE
1987         if (pservice->hw_info->hw_id == HEVC_ID)
1988                 simulate_init(pservice);
1989 #endif
1990
1991 #if HEVC_TEST_ENABLE
1992         hevc_test_case0(pservice);
1993 #endif
1994
1995         return 0;
1996
1997 err:
1998         pr_info("init failed\n");
1999         vcodec_exit_mode_nolock(pservice->dev_id, config);
2000         vpu_service_power_off(pservice);
2001         vpu_put_clk(pservice);
2002         wake_lock_destroy(&pservice->wake_lock);
2003
2004         if (res)
2005                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2006         if (pservice->irq_enc > 0)
2007                 free_irq(pservice->irq_enc, (void *)pservice);
2008         if (pservice->irq_dec > 0)
2009                 free_irq(pservice->irq_dec, (void *)pservice);
2010
2011         if (pservice->child_dev) {
2012                 device_destroy(pservice->cls, pservice->dev_t);
2013                 cdev_del(&pservice->cdev);
2014                 unregister_chrdev_region(pservice->dev_t, 1);
2015         }
2016
2017         if (pservice->cls)
2018                 class_destroy(pservice->cls);
2019
2020         return ret;
2021 }
2022
2023 static int vcodec_remove(struct platform_device *pdev)
2024 {
2025         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2026         struct resource *res;
2027
2028         device_destroy(pservice->cls, pservice->dev_t);
2029         class_destroy(pservice->cls);
2030         cdev_del(&pservice->cdev);
2031         unregister_chrdev_region(pservice->dev_t, 1);
2032
2033         free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);
2034         free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);
2035         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2036         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2037         vpu_put_clk(pservice);
2038         wake_lock_destroy(&pservice->wake_lock);
2039
2040 #ifdef CONFIG_DEBUG_FS
2041         debugfs_remove(pservice->debugfs_file_regs);
2042         debugfs_remove(pservice->debugfs_dir);
2043 #endif
2044
2045         return 0;
2046 }
2047
2048 #if defined(CONFIG_OF)
2049 static const struct of_device_id vcodec_service_dt_ids[] = {
2050         {.compatible = "vpu_service",},
2051         {.compatible = "rockchip,hevc_service",},
2052         {},
2053 };
2054 #endif
2055
2056 static struct platform_driver vcodec_driver = {
2057         .probe = vcodec_probe,
2058         .remove = vcodec_remove,
2059         .driver = {
2060                 .name = "vcodec",
2061                 .owner = THIS_MODULE,
2062 #if defined(CONFIG_OF)
2063                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2064 #endif
2065         },
2066 };
2067
2068 static void get_hw_info(struct vpu_service_info *pservice)
2069 {
2070         VPUHwDecConfig_t *dec = &pservice->dec_config;
2071         VPUHwEncConfig_t *enc = &pservice->enc_config;
2072
2073         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {
2074                 u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];
2075                 u32 asicID      = pservice->dec_dev.hwregs[0];
2076
2077                 dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;
2078                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2079                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2080                         dec->jpegSupport = JPEG_PROGRESSIVE;
2081                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2082                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2083                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2084                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2085                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2086                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2087
2088                 if (soc_is_rk3190() || soc_is_rk3288())
2089                         dec->maxDecPicWidth = 4096;
2090                 else if (cpu_is_rk3036() || cpu_is_rk312x())
2091                         dec->maxDecPicWidth = 1920;
2092                 else
2093                         dec->maxDecPicWidth = configReg & 0x07FFU;
2094
2095                 /* 2nd Config register */
2096                 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];
2097                 if (dec->refBufSupport) {
2098                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2099                                 dec->refBufSupport |= 2;
2100                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2101                                 dec->refBufSupport |= 4;
2102                 }
2103                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2104                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2105                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2106                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2107
2108                 /* JPEG xtensions */
2109                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2110                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2111                 else
2112                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2113
2114                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2115                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2116                 else
2117                         dec->rvSupport = RV_NOT_SUPPORTED;
2118                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2119
2120                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2121                         dec->refBufSupport |= 8; /* enable HW support for offset */
2122
2123                 /// invalidate fuse register value in rk319x vpu and following.
2124                 if (!soc_is_rk3190() && !soc_is_rk3288() && !cpu_is_rk3036() && !cpu_is_rk312x()) {
2125                         VPUHwFuseStatus_t hwFuseSts;
2126                         /* Decoder fuse configuration */
2127                         u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2128
2129                         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
2130                         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
2131                         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
2132                         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
2133                         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
2134                         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
2135                         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
2136                         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
2137                         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
2138                         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
2139                         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
2140                         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
2141                         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
2142                         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
2143
2144                         /* check max. decoder output width */
2145
2146                         if (fuseReg & 0x8000U)
2147                                 hwFuseSts.maxDecPicWidthFuse = 1920;
2148                         else if (fuseReg & 0x4000U)
2149                                 hwFuseSts.maxDecPicWidthFuse = 1280;
2150                         else if (fuseReg & 0x2000U)
2151                                 hwFuseSts.maxDecPicWidthFuse = 720;
2152                         else if (fuseReg & 0x1000U)
2153                                 hwFuseSts.maxDecPicWidthFuse = 352;
2154                         else    /* remove warning */
2155                                 hwFuseSts.maxDecPicWidthFuse = 352;
2156
2157                         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
2158
2159                         /* Pp configuration */
2160                         configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
2161
2162                         if ((configReg >> DWL_PP_E) & 0x01U) {
2163                                 dec->ppSupport = 1;
2164                                 dec->maxPpOutPicWidth = configReg & 0x07FFU;
2165                                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
2166                                 dec->ppConfig = configReg;
2167                         } else {
2168                                 dec->ppSupport = 0;
2169                                 dec->maxPpOutPicWidth = 0;
2170                                 dec->ppConfig = 0;
2171                         }
2172
2173                         /* check the HW versio */
2174                         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
2175                                 /* Pp configuration */
2176                                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2177                                 if ((configReg >> DWL_PP_E) & 0x01U) {
2178                                         /* Pp fuse configuration */
2179                                         u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
2180
2181                                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
2182                                                 hwFuseSts.ppSupportFuse = 1;
2183                                                 /* check max. pp output width */
2184                                                 if (fuseRegPp & 0x8000U)
2185                                                         hwFuseSts.maxPpOutPicWidthFuse = 1920;
2186                                                 else if (fuseRegPp & 0x4000U)
2187                                                         hwFuseSts.maxPpOutPicWidthFuse = 1280;
2188                                                 else if (fuseRegPp & 0x2000U)
2189                                                         hwFuseSts.maxPpOutPicWidthFuse = 720;
2190                                                 else if (fuseRegPp & 0x1000U)
2191                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;
2192                                                 else
2193                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;
2194                                                 hwFuseSts.ppConfigFuse = fuseRegPp;
2195                                         } else {
2196                                                 hwFuseSts.ppSupportFuse = 0;
2197                                                 hwFuseSts.maxPpOutPicWidthFuse = 0;
2198                                                 hwFuseSts.ppConfigFuse = 0;
2199                                         }
2200                                 } else {
2201                                         hwFuseSts.ppSupportFuse = 0;
2202                                         hwFuseSts.maxPpOutPicWidthFuse = 0;
2203                                         hwFuseSts.ppConfigFuse = 0;
2204                                 }
2205
2206                                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
2207                                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
2208                                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
2209                                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
2210                                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
2211                                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
2212                                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
2213                                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
2214                                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
2215                                         dec->jpegSupport = JPEG_BASELINE;
2216                                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
2217                                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
2218                                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
2219                                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
2220                                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
2221                                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
2222
2223                                 /* check the pp config vs fuse status */
2224                                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
2225                                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
2226                                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
2227                                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
2228                                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
2229
2230                                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
2231                                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
2232                                 }
2233                                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
2234                                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
2235                                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;
2236                                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;
2237                                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;
2238                         }
2239                 }
2240
2241                 if (!cpu_is_rk3036()) {
2242                         configReg = pservice->enc_dev.hwregs[63];
2243                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2244                         enc->h264Enabled = (configReg >> 27) & 1;
2245                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2246                         enc->jpegEnabled = (configReg >> 25) & 1;
2247                         enc->vsEnabled = (configReg >> 24) & 1;
2248                         enc->rgbEnabled = (configReg >> 28) & 1;
2249                         /*enc->busType = (configReg >> 20) & 15;
2250                         enc->synthesisLanguage = (configReg >> 16) & 15;
2251                         enc->busWidth = (configReg >> 12) & 15;*/
2252                         enc->reg_size = pservice->reg_size;
2253                         enc->reserv[0] = enc->reserv[1] = 0;
2254                 }
2255
2256                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2257                 if (pservice->auto_freq) {
2258                         pr_info("vpu_service set to auto frequency mode\n");
2259                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2260                 }
2261
2262                 pservice->bug_dec_addr = cpu_is_rk30xx();
2263         } else {
2264                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2265                         dec->maxDecPicWidth = 1920;
2266                 else
2267                         dec->maxDecPicWidth = 4096;
2268                 /* disable frequency switch in hevc.*/
2269                 pservice->auto_freq = false;
2270         }
2271 }
2272
2273 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2274 {
2275         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2276         vpu_device *dev = &pservice->dec_dev;
2277         u32 raw_status;
2278         u32 irq_status;
2279
2280         vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);
2281
2282         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2283
2284         pr_debug("dec_irq\n");
2285
2286         if (irq_status & DEC_INTERRUPT_BIT) {
2287                 pr_debug("dec_isr dec %x\n", irq_status);
2288                 if ((irq_status & 0x40001) == 0x40001)
2289                 {
2290                         do {
2291                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2292                         } while ((irq_status & 0x40001) == 0x40001);
2293                 }
2294
2295                 /* clear dec IRQ */
2296                 if (pservice->hw_info->hw_id != HEVC_ID)
2297                         writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
2298                 else
2299                         writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2300                 atomic_add(1, &dev->irq_count_codec);
2301         }
2302
2303         if (pservice->hw_info->hw_id != HEVC_ID) {
2304                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2305                 if (irq_status & PP_INTERRUPT_BIT) {
2306                         pr_debug("vdpu_isr pp  %x\n", irq_status);
2307                         /* clear pp IRQ */
2308                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2309                         atomic_add(1, &dev->irq_count_pp);
2310                 }
2311         }
2312
2313         pservice->irq_status = raw_status;
2314
2315         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2316
2317         return IRQ_WAKE_THREAD;
2318 }
2319
2320 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2321 {
2322         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2323         vpu_device *dev = &pservice->dec_dev;
2324
2325         mutex_lock(pservice->lock);
2326         if (atomic_read(&dev->irq_count_codec)) {
2327 #if VPU_SERVICE_SHOW_TIME
2328                 do_gettimeofday(&dec_end);
2329                 pr_info("dec task: %ld ms\n",
2330                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2331                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2332 #endif
2333                 atomic_sub(1, &dev->irq_count_codec);
2334                 if (NULL == pservice->reg_codec) {
2335                         pr_err("error: dec isr with no task waiting\n");
2336                 } else {
2337                         reg_from_run_to_done(pservice, *pservice->reg_codec);
2338                 }
2339         }
2340
2341         if (atomic_read(&dev->irq_count_pp)) {
2342
2343 #if VPU_SERVICE_SHOW_TIME
2344                 do_gettimeofday(&pp_end);
2345                 printk("pp  task: %ld ms\n",
2346                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2347                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2348 #endif
2349
2350                 atomic_sub(1, &dev->irq_count_pp);
2351                 if (NULL == pservice->reg_pproc) {
2352                         pr_err("error: pp isr with no task waiting\n");
2353                 } else {
2354                         reg_from_run_to_done(pservice, pservice->reg_pproc);
2355                 }
2356         }
2357         try_set_reg(pservice);
2358         mutex_unlock(pservice->lock);
2359         return IRQ_HANDLED;
2360 }
2361
2362 static irqreturn_t vepu_irq(int irq, void *dev_id)
2363 {
2364         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2365         vpu_device *dev = &pservice->enc_dev;
2366         u32 irq_status;
2367
2368         vcodec_enter_mode_nolock(pservice->dev_id,  &pservice->reserved_mode);
2369         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2370
2371         pr_debug("vepu_irq irq status %x\n", irq_status);
2372
2373 #if VPU_SERVICE_SHOW_TIME
2374         do_gettimeofday(&enc_end);
2375         pr_info("enc task: %ld ms\n",
2376                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2377                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2378 #endif
2379         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2380                 /* clear enc IRQ */
2381                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2382                 atomic_add(1, &dev->irq_count_codec);
2383         }
2384
2385         pservice->irq_status = irq_status;
2386
2387         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2388
2389         return IRQ_WAKE_THREAD;
2390 }
2391
2392 static irqreturn_t vepu_isr(int irq, void *dev_id)
2393 {
2394         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2395         vpu_device *dev = &pservice->enc_dev;
2396
2397         mutex_lock(pservice->lock);
2398         if (atomic_read(&dev->irq_count_codec)) {
2399                 atomic_sub(1, &dev->irq_count_codec);
2400                 if (NULL == pservice->reg_codec) {
2401                         pr_err("error: enc isr with no task waiting\n");
2402                 } else {
2403                         reg_from_run_to_done(pservice, *pservice->reg_codec);
2404                 }
2405         }
2406         try_set_reg(pservice);
2407         mutex_unlock(pservice->lock);
2408         return IRQ_HANDLED;
2409 }
2410
2411 static int __init vcodec_service_init(void)
2412 {
2413         int ret;
2414
2415         g_combo.hevc_srv = NULL;
2416         g_combo.vpu_srv = NULL;
2417         INIT_LIST_HEAD(&g_combo.waiting);
2418         INIT_LIST_HEAD(&g_combo.running);
2419         mutex_init(&g_combo.run_lock);
2420         g_combo.reg_codec = NULL;
2421         g_combo.current_hw_mode = VCODEC_DEVICE_ID_VPU;
2422
2423         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2424                 pr_err("Platform device register failed (%d).\n", ret);
2425                 return ret;
2426         }
2427
2428 #ifdef CONFIG_DEBUG_FS
2429         vcodec_debugfs_init();
2430 #endif
2431
2432         return ret;
2433 }
2434
2435 static void __exit vcodec_service_exit(void)
2436 {
2437 #ifdef CONFIG_DEBUG_FS
2438         vcodec_debugfs_exit();
2439 #endif
2440
2441         platform_driver_unregister(&vcodec_driver);
2442 }
2443
2444 module_init(vcodec_service_init);
2445 module_exit(vcodec_service_exit);
2446
2447 #ifdef CONFIG_DEBUG_FS
2448 #include <linux/seq_file.h>
2449
2450 static int vcodec_debugfs_init()
2451 {
2452         parent = debugfs_create_dir("vcodec", NULL);
2453         if (!parent)
2454                 return -1;
2455
2456         return 0;
2457 }
2458
2459 static void vcodec_debugfs_exit()
2460 {
2461         debugfs_remove(parent);
2462 }
2463
2464 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2465 {
2466         return debugfs_create_dir(dirname, parent);
2467 }
2468
2469 static int debug_vcodec_show(struct seq_file *s, void *unused)
2470 {
2471         struct vpu_service_info *pservice = s->private;
2472         unsigned int i, n;
2473         vpu_reg *reg, *reg_tmp;
2474         vpu_session *session, *session_tmp;
2475
2476         mutex_lock(pservice->lock);
2477         vpu_service_power_on(pservice);
2478         if (pservice->hw_info->hw_id != HEVC_ID) {
2479                 seq_printf(s, "\nENC Registers:\n");
2480                 n = pservice->enc_dev.iosize >> 2;
2481                 for (i = 0; i < n; i++) {
2482                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));
2483                 }
2484         }
2485         seq_printf(s, "\nDEC Registers:\n");
2486         n = pservice->dec_dev.iosize >> 2;
2487         for (i = 0; i < n; i++)
2488                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2489
2490         seq_printf(s, "\nvpu service status:\n");
2491         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2492                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2493                 /*seq_printf(s, "waiting reg set %d\n");*/
2494                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2495                         seq_printf(s, "waiting register set\n");
2496                 }
2497                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2498                         seq_printf(s, "running register set\n");
2499                 }
2500                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2501                         seq_printf(s, "done    register set\n");
2502                 }
2503         }
2504         mutex_unlock(pservice->lock);
2505
2506         return 0;
2507 }
2508
2509 static int debug_vcodec_open(struct inode *inode, struct file *file)
2510 {
2511         return single_open(file, debug_vcodec_show, inode->i_private);
2512 }
2513
2514 #endif
2515
2516 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2517 #include "hevc_test_inc/pps_00.h"
2518 #include "hevc_test_inc/register_00.h"
2519 #include "hevc_test_inc/rps_00.h"
2520 #include "hevc_test_inc/scaling_list_00.h"
2521 #include "hevc_test_inc/stream_00.h"
2522
2523 #include "hevc_test_inc/pps_01.h"
2524 #include "hevc_test_inc/register_01.h"
2525 #include "hevc_test_inc/rps_01.h"
2526 #include "hevc_test_inc/scaling_list_01.h"
2527 #include "hevc_test_inc/stream_01.h"
2528
2529 #include "hevc_test_inc/cabac.h"
2530
2531 extern struct ion_client *rockchip_ion_client_create(const char * name);
2532
2533 static struct ion_client *ion_client = NULL;
2534 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2535 {
2536         int size = (len+15) & (~15);
2537         struct ion_handle *handle;
2538         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2539
2540         if (ion_client == NULL)
2541                 ion_client = rockchip_ion_client_create("vcodec");
2542
2543         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2544
2545         ptr = ion_map_kernel(ion_client, handle);
2546
2547         ion_phys(ion_client, handle, phy, &size);
2548
2549         memcpy(ptr, tbl, len);
2550
2551         return ptr;
2552 }
2553
2554 u8* get_align_ptr_no_copy(int len, u32 *phy)
2555 {
2556         int size = (len+15) & (~15);
2557         struct ion_handle *handle;
2558         u8 *ptr;
2559
2560         if (ion_client == NULL)
2561                 ion_client = rockchip_ion_client_create("vcodec");
2562
2563         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2564
2565         ptr = ion_map_kernel(ion_client, handle);
2566
2567         ion_phys(ion_client, handle, phy, &size);
2568
2569         return ptr;
2570 }
2571
2572 #define TEST_CNT    2
2573 static int hevc_test_case0(vpu_service_info *pservice)
2574 {
2575         vpu_session session;
2576         vpu_reg *reg;
2577         unsigned long size = 272;//sizeof(register_00); // registers array length
2578         int testidx = 0;
2579         int ret = 0;
2580
2581         u8 *pps_tbl[TEST_CNT];
2582         u8 *register_tbl[TEST_CNT];
2583         u8 *rps_tbl[TEST_CNT];
2584         u8 *scaling_list_tbl[TEST_CNT];
2585         u8 *stream_tbl[TEST_CNT];
2586
2587         int stream_size[2];
2588         int pps_size[2];
2589         int rps_size[2];
2590         int scl_size[2];
2591         int cabac_size[2];
2592
2593         u32 phy_pps;
2594         u32 phy_rps;
2595         u32 phy_scl;
2596         u32 phy_str;
2597         u32 phy_yuv;
2598         u32 phy_ref;
2599         u32 phy_cabac;
2600
2601         volatile u8 *stream_buf;
2602         volatile u8 *pps_buf;
2603         volatile u8 *rps_buf;
2604         volatile u8 *scl_buf;
2605         volatile u8 *yuv_buf;
2606         volatile u8 *cabac_buf;
2607         volatile u8 *ref_buf;
2608
2609         u8 *pps;
2610         u8 *yuv[2];
2611         int i;
2612
2613         pps_tbl[0] = pps_00;
2614         pps_tbl[1] = pps_01;
2615
2616         register_tbl[0] = register_00;
2617         register_tbl[1] = register_01;
2618
2619         rps_tbl[0] = rps_00;
2620         rps_tbl[1] = rps_01;
2621
2622         scaling_list_tbl[0] = scaling_list_00;
2623         scaling_list_tbl[1] = scaling_list_01;
2624
2625         stream_tbl[0] = stream_00;
2626         stream_tbl[1] = stream_01;
2627
2628         stream_size[0] = sizeof(stream_00);
2629         stream_size[1] = sizeof(stream_01);
2630
2631         pps_size[0] = sizeof(pps_00);
2632         pps_size[1] = sizeof(pps_01);
2633
2634         rps_size[0] = sizeof(rps_00);
2635         rps_size[1] = sizeof(rps_01);
2636
2637         scl_size[0] = sizeof(scaling_list_00);
2638         scl_size[1] = sizeof(scaling_list_01);
2639
2640         cabac_size[0] = sizeof(Cabac_table);
2641         cabac_size[1] = sizeof(Cabac_table);
2642
2643         /* create session */
2644         session.pid = current->pid;
2645         session.type = VPU_DEC;
2646         INIT_LIST_HEAD(&session.waiting);
2647         INIT_LIST_HEAD(&session.running);
2648         INIT_LIST_HEAD(&session.done);
2649         INIT_LIST_HEAD(&session.list_session);
2650         init_waitqueue_head(&session.wait);
2651         atomic_set(&session.task_running, 0);
2652         list_add_tail(&session.list_session, &pservice->session);
2653
2654         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2655         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2656
2657         while (testidx < TEST_CNT) {
2658                 /* create registers */
2659                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2660                 if (NULL == reg) {
2661                         pr_err("error: kmalloc fail in reg_init\n");
2662                         return -1;
2663                 }
2664
2665                 if (size > pservice->reg_size) {
2666                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2667                         size = pservice->reg_size;
2668                 }
2669                 reg->session = &session;
2670                 reg->type = session.type;
2671                 reg->size = size;
2672                 reg->freq = VPU_FREQ_DEFAULT;
2673                 reg->reg = (unsigned long *)&reg[1];
2674                 INIT_LIST_HEAD(&reg->session_link);
2675                 INIT_LIST_HEAD(&reg->status_link);
2676
2677                 /* TODO: stuff registers */
2678                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2679
2680                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2681                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2682                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2683                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2684                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2685
2686                 pps = pps_buf;
2687
2688                 /* TODO: replace reigster address */
2689                 for (i=0; i<64; i++) {
2690                         u32 scaling_offset;
2691                         u32 tmp;
2692
2693                         scaling_offset = (u32)pps[i*80+74];
2694                         scaling_offset += (u32)pps[i*80+75] << 8;
2695                         scaling_offset += (u32)pps[i*80+76] << 16;
2696                         scaling_offset += (u32)pps[i*80+77] << 24;
2697
2698                         tmp = phy_scl + scaling_offset;
2699
2700                         pps[i*80+74] = tmp & 0xff;
2701                         pps[i*80+75] = (tmp >> 8) & 0xff;
2702                         pps[i*80+76] = (tmp >> 16) & 0xff;
2703                         pps[i*80+77] = (tmp >> 24) & 0xff;
2704                 }
2705
2706                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2707                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2708
2709                 reg->reg[1] = 0x21;
2710                 reg->reg[4] = phy_str;
2711                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2712                 reg->reg[6] = phy_cabac;
2713                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2714                 reg->reg[42] = phy_pps;
2715                 reg->reg[43] = phy_rps;
2716                 for (i = 10; i <= 24; i++)
2717                         reg->reg[i] = phy_yuv;
2718
2719                 mutex_lock(pservice->lock);
2720                 list_add_tail(&reg->status_link, pservice->waiting);
2721                 list_add_tail(&reg->session_link, &session.waiting);
2722                 mutex_unlock(pservice->lock);
2723
2724                 printk("%s %d %p\n", __func__, __LINE__, pservice);
2725
2726                 /* stuff hardware */
2727                 try_set_reg(pservice);
2728
2729                 /* wait for result */
2730                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2731                 if (!list_empty(&session.done)) {
2732                         if (ret < 0)
2733                                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2734                         ret = 0;
2735                 } else {
2736                         if (unlikely(ret < 0)) {
2737                                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);
2738                         } else if (0 == ret) {
2739                                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2740                                 ret = -ETIMEDOUT;
2741                         }
2742                 }
2743                 if (ret < 0) {
2744                         int task_running = atomic_read(&session.task_running);
2745                         int n;
2746                         mutex_lock(pservice->lock);
2747                         vpu_service_dump(pservice);
2748                         if (task_running) {
2749                                 atomic_set(&session.task_running, 0);
2750                                 atomic_sub(task_running, &pservice->total_running);
2751                                 printk("%d task is running but not return, reset hardware...", task_running);
2752                                 vpu_reset(pservice);
2753                                 printk("done\n");
2754                         }
2755                         vpu_service_session_clear(pservice, &session);
2756                         mutex_unlock(pservice->lock);
2757
2758                         printk("\nDEC Registers:\n");
2759                         n = pservice->dec_dev.iosize >> 2;
2760                         for (i=0; i<n; i++)
2761                                 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2762
2763                         pr_err("test index %d failed\n", testidx);
2764                         break;
2765                 } else {
2766                         pr_info("test index %d success\n", testidx);
2767
2768                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2769
2770                         for (i=0; i<68; i++) {
2771                                 if (i % 4 == 0)
2772                                         printk("%02d: ", i);
2773                                 printk("%08x ", reg->reg[i]);
2774                                 if ((i+1) % 4 == 0)
2775                                         printk("\n");
2776                         }
2777
2778                         testidx++;
2779                 }
2780
2781                 reg_deinit(pservice, reg);
2782         }
2783
2784         return 0;
2785 }
2786
2787 #endif
2788