arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/fs.h>
  25 #include <linux/ioport.h>
  26 #include <linux/miscdevice.h>
  27 #include <linux/mm.h>
  28 #include <linux/poll.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/sched.h>
  31 #include <linux/slab.h>
  32 #include <linux/wakelock.h>
  33 #include <linux/cdev.h>
  34 #include <linux/of.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39 #include <linux/regmap.h>
  40 #include <linux/mfd/syscon.h>
  41
  42 #include <asm/cacheflush.h>
  43 #include <linux/uaccess.h>
  44 #include <linux/rockchip/grf.h>
  45
  46 #if defined(CONFIG_ION_ROCKCHIP)
  47 #include <linux/rockchip_ion.h>
  48 #endif
  49
  50 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  51 #define CONFIG_VCODEC_MMU
  52 #endif
  53
  54 #ifdef CONFIG_VCODEC_MMU
  55 #include <linux/rockchip-iovmm.h>
  56 #include <linux/dma-buf.h>
  57 #endif
  58
  59 #ifdef CONFIG_DEBUG_FS
  60 #include <linux/debugfs.h>
  61 #endif
  62
  63 #if defined(CONFIG_ARCH_RK319X)
  64 #include <mach/grf.h>
  65 #endif
  66
  67 #include "vcodec_service.h"
  68
  69 static int debug;
  70 module_param(debug, int, S_IRUGO | S_IWUSR);
  71 MODULE_PARM_DESC(debug,
  72                  "Debug level - higher value produces more verbose messages");
  73
  74 #define HEVC_TEST_ENABLE        0
  75 #define VCODEC_CLOCK_ENABLE     1
  76
  77 typedef enum {
  78         VPU_DEC_ID_9190         = 0x6731,
  79         VPU_ID_8270             = 0x8270,
  80         VPU_ID_4831             = 0x4831,
  81         HEVC_ID                 = 0x6867,
  82 } VPU_HW_ID;
  83
  84 enum VPU_HW_SPEC {
  85         VPU_TYPE_VPU,
  86         VPU_TYPE_HEVC,
  87         VPU_TYPE_COMBO_NOENC,
  88         VPU_TYPE_COMBO
  89 };
  90
  91 typedef enum {
  92         VPU_DEC_TYPE_9190       = 0,
  93         VPU_ENC_TYPE_8270       = 0x100,
  94         VPU_ENC_TYPE_4831       ,
  95 } VPU_HW_TYPE_E;
  96
  97 typedef enum VPU_FREQ {
  98         VPU_FREQ_200M,
  99         VPU_FREQ_266M,
 100         VPU_FREQ_300M,
 101         VPU_FREQ_400M,
 102         VPU_FREQ_500M,
 103         VPU_FREQ_600M,
 104         VPU_FREQ_DEFAULT,
 105         VPU_FREQ_BUT,
 106 } VPU_FREQ;
 107
 108 typedef struct {
 109         VPU_HW_ID               hw_id;
 110         unsigned long           hw_addr;
 111         unsigned long           enc_offset;
 112         unsigned long           enc_reg_num;
 113         unsigned long           enc_io_size;
 114         unsigned long           dec_offset;
 115         unsigned long           dec_reg_num;
 116         unsigned long           dec_io_size;
 117 } VPU_HW_INFO_E;
 118
 119 struct extra_info_elem {
 120         u32 index;
 121         u32 offset;
 122 };
 123
 124 #define EXTRA_INFO_MAGIC        0x4C4A46
 125
 126 struct extra_info_for_iommu {
 127         u32 magic;
 128         u32 cnt;
 129         struct extra_info_elem elem[20];
 130 };
 131
 132 #define VPU_SERVICE_SHOW_TIME                   0
 133
 134 #if VPU_SERVICE_SHOW_TIME
 135 static struct timeval enc_start, enc_end;
 136 static struct timeval dec_start, dec_end;
 137 static struct timeval pp_start,  pp_end;
 138 #endif
 139
 140 #define MHZ                                     (1000*1000)
 141
 142 #define REG_NUM_9190_DEC                        (60)
 143 #define REG_NUM_9190_PP                         (41)
 144 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 145
 146 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 147
 148 #define REG_NUM_ENC_8270                        (96)
 149 #define REG_SIZE_ENC_8270                       (0x200)
 150 #define REG_NUM_ENC_4831                        (164)
 151 #define REG_SIZE_ENC_4831                       (0x400)
 152
 153 #define REG_NUM_HEVC_DEC                        (68)
 154
 155 #define SIZE_REG(reg)                           ((reg)*4)
 156
 157 static VPU_HW_INFO_E vpu_hw_set[] = {
 158         [0] = {
 159                 .hw_id          = VPU_ID_8270,
 160                 .hw_addr        = 0,
 161                 .enc_offset     = 0x0,
 162                 .enc_reg_num    = REG_NUM_ENC_8270,
 163                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 164                 .dec_offset     = REG_SIZE_ENC_8270,
 165                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 166                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 167         },
 168         [1] = {
 169                 .hw_id          = VPU_ID_4831,
 170                 .hw_addr        = 0,
 171                 .enc_offset     = 0x0,
 172                 .enc_reg_num    = REG_NUM_ENC_4831,
 173                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 174                 .dec_offset     = REG_SIZE_ENC_4831,
 175                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 176                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 177         },
 178         [2] = {
 179                 .hw_id          = HEVC_ID,
 180                 .hw_addr        = 0,
 181                 .dec_offset     = 0x0,
 182                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 183                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 184         },
 185         [3] = {
 186                 .hw_id          = VPU_DEC_ID_9190,
 187                 .hw_addr        = 0,
 188                 .enc_offset     = 0x0,
 189                 .enc_reg_num    = 0,
 190                 .enc_io_size    = 0,
 191                 .dec_offset     = 0,
 192                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 193                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 194         },
 195 };
 196
 197
 198 #define DEC_INTERRUPT_REGISTER                  1
 199 #define PP_INTERRUPT_REGISTER                   60
 200 #define ENC_INTERRUPT_REGISTER                  1
 201
 202 #define DEC_INTERRUPT_BIT                       0x100
 203 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 204 #define PP_INTERRUPT_BIT                        0x100
 205 #define ENC_INTERRUPT_BIT                       0x1
 206
 207 #define HEVC_DEC_INT_RAW_BIT                    0x200
 208 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 209 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 210 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 211
 212 #define VPU_REG_EN_ENC                          14
 213 #define VPU_REG_ENC_GATE                        2
 214 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 215
 216 #define VPU_REG_EN_DEC                          1
 217 #define VPU_REG_DEC_GATE                        2
 218 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 219 #define VPU_REG_EN_PP                           0
 220 #define VPU_REG_PP_GATE                         1
 221 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 222 #define VPU_REG_EN_DEC_PP                       1
 223 #define VPU_REG_DEC_PP_GATE                     61
 224 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 225
 226 #define DEBUG
 227 #ifdef DEBUG
 228 #define vpu_debug(level, fmt, args...)                          \
 229         do {                                                    \
 230                 if (debug >= level)                             \
 231                         pr_info("%s:%d: " fmt,                  \
 232                                  __func__, __LINE__, ##args);   \
 233         } while (0)
 234 #else
 235 #define vpu_debug(level, fmt, args...)
 236 #endif
 237
 238 #define vpu_debug_enter() vpu_debug(4, "enter\n")
 239 #define vpu_debug_leave() vpu_debug(4, "leave\n")
 240
 241 #define vpu_err(fmt, args...)                           \
 242                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 243
 244 #if defined(CONFIG_VCODEC_MMU)
 245 static u8 addr_tbl_vpu_h264dec[] = {
 246         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 247         25, 26, 27, 28, 29, 40, 41
 248 };
 249
 250 static u8 addr_tbl_vpu_vp8dec[] = {
 251         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 252 };
 253
 254 static u8 addr_tbl_vpu_vp6dec[] = {
 255         12, 13, 14, 18, 27, 40
 256 };
 257
 258 static u8 addr_tbl_vpu_vc1dec[] = {
 259         12, 13, 14, 15, 16, 17, 27, 41
 260 };
 261
 262 static u8 addr_tbl_vpu_jpegdec[] = {
 263         12, 40, 66, 67
 264 };
 265
 266 static u8 addr_tbl_vpu_defaultdec[] = {
 267         12, 13, 14, 15, 16, 17, 40, 41
 268 };
 269
 270 static u8 addr_tbl_vpu_enc[] = {
 271         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 272 };
 273
 274 static u8 addr_tbl_hevc_dec[] = {
 275         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 276         21, 22, 23, 24, 42, 43
 277 };
 278 #endif
 279
 280 enum VPU_DEC_FMT {
 281         VPU_DEC_FMT_H264,
 282         VPU_DEC_FMT_MPEG4,
 283         VPU_DEC_FMT_H263,
 284         VPU_DEC_FMT_JPEG,
 285         VPU_DEC_FMT_VC1,
 286         VPU_DEC_FMT_MPEG2,
 287         VPU_DEC_FMT_MPEG1,
 288         VPU_DEC_FMT_VP6,
 289         VPU_DEC_FMT_RV,
 290         VPU_DEC_FMT_VP7,
 291         VPU_DEC_FMT_VP8,
 292         VPU_DEC_FMT_AVS,
 293         VPU_DEC_FMT_SVC,
 294         VPU_DEC_FMT_VC2,
 295         VPU_DEC_FMT_MVC,
 296         VPU_DEC_FMT_THEORA,
 297         VPU_DEC_FMT_RES
 298 };
 299
 300 /**
 301  * struct for process session which connect to vpu
 302  *
 303  * @author ChenHengming (2011-5-3)
 304  */
 305 typedef struct vpu_session {
 306         VPU_CLIENT_TYPE         type;
 307         /* a linked list of data so we can access them for debugging */
 308         struct list_head        list_session;
 309         /* a linked list of register data waiting for process */
 310         struct list_head        waiting;
 311         /* a linked list of register data in processing */
 312         struct list_head        running;
 313         /* a linked list of register data processed */
 314         struct list_head        done;
 315         wait_queue_head_t       wait;
 316         pid_t                   pid;
 317         atomic_t                task_running;
 318 } vpu_session;
 319
 320 /**
 321  * struct for process register set
 322  *
 323  * @author ChenHengming (2011-5-4)
 324  */
 325 typedef struct vpu_reg {
 326         VPU_CLIENT_TYPE         type;
 327         VPU_FREQ                freq;
 328         vpu_session             *session;
 329         struct list_head        session_link;           /* link to vpu service session */
 330         struct list_head        status_link;            /* link to register set list */
 331         unsigned long           size;
 332 #if defined(CONFIG_VCODEC_MMU)
 333         struct list_head        mem_region_list;
 334 #endif
 335         unsigned long           *reg;
 336 } vpu_reg;
 337
 338 typedef struct vpu_device {
 339         atomic_t                irq_count_codec;
 340         atomic_t                irq_count_pp;
 341         unsigned long           iobaseaddr;
 342         unsigned int            iosize;
 343         volatile u32            *hwregs;
 344 } vpu_device;
 345
 346 enum vcodec_device_id {
 347         VCODEC_DEVICE_ID_VPU,
 348         VCODEC_DEVICE_ID_HEVC,
 349         VCODEC_DEVICE_ID_COMBO
 350 };
 351
 352 enum VCODEC_RUNNING_MODE {
 353         VCODEC_RUNNING_MODE_NONE = -1,
 354         VCODEC_RUNNING_MODE_VPU,
 355         VCODEC_RUNNING_MODE_HEVC,
 356 };
 357
 358 struct vcodec_mem_region {
 359         struct list_head srv_lnk;
 360         struct list_head reg_lnk;
 361         struct list_head session_lnk;
 362         unsigned long iova;     /* virtual address for iommu */
 363         unsigned long len;
 364         u32 reg_idx;
 365         struct ion_handle *hdl;
 366 };
 367
 368 enum vpu_ctx_state {
 369         MMU_ACTIVATED   = BIT(0)
 370 };
 371
 372 struct vpu_subdev_data {
 373         struct cdev cdev;
 374         dev_t dev_t;
 375         struct class *cls;
 376         struct device *child_dev;
 377
 378         int irq_enc;
 379         int irq_dec;
 380         struct vpu_service_info *pservice;
 381
 382         u32 *regs;
 383         enum VCODEC_RUNNING_MODE mode;
 384         struct list_head lnk_service;
 385
 386         struct device *dev;
 387
 388         vpu_device enc_dev;
 389         vpu_device dec_dev;
 390         VPU_HW_INFO_E *hw_info;
 391
 392         unsigned long reg_size;
 393         unsigned long state;
 394
 395 #if defined(CONFIG_VCODEC_MMU)
 396         struct device *mmu_dev;
 397 #endif
 398 };
 399
 400 typedef struct vpu_service_info {
 401         struct wake_lock        wake_lock;
 402         struct delayed_work     power_off_work;
 403         struct mutex            lock;
 404         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */
 405         struct list_head        running;                /* link to link_reg in struct vpu_reg */
 406         struct list_head        done;                   /* link to link_reg in struct vpu_reg */
 407         struct list_head        session;                /* link to list_session in struct vpu_session */
 408         atomic_t                total_running;
 409         bool                    enabled;
 410         vpu_reg                 *reg_codec;
 411         vpu_reg                 *reg_pproc;
 412         vpu_reg                 *reg_resev;
 413         VPUHwDecConfig_t        dec_config;
 414         VPUHwEncConfig_t        enc_config;
 415
 416         bool                    auto_freq;
 417         bool                    bug_dec_addr;
 418         atomic_t                freq_status;
 419
 420         struct clk              *aclk_vcodec;
 421         struct clk              *hclk_vcodec;
 422         struct clk              *clk_core;
 423         struct clk              *clk_cabac;
 424         struct clk              *pd_video;
 425
 426         struct device           *dev;
 427
 428         struct dentry           *debugfs_dir;
 429         struct dentry           *debugfs_file_regs;
 430
 431         u32 irq_status;
 432 #if defined(CONFIG_VCODEC_MMU)
 433         struct ion_client       *ion_client;
 434         struct list_head        mem_region_list;
 435 #endif
 436
 437         enum vcodec_device_id   dev_id;
 438
 439         enum VCODEC_RUNNING_MODE curr_mode;
 440         u32 prev_mode;
 441
 442         struct delayed_work     simulate_work;
 443
 444         u32 mode_bit;
 445         u32 mode_ctrl;
 446         u32 *reg_base;
 447         u32 ioaddr;
 448         u32 *grf_base;
 449         char *name;
 450
 451         u32 subcnt;
 452         struct list_head subdev_list;
 453 } vpu_service_info;
 454
 455 struct vcodec_combo {
 456         struct vpu_service_info *vpu_srv;
 457         struct vpu_service_info *hevc_srv;
 458         struct list_head waiting;
 459         struct list_head running;
 460         struct mutex run_lock;
 461         vpu_reg *reg_codec;
 462         enum vcodec_device_id current_hw_mode;
 463 };
 464
 465 typedef struct vpu_request {
 466         unsigned long *req;
 467         unsigned long size;
 468 } vpu_request;
 469
 470 /* debugfs root directory for all device (vpu, hevc).*/
 471 static struct dentry *parent;
 472
 473 #ifdef CONFIG_DEBUG_FS
 474 static int vcodec_debugfs_init(void);
 475 static void vcodec_debugfs_exit(void);
 476 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 477 static int debug_vcodec_open(struct inode *inode, struct file *file);
 478
 479 static const struct file_operations debug_vcodec_fops = {
 480         .open = debug_vcodec_open,
 481         .read = seq_read,
 482         .llseek = seq_lseek,
 483         .release = single_release,
 484 };
 485 #endif
 486
 487 #define VDPU_SOFT_RESET_REG     101
 488 #define VDPU_CLEAN_CACHE_REG    516
 489 #define VEPU_CLEAN_CACHE_REG    772
 490 #define HEVC_CLEAN_CACHE_REG    260
 491
 492 #define VPU_REG_ENABLE(base, reg)       do { \
 493                                                 base[reg] = 1; \
 494                                         } while (0)
 495
 496 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 497 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 498 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 499 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 500
 501 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 502 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 503
 504 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 505 {
 506         int bits;
 507         u32 raw = 0;
 508         struct vpu_service_info *pservice = data->pservice;
 509         struct vpu_subdev_data *subdata, *n;
 510         if (pservice->subcnt < 2 || pservice->curr_mode == data->mode) {
 511                 pservice->prev_mode = pservice->curr_mode;
 512                 return;
 513         }
 514         vpu_debug(3, "vcodec enter mode %d\n", data->mode);
 515 #if defined(CONFIG_VCODEC_MMU)
 516         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 517                 if (data != subdata && subdata->mmu_dev &&
 518                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 519                         clear_bit(MMU_ACTIVATED, &subdata->state);
 520                         rockchip_iovmm_deactivate(subdata->dev);
 521                 }
 522         }
 523 #endif
 524         bits = 1 << pservice->mode_bit;
 525         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 526         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 527                 writel_relaxed(raw | bits | (bits << 16),
 528                         pservice->grf_base + pservice->mode_ctrl / 4);
 529         else
 530                 writel_relaxed((raw & (~bits)) | (bits << 16),
 531                         pservice->grf_base + pservice->mode_ctrl / 4);
 532 #if defined(CONFIG_VCODEC_MMU)
 533         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 534                 set_bit(MMU_ACTIVATED, &data->state);
 535                 rockchip_iovmm_activate(data->dev);
 536         }
 537 #endif
 538         pservice->prev_mode = pservice->curr_mode;
 539         pservice->curr_mode = data->mode;
 540 }
 541
 542 static void vcodec_exit_mode(struct vpu_service_info *pservice)
 543 {
 544
 545 }
 546
 547 static int vpu_get_clk(struct vpu_service_info *pservice)
 548 {
 549 #if VCODEC_CLOCK_ENABLE
 550         switch (pservice->dev_id) {
 551         case VCODEC_DEVICE_ID_HEVC:
 552                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 553                 if (IS_ERR(pservice->clk_cabac)) {
 554                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 555                         return -1;
 556                 }
 557
 558                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 559                 if (IS_ERR(pservice->pd_video)) {
 560                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 561                         return -1;
 562                 }
 563         case VCODEC_DEVICE_ID_COMBO:
 564                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 565                 if (IS_ERR(pservice->clk_core)) {
 566                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 567                         return -1;
 568                 }
 569         case VCODEC_DEVICE_ID_VPU:
 570                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 571                 if (IS_ERR(pservice->aclk_vcodec)) {
 572                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 573                         return -1;
 574                 }
 575
 576                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 577                 if (IS_ERR(pservice->hclk_vcodec)) {
 578                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 579                         return -1;
 580                 }
 581                 if (pservice->pd_video == NULL) {
 582                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 583                         if (IS_ERR(pservice->pd_video))
 584                                 pservice->pd_video = NULL;
 585                 }
 586                 break;
 587         default:
 588                 ;
 589         }
 590
 591         return 0;
 592 #else
 593         return 0;
 594 #endif
 595 }
 596
 597 static void vpu_put_clk(struct vpu_service_info *pservice)
 598 {
 599 #if VCODEC_CLOCK_ENABLE
 600         if (pservice->pd_video)
 601                 devm_clk_put(pservice->dev, pservice->pd_video);
 602         if (pservice->aclk_vcodec)
 603                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 604         if (pservice->hclk_vcodec)
 605                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 606         if (pservice->clk_core)
 607                 devm_clk_put(pservice->dev, pservice->clk_core);
 608         if (pservice->clk_cabac)
 609                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 610 #endif
 611 }
 612
 613 static void vpu_reset(struct vpu_service_info *pservice)
 614 {
 615 #if defined(CONFIG_ARCH_RK29)
 616         clk_disable(aclk_ddr_vepu);
 617         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 618         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 619         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 620         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 621         mdelay(10);
 622         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 623         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 624         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 625         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 626         clk_enable(aclk_ddr_vepu);
 627 #elif defined(CONFIG_ARCH_RK30)
 628         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 629         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 630         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 631         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 632         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 633         mdelay(1);
 634         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 635         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 636         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 637         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 638         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 639 #endif
 640         pservice->reg_codec = NULL;
 641         pservice->reg_pproc = NULL;
 642         pservice->reg_resev = NULL;
 643 }
 644
 645 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 646 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 647 {
 648         vpu_reg *reg, *n;
 649         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 650                 reg_deinit(data, reg);
 651         }
 652         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 653                 reg_deinit(data, reg);
 654         }
 655         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 656                 reg_deinit(data, reg);
 657         }
 658 }
 659
 660 static void vpu_service_dump(struct vpu_service_info *pservice)
 661 {
 662 }
 663
 664 static void vpu_service_power_off(struct vpu_service_info *pservice)
 665 {
 666         int total_running;
 667         struct vpu_subdev_data *data = NULL, *n;
 668         if (!pservice->enabled)
 669                 return;
 670
 671         pservice->enabled = false;
 672         total_running = atomic_read(&pservice->total_running);
 673         if (total_running) {
 674                 pr_alert("alert: power off when %d task running!!\n", total_running);
 675                 mdelay(50);
 676                 pr_alert("alert: delay 50 ms for running task\n");
 677                 vpu_service_dump(pservice);
 678         }
 679
 680         pr_info("%s: power off...", dev_name(pservice->dev));
 681         udelay(10);
 682 #if defined(CONFIG_VCODEC_MMU)
 683         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 684                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 685                         clear_bit(MMU_ACTIVATED, &data->state);
 686                         rockchip_iovmm_deactivate(data->dev);
 687                 }
 688         }
 689         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 690 #endif
 691
 692 #if VCODEC_CLOCK_ENABLE
 693         if (pservice->pd_video)
 694                 clk_disable_unprepare(pservice->pd_video);
 695         if (pservice->hclk_vcodec)
 696                 clk_disable_unprepare(pservice->hclk_vcodec);
 697         if (pservice->aclk_vcodec)
 698                 clk_disable_unprepare(pservice->aclk_vcodec);
 699         if (pservice->clk_core)
 700                 clk_disable_unprepare(pservice->clk_core);
 701         if (pservice->clk_cabac)
 702                 clk_disable_unprepare(pservice->clk_cabac);
 703 #endif
 704
 705         wake_unlock(&pservice->wake_lock);
 706         pr_info("done\n");
 707 }
 708
 709 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 710 {
 711         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 712 }
 713
 714 static void vpu_power_off_work(struct work_struct *work_s)
 715 {
 716         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 717         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 718
 719         if (mutex_trylock(&pservice->lock)) {
 720                 vpu_service_power_off(pservice);
 721                 mutex_unlock(&pservice->lock);
 722         } else {
 723                 /* Come back later if the device is busy... */
 724                 vpu_queue_power_off_work(pservice);
 725         }
 726 }
 727
 728 static void vpu_service_power_on(struct vpu_service_info *pservice)
 729 {
 730         static ktime_t last;
 731         ktime_t now = ktime_get();
 732         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 733                 cancel_delayed_work_sync(&pservice->power_off_work);
 734                 vpu_queue_power_off_work(pservice);
 735                 last = now;
 736         }
 737         if (pservice->enabled)
 738                 return ;
 739
 740         pservice->enabled = true;
 741         pr_info("%s: power on\n", dev_name(pservice->dev));
 742
 743 #define BIT_VCODEC_CLK_SEL      (1<<10)
 744         if (cpu_is_rk312x())
 745                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 746                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 747                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 748
 749 #if VCODEC_CLOCK_ENABLE
 750         if (pservice->aclk_vcodec)
 751                 clk_prepare_enable(pservice->aclk_vcodec);
 752         if (pservice->hclk_vcodec)
 753                 clk_prepare_enable(pservice->hclk_vcodec);
 754         if (pservice->clk_core)
 755                 clk_prepare_enable(pservice->clk_core);
 756         if (pservice->clk_cabac)
 757                 clk_prepare_enable(pservice->clk_cabac);
 758         if (pservice->pd_video)
 759                 clk_prepare_enable(pservice->pd_video);
 760 #endif
 761
 762         udelay(10);
 763         wake_lock(&pservice->wake_lock);
 764 }
 765
 766 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 767 {
 768         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
 769         return ((type == 8) || (type == 4));
 770 }
 771
 772 static inline bool reg_check_interlace(vpu_reg *reg)
 773 {
 774         unsigned long type = (reg->reg[3] & (1 << 23));
 775         return (type > 0);
 776 }
 777
 778 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 779 {
 780         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 781         return type;
 782 }
 783
 784 static inline int reg_probe_width(vpu_reg *reg)
 785 {
 786         int width_in_mb = reg->reg[4] >> 23;
 787         return width_in_mb * 16;
 788 }
 789
 790 #if defined(CONFIG_VCODEC_MMU)
 791 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
 792 {
 793         struct vpu_service_info *pservice = data->pservice;
 794         struct ion_handle *hdl;
 795         int ret = 0;
 796         struct vcodec_mem_region *mem_region;
 797
 798         hdl = ion_import_dma_buf(pservice->ion_client, fd);
 799         if (IS_ERR(hdl)) {
 800                 vpu_err("import dma-buf from fd %d failed\n", fd);
 801                 return PTR_ERR(hdl);
 802         }
 803         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 804
 805         if (mem_region == NULL) {
 806                 vpu_err("allocate memory for iommu memory region failed\n");
 807                 ion_free(pservice->ion_client, hdl);
 808                 return -1;
 809         }
 810
 811         mem_region->hdl = hdl;
 812         vcodec_enter_mode(data);
 813         ret = ion_map_iommu(data->dev, pservice->ion_client,
 814                 mem_region->hdl, &mem_region->iova, &mem_region->len);
 815         vcodec_exit_mode(pservice);
 816
 817         if (ret < 0) {
 818                 vpu_err("ion map iommu failed\n");
 819                 kfree(mem_region);
 820                 ion_free(pservice->ion_client, hdl);
 821                 return ret;
 822         }
 823         INIT_LIST_HEAD(&mem_region->reg_lnk);
 824         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 825         return mem_region->iova;
 826 }
 827
 828 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
 829                                 int size, vpu_reg *reg,
 830                                 struct extra_info_for_iommu *ext_inf)
 831 {
 832         struct vpu_service_info *pservice = data->pservice;
 833         int i;
 834         int usr_fd = 0;
 835         int offset = 0;
 836
 837         if (tbl == NULL || size <= 0) {
 838                 dev_err(pservice->dev, "input arguments invalidate\n");
 839                 return -1;
 840         }
 841
 842         vpu_service_power_on(pservice);
 843
 844         for (i = 0; i < size; i++) {
 845                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 846
 847                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
 848                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 849                         /* special for vpu dec num 41 regitster */
 850                         offset = reg->reg[tbl[i]] >> 10 << 4;
 851                 else
 852                         offset = reg->reg[tbl[i]] >> 10;
 853
 854                 if (usr_fd != 0) {
 855                         struct ion_handle *hdl;
 856                         int ret = 0;
 857                         struct vcodec_mem_region *mem_region;
 858
 859                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 860                         if (IS_ERR(hdl)) {
 861                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 862                                 return PTR_ERR(hdl);
 863                         }
 864
 865                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
 866                                 int i = 0;
 867                                 char *pps;
 868                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
 869                                 for (i=0; i<64; i++) {
 870                                         u32 scaling_offset;
 871                                         u32 tmp;
 872                                         int scaling_fd= 0;
 873                                         scaling_offset = (u32)pps[i*80+74];
 874                                         scaling_offset += (u32)pps[i*80+75] << 8;
 875                                         scaling_offset += (u32)pps[i*80+76] << 16;
 876                                         scaling_offset += (u32)pps[i*80+77] << 24;
 877                                         scaling_fd = scaling_offset&0x3ff;
 878                                         scaling_offset = scaling_offset >> 10;
 879                                         if(scaling_fd > 0) {
 880                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
 881                                                 tmp += scaling_offset;
 882                                                 pps[i*80+74] = tmp & 0xff;
 883                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
 884                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
 885                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
 886                                         }
 887                                 }
 888                         }
 889
 890                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 891
 892                         if (mem_region == NULL) {
 893                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 894                                 ion_free(pservice->ion_client, hdl);
 895                                 return -1;
 896                         }
 897
 898                         mem_region->hdl = hdl;
 899                         mem_region->reg_idx = tbl[i];
 900                         vcodec_enter_mode(data);
 901                         ret = ion_map_iommu(data->dev,
 902                                             pservice->ion_client,
 903                                             mem_region->hdl,
 904                                             &mem_region->iova,
 905                                             &mem_region->len);
 906                         vcodec_exit_mode(pservice);
 907
 908                         if (ret < 0) {
 909                                 dev_err(pservice->dev, "ion map iommu failed\n");
 910                                 kfree(mem_region);
 911                                 ion_free(pservice->ion_client, hdl);
 912                                 return ret;
 913                         }
 914                         reg->reg[tbl[i]] = mem_region->iova + offset;
 915                         INIT_LIST_HEAD(&mem_region->reg_lnk);
 916                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 917                 }
 918         }
 919
 920         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
 921                 for (i=0; i<ext_inf->cnt; i++) {
 922                         vpu_debug(3, "reg[%d] + offset %d\n", ext_inf->elem[i].index, ext_inf->elem[i].offset);
 923                         reg->reg[ext_inf->elem[i].index] += ext_inf->elem[i].offset;
 924                 }
 925         }
 926
 927         return 0;
 928 }
 929
 930 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
 931                                         vpu_reg *reg,
 932                                         struct extra_info_for_iommu *ext_inf)
 933 {
 934         VPU_HW_ID hw_id;
 935         u8 *tbl;
 936         int size = 0;
 937
 938         hw_id = data->hw_info->hw_id;
 939
 940         if (hw_id == HEVC_ID) {
 941                 tbl = addr_tbl_hevc_dec;
 942                 size = sizeof(addr_tbl_hevc_dec);
 943         } else {
 944                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 945                         switch (reg_check_fmt(reg)) {
 946                         case VPU_DEC_FMT_H264:
 947                                 {
 948                                         tbl = addr_tbl_vpu_h264dec;
 949                                         size = sizeof(addr_tbl_vpu_h264dec);
 950                                         break;
 951                                 }
 952                         case VPU_DEC_FMT_VP8:
 953                         case VPU_DEC_FMT_VP7:
 954                                 {
 955                                         tbl = addr_tbl_vpu_vp8dec;
 956                                         size = sizeof(addr_tbl_vpu_vp8dec);
 957                                         break;
 958                                 }
 959
 960                         case VPU_DEC_FMT_VP6:
 961                                 {
 962                                         tbl = addr_tbl_vpu_vp6dec;
 963                                         size = sizeof(addr_tbl_vpu_vp6dec);
 964                                         break;
 965                                 }
 966                         case VPU_DEC_FMT_VC1:
 967                                 {
 968                                         tbl = addr_tbl_vpu_vc1dec;
 969                                         size = sizeof(addr_tbl_vpu_vc1dec);
 970                                         break;
 971                                 }
 972
 973                         case VPU_DEC_FMT_JPEG:
 974                                 {
 975                                         tbl = addr_tbl_vpu_jpegdec;
 976                                         size = sizeof(addr_tbl_vpu_jpegdec);
 977                                         break;
 978                                 }
 979                         default:
 980                                 tbl = addr_tbl_vpu_defaultdec;
 981                                 size = sizeof(addr_tbl_vpu_defaultdec);
 982                                 break;
 983                         }
 984                 } else if (reg->type == VPU_ENC) {
 985                         tbl = addr_tbl_vpu_enc;
 986                         size = sizeof(addr_tbl_vpu_enc);
 987                 }
 988         }
 989
 990         if (size != 0) {
 991                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
 992         } else {
 993                 return -1;
 994         }
 995 }
 996 #endif
 997
 998 static vpu_reg *reg_init(struct vpu_subdev_data *data,
 999         vpu_session *session, void __user *src, unsigned long size)
1000 {
1001         struct vpu_service_info *pservice = data->pservice;
1002         int extra_size = 0;
1003         struct extra_info_for_iommu extra_info;
1004         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1005
1006         vpu_debug_enter();
1007
1008         if (NULL == reg) {
1009                 vpu_err("error: kmalloc fail in reg_init\n");
1010                 return NULL;
1011         }
1012
1013         if (size > data->reg_size) {
1014                 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n",
1015                   size, pservice->reg_size);
1016                 size = pservice->reg_size;*/
1017                 extra_size = size - data->reg_size;
1018                 size = data->reg_size;
1019         }
1020         reg->session = session;
1021         reg->type = session->type;
1022         reg->size = size;
1023         reg->freq = VPU_FREQ_DEFAULT;
1024         reg->reg = (unsigned long *)&reg[1];
1025         INIT_LIST_HEAD(&reg->session_link);
1026         INIT_LIST_HEAD(&reg->status_link);
1027
1028 #if defined(CONFIG_VCODEC_MMU)
1029         if (data->mmu_dev)
1030                 INIT_LIST_HEAD(&reg->mem_region_list);
1031 #endif
1032
1033         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1034                 vpu_err("error: copy_from_user failed in reg_init\n");
1035                 kfree(reg);
1036                 return NULL;
1037         }
1038
1039         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1040                 vpu_err("error: copy_from_user failed in reg_init\n");
1041                 kfree(reg);
1042                 return NULL;
1043         }
1044
1045 #if defined(CONFIG_VCODEC_MMU)
1046         if (data->mmu_dev &&
1047             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1048                 vpu_err("error: translate reg address failed\n");
1049                 kfree(reg);
1050                 return NULL;
1051         }
1052 #endif
1053
1054         mutex_lock(&pservice->lock);
1055         list_add_tail(&reg->status_link, &pservice->waiting);
1056         list_add_tail(&reg->session_link, &session->waiting);
1057         mutex_unlock(&pservice->lock);
1058
1059         if (pservice->auto_freq) {
1060                 if (!soc_is_rk2928g()) {
1061                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1062                                 if (reg_check_rmvb_wmv(reg)) {
1063                                         reg->freq = VPU_FREQ_200M;
1064                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1065                                         if (reg_probe_width(reg) > 3200) {
1066                                                 // raise frequency for 4k avc.
1067                                                 reg->freq = VPU_FREQ_500M;
1068                                         }
1069                                 } else {
1070                                         if (reg_check_interlace(reg)) {
1071                                                 reg->freq = VPU_FREQ_400M;
1072                                         }
1073                                 }
1074                         }
1075                         if (reg->type == VPU_PP) {
1076                                 reg->freq = VPU_FREQ_400M;
1077                         }
1078                 }
1079         }
1080         vpu_debug_leave();
1081         return reg;
1082 }
1083
1084 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1085 {
1086         struct vpu_service_info *pservice = data->pservice;
1087 #if defined(CONFIG_VCODEC_MMU)
1088         struct vcodec_mem_region *mem_region = NULL, *n;
1089 #endif
1090
1091         list_del_init(&reg->session_link);
1092         list_del_init(&reg->status_link);
1093         if (reg == pservice->reg_codec)
1094                 pservice->reg_codec = NULL;
1095         if (reg == pservice->reg_pproc)
1096                 pservice->reg_pproc = NULL;
1097
1098 #if defined(CONFIG_VCODEC_MMU)
1099         /* release memory region attach to this registers table. */
1100         if (data->mmu_dev) {
1101                 list_for_each_entry_safe(mem_region, n,
1102                         &reg->mem_region_list, reg_lnk) {
1103                         /* do not unmap iommu manually,
1104                            unmap will proccess when memory release */
1105                         /*vcodec_enter_mode(data);
1106                         ion_unmap_iommu(data->dev,
1107                                         pservice->ion_client,
1108                                         mem_region->hdl);
1109                         vcodec_exit_mode();*/
1110                         ion_free(pservice->ion_client, mem_region->hdl);
1111                         list_del_init(&mem_region->reg_lnk);
1112                         kfree(mem_region);
1113                 }
1114         }
1115 #endif
1116
1117         kfree(reg);
1118 }
1119
1120 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1121 {
1122         vpu_debug_enter();
1123         list_del_init(&reg->status_link);
1124         list_add_tail(&reg->status_link, &pservice->running);
1125
1126         list_del_init(&reg->session_link);
1127         list_add_tail(&reg->session_link, &reg->session->running);
1128         vpu_debug_leave();
1129 }
1130
1131 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1132 {
1133         int i;
1134         u32 *dst = (u32 *)&reg->reg[0];
1135         vpu_debug_enter();
1136         for (i = 0; i < count; i++)
1137                 *dst++ = *src++;
1138         vpu_debug_leave();
1139 }
1140
1141 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1142         vpu_reg *reg)
1143 {
1144         struct vpu_service_info *pservice = data->pservice;
1145         int irq_reg = -1;
1146
1147         vpu_debug_enter();
1148
1149         list_del_init(&reg->status_link);
1150         list_add_tail(&reg->status_link, &pservice->done);
1151
1152         list_del_init(&reg->session_link);
1153         list_add_tail(&reg->session_link, &reg->session->done);
1154
1155         vcodec_enter_mode(data);
1156         switch (reg->type) {
1157         case VPU_ENC : {
1158                 pservice->reg_codec = NULL;
1159                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1160                 irq_reg = ENC_INTERRUPT_REGISTER;
1161                 break;
1162         }
1163         case VPU_DEC : {
1164                 int reg_len = REG_NUM_9190_DEC;
1165                 pservice->reg_codec = NULL;
1166                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1167                 irq_reg = DEC_INTERRUPT_REGISTER;
1168                 break;
1169         }
1170         case VPU_PP : {
1171                 pservice->reg_pproc = NULL;
1172                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1173                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1174                 break;
1175         }
1176         case VPU_DEC_PP : {
1177                 pservice->reg_codec = NULL;
1178                 pservice->reg_pproc = NULL;
1179                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1180                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1181                 break;
1182         }
1183         default : {
1184                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1185                 break;
1186         }
1187         }
1188         vcodec_exit_mode(pservice);
1189
1190         if (irq_reg != -1) {
1191                 reg->reg[irq_reg] = pservice->irq_status;
1192         }
1193
1194         atomic_sub(1, &reg->session->task_running);
1195         atomic_sub(1, &pservice->total_running);
1196         wake_up(&reg->session->wait);
1197
1198         vpu_debug_leave();
1199 }
1200
1201 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1202 {
1203         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1204         if (curr == reg->freq) {
1205                 return ;
1206         }
1207         atomic_set(&pservice->freq_status, reg->freq);
1208         switch (reg->freq) {
1209         case VPU_FREQ_200M : {
1210                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1211         } break;
1212         case VPU_FREQ_266M : {
1213                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1214         } break;
1215         case VPU_FREQ_300M : {
1216                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1217         } break;
1218         case VPU_FREQ_400M : {
1219                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1220         } break;
1221         case VPU_FREQ_500M : {
1222                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1223         } break;
1224         case VPU_FREQ_600M : {
1225                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1226         } break;
1227         default : {
1228                 if (soc_is_rk2928g()) {
1229                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1230                 } else {
1231                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1232                 }
1233         } break;
1234         }
1235 }
1236
1237 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1238 {
1239         struct vpu_service_info *pservice = data->pservice;
1240         int i;
1241         u32 *src = (u32 *)&reg->reg[0];
1242         vpu_debug_enter();
1243
1244         atomic_add(1, &pservice->total_running);
1245         atomic_add(1, &reg->session->task_running);
1246         if (pservice->auto_freq)
1247                 vpu_service_set_freq(pservice, reg);
1248
1249         vcodec_enter_mode(data);
1250
1251         switch (reg->type) {
1252         case VPU_ENC : {
1253                 int enc_count = data->hw_info->enc_reg_num;
1254                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1255
1256                 pservice->reg_codec = reg;
1257
1258                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1259
1260                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1261                         dst[i] = src[i];
1262
1263                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1264                         dst[i] = src[i];
1265
1266                 VEPU_CLEAN_CACHE(dst);
1267
1268                 dsb();
1269
1270                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1271                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1272
1273 #if VPU_SERVICE_SHOW_TIME
1274                 do_gettimeofday(&enc_start);
1275 #endif
1276
1277         } break;
1278         case VPU_DEC : {
1279                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1280
1281                 pservice->reg_codec = reg;
1282
1283                 if (data->hw_info->hw_id != HEVC_ID) {
1284                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1285                                 dst[i] = src[i];
1286                         VDPU_CLEAN_CACHE(dst);
1287                 } else {
1288                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1289                                 dst[i] = src[i];
1290                         HEVC_CLEAN_CACHE(dst);
1291                 }
1292
1293                 dsb();
1294
1295                 if (data->hw_info->hw_id != HEVC_ID) {
1296                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1297                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1298                 } else {
1299                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1300                 }
1301                 dsb();
1302                 dmb();
1303 #if VPU_SERVICE_SHOW_TIME
1304                 do_gettimeofday(&dec_start);
1305 #endif
1306         } break;
1307         case VPU_PP : {
1308                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1309                 pservice->reg_pproc = reg;
1310
1311                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1312
1313                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1314                         dst[i] = src[i];
1315
1316                 dsb();
1317
1318                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1319 #if VPU_SERVICE_SHOW_TIME
1320                 do_gettimeofday(&pp_start);
1321 #endif
1322
1323         } break;
1324         case VPU_DEC_PP : {
1325                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1326                 pservice->reg_codec = reg;
1327                 pservice->reg_pproc = reg;
1328
1329                 VDPU_SOFT_RESET(dst);
1330                 VDPU_CLEAN_CACHE(dst);
1331
1332                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1333                         dst[i] = src[i];
1334
1335                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1336                 dsb();
1337
1338                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1339                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1340                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1341 #if VPU_SERVICE_SHOW_TIME
1342                 do_gettimeofday(&dec_start);
1343 #endif
1344         } break;
1345         default : {
1346                 vpu_err("error: unsupport session type %d", reg->type);
1347                 atomic_sub(1, &pservice->total_running);
1348                 atomic_sub(1, &reg->session->task_running);
1349                 break;
1350         }
1351         }
1352
1353         vcodec_exit_mode(pservice);
1354         vpu_debug_leave();
1355 }
1356
1357 static void try_set_reg(struct vpu_subdev_data *data)
1358 {
1359         struct vpu_service_info *pservice = data->pservice;
1360         vpu_debug_enter();
1361         if (!list_empty(&pservice->waiting)) {
1362                 int can_set = 0;
1363                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1364
1365                 vpu_service_power_on(pservice);
1366
1367                 switch (reg->type) {
1368                 case VPU_ENC : {
1369                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1370                                 can_set = 1;
1371                 } break;
1372                 case VPU_DEC : {
1373                         if (NULL == pservice->reg_codec)
1374                                 can_set = 1;
1375                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {
1376                                 can_set = 0;
1377                         }
1378                 } break;
1379                 case VPU_PP : {
1380                         if (NULL == pservice->reg_codec) {
1381                                 if (NULL == pservice->reg_pproc)
1382                                         can_set = 1;
1383                         } else {
1384                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1385                                         can_set = 1;
1386                                 /* can not charge frequency when vpu is working */
1387                                 if (pservice->auto_freq) {
1388                                         can_set = 0;
1389                                 }
1390                         }
1391                 } break;
1392                 case VPU_DEC_PP : {
1393                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1394                                 can_set = 1;
1395                         } break;
1396                 default : {
1397                         printk("undefined reg type %d\n", reg->type);
1398                 } break;
1399                 }
1400                 if (can_set) {
1401                         reg_from_wait_to_run(pservice, reg);
1402                         reg_copy_to_hw(data, reg);
1403                 }
1404         }
1405         vpu_debug_leave();
1406 }
1407
1408 static int return_reg(struct vpu_subdev_data *data,
1409         vpu_reg *reg, u32 __user *dst)
1410 {
1411         int ret = 0;
1412         vpu_debug_enter();
1413         switch (reg->type) {
1414         case VPU_ENC : {
1415                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1416                         ret = -EFAULT;
1417                 break;
1418         }
1419         case VPU_DEC : {
1420                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1421                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1422                         ret = -EFAULT;
1423                 break;
1424         }
1425         case VPU_PP : {
1426                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1427                         ret = -EFAULT;
1428                 break;
1429         }
1430         case VPU_DEC_PP : {
1431                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1432                         ret = -EFAULT;
1433                 break;
1434         }
1435         default : {
1436                 ret = -EFAULT;
1437                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1438                 break;
1439         }
1440         }
1441         reg_deinit(data, reg);
1442         vpu_debug_leave();
1443         return ret;
1444 }
1445
1446 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1447         unsigned long arg)
1448 {
1449         struct vpu_subdev_data *data =
1450                 container_of(filp->f_dentry->d_inode->i_cdev,
1451                         struct vpu_subdev_data, cdev);
1452         struct vpu_service_info *pservice = data->pservice;
1453         vpu_session *session = (vpu_session *)filp->private_data;
1454         vpu_debug_enter();
1455         vpu_debug(3, "cmd %x, VPU_IOC_SET_CLIENT_TYPE %x\n", cmd, VPU_IOC_SET_CLIENT_TYPE);
1456         if (NULL == session)
1457                 return -EINVAL;
1458
1459         switch (cmd) {
1460         case VPU_IOC_SET_CLIENT_TYPE : {
1461                 session->type = (VPU_CLIENT_TYPE)arg;
1462                 break;
1463         }
1464         case VPU_IOC_GET_HW_FUSE_STATUS : {
1465                 vpu_request req;
1466                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1467                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1468                         return -EFAULT;
1469                 } else {
1470                         if (VPU_ENC != session->type) {
1471                                 if (copy_to_user((void __user *)req.req,
1472                                         &pservice->dec_config,
1473                                         sizeof(VPUHwDecConfig_t))) {
1474                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1475                                                 session->type);
1476                                         return -EFAULT;
1477                                 }
1478                         } else {
1479                                 if (copy_to_user((void __user *)req.req,
1480                                         &pservice->enc_config,
1481                                         sizeof(VPUHwEncConfig_t))) {
1482                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1483                                                 session->type);
1484                                         return -EFAULT;
1485                                 }
1486                         }
1487                 }
1488
1489                 break;
1490         }
1491         case VPU_IOC_SET_REG : {
1492                 vpu_request req;
1493                 vpu_reg *reg;
1494                 if (copy_from_user(&req, (void __user *)arg,
1495                         sizeof(vpu_request))) {
1496                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1497                         return -EFAULT;
1498                 }
1499                 reg = reg_init(data, session,
1500                         (void __user *)req.req, req.size);
1501                 if (NULL == reg) {
1502                         return -EFAULT;
1503                 } else {
1504                         mutex_lock(&pservice->lock);
1505                         try_set_reg(data);
1506                         mutex_unlock(&pservice->lock);
1507                 }
1508
1509                 break;
1510         }
1511         case VPU_IOC_GET_REG : {
1512                 vpu_request req;
1513                 vpu_reg *reg;
1514                 if (copy_from_user(&req, (void __user *)arg,
1515                         sizeof(vpu_request))) {
1516                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1517                         return -EFAULT;
1518                 } else {
1519                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1520                         if (!list_empty(&session->done)) {
1521                                 if (ret < 0) {
1522                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1523                                 }
1524                                 ret = 0;
1525                         } else {
1526                                 if (unlikely(ret < 0)) {
1527                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1528                                 } else if (0 == ret) {
1529                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1530                                         ret = -ETIMEDOUT;
1531                                 }
1532                         }
1533                         if (ret < 0) {
1534                                 int task_running = atomic_read(&session->task_running);
1535                                 mutex_lock(&pservice->lock);
1536                                 vpu_service_dump(pservice);
1537                                 if (task_running) {
1538                                         atomic_set(&session->task_running, 0);
1539                                         atomic_sub(task_running, &pservice->total_running);
1540                                         printk("%d task is running but not return, reset hardware...", task_running);
1541                                         vpu_reset(pservice);
1542                                         printk("done\n");
1543                                 }
1544                                 vpu_service_session_clear(data, session);
1545                                 mutex_unlock(&pservice->lock);
1546                                 return ret;
1547                         }
1548                 }
1549                 mutex_lock(&pservice->lock);
1550                 reg = list_entry(session->done.next, vpu_reg, session_link);
1551                 return_reg(data, reg, (u32 __user *)req.req);
1552                 mutex_unlock(&pservice->lock);
1553                 break;
1554         }
1555         case VPU_IOC_PROBE_IOMMU_STATUS: {
1556                 int iommu_enable = 0;
1557
1558 #if defined(CONFIG_VCODEC_MMU)
1559                 iommu_enable = data->mmu_dev ? 1 : 0;
1560 #endif
1561
1562                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1563                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1564                         return -EFAULT;
1565                 }
1566                 break;
1567         }
1568         default : {
1569                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1570                 break;
1571         }
1572         }
1573         vpu_debug_leave();
1574         return 0;
1575 }
1576
1577 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1578 {
1579         int ret = -EINVAL, i = 0;
1580         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1581         u32 enc_id = *tmp;
1582
1583         enc_id = (enc_id >> 16) & 0xFFFF;
1584         pr_info("checking hw id %x\n", enc_id);
1585         data->hw_info = NULL;
1586         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1587                 if (enc_id == vpu_hw_set[i].hw_id) {
1588                         data->hw_info = &vpu_hw_set[i];
1589                         ret = 0;
1590                         break;
1591                 }
1592         }
1593         iounmap((void *)tmp);
1594         return ret;
1595 }
1596
1597 static int vpu_service_open(struct inode *inode, struct file *filp)
1598 {
1599         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1600         struct vpu_service_info *pservice = data->pservice;
1601         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1602
1603         vpu_debug_enter();
1604
1605         if (NULL == session) {
1606                 vpu_err("error: unable to allocate memory for vpu_session.");
1607                 return -ENOMEM;
1608         }
1609
1610         session->type   = VPU_TYPE_BUTT;
1611         session->pid    = current->pid;
1612         INIT_LIST_HEAD(&session->waiting);
1613         INIT_LIST_HEAD(&session->running);
1614         INIT_LIST_HEAD(&session->done);
1615         INIT_LIST_HEAD(&session->list_session);
1616         init_waitqueue_head(&session->wait);
1617         atomic_set(&session->task_running, 0);
1618         mutex_lock(&pservice->lock);
1619         list_add_tail(&session->list_session, &pservice->session);
1620         filp->private_data = (void *)session;
1621         mutex_unlock(&pservice->lock);
1622
1623         pr_debug("dev opened\n");
1624         vpu_debug_leave();
1625         return nonseekable_open(inode, filp);
1626 }
1627
1628 static int vpu_service_release(struct inode *inode, struct file *filp)
1629 {
1630         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1631         struct vpu_service_info *pservice = data->pservice;
1632         int task_running;
1633         vpu_session *session = (vpu_session *)filp->private_data;
1634         vpu_debug_enter();
1635         if (NULL == session)
1636                 return -EINVAL;
1637
1638         task_running = atomic_read(&session->task_running);
1639         if (task_running) {
1640                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1641                 msleep(50);
1642         }
1643         wake_up(&session->wait);
1644
1645         mutex_lock(&pservice->lock);
1646         /* remove this filp from the asynchronusly notified filp's */
1647         list_del_init(&session->list_session);
1648         vpu_service_session_clear(data, session);
1649         kfree(session);
1650         filp->private_data = NULL;
1651         mutex_unlock(&pservice->lock);
1652
1653         pr_debug("dev closed\n");
1654         vpu_debug_leave();
1655         return 0;
1656 }
1657
1658 static const struct file_operations vpu_service_fops = {
1659         .unlocked_ioctl = vpu_service_ioctl,
1660         .open           = vpu_service_open,
1661         .release        = vpu_service_release,
1662         //.fasync       = vpu_service_fasync,
1663 };
1664
1665 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1666 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1667 static irqreturn_t vepu_irq(int irq, void *dev_id);
1668 static irqreturn_t vepu_isr(int irq, void *dev_id);
1669 static void get_hw_info(struct vpu_subdev_data *data);
1670
1671 #ifdef CONFIG_VCODEC_MMU
1672 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1673 {
1674         struct device_node *dn = NULL;
1675         struct platform_device *pd = NULL;
1676         struct device *ret = NULL ;
1677
1678         dn = of_find_compatible_node(NULL,NULL,compt);
1679         if(!dn) {
1680                 printk("can't find device node %s \r\n",compt);
1681                 return NULL;
1682         }
1683
1684         pd = of_find_device_by_node(dn);
1685         if(!pd) {
1686                 printk("can't find platform device in device node %s\n",compt);
1687                 return  NULL;
1688         }
1689         ret = &pd->dev;
1690
1691         return ret;
1692
1693 }
1694 #ifdef CONFIG_IOMMU_API
1695 static inline void platform_set_sysmmu(struct device *iommu,
1696         struct device *dev)
1697 {
1698         dev->archdata.iommu = iommu;
1699 }
1700 #else
1701 static inline void platform_set_sysmmu(struct device *iommu,
1702         struct device *dev)
1703 {
1704 }
1705 #endif
1706
1707 int vcodec_sysmmu_fault_hdl(struct device *dev,
1708                                 enum rk_iommu_inttype itype,
1709                                 unsigned long pgtable_base,
1710                                 unsigned long fault_addr, unsigned int status)
1711 {
1712         struct platform_device *pdev;
1713         struct vpu_service_info *pservice;
1714
1715         vpu_debug_enter();
1716
1717         pdev = container_of(dev, struct platform_device, dev);
1718
1719         pservice = platform_get_drvdata(pdev);
1720
1721         if (pservice->reg_codec) {
1722                 struct vcodec_mem_region *mem, *n;
1723                 int i = 0;
1724                 vpu_debug(3, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1725                 list_for_each_entry_safe(mem, n,
1726                                          &pservice->reg_codec->mem_region_list,
1727                                          reg_lnk) {
1728                         vpu_debug(3, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1729                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
1730                         i++;
1731                 }
1732
1733                 pr_alert("vcodec, page fault occur, reset hw\n");
1734                 pservice->reg_codec->reg[101] = 1;
1735                 vpu_reset(pservice);
1736         }
1737
1738         return 0;
1739 }
1740 #endif
1741
1742 #if HEVC_TEST_ENABLE
1743 static int hevc_test_case0(vpu_service_info *pservice);
1744 #endif
1745 #if defined(CONFIG_ION_ROCKCHIP)
1746 extern struct ion_client *rockchip_ion_client_create(const char * name);
1747 #endif
1748
1749 static int vcodec_subdev_probe(struct platform_device *pdev,
1750         struct vpu_service_info *pservice)
1751 {
1752         int ret = 0;
1753         struct resource *res = NULL;
1754         u32 ioaddr = 0;
1755         struct device *dev = &pdev->dev;
1756         char *name = (char*)dev_name(dev);
1757         struct device_node *np = pdev->dev.of_node;
1758         struct vpu_subdev_data *data =
1759                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
1760 #if defined(CONFIG_VCODEC_MMU)
1761         u32 iommu_en = 0;
1762         char mmu_dev_dts_name[40];
1763         of_property_read_u32(np, "iommu_enabled", &iommu_en);
1764 #endif
1765         pr_info("probe device %s\n", dev_name(dev));
1766
1767         data->pservice = pservice;
1768         data->dev = dev;
1769
1770         of_property_read_string(np, "name", (const char**)&name);
1771         of_property_read_u32(np, "dev_mode", &data->mode);
1772         dev_set_name(dev, name);
1773
1774         if (pservice->reg_base == 0) {
1775                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1776                 data->regs = devm_ioremap_resource(dev, res);
1777                 if (IS_ERR(data->regs)) {
1778                         ret = PTR_ERR(data->regs);
1779                         goto err;
1780                 }
1781                 ioaddr = res->start;
1782         } else {
1783                 data->regs = pservice->reg_base;
1784                 ioaddr = pservice->ioaddr;
1785         }
1786
1787         clear_bit(MMU_ACTIVATED, &data->state);
1788         vcodec_enter_mode(data);
1789         ret = vpu_service_check_hw(data, ioaddr);
1790         if (ret < 0) {
1791                 vpu_err("error: hw info check faild\n");
1792                 goto err;
1793         }
1794
1795         data->dec_dev.iosize = data->hw_info->dec_io_size;
1796         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
1797         data->reg_size = data->dec_dev.iosize;
1798
1799         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
1800                 data->enc_dev.iosize = data->hw_info->enc_io_size;
1801                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
1802                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
1803         }
1804
1805         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1806         if (data->irq_enc > 0) {
1807                 ret = devm_request_threaded_irq(dev,
1808                         data->irq_enc, vepu_irq, vepu_isr,
1809                         IRQF_SHARED, dev_name(dev),
1810                         (void *)data);
1811                 if (ret) {
1812                         dev_err(dev,
1813                                 "error: can't request vepu irq %d\n",
1814                                 data->irq_enc);
1815                         goto err;
1816                 }
1817         }
1818         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1819         if (data->irq_dec > 0) {
1820                 ret = devm_request_threaded_irq(dev,
1821                         data->irq_dec, vdpu_irq, vdpu_isr,
1822                         IRQF_SHARED, dev_name(dev),
1823                         (void *)data);
1824                 if (ret) {
1825                         dev_err(dev,
1826                                 "error: can't request vdpu irq %d\n",
1827                                 data->irq_dec);
1828                         goto err;
1829                 }
1830         }
1831         atomic_set(&data->dec_dev.irq_count_codec, 0);
1832         atomic_set(&data->dec_dev.irq_count_pp, 0);
1833         atomic_set(&data->enc_dev.irq_count_codec, 0);
1834         atomic_set(&data->enc_dev.irq_count_pp, 0);
1835 #if defined(CONFIG_VCODEC_MMU)
1836         if (iommu_en) {
1837                 vcodec_enter_mode(data);
1838                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
1839                         sprintf(mmu_dev_dts_name,
1840                                 HEVC_IOMMU_COMPATIBLE_NAME);
1841                 else
1842                         sprintf(mmu_dev_dts_name,
1843                                 VPU_IOMMU_COMPATIBLE_NAME);
1844
1845                 data->mmu_dev =
1846                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
1847
1848                 if (data->mmu_dev)
1849                         platform_set_sysmmu(data->mmu_dev, dev);
1850
1851                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
1852         }
1853 #endif
1854         /* create device node */
1855         ret = alloc_chrdev_region(&data->dev_t, 0, 1, dev_name(dev));
1856         if (ret) {
1857                 dev_err(dev, "alloc dev_t failed\n");
1858                 goto err;
1859         }
1860
1861         cdev_init(&data->cdev, &vpu_service_fops);
1862
1863         data->cdev.owner = THIS_MODULE;
1864         data->cdev.ops = &vpu_service_fops;
1865
1866         ret = cdev_add(&data->cdev, data->dev_t, 1);
1867
1868         if (ret) {
1869                 dev_err(dev, "add dev_t failed\n");
1870                 goto err;
1871         }
1872
1873         data->cls = class_create(THIS_MODULE, dev_name(dev));
1874
1875         if (IS_ERR(data->cls)) {
1876                 ret = PTR_ERR(data->cls);
1877                 dev_err(dev, "class_create err:%d\n", ret);
1878                 goto err;
1879         }
1880
1881         data->child_dev = device_create(data->cls, dev,
1882                 data->dev_t, NULL, dev_name(dev));
1883
1884         get_hw_info(data);
1885
1886         platform_set_drvdata(pdev, data);
1887
1888         INIT_LIST_HEAD(&data->lnk_service);
1889         list_add_tail(&data->lnk_service, &pservice->subdev_list);
1890         return 0;
1891 err:
1892         if (data->irq_enc > 0)
1893                 free_irq(data->irq_enc, (void *)data);
1894         if (data->irq_dec > 0)
1895                 free_irq(data->irq_dec, (void *)data);
1896
1897         if (data->child_dev) {
1898                 device_destroy(data->cls, data->dev_t);
1899                 cdev_del(&data->cdev);
1900                 unregister_chrdev_region(data->dev_t, 1);
1901         }
1902
1903         if (data->cls)
1904                 class_destroy(data->cls);
1905         return -1;
1906 }
1907
1908 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
1909 {
1910         device_destroy(data->cls, data->dev_t);
1911         class_destroy(data->cls);
1912         cdev_del(&data->cdev);
1913         unregister_chrdev_region(data->dev_t, 1);
1914
1915         free_irq(data->irq_enc, (void *)&data);
1916         free_irq(data->irq_dec, (void *)&data);
1917 }
1918
1919 static void vcodec_read_property(struct device_node *np,
1920         struct vpu_service_info *pservice)
1921 {
1922         pservice->mode_bit = 0;
1923         pservice->mode_ctrl = 0;
1924         pservice->subcnt = 0;
1925
1926         of_property_read_u32(np, "subcnt", &pservice->subcnt);
1927
1928         if (pservice->subcnt > 1) {
1929                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
1930                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
1931         }
1932         pservice->grf_base = RK_GRF_VIRT;/*syscon_regmap_lookup_by_phandle(np, "rockchip,grf");*/
1933         if (IS_ERR(pservice->grf_base)) {
1934                 vpu_err("can't find vpu grf property\n");
1935                 return;
1936         }
1937         of_property_read_string(np, "name", (const char**)&pservice->name);
1938 }
1939
1940 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
1941 {
1942         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
1943         pservice->curr_mode = -1;
1944
1945         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
1946         INIT_LIST_HEAD(&pservice->waiting);
1947         INIT_LIST_HEAD(&pservice->running);
1948         mutex_init(&pservice->lock);
1949
1950         INIT_LIST_HEAD(&pservice->done);
1951         INIT_LIST_HEAD(&pservice->session);
1952         INIT_LIST_HEAD(&pservice->subdev_list);
1953
1954         pservice->reg_pproc     = NULL;
1955         atomic_set(&pservice->total_running, 0);
1956         pservice->enabled = false;
1957
1958         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
1959
1960         pservice->ion_client = rockchip_ion_client_create("vpu");
1961         if (IS_ERR(pservice->ion_client)) {
1962                 vpu_err("failed to create ion client for vcodec ret %ld\n",
1963                         PTR_ERR(pservice->ion_client));
1964         } else {
1965                 vpu_debug(3, "vcodec ion client create success!\n");
1966         }
1967 }
1968
1969 static int vcodec_probe(struct platform_device *pdev)
1970 {
1971         int i;
1972         int ret = 0;
1973         struct resource *res = NULL;
1974         struct device *dev = &pdev->dev;
1975         struct device_node *np = pdev->dev.of_node;
1976         struct vpu_service_info *pservice =
1977                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
1978
1979         pr_info("probe device %s\n", dev_name(dev));
1980
1981         vcodec_read_property(np, pservice);
1982         vcodec_init_drvdata(pservice);
1983
1984         if (strncmp(pservice->name, "hevc_service", 12) == 0)
1985                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
1986         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
1987                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
1988         else
1989                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
1990
1991         pservice->dev = dev;
1992
1993         if (0 > vpu_get_clk(pservice))
1994                 goto err;
1995
1996         vpu_service_power_on(pservice);
1997
1998         if (of_property_read_bool(np, "reg")) {
1999                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2000
2001                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2002                 if (IS_ERR(pservice->reg_base)) {
2003                         vpu_err("ioremap registers base failed\n");
2004                         ret = PTR_ERR(pservice->reg_base);
2005                         goto err;
2006                 }
2007                 pservice->ioaddr = res->start;
2008         } else {
2009                 pservice->reg_base = 0;
2010         }
2011
2012         if (of_property_read_bool(np, "subcnt")) {
2013                 for (i = 0; i<pservice->subcnt; i++) {
2014                         struct device_node *sub_np;
2015                         struct platform_device *sub_pdev;
2016                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2017                         sub_pdev = of_find_device_by_node(sub_np);
2018
2019                         vcodec_subdev_probe(sub_pdev, pservice);
2020                 }
2021         } else {
2022                 vcodec_subdev_probe(pdev, pservice);
2023         }
2024         platform_set_drvdata(pdev, pservice);
2025
2026 #ifdef CONFIG_DEBUG_FS
2027         pservice->debugfs_dir =
2028                 vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
2029         if (pservice->debugfs_dir == NULL)
2030                 vpu_err("create debugfs dir %s failed\n", dev_name(dev));
2031
2032         pservice->debugfs_file_regs =
2033                 debugfs_create_file("regs", 0664,
2034                                     pservice->debugfs_dir, pservice,
2035                                     &debug_vcodec_fops);
2036 #endif
2037
2038         vpu_service_power_off(pservice);
2039
2040         pr_info("init success\n");
2041
2042         return 0;
2043
2044 err:
2045         pr_info("init failed\n");
2046         vpu_service_power_off(pservice);
2047         vpu_put_clk(pservice);
2048         wake_lock_destroy(&pservice->wake_lock);
2049
2050         if (res)
2051                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2052
2053         return ret;
2054 }
2055
2056 static int vcodec_remove(struct platform_device *pdev)
2057 {
2058         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2059         struct resource *res;
2060         struct vpu_subdev_data *data, *n;
2061
2062         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2063                 vcodec_subdev_remove(data);
2064         }
2065
2066         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2067         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2068         vpu_put_clk(pservice);
2069         wake_lock_destroy(&pservice->wake_lock);
2070
2071 #ifdef CONFIG_DEBUG_FS
2072         debugfs_remove(pservice->debugfs_file_regs);
2073         debugfs_remove(pservice->debugfs_dir);
2074 #endif
2075
2076         return 0;
2077 }
2078
2079 #if defined(CONFIG_OF)
2080 static const struct of_device_id vcodec_service_dt_ids[] = {
2081         {.compatible = "vpu_service",},
2082         {.compatible = "rockchip,hevc_service",},
2083         {.compatible = "rockchip,vpu_combo",},
2084         {},
2085 };
2086 #endif
2087
2088 static struct platform_driver vcodec_driver = {
2089         .probe = vcodec_probe,
2090         .remove = vcodec_remove,
2091         .driver = {
2092                 .name = "vcodec",
2093                 .owner = THIS_MODULE,
2094 #if defined(CONFIG_OF)
2095                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2096 #endif
2097         },
2098 };
2099
2100 static void get_hw_info(struct vpu_subdev_data *data)
2101 {
2102         struct vpu_service_info *pservice = data->pservice;
2103         VPUHwDecConfig_t *dec = &pservice->dec_config;
2104         VPUHwEncConfig_t *enc = &pservice->enc_config;
2105         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2106                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2107                 u32 asicID      = data->dec_dev.hwregs[0];
2108
2109                 dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;
2110                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2111                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2112                         dec->jpegSupport = JPEG_PROGRESSIVE;
2113                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2114                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2115                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2116                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2117                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2118                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2119
2120                 dec->maxDecPicWidth = 4096;
2121
2122                 /* 2nd Config register */
2123                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2124                 if (dec->refBufSupport) {
2125                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2126                                 dec->refBufSupport |= 2;
2127                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2128                                 dec->refBufSupport |= 4;
2129                 }
2130                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2131                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2132                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2133                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2134
2135                 /* JPEG xtensions */
2136                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2137                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2138                 else
2139                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2140
2141                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2142                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2143                 else
2144                         dec->rvSupport = RV_NOT_SUPPORTED;
2145                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2146
2147                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2148                         dec->refBufSupport |= 8; /* enable HW support for offset */
2149
2150                 if (!cpu_is_rk3036()) {
2151                         configReg = data->enc_dev.hwregs[63];
2152                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2153                         enc->h264Enabled = (configReg >> 27) & 1;
2154                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2155                         enc->jpegEnabled = (configReg >> 25) & 1;
2156                         enc->vsEnabled = (configReg >> 24) & 1;
2157                         enc->rgbEnabled = (configReg >> 28) & 1;
2158                         enc->reg_size = data->reg_size;
2159                         enc->reserv[0] = enc->reserv[1] = 0;
2160                 }
2161                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2162                 if (pservice->auto_freq) {
2163                         vpu_debug(3, "vpu_service set to auto frequency mode\n");
2164                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2165                 }
2166
2167                 pservice->bug_dec_addr = cpu_is_rk30xx();
2168         } else {
2169                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2170                         dec->maxDecPicWidth = 1920;
2171                 else
2172                         dec->maxDecPicWidth = 4096;
2173                 /* disable frequency switch in hevc.*/
2174                 pservice->auto_freq = false;
2175         }
2176 }
2177
2178 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2179 {
2180         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2181         struct vpu_service_info *pservice = data->pservice;
2182         vpu_device *dev = &data->dec_dev;
2183         u32 raw_status;
2184         u32 irq_status;
2185
2186         vcodec_enter_mode(data);
2187
2188         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2189
2190         vpu_debug(3, "%s status %08x\n", __func__, raw_status);
2191
2192         if (irq_status & DEC_INTERRUPT_BIT) {
2193                 pr_debug("dec_isr dec %x\n", irq_status);
2194                 if ((irq_status & 0x40001) == 0x40001) {
2195                         do {
2196                                 irq_status =
2197                                         readl(dev->hwregs +
2198                                                 DEC_INTERRUPT_REGISTER);
2199                         } while ((irq_status & 0x40001) == 0x40001);
2200                 }
2201
2202                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2203                 atomic_add(1, &dev->irq_count_codec);
2204         }
2205
2206         if (data->hw_info->hw_id != HEVC_ID) {
2207                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2208                 if (irq_status & PP_INTERRUPT_BIT) {
2209                         pr_debug("vdpu_isr pp  %x\n", irq_status);
2210                         /* clear pp IRQ */
2211                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2212                         atomic_add(1, &dev->irq_count_pp);
2213                 }
2214         }
2215
2216         pservice->irq_status = raw_status;
2217
2218         vcodec_exit_mode(pservice);
2219
2220         return IRQ_WAKE_THREAD;
2221 }
2222
2223 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2224 {
2225         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2226         struct vpu_service_info *pservice = data->pservice;
2227         vpu_device *dev = &data->dec_dev;
2228
2229         mutex_lock(&pservice->lock);
2230         if (atomic_read(&dev->irq_count_codec)) {
2231 #if VPU_SERVICE_SHOW_TIME
2232                 do_gettimeofday(&dec_end);
2233                 vpu_debug(3, "dec task: %ld ms\n",
2234                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2235                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2236 #endif
2237                 atomic_sub(1, &dev->irq_count_codec);
2238                 if (NULL == pservice->reg_codec) {
2239                         vpu_err("error: dec isr with no task waiting\n");
2240                 } else {
2241                         reg_from_run_to_done(data, pservice->reg_codec);
2242                 }
2243         }
2244
2245         if (atomic_read(&dev->irq_count_pp)) {
2246 #if VPU_SERVICE_SHOW_TIME
2247                 do_gettimeofday(&pp_end);
2248                 printk("pp  task: %ld ms\n",
2249                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2250                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2251 #endif
2252                 atomic_sub(1, &dev->irq_count_pp);
2253                 if (NULL == pservice->reg_pproc) {
2254                         vpu_err("error: pp isr with no task waiting\n");
2255                 } else {
2256                         reg_from_run_to_done(data, pservice->reg_pproc);
2257                 }
2258         }
2259         try_set_reg(data);
2260         mutex_unlock(&pservice->lock);
2261         return IRQ_HANDLED;
2262 }
2263
2264 static irqreturn_t vepu_irq(int irq, void *dev_id)
2265 {
2266         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2267         struct vpu_service_info *pservice = data->pservice;
2268         vpu_device *dev = &data->enc_dev;
2269         u32 irq_status;
2270
2271         vcodec_enter_mode(data);
2272         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2273
2274         pr_debug("vepu_irq irq status %x\n", irq_status);
2275
2276 #if VPU_SERVICE_SHOW_TIME
2277         do_gettimeofday(&enc_end);
2278         vpu_debug(3, "enc task: %ld ms\n",
2279                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2280                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2281 #endif
2282         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2283                 /* clear enc IRQ */
2284                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2285                 atomic_add(1, &dev->irq_count_codec);
2286         }
2287
2288         pservice->irq_status = irq_status;
2289
2290         vcodec_exit_mode(pservice);
2291
2292         return IRQ_WAKE_THREAD;
2293 }
2294
2295 static irqreturn_t vepu_isr(int irq, void *dev_id)
2296 {
2297         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2298         struct vpu_service_info *pservice = data->pservice;
2299         vpu_device *dev = &data->enc_dev;
2300
2301         mutex_lock(&pservice->lock);
2302         if (atomic_read(&dev->irq_count_codec)) {
2303                 atomic_sub(1, &dev->irq_count_codec);
2304                 if (NULL == pservice->reg_codec) {
2305                         vpu_err("error: enc isr with no task waiting\n");
2306                 } else {
2307                         reg_from_run_to_done(data, pservice->reg_codec);
2308                 }
2309         }
2310         try_set_reg(data);
2311         mutex_unlock(&pservice->lock);
2312         return IRQ_HANDLED;
2313 }
2314
2315 static int __init vcodec_service_init(void)
2316 {
2317         int ret;
2318
2319         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2320                 vpu_err("Platform device register failed (%d).\n", ret);
2321                 return ret;
2322         }
2323
2324 #ifdef CONFIG_DEBUG_FS
2325         vcodec_debugfs_init();
2326 #endif
2327
2328         return ret;
2329 }
2330
2331 static void __exit vcodec_service_exit(void)
2332 {
2333 #ifdef CONFIG_DEBUG_FS
2334         vcodec_debugfs_exit();
2335 #endif
2336
2337         platform_driver_unregister(&vcodec_driver);
2338 }
2339
2340 module_init(vcodec_service_init);
2341 module_exit(vcodec_service_exit);
2342
2343 #ifdef CONFIG_DEBUG_FS
2344 #include <linux/seq_file.h>
2345
2346 static int vcodec_debugfs_init()
2347 {
2348         parent = debugfs_create_dir("vcodec", NULL);
2349         if (!parent)
2350                 return -1;
2351
2352         return 0;
2353 }
2354
2355 static void vcodec_debugfs_exit()
2356 {
2357         debugfs_remove(parent);
2358 }
2359
2360 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2361 {
2362         return debugfs_create_dir(dirname, parent);
2363 }
2364
2365 static int debug_vcodec_show(struct seq_file *s, void *unused)
2366 {
2367         struct vpu_subdev_data *data = s->private;
2368         struct vpu_service_info *pservice = data->pservice;
2369         unsigned int i, n;
2370         vpu_reg *reg, *reg_tmp;
2371         vpu_session *session, *session_tmp;
2372
2373         mutex_lock(&pservice->lock);
2374         vpu_service_power_on(pservice);
2375         if (data->hw_info->hw_id != HEVC_ID) {
2376                 seq_printf(s, "\nENC Registers:\n");
2377                 n = data->enc_dev.iosize >> 2;
2378                 for (i = 0; i < n; i++)
2379                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2380         }
2381         seq_printf(s, "\nDEC Registers:\n");
2382         n = data->dec_dev.iosize >> 2;
2383         for (i = 0; i < n; i++)
2384                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2385
2386         seq_printf(s, "\nvpu service status:\n");
2387         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2388                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2389                 /*seq_printf(s, "waiting reg set %d\n");*/
2390                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2391                         seq_printf(s, "waiting register set\n");
2392                 }
2393                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2394                         seq_printf(s, "running register set\n");
2395                 }
2396                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2397                         seq_printf(s, "done    register set\n");
2398                 }
2399         }
2400         mutex_unlock(&pservice->lock);
2401
2402         return 0;
2403 }
2404
2405 static int debug_vcodec_open(struct inode *inode, struct file *file)
2406 {
2407         return single_open(file, debug_vcodec_show, inode->i_private);
2408 }
2409
2410 #endif
2411
2412 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2413 #include "hevc_test_inc/pps_00.h"
2414 #include "hevc_test_inc/register_00.h"
2415 #include "hevc_test_inc/rps_00.h"
2416 #include "hevc_test_inc/scaling_list_00.h"
2417 #include "hevc_test_inc/stream_00.h"
2418
2419 #include "hevc_test_inc/pps_01.h"
2420 #include "hevc_test_inc/register_01.h"
2421 #include "hevc_test_inc/rps_01.h"
2422 #include "hevc_test_inc/scaling_list_01.h"
2423 #include "hevc_test_inc/stream_01.h"
2424
2425 #include "hevc_test_inc/cabac.h"
2426
2427 extern struct ion_client *rockchip_ion_client_create(const char * name);
2428
2429 static struct ion_client *ion_client = NULL;
2430 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2431 {
2432         int size = (len+15) & (~15);
2433         struct ion_handle *handle;
2434         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2435
2436         if (ion_client == NULL)
2437                 ion_client = rockchip_ion_client_create("vcodec");
2438
2439         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2440
2441         ptr = ion_map_kernel(ion_client, handle);
2442
2443         ion_phys(ion_client, handle, phy, &size);
2444
2445         memcpy(ptr, tbl, len);
2446
2447         return ptr;
2448 }
2449
2450 u8* get_align_ptr_no_copy(int len, u32 *phy)
2451 {
2452         int size = (len+15) & (~15);
2453         struct ion_handle *handle;
2454         u8 *ptr;
2455
2456         if (ion_client == NULL)
2457                 ion_client = rockchip_ion_client_create("vcodec");
2458
2459         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2460
2461         ptr = ion_map_kernel(ion_client, handle);
2462
2463         ion_phys(ion_client, handle, phy, &size);
2464
2465         return ptr;
2466 }
2467
2468 #define TEST_CNT    2
2469 static int hevc_test_case0(vpu_service_info *pservice)
2470 {
2471         vpu_session session;
2472         vpu_reg *reg;
2473         unsigned long size = 272;//sizeof(register_00); // registers array length
2474         int testidx = 0;
2475         int ret = 0;
2476         u8 *pps_tbl[TEST_CNT];
2477         u8 *register_tbl[TEST_CNT];
2478         u8 *rps_tbl[TEST_CNT];
2479         u8 *scaling_list_tbl[TEST_CNT];
2480         u8 *stream_tbl[TEST_CNT];
2481
2482         int stream_size[2];
2483         int pps_size[2];
2484         int rps_size[2];
2485         int scl_size[2];
2486         int cabac_size[2];
2487
2488         u32 phy_pps;
2489         u32 phy_rps;
2490         u32 phy_scl;
2491         u32 phy_str;
2492         u32 phy_yuv;
2493         u32 phy_ref;
2494         u32 phy_cabac;
2495
2496         volatile u8 *stream_buf;
2497         volatile u8 *pps_buf;
2498         volatile u8 *rps_buf;
2499         volatile u8 *scl_buf;
2500         volatile u8 *yuv_buf;
2501         volatile u8 *cabac_buf;
2502         volatile u8 *ref_buf;
2503
2504         u8 *pps;
2505         u8 *yuv[2];
2506         int i;
2507
2508         pps_tbl[0] = pps_00;
2509         pps_tbl[1] = pps_01;
2510
2511         register_tbl[0] = register_00;
2512         register_tbl[1] = register_01;
2513
2514         rps_tbl[0] = rps_00;
2515         rps_tbl[1] = rps_01;
2516
2517         scaling_list_tbl[0] = scaling_list_00;
2518         scaling_list_tbl[1] = scaling_list_01;
2519
2520         stream_tbl[0] = stream_00;
2521         stream_tbl[1] = stream_01;
2522
2523         stream_size[0] = sizeof(stream_00);
2524         stream_size[1] = sizeof(stream_01);
2525
2526         pps_size[0] = sizeof(pps_00);
2527         pps_size[1] = sizeof(pps_01);
2528
2529         rps_size[0] = sizeof(rps_00);
2530         rps_size[1] = sizeof(rps_01);
2531
2532         scl_size[0] = sizeof(scaling_list_00);
2533         scl_size[1] = sizeof(scaling_list_01);
2534
2535         cabac_size[0] = sizeof(Cabac_table);
2536         cabac_size[1] = sizeof(Cabac_table);
2537
2538         /* create session */
2539         session.pid = current->pid;
2540         session.type = VPU_DEC;
2541         INIT_LIST_HEAD(&session.waiting);
2542         INIT_LIST_HEAD(&session.running);
2543         INIT_LIST_HEAD(&session.done);
2544         INIT_LIST_HEAD(&session.list_session);
2545         init_waitqueue_head(&session.wait);
2546         atomic_set(&session.task_running, 0);
2547         list_add_tail(&session.list_session, &pservice->session);
2548
2549         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2550         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2551
2552         while (testidx < TEST_CNT) {
2553                 /* create registers */
2554                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2555                 if (NULL == reg) {
2556                         vpu_err("error: kmalloc fail in reg_init\n");
2557                         return -1;
2558                 }
2559
2560                 if (size > pservice->reg_size) {
2561                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2562                         size = pservice->reg_size;
2563                 }
2564                 reg->session = &session;
2565                 reg->type = session.type;
2566                 reg->size = size;
2567                 reg->freq = VPU_FREQ_DEFAULT;
2568                 reg->reg = (unsigned long *)&reg[1];
2569                 INIT_LIST_HEAD(&reg->session_link);
2570                 INIT_LIST_HEAD(&reg->status_link);
2571
2572                 /* TODO: stuff registers */
2573                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2574
2575                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2576                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2577                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2578                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2579                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2580
2581                 pps = pps_buf;
2582
2583                 /* TODO: replace reigster address */
2584                 for (i=0; i<64; i++) {
2585                         u32 scaling_offset;
2586                         u32 tmp;
2587
2588                         scaling_offset = (u32)pps[i*80+74];
2589                         scaling_offset += (u32)pps[i*80+75] << 8;
2590                         scaling_offset += (u32)pps[i*80+76] << 16;
2591                         scaling_offset += (u32)pps[i*80+77] << 24;
2592
2593                         tmp = phy_scl + scaling_offset;
2594
2595                         pps[i*80+74] = tmp & 0xff;
2596                         pps[i*80+75] = (tmp >> 8) & 0xff;
2597                         pps[i*80+76] = (tmp >> 16) & 0xff;
2598                         pps[i*80+77] = (tmp >> 24) & 0xff;
2599                 }
2600
2601                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2602                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2603
2604                 reg->reg[1] = 0x21;
2605                 reg->reg[4] = phy_str;
2606                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2607                 reg->reg[6] = phy_cabac;
2608                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2609                 reg->reg[42] = phy_pps;
2610                 reg->reg[43] = phy_rps;
2611                 for (i = 10; i <= 24; i++)
2612                         reg->reg[i] = phy_yuv;
2613
2614                 mutex_lock(pservice->lock);
2615                 list_add_tail(&reg->status_link, &pservice->waiting);
2616                 list_add_tail(&reg->session_link, &session.waiting);
2617                 mutex_unlock(pservice->lock);
2618
2619                 /* stuff hardware */
2620                 try_set_reg(data);
2621
2622                 /* wait for result */
2623                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2624                 if (!list_empty(&session.done)) {
2625                         if (ret < 0)
2626                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2627                         ret = 0;
2628                 } else {
2629                         if (unlikely(ret < 0)) {
2630                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2631                         } else if (0 == ret) {
2632                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2633                                 ret = -ETIMEDOUT;
2634                         }
2635                 }
2636                 if (ret < 0) {
2637                         int task_running = atomic_read(&session.task_running);
2638                         int n;
2639                         mutex_lock(pservice->lock);
2640                         vpu_service_dump(pservice);
2641                         if (task_running) {
2642                                 atomic_set(&session.task_running, 0);
2643                                 atomic_sub(task_running, &pservice->total_running);
2644                                 printk("%d task is running but not return, reset hardware...", task_running);
2645                                 vpu_reset(pservice);
2646                                 printk("done\n");
2647                         }
2648                         vpu_service_session_clear(pservice, &session);
2649                         mutex_unlock(pservice->lock);
2650
2651                         printk("\nDEC Registers:\n");
2652                         n = data->dec_dev.iosize >> 2;
2653                         for (i=0; i<n; i++)
2654                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2655
2656                         vpu_err("test index %d failed\n", testidx);
2657                         break;
2658                 } else {
2659                         vpu_debug(3, "test index %d success\n", testidx);
2660
2661                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2662
2663                         for (i=0; i<68; i++) {
2664                                 if (i % 4 == 0)
2665                                         printk("%02d: ", i);
2666                                 printk("%08x ", reg->reg[i]);
2667                                 if ((i+1) % 4 == 0)
2668                                         printk("\n");
2669                         }
2670
2671                         testidx++;
2672                 }
2673
2674                 reg_deinit(data, reg);
2675         }
2676
2677         return 0;
2678 }
2679
2680 #endif
2681