arch/arm/mach-rockchip/vcodec_service.c

   1
   2 /* arch/arm/mach-rk29/vpu.c
   3  *
   4  * Copyright (C) 2010 ROCKCHIP, Inc.
   5  * author: chenhengming chm@rock-chips.com
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/fs.h>
  26 #include <linux/ioport.h>
  27 #include <linux/miscdevice.h>
  28 #include <linux/mm.h>
  29 #include <linux/poll.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/sched.h>
  32 #include <linux/slab.h>
  33 #include <linux/wakelock.h>
  34 #include <linux/cdev.h>
  35 #include <linux/of.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39
  40 #include <asm/cacheflush.h>
  41 #include <linux/uaccess.h>
  42 #include <linux/rockchip/grf.h>
  43
  44 #if defined(CONFIG_ION_ROCKCHIP)
  45 #include <linux/rockchip_ion.h>
  46 #endif
  47
  48 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  49 #define CONFIG_VCODEC_MMU
  50 #endif
  51
  52 #ifdef CONFIG_VCODEC_MMU
  53 #include <linux/rockchip-iovmm.h>
  54 #include <linux/dma-buf.h>
  55 #endif
  56
  57 #ifdef CONFIG_DEBUG_FS
  58 #include <linux/debugfs.h>
  59 #endif
  60
  61 #if defined(CONFIG_ARCH_RK319X)
  62 #include <mach/grf.h>
  63 #endif
  64
  65 #include "vcodec_service.h"
  66
  67 #define HEVC_TEST_ENABLE        0
  68 #define HEVC_SIM_ENABLE         0
  69 #define VCODEC_CLOCK_ENABLE     1
  70
  71 typedef enum {
  72         VPU_DEC_ID_9190         = 0x6731,
  73         VPU_ID_8270             = 0x8270,
  74         VPU_ID_4831             = 0x4831,
  75         HEVC_ID                 = 0x6867,
  76 } VPU_HW_ID;
  77
  78 typedef enum {
  79         VPU_DEC_TYPE_9190       = 0,
  80         VPU_ENC_TYPE_8270       = 0x100,
  81         VPU_ENC_TYPE_4831       ,
  82 } VPU_HW_TYPE_E;
  83
  84 typedef enum VPU_FREQ {
  85         VPU_FREQ_200M,
  86         VPU_FREQ_266M,
  87         VPU_FREQ_300M,
  88         VPU_FREQ_400M,
  89         VPU_FREQ_500M,
  90         VPU_FREQ_600M,
  91         VPU_FREQ_DEFAULT,
  92         VPU_FREQ_BUT,
  93 } VPU_FREQ;
  94
  95 typedef struct {
  96         VPU_HW_ID               hw_id;
  97         unsigned long           hw_addr;
  98         unsigned long           enc_offset;
  99         unsigned long           enc_reg_num;
 100         unsigned long           enc_io_size;
 101         unsigned long           dec_offset;
 102         unsigned long           dec_reg_num;
 103         unsigned long           dec_io_size;
 104 } VPU_HW_INFO_E;
 105
 106 struct extra_info_elem {
 107         u32 index;
 108         u32 offset;
 109 };
 110
 111 #define EXTRA_INFO_MAGIC        0x4C4A46
 112
 113 struct extra_info_for_iommu {
 114         u32 magic;
 115         u32 cnt;
 116         struct extra_info_elem elem[20];
 117 };
 118
 119 #define VPU_SERVICE_SHOW_TIME                   0
 120
 121 #if VPU_SERVICE_SHOW_TIME
 122 static struct timeval enc_start, enc_end;
 123 static struct timeval dec_start, dec_end;
 124 static struct timeval pp_start,  pp_end;
 125 #endif
 126
 127 #define MHZ                                     (1000*1000)
 128
 129 #define REG_NUM_9190_DEC                        (60)
 130 #define REG_NUM_9190_PP                         (41)
 131 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 132
 133 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 134
 135 #define REG_NUM_ENC_8270                        (96)
 136 #define REG_SIZE_ENC_8270                       (0x200)
 137 #define REG_NUM_ENC_4831                        (164)
 138 #define REG_SIZE_ENC_4831                       (0x400)
 139
 140 #define REG_NUM_HEVC_DEC                        (68)
 141
 142 #define SIZE_REG(reg)                           ((reg)*4)
 143
 144 static VPU_HW_INFO_E vpu_hw_set[] = {
 145         [0] = {
 146                 .hw_id          = VPU_ID_8270,
 147                 .hw_addr        = 0,
 148                 .enc_offset     = 0x0,
 149                 .enc_reg_num    = REG_NUM_ENC_8270,
 150                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 151                 .dec_offset     = REG_SIZE_ENC_8270,
 152                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 153                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 154         },
 155         [1] = {
 156                 .hw_id          = VPU_ID_4831,
 157                 .hw_addr        = 0,
 158                 .enc_offset     = 0x0,
 159                 .enc_reg_num    = REG_NUM_ENC_4831,
 160                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 161                 .dec_offset     = REG_SIZE_ENC_4831,
 162                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 163                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 164         },
 165         [2] = {
 166                 .hw_id          = HEVC_ID,
 167                 .hw_addr        = 0,
 168                 .dec_offset     = 0x0,
 169                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 170                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 171         },
 172         [3] = {
 173                 .hw_id          = VPU_DEC_ID_9190,
 174                 .hw_addr        = 0,
 175                 .enc_offset     = 0x0,
 176                 .enc_reg_num    = 0,
 177                 .enc_io_size    = 0,
 178                 .dec_offset     = REG_SIZE_ENC_4831,
 179                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 180                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 181         },
 182
 183 };
 184
 185
 186 #define DEC_INTERRUPT_REGISTER                  1
 187 #define PP_INTERRUPT_REGISTER                   60
 188 #define ENC_INTERRUPT_REGISTER                  1
 189
 190 #define DEC_INTERRUPT_BIT                       0x100
 191 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 192 #define PP_INTERRUPT_BIT                        0x100
 193 #define ENC_INTERRUPT_BIT                       0x1
 194
 195 #define HEVC_DEC_INT_RAW_BIT                    0x200
 196 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 197 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 198 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 199
 200 #define VPU_REG_EN_ENC                          14
 201 #define VPU_REG_ENC_GATE                        2
 202 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 203
 204 #define VPU_REG_EN_DEC                          1
 205 #define VPU_REG_DEC_GATE                        2
 206 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 207 #define VPU_REG_EN_PP                           0
 208 #define VPU_REG_PP_GATE                         1
 209 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 210 #define VPU_REG_EN_DEC_PP                       1
 211 #define VPU_REG_DEC_PP_GATE                     61
 212 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 213
 214 #if defined(CONFIG_VCODEC_MMU)
 215 static u8 addr_tbl_vpu_h264dec[] = {
 216         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 217         25, 26, 27, 28, 29, 40, 41
 218 };
 219
 220 static u8 addr_tbl_vpu_vp8dec[] = {
 221         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 222 };
 223
 224 static u8 addr_tbl_vpu_vp6dec[] = {
 225         12, 13, 14, 18, 27, 40
 226 };
 227
 228 static u8 addr_tbl_vpu_vc1dec[] = {
 229         12, 13, 14, 15, 16, 17, 27, 41
 230 };
 231
 232 static u8 addr_tbl_vpu_jpegdec[] = {
 233         12, 40, 66, 67
 234 };
 235
 236 static u8 addr_tbl_vpu_defaultdec[] = {
 237         12, 13, 14, 15, 16, 17, 40, 41
 238 };
 239
 240 static u8 addr_tbl_vpu_enc[] = {
 241         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 242 };
 243
 244 static u8 addr_tbl_hevc_dec[] = {
 245         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 246         21, 22, 23, 24, 42, 43
 247 };
 248 #endif
 249
 250 enum VPU_DEC_FMT {
 251         VPU_DEC_FMT_H264,
 252         VPU_DEC_FMT_MPEG4,
 253         VPU_DEC_FMT_H263,
 254         VPU_DEC_FMT_JPEG,
 255         VPU_DEC_FMT_VC1,
 256         VPU_DEC_FMT_MPEG2,
 257         VPU_DEC_FMT_MPEG1,
 258         VPU_DEC_FMT_VP6,
 259         VPU_DEC_FMT_RV,
 260         VPU_DEC_FMT_VP7,
 261         VPU_DEC_FMT_VP8,
 262         VPU_DEC_FMT_AVS,
 263         VPU_DEC_FMT_SVC,
 264         VPU_DEC_FMT_VC2,
 265         VPU_DEC_FMT_MVC,
 266         VPU_DEC_FMT_THEORA,
 267         VPU_DEC_FMT_RES
 268 };
 269
 270 /**
 271  * struct for process session which connect to vpu
 272  *
 273  * @author ChenHengming (2011-5-3)
 274  */
 275 typedef struct vpu_session {
 276         VPU_CLIENT_TYPE         type;
 277         /* a linked list of data so we can access them for debugging */
 278         struct list_head        list_session;
 279         /* a linked list of register data waiting for process */
 280         struct list_head        waiting;
 281         /* a linked list of register data in processing */
 282         struct list_head        running;
 283         /* a linked list of register data processed */
 284         struct list_head        done;
 285         wait_queue_head_t       wait;
 286         pid_t                   pid;
 287         atomic_t                task_running;
 288 } vpu_session;
 289
 290 /**
 291  * struct for process register set
 292  *
 293  * @author ChenHengming (2011-5-4)
 294  */
 295 typedef struct vpu_reg {
 296         VPU_CLIENT_TYPE         type;
 297         VPU_FREQ                freq;
 298         vpu_session             *session;
 299         struct list_head        session_link;           /* link to vpu service session */
 300         struct list_head        status_link;            /* link to register set list */
 301         unsigned long           size;
 302 #if defined(CONFIG_VCODEC_MMU)
 303         struct list_head        mem_region_list;
 304 #endif
 305         unsigned long           *reg;
 306 } vpu_reg;
 307
 308 typedef struct vpu_device {
 309         atomic_t                irq_count_codec;
 310         atomic_t                irq_count_pp;
 311         unsigned long           iobaseaddr;
 312         unsigned int            iosize;
 313         volatile u32            *hwregs;
 314 } vpu_device;
 315
 316 enum vcodec_device_id {
 317         VCODEC_DEVICE_ID_VPU,
 318         VCODEC_DEVICE_ID_HEVC
 319 };
 320
 321 struct vcodec_mem_region {
 322         struct list_head srv_lnk;
 323         struct list_head reg_lnk;
 324         struct list_head session_lnk;
 325         unsigned long iova;     /* virtual address for iommu */
 326         unsigned long len;
 327         u32 reg_idx;
 328         struct ion_handle *hdl;
 329 };
 330
 331 typedef struct vpu_service_info {
 332         struct wake_lock        wake_lock;
 333         struct delayed_work     power_off_work;
 334         struct mutex            *lock;
 335         struct list_head        *waiting;               /* link to link_reg in struct vpu_reg */
 336         struct list_head        *running;               /* link to link_reg in struct vpu_reg */
 337         struct list_head        done;                   /* link to link_reg in struct vpu_reg */
 338         struct list_head        session;                /* link to list_session in struct vpu_session */
 339         atomic_t                total_running;
 340         bool                    enabled;
 341         vpu_reg                 **reg_codec;
 342         vpu_reg                 *reg_pproc;
 343         vpu_reg                 *reg_resev;
 344         VPUHwDecConfig_t        dec_config;
 345         VPUHwEncConfig_t        enc_config;
 346         VPU_HW_INFO_E           *hw_info;
 347         unsigned long           reg_size;
 348         bool                    auto_freq;
 349         bool                    bug_dec_addr;
 350         atomic_t                freq_status;
 351
 352         struct clk              *aclk_vcodec;
 353         struct clk              *hclk_vcodec;
 354         struct clk              *clk_core;
 355         struct clk              *clk_cabac;
 356         struct clk              *pd_video;
 357
 358         int                     irq_dec;
 359         int                     irq_enc;
 360
 361         vpu_device              enc_dev;
 362         vpu_device              dec_dev;
 363
 364         struct device           *dev;
 365
 366         struct cdev             cdev;
 367         dev_t                   dev_t;
 368         struct class            *cls;
 369         struct device           *child_dev;
 370
 371         struct dentry           *debugfs_dir;
 372         struct dentry           *debugfs_file_regs;
 373
 374         u32 irq_status;
 375 #if defined(CONFIG_VCODEC_MMU)
 376         struct ion_client       *ion_client;
 377         struct list_head        mem_region_list;
 378         struct device           *mmu_dev;
 379 #endif
 380
 381         enum vcodec_device_id   dev_id;
 382
 383         u32                     reserved_mode;
 384
 385         struct delayed_work     simulate_work;
 386 } vpu_service_info;
 387
 388 struct vcodec_combo {
 389         struct vpu_service_info *vpu_srv;
 390         struct vpu_service_info *hevc_srv;
 391         struct list_head waiting;
 392         struct list_head running;
 393         struct mutex run_lock;
 394         vpu_reg *reg_codec;
 395         enum vcodec_device_id current_hw_mode;
 396 };
 397
 398 typedef struct vpu_request
 399 {
 400         unsigned long *req;
 401         unsigned long size;
 402 } vpu_request;
 403
 404 /// global variable
 405 //static struct clk *pd_video;
 406 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).
 407 /* mutex for selecting operation registers of vpu or hevc */
 408 static struct mutex g_mode_mutex;
 409 static struct vcodec_combo g_combo;
 410
 411 #ifdef CONFIG_DEBUG_FS
 412 static int vcodec_debugfs_init(void);
 413 static void vcodec_debugfs_exit(void);
 414 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 415 static int debug_vcodec_open(struct inode *inode, struct file *file);
 416
 417 static const struct file_operations debug_vcodec_fops = {
 418         .open = debug_vcodec_open,
 419         .read = seq_read,
 420         .llseek = seq_lseek,
 421         .release = single_release,
 422 };
 423 #endif
 424
 425 #define VDPU_SOFT_RESET_REG     101
 426 #define VDPU_CLEAR_CACHE_REG    516
 427 #define VEPU_CLEAR_CACHE_REG    772
 428 #define HEVC_CLEAR_CACHE_REG    260
 429
 430 #define VPU_REG_ENABLE(base, reg)       do { \
 431                                                 base[reg] = 1; \
 432                                         } while (0)
 433
 434 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 435 #define VDPU_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAR_CACHE_REG)
 436 #define VEPU_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAR_CACHE_REG)
 437 #define HEVC_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAR_CACHE_REG)
 438
 439 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 440 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 441 #define VPU_SIMULATE_DELAY              msecs_to_jiffies(15)
 442
 443 #define BIT_VCODEC_SEL_RK3036           (1<<3)
 444 #define BIT_VCODEC_SEL_RK312X           (1<<15)
 445 static void vcodec_enter_mode_nolock(enum vcodec_device_id id, u32 *reserved_mode)
 446 {
 447         if (cpu_is_rk3036() || cpu_is_rk312x()) {
 448                 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
 449                 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 450                 if (reserved_mode)
 451                         *reserved_mode = readl_relaxed(addr);
 452                 if (id == VCODEC_DEVICE_ID_HEVC)
 453                         writel_relaxed(readl_relaxed(addr) | (bits) | (bits << 16), addr);
 454                 else
 455                         writel_relaxed((readl_relaxed(addr) & (~bits)) | (bits << 16), addr);
 456         }
 457 }
 458
 459 static void vcodec_exit_mode_nolock(enum vcodec_device_id id, u32 reserved_mode)
 460 {
 461         if (cpu_is_rk3036() || cpu_is_rk312x()) {
 462                 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
 463                 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 464                 writel_relaxed(reserved_mode | (bits << 16), addr);
 465         }
 466 }
 467
 468 static void vcodec_enter_mode(enum vcodec_device_id id)
 469 {
 470         if (cpu_is_rk3036() || cpu_is_rk312x())
 471                 mutex_lock(&g_mode_mutex);
 472         vcodec_enter_mode_nolock(id, NULL);
 473 }
 474
 475 static void vcodec_exit_mode(void)
 476 {
 477         if (cpu_is_rk3036() || cpu_is_rk312x())
 478                 mutex_unlock(&g_mode_mutex);
 479 }
 480
 481 static int vpu_get_clk(struct vpu_service_info *pservice)
 482 {
 483 #if VCODEC_CLOCK_ENABLE
 484         do {
 485                 pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");
 486                 if (IS_ERR(pservice->aclk_vcodec)) {
 487                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 488                         break;
 489                 }
 490
 491                 pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");
 492                 if (IS_ERR(pservice->hclk_vcodec)) {
 493                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 494                         break;
 495                 }
 496
 497                 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 498                         pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 499                         if (IS_ERR(pservice->clk_core)) {
 500                                 dev_err(pservice->dev, "failed on clk_get clk_core\n");
 501                                 break;
 502                         }
 503
 504                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 505                                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 506                                 if (IS_ERR(pservice->clk_cabac)) {
 507                                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 508                                         break;
 509                                 }
 510                         } else {
 511                                 pservice->clk_cabac = NULL;
 512                         }
 513
 514                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 515                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 516                                 if (IS_ERR(pservice->pd_video)) {
 517                                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 518                                         break;
 519                                 }
 520                         } else {
 521                                 pservice->pd_video = NULL;
 522                         }
 523                 } else {
 524                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 525                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 526                                 if (IS_ERR(pservice->pd_video)) {
 527                                         dev_err(pservice->dev, "failed on clk_get pd_video\n");
 528                                         break;
 529                                 }
 530                         } else {
 531                                 pservice->pd_video = NULL;
 532                         }
 533                 }
 534
 535                 if (cpu_is_rk312x()) {
 536                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 537                         if (IS_ERR(pservice->pd_video)) {
 538                                 dev_err(pservice->dev, "failed on clk_get pd_video\n");
 539                                 break;
 540                         }
 541                 }
 542
 543                 return 0;
 544         } while (0);
 545
 546         return -1;
 547 #else
 548         return 0;
 549 #endif
 550 }
 551
 552 static void vpu_put_clk(struct vpu_service_info *pservice)
 553 {
 554 #if VCODEC_CLOCK_ENABLE
 555         if (pservice->pd_video) {
 556                 devm_clk_put(pservice->dev, pservice->pd_video);
 557         }
 558
 559         if (pservice->aclk_vcodec) {
 560                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 561         }
 562
 563         if (pservice->hclk_vcodec) {
 564                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 565         }
 566
 567         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 568                 if (pservice->clk_core) {
 569                         devm_clk_put(pservice->dev, pservice->clk_core);
 570                 }
 571
 572                 if (pservice->clk_cabac) {
 573                         devm_clk_put(pservice->dev, pservice->clk_cabac);
 574                 }
 575         }
 576 #endif
 577 }
 578
 579 static void vpu_reset(struct vpu_service_info *pservice)
 580 {
 581 #if defined(CONFIG_ARCH_RK29)
 582         clk_disable(aclk_ddr_vepu);
 583         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 584         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 585         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 586         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 587         mdelay(10);
 588         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 589         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 590         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 591         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 592         clk_enable(aclk_ddr_vepu);
 593 #elif defined(CONFIG_ARCH_RK30)
 594         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 595         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 596         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 597         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 598         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 599         mdelay(1);
 600         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 601         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 602         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 603         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 604         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 605 #endif
 606         *pservice->reg_codec = NULL;
 607         pservice->reg_pproc = NULL;
 608         pservice->reg_resev = NULL;
 609 }
 610
 611 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);
 612 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)
 613 {
 614         vpu_reg *reg, *n;
 615         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 616                 reg_deinit(pservice, reg);
 617         }
 618         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 619                 reg_deinit(pservice, reg);
 620         }
 621         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 622                 reg_deinit(pservice, reg);
 623         }
 624 }
 625
 626 static void vpu_service_dump(struct vpu_service_info *pservice)
 627 {
 628         int running;
 629         vpu_reg *reg, *reg_tmp;
 630         vpu_session *session, *session_tmp;
 631
 632         running = atomic_read(&pservice->total_running);
 633         printk("total_running %d\n", running);
 634
 635         printk("reg_codec 0x%.8x\n", (unsigned int)(*pservice->reg_codec));
 636         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);
 637         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);
 638
 639         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
 640                 printk("session pid %d type %d:\n", session->pid, session->type);
 641                 running = atomic_read(&session->task_running);
 642                 printk("task_running %d\n", running);
 643                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
 644                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);
 645                 }
 646                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
 647                         printk("running register set 0x%.8x\n", (unsigned int)reg);
 648                 }
 649                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
 650                         printk("done    register set 0x%.8x\n", (unsigned int)reg);
 651                 }
 652         }
 653 }
 654
 655 static void vpu_service_power_off(struct vpu_service_info *pservice)
 656 {
 657         int total_running;
 658         if (!pservice->enabled)
 659                 return;
 660
 661         pservice->enabled = false;
 662         total_running = atomic_read(&pservice->total_running);
 663         if (total_running) {
 664                 pr_alert("alert: power off when %d task running!!\n", total_running);
 665                 mdelay(50);
 666                 pr_alert("alert: delay 50 ms for running task\n");
 667                 vpu_service_dump(pservice);
 668         }
 669
 670         pr_info("%s: power off...", dev_name(pservice->dev));
 671         udelay(10);
 672
 673 #if defined(CONFIG_VCODEC_MMU)
 674         if (pservice->mmu_dev && !(cpu_is_rk3036() || cpu_is_rk312x())) {
 675                 vcodec_enter_mode(pservice->dev_id);
 676                 rockchip_iovmm_deactivate(pservice->dev);
 677                 vcodec_exit_mode();
 678         }
 679 #endif
 680
 681 #if VCODEC_CLOCK_ENABLE
 682         if (pservice->pd_video)
 683                 clk_disable_unprepare(pservice->pd_video);
 684         if (pservice->hclk_vcodec)
 685                 clk_disable_unprepare(pservice->hclk_vcodec);
 686         if (pservice->aclk_vcodec)
 687                 clk_disable_unprepare(pservice->aclk_vcodec);
 688         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 689                 if (pservice->clk_core)
 690                         clk_disable_unprepare(pservice->clk_core);
 691                 if (pservice->clk_cabac)
 692                         clk_disable_unprepare(pservice->clk_cabac);
 693         }
 694 #endif
 695
 696         wake_unlock(&pservice->wake_lock);
 697         pr_info("done\n");
 698 }
 699
 700 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 701 {
 702         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 703 }
 704
 705 static void vpu_power_off_work(struct work_struct *work_s)
 706 {
 707         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 708         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 709
 710         if (mutex_trylock(pservice->lock)) {
 711                 vpu_service_power_off(pservice);
 712                 mutex_unlock(pservice->lock);
 713         } else {
 714                 /* Come back later if the device is busy... */
 715                 vpu_queue_power_off_work(pservice);
 716         }
 717 }
 718
 719 static void vpu_service_power_on(struct vpu_service_info *pservice)
 720 {
 721         static ktime_t last;
 722         ktime_t now = ktime_get();
 723         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 724                 cancel_delayed_work_sync(&pservice->power_off_work);
 725                 vpu_queue_power_off_work(pservice);
 726                 last = now;
 727         }
 728         if (pservice->enabled)
 729                 return ;
 730
 731         pservice->enabled = true;
 732         printk("%s: power on\n", dev_name(pservice->dev));
 733
 734 #if VCODEC_CLOCK_ENABLE
 735         if (pservice->aclk_vcodec)
 736                 clk_prepare_enable(pservice->aclk_vcodec);
 737
 738         if (pservice->hclk_vcodec)
 739                 clk_prepare_enable(pservice->hclk_vcodec);
 740
 741         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 742                 if (pservice->clk_core)
 743                         clk_prepare_enable(pservice->clk_core);
 744         if (pservice->clk_cabac)
 745                 clk_prepare_enable(pservice->clk_cabac);
 746         }
 747
 748         if (pservice->pd_video)
 749                 clk_prepare_enable(pservice->pd_video);
 750 #endif
 751
 752 #if defined(CONFIG_ARCH_RK319X)
 753         /// select aclk_vepu as vcodec clock source.
 754 #define BIT_VCODEC_SEL  (1<<7)
 755         writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) |
 756                 (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),
 757                 RK319X_GRF_BASE + GRF_SOC_CON1);
 758 #endif
 759 #define BIT_VCODEC_CLK_SEL      (1<<10)
 760         if (cpu_is_rk312x())
 761                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 762                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 763                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 764
 765         udelay(10);
 766         wake_lock(&pservice->wake_lock);
 767
 768 #if defined(CONFIG_VCODEC_MMU)
 769         if (pservice->mmu_dev && !(cpu_is_rk3036() || cpu_is_rk312x())) {
 770                 vcodec_enter_mode(pservice->dev_id);
 771                 rockchip_iovmm_activate(pservice->dev);
 772                 vcodec_exit_mode();
 773         }
 774 #endif
 775 }
 776
 777 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 778 {
 779         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
 780         return ((type == 8) || (type == 4));
 781 }
 782
 783 static inline bool reg_check_interlace(vpu_reg *reg)
 784 {
 785         unsigned long type = (reg->reg[3] & (1 << 23));
 786         return (type > 0);
 787 }
 788
 789 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 790 {
 791         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 792         return type;
 793 }
 794
 795 static inline int reg_probe_width(vpu_reg *reg)
 796 {
 797         int width_in_mb = reg->reg[4] >> 23;
 798         return width_in_mb * 16;
 799 }
 800
 801 #if defined(CONFIG_VCODEC_MMU)
 802 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl,
 803                                 int size, vpu_reg *reg,
 804                                 struct extra_info_for_iommu *ext_inf)
 805 {
 806         int i;
 807         int usr_fd = 0;
 808         int offset = 0;
 809
 810         if (tbl == NULL || size <= 0) {
 811                 dev_err(pservice->dev, "input arguments invalidate\n");
 812                 return -1;
 813         }
 814
 815         vpu_service_power_on(pservice);
 816
 817         for (i = 0; i < size; i++) {
 818                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 819
 820                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID &&
 821                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 822                         /* special for vpu dec num 41 regitster */
 823                         offset = reg->reg[tbl[i]] >> 10 << 4;
 824                 else
 825                         offset = reg->reg[tbl[i]] >> 10;
 826
 827                 if (usr_fd != 0) {
 828                         struct ion_handle *hdl;
 829                         int ret = 0;
 830                         struct vcodec_mem_region *mem_region;
 831
 832                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 833                         if (IS_ERR(hdl)) {
 834                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 835                                 return PTR_ERR(hdl);
 836                         }
 837
 838                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 839
 840                         if (mem_region == NULL) {
 841                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 842                                 ion_free(pservice->ion_client, hdl);
 843                                 return -1;
 844                         }
 845
 846                         mem_region->hdl = hdl;
 847                         mem_region->reg_idx = tbl[i];
 848                         vcodec_enter_mode(pservice->dev_id);
 849                         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);
 850                         vcodec_exit_mode();
 851
 852                         if (ret < 0) {
 853                                 dev_err(pservice->dev, "ion map iommu failed\n");
 854                                 kfree(mem_region);
 855                                 ion_free(pservice->ion_client, hdl);
 856                                 return ret;
 857                         }
 858                         reg->reg[tbl[i]] = mem_region->iova + offset;
 859                         INIT_LIST_HEAD(&mem_region->reg_lnk);
 860                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 861                 }
 862         }
 863
 864         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
 865                 for (i=0; i<ext_inf->cnt; i++) {
 866                         pr_info("reg[%d] + offset %d\n", ext_inf->elem[i].index, ext_inf->elem[i].offset);
 867                         reg->reg[ext_inf->elem[i].index] += ext_inf->elem[i].offset;
 868                 }
 869         }
 870
 871         return 0;
 872 }
 873
 874 static int vcodec_reg_address_translate(struct vpu_service_info *pservice,
 875                                         vpu_reg *reg,
 876                                         struct extra_info_for_iommu *ext_inf)
 877 {
 878         VPU_HW_ID hw_id;
 879         u8 *tbl;
 880         int size = 0;
 881
 882         hw_id = pservice->hw_info->hw_id;
 883
 884         if (hw_id == HEVC_ID) {
 885                 tbl = addr_tbl_hevc_dec;
 886                 size = sizeof(addr_tbl_hevc_dec);
 887         } else {
 888                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 889                         switch (reg_check_fmt(reg)) {
 890                         case VPU_DEC_FMT_H264:
 891                                 {
 892                                         tbl = addr_tbl_vpu_h264dec;
 893                                         size = sizeof(addr_tbl_vpu_h264dec);
 894                                         break;
 895                                 }
 896                         case VPU_DEC_FMT_VP8:
 897                         case VPU_DEC_FMT_VP7:
 898                                 {
 899                                         tbl = addr_tbl_vpu_vp8dec;
 900                                         size = sizeof(addr_tbl_vpu_vp8dec);
 901                                         break;
 902                                 }
 903
 904                         case VPU_DEC_FMT_VP6:
 905                                 {
 906                                         tbl = addr_tbl_vpu_vp6dec;
 907                                         size = sizeof(addr_tbl_vpu_vp6dec);
 908                                         break;
 909                                 }
 910                         case VPU_DEC_FMT_VC1:
 911                                 {
 912                                         tbl = addr_tbl_vpu_vc1dec;
 913                                         size = sizeof(addr_tbl_vpu_vc1dec);
 914                                         break;
 915                                 }
 916
 917                         case VPU_DEC_FMT_JPEG:
 918                                 {
 919                                         tbl = addr_tbl_vpu_jpegdec;
 920                                         size = sizeof(addr_tbl_vpu_jpegdec);
 921                                         break;
 922                                 }
 923                         default:
 924                                 tbl = addr_tbl_vpu_defaultdec;
 925                                 size = sizeof(addr_tbl_vpu_defaultdec);
 926                                 break;
 927                         }
 928                 } else if (reg->type == VPU_ENC) {
 929                         tbl = addr_tbl_vpu_enc;
 930                         size = sizeof(addr_tbl_vpu_enc);
 931                 }
 932         }
 933
 934         if (size != 0) {
 935                 return vcodec_bufid_to_iova(pservice, tbl, size, reg, ext_inf);
 936         } else {
 937                 return -1;
 938         }
 939 }
 940 #endif
 941
 942 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)
 943 {
 944         int extra_size = 0;
 945         struct extra_info_for_iommu extra_info;
 946         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
 947         if (NULL == reg) {
 948                 pr_err("error: kmalloc fail in reg_init\n");
 949                 return NULL;
 950         }
 951
 952         if (size > pservice->reg_size) {
 953                 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
 954                 size = pservice->reg_size;*/
 955                 extra_size = size - pservice->reg_size;
 956                 size = pservice->reg_size;
 957         }
 958         reg->session = session;
 959         reg->type = session->type;
 960         reg->size = size;
 961         reg->freq = VPU_FREQ_DEFAULT;
 962         reg->reg = (unsigned long *)&reg[1];
 963         INIT_LIST_HEAD(&reg->session_link);
 964         INIT_LIST_HEAD(&reg->status_link);
 965
 966 #if defined(CONFIG_VCODEC_MMU)
 967         if (pservice->mmu_dev)
 968                 INIT_LIST_HEAD(&reg->mem_region_list);
 969 #endif
 970
 971         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
 972                 pr_err("error: copy_from_user failed in reg_init\n");
 973                 kfree(reg);
 974                 return NULL;
 975         }
 976
 977         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
 978                 pr_err("error: copy_from_user failed in reg_init\n");
 979                 kfree(reg);
 980                 return NULL;
 981         }
 982
 983 #if defined(CONFIG_VCODEC_MMU)
 984         if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg, &extra_info)) {
 985                 pr_err("error: translate reg address failed\n");
 986                 kfree(reg);
 987                 return NULL;
 988         }
 989 #endif
 990
 991         mutex_lock(pservice->lock);
 992         list_add_tail(&reg->status_link, pservice->waiting);
 993         list_add_tail(&reg->session_link, &session->waiting);
 994         mutex_unlock(pservice->lock);
 995
 996         if (pservice->auto_freq) {
 997                 if (!soc_is_rk2928g()) {
 998                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 999                                 if (reg_check_rmvb_wmv(reg)) {
1000                                         reg->freq = VPU_FREQ_200M;
1001                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1002                                         if (reg_probe_width(reg) > 3200) {
1003                                                 // raise frequency for 4k avc.
1004                                                 reg->freq = VPU_FREQ_500M;
1005                                         }
1006                                 } else {
1007                                         if (reg_check_interlace(reg)) {
1008                                                 reg->freq = VPU_FREQ_400M;
1009                                         }
1010                                 }
1011                         }
1012                         if (reg->type == VPU_PP) {
1013                                 reg->freq = VPU_FREQ_400M;
1014                         }
1015                 }
1016         }
1017
1018         /*reg->reg[2] &= (~0x800000L);*/
1019
1020         return reg;
1021 }
1022
1023 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)
1024 {
1025 #if defined(CONFIG_VCODEC_MMU)
1026         struct vcodec_mem_region *mem_region = NULL, *n;
1027 #endif
1028
1029         list_del_init(&reg->session_link);
1030         list_del_init(&reg->status_link);
1031         if (reg == (*pservice->reg_codec))
1032                 *pservice->reg_codec = NULL;
1033         if (reg == pservice->reg_pproc)
1034                 pservice->reg_pproc = NULL;
1035
1036 #if defined(CONFIG_VCODEC_MMU)
1037         // release memory region attach to this registers table.
1038         if (pservice->mmu_dev) {
1039                 list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {
1040                         /* do not unmap iommu manually,
1041                            unmap will proccess when memory release */
1042                         /*vcodec_enter_mode(pservice->dev_id);
1043                         ion_unmap_iommu(pservice->dev,
1044                                         pservice->ion_client,
1045                                         mem_region->hdl);
1046                         vcodec_exit_mode();*/
1047                         ion_free(pservice->ion_client, mem_region->hdl);
1048                         list_del_init(&mem_region->reg_lnk);
1049                         kfree(mem_region);
1050                 }
1051         }
1052 #endif
1053
1054         kfree(reg);
1055 }
1056
1057 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1058 {
1059         list_del_init(&reg->status_link);
1060         list_add_tail(&reg->status_link, pservice->running);
1061
1062         list_del_init(&reg->session_link);
1063         list_add_tail(&reg->session_link, &reg->session->running);
1064 }
1065
1066 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1067 {
1068         int i;
1069         u32 *dst = (u32 *)&reg->reg[0];
1070
1071         for (i = 0; i < count; i++)
1072                 *dst++ = *src++;
1073 }
1074
1075 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)
1076 {
1077         int irq_reg = -1;
1078         list_del_init(&reg->status_link);
1079         list_add_tail(&reg->status_link, &pservice->done);
1080
1081         list_del_init(&reg->session_link);
1082         list_add_tail(&reg->session_link, &reg->session->done);
1083
1084         vcodec_enter_mode(pservice->dev_id);
1085         switch (reg->type) {
1086         case VPU_ENC : {
1087                 *pservice->reg_codec = NULL;
1088                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);
1089                 irq_reg = ENC_INTERRUPT_REGISTER;
1090                 break;
1091         }
1092         case VPU_DEC : {
1093                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1094                 *pservice->reg_codec = NULL;
1095                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);
1096                 irq_reg = DEC_INTERRUPT_REGISTER;
1097                 break;
1098         }
1099         case VPU_PP : {
1100                 pservice->reg_pproc = NULL;
1101                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1102                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1103                 break;
1104         }
1105         case VPU_DEC_PP : {
1106                 *pservice->reg_codec = NULL;
1107                 pservice->reg_pproc = NULL;
1108                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1109                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1110                 break;
1111         }
1112         default : {
1113                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
1114                 break;
1115         }
1116         }
1117         if (cpu_is_rk3036() || cpu_is_rk312x())
1118                 rockchip_iovmm_deactivate(pservice->dev);
1119         vcodec_exit_mode();
1120
1121         if (irq_reg != -1) {
1122                 reg->reg[irq_reg] = pservice->irq_status;
1123         }
1124
1125         atomic_sub(1, &reg->session->task_running);
1126         atomic_sub(1, &pservice->total_running);
1127         wake_up(&reg->session->wait);
1128 }
1129
1130 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1131 {
1132         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1133         if (curr == reg->freq) {
1134                 return ;
1135         }
1136         atomic_set(&pservice->freq_status, reg->freq);
1137         switch (reg->freq) {
1138         case VPU_FREQ_200M : {
1139                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1140                 //printk("default: 200M\n");
1141         } break;
1142         case VPU_FREQ_266M : {
1143                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1144                 //printk("default: 266M\n");
1145         } break;
1146         case VPU_FREQ_300M : {
1147                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1148                 //printk("default: 300M\n");
1149         } break;
1150         case VPU_FREQ_400M : {
1151                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1152                 //printk("default: 400M\n");
1153         } break;
1154         case VPU_FREQ_500M : {
1155                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1156         } break;
1157         case VPU_FREQ_600M : {
1158                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1159         } break;
1160         default : {
1161                 if (soc_is_rk2928g()) {
1162                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1163                 } else {
1164                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1165                 }
1166                 //printk("default: 300M\n");
1167         } break;
1168         }
1169 }
1170
1171 #if HEVC_SIM_ENABLE
1172 static void simulate_start(struct vpu_service_info *pservice);
1173 #endif
1174 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)
1175 {
1176         int i;
1177         u32 *src = (u32 *)&reg->reg[0];
1178         atomic_add(1, &pservice->total_running);
1179         atomic_add(1, &reg->session->task_running);
1180         if (pservice->auto_freq) {
1181                 vpu_service_set_freq(pservice, reg);
1182         }
1183
1184         vcodec_enter_mode(pservice->dev_id);
1185
1186         if (cpu_is_rk3036() || cpu_is_rk312x())
1187                 rockchip_iovmm_activate(pservice->dev);
1188
1189         switch (reg->type) {
1190         case VPU_ENC : {
1191                 int enc_count = pservice->hw_info->enc_reg_num;
1192                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;
1193
1194                 *pservice->reg_codec = reg;
1195
1196                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1197
1198                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1199                         dst[i] = src[i];
1200
1201                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1202                         dst[i] = src[i];
1203
1204                 VEPU_CLEAR_CACHE(dst);
1205
1206                 dsb();
1207
1208                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1209                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1210
1211 #if VPU_SERVICE_SHOW_TIME
1212                 do_gettimeofday(&enc_start);
1213 #endif
1214
1215         } break;
1216         case VPU_DEC : {
1217                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1218
1219                 *pservice->reg_codec = reg;
1220
1221                 if (pservice->hw_info->hw_id != HEVC_ID) {
1222                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1223                                 dst[i] = src[i];
1224                         VDPU_CLEAR_CACHE(dst);
1225                 } else {
1226                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1227                                 dst[i] = src[i];
1228                         HEVC_CLEAR_CACHE(dst);
1229                 }
1230
1231                 dsb();
1232
1233                 if (pservice->hw_info->hw_id != HEVC_ID) {
1234                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1235                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];
1236                 } else {
1237                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1238                 }
1239
1240                 dsb();
1241                 dmb();
1242
1243 #if VPU_SERVICE_SHOW_TIME
1244                 do_gettimeofday(&dec_start);
1245 #endif
1246
1247         } break;
1248         case VPU_PP : {
1249                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1250                 pservice->reg_pproc = reg;
1251
1252                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1253
1254                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1255                         dst[i] = src[i];
1256
1257                 dsb();
1258
1259                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1260
1261 #if VPU_SERVICE_SHOW_TIME
1262                 do_gettimeofday(&pp_start);
1263 #endif
1264
1265         } break;
1266         case VPU_DEC_PP : {
1267                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1268                 *pservice->reg_codec = reg;
1269                 pservice->reg_pproc = reg;
1270
1271                 VDPU_SOFT_RESET(dst);
1272                 VDPU_CLEAR_CACHE(dst);
1273
1274                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1275                         dst[i] = src[i];
1276
1277                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1278                 dsb();
1279
1280                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1281                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1282                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1283
1284 #if VPU_SERVICE_SHOW_TIME
1285                 do_gettimeofday(&dec_start);
1286 #endif
1287
1288         } break;
1289         default : {
1290                 pr_err("error: unsupport session type %d", reg->type);
1291                 atomic_sub(1, &pservice->total_running);
1292                 atomic_sub(1, &reg->session->task_running);
1293                 break;
1294         }
1295         }
1296
1297         vcodec_exit_mode();
1298
1299 #if HEVC_SIM_ENABLE
1300         if (pservice->hw_info->hw_id == HEVC_ID) {
1301                 simulate_start(pservice);
1302         }
1303 #endif
1304 }
1305
1306 static void try_set_reg(struct vpu_service_info *pservice)
1307 {
1308         // first get reg from reg list
1309         if (!list_empty(pservice->waiting)) {
1310                 int can_set = 0;
1311                 vpu_reg *reg = list_entry(pservice->waiting->next, vpu_reg, status_link);
1312
1313                 vpu_service_power_on(pservice);
1314
1315                 switch (reg->type) {
1316                 case VPU_ENC : {
1317                         if ((NULL == *pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1318                                 can_set = 1;
1319                 } break;
1320                 case VPU_DEC : {
1321                         if (NULL == *pservice->reg_codec)
1322                                 can_set = 1;
1323                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {
1324                                 can_set = 0;
1325                         }
1326                 } break;
1327                 case VPU_PP : {
1328                         if (NULL == *pservice->reg_codec) {
1329                                 if (NULL == pservice->reg_pproc)
1330                                         can_set = 1;
1331                         } else {
1332                                 if ((VPU_DEC == (*pservice->reg_codec)->type) && (NULL == pservice->reg_pproc))
1333                                         can_set = 1;
1334                                 // can not charge frequency when vpu is working
1335                                 if (pservice->auto_freq) {
1336                                         can_set = 0;
1337                                 }
1338                         }
1339                 } break;
1340                 case VPU_DEC_PP : {
1341                         if ((NULL == *pservice->reg_codec) && (NULL == pservice->reg_pproc))
1342                                 can_set = 1;
1343                         } break;
1344                 default : {
1345                         printk("undefined reg type %d\n", reg->type);
1346                 } break;
1347                 }
1348                 if (can_set) {
1349                         reg_from_wait_to_run(pservice, reg);
1350                         reg_copy_to_hw(pservice, reg);
1351                 }
1352         }
1353 }
1354
1355 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)
1356 {
1357         int ret = 0;
1358         switch (reg->type) {
1359         case VPU_ENC : {
1360                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))
1361                         ret = -EFAULT;
1362                 break;
1363         }
1364         case VPU_DEC : {
1365                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1366                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1367                         ret = -EFAULT;
1368                 break;
1369         }
1370         case VPU_PP : {
1371                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1372                         ret = -EFAULT;
1373                 break;
1374         }
1375         case VPU_DEC_PP : {
1376                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1377                         ret = -EFAULT;
1378                 break;
1379         }
1380         default : {
1381                 ret = -EFAULT;
1382                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);
1383                 break;
1384         }
1385         }
1386         reg_deinit(pservice, reg);
1387         return ret;
1388 }
1389
1390 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1391 {
1392     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);
1393         vpu_session *session = (vpu_session *)filp->private_data;
1394         if (NULL == session) {
1395                 return -EINVAL;
1396         }
1397
1398         switch (cmd) {
1399         case VPU_IOC_SET_CLIENT_TYPE : {
1400                 session->type = (VPU_CLIENT_TYPE)arg;
1401                 break;
1402         }
1403         case VPU_IOC_GET_HW_FUSE_STATUS : {
1404                 vpu_request req;
1405                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1406                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1407                         return -EFAULT;
1408                 } else {
1409                         if (VPU_ENC != session->type) {
1410                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {
1411                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1412                                         return -EFAULT;
1413                                 }
1414                         } else {
1415                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {
1416                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1417                                         return -EFAULT;
1418                                 }
1419                         }
1420                 }
1421
1422                 break;
1423         }
1424         case VPU_IOC_SET_REG : {
1425                 vpu_request req;
1426                 vpu_reg *reg;
1427                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1428                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1429                         return -EFAULT;
1430                 }
1431                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);
1432                 if (NULL == reg) {
1433                         return -EFAULT;
1434                 } else {
1435                         mutex_lock(pservice->lock);
1436                         try_set_reg(pservice);
1437                         mutex_unlock(pservice->lock);
1438                 }
1439
1440                 break;
1441         }
1442         case VPU_IOC_GET_REG : {
1443                 vpu_request req;
1444                 vpu_reg *reg;
1445                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1446                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1447                         return -EFAULT;
1448                 } else {
1449                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1450                         if (!list_empty(&session->done)) {
1451                                 if (ret < 0) {
1452                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1453                                 }
1454                                 ret = 0;
1455                         } else {
1456                                 if (unlikely(ret < 0)) {
1457                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
1458                                 } else if (0 == ret) {
1459                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1460                                         ret = -ETIMEDOUT;
1461                                 }
1462                         }
1463                         if (ret < 0) {
1464                                 int task_running = atomic_read(&session->task_running);
1465                                 mutex_lock(pservice->lock);
1466                                 vpu_service_dump(pservice);
1467                                 if (task_running) {
1468                                         atomic_set(&session->task_running, 0);
1469                                         atomic_sub(task_running, &pservice->total_running);
1470                                         printk("%d task is running but not return, reset hardware...", task_running);
1471                                         vpu_reset(pservice);
1472                                         printk("done\n");
1473                                 }
1474                                 vpu_service_session_clear(pservice, session);
1475                                 mutex_unlock(pservice->lock);
1476                                 return ret;
1477                         }
1478                 }
1479                 mutex_lock(pservice->lock);
1480                 reg = list_entry(session->done.next, vpu_reg, session_link);
1481                 return_reg(pservice, reg, (u32 __user *)req.req);
1482                 mutex_unlock(pservice->lock);
1483                 break;
1484         }
1485         case VPU_IOC_PROBE_IOMMU_STATUS: {
1486                 int iommu_enable = 0;
1487
1488 #if defined(CONFIG_VCODEC_MMU)
1489                 iommu_enable = pservice->mmu_dev ? 1 : 0;
1490 #endif
1491
1492                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1493                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1494                         return -EFAULT;
1495                 }
1496                 break;
1497         }
1498         default : {
1499                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1500                 break;
1501         }
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
1508 {
1509         int ret = -EINVAL, i = 0;
1510         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1511         u32 enc_id = *tmp;
1512
1513 #if HEVC_SIM_ENABLE
1514         /// temporary, hevc driver test.
1515         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {
1516                 p->hw_info = &vpu_hw_set[2];
1517                 return 0;
1518         }
1519 #endif
1520         enc_id = (enc_id >> 16) & 0xFFFF;
1521         pr_info("checking hw id %x\n", enc_id);
1522         p->hw_info = NULL;
1523         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1524                 if (enc_id == vpu_hw_set[i].hw_id) {
1525                         p->hw_info = &vpu_hw_set[i];
1526                         ret = 0;
1527                         break;
1528                 }
1529         }
1530         iounmap((void *)tmp);
1531         return ret;
1532 }
1533
1534 static int vpu_service_open(struct inode *inode, struct file *filp)
1535 {
1536         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1537         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1538         if (NULL == session) {
1539                 pr_err("error: unable to allocate memory for vpu_session.");
1540                 return -ENOMEM;
1541         }
1542
1543         session->type   = VPU_TYPE_BUTT;
1544         session->pid    = current->pid;
1545         INIT_LIST_HEAD(&session->waiting);
1546         INIT_LIST_HEAD(&session->running);
1547         INIT_LIST_HEAD(&session->done);
1548         INIT_LIST_HEAD(&session->list_session);
1549         init_waitqueue_head(&session->wait);
1550         atomic_set(&session->task_running, 0);
1551         mutex_lock(pservice->lock);
1552         list_add_tail(&session->list_session, &pservice->session);
1553         filp->private_data = (void *)session;
1554         mutex_unlock(pservice->lock);
1555
1556         pr_debug("dev opened\n");
1557         return nonseekable_open(inode, filp);
1558 }
1559
1560 static int vpu_service_release(struct inode *inode, struct file *filp)
1561 {
1562         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1563         int task_running;
1564         vpu_session *session = (vpu_session *)filp->private_data;
1565         if (NULL == session)
1566                 return -EINVAL;
1567
1568         task_running = atomic_read(&session->task_running);
1569         if (task_running) {
1570                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1571                 msleep(50);
1572         }
1573         wake_up(&session->wait);
1574
1575         mutex_lock(pservice->lock);
1576         /* remove this filp from the asynchronusly notified filp's */
1577         list_del_init(&session->list_session);
1578         vpu_service_session_clear(pservice, session);
1579         kfree(session);
1580         filp->private_data = NULL;
1581         mutex_unlock(pservice->lock);
1582
1583         pr_debug("dev closed\n");
1584         return 0;
1585 }
1586
1587 static const struct file_operations vpu_service_fops = {
1588         .unlocked_ioctl = vpu_service_ioctl,
1589         .open           = vpu_service_open,
1590         .release        = vpu_service_release,
1591         //.fasync       = vpu_service_fasync,
1592 };
1593
1594 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1595 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1596 static irqreturn_t vepu_irq(int irq, void *dev_id);
1597 static irqreturn_t vepu_isr(int irq, void *dev_id);
1598 static void get_hw_info(struct vpu_service_info *pservice);
1599
1600 #if HEVC_SIM_ENABLE
1601 static void simulate_work(struct work_struct *work_s)
1602 {
1603         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
1604         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);
1605         vpu_device *dev = &pservice->dec_dev;
1606
1607         if (!list_empty(&pservice->running)) {
1608                 atomic_add(1, &dev->irq_count_codec);
1609                 vdpu_isr(0, (void*)pservice);
1610         } else {
1611                 //simulate_start(pservice);
1612                 pr_err("empty running queue\n");
1613         }
1614 }
1615
1616 static void simulate_init(struct vpu_service_info *pservice)
1617 {
1618         INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);
1619 }
1620
1621 static void simulate_start(struct vpu_service_info *pservice)
1622 {
1623         cancel_delayed_work_sync(&pservice->power_off_work);
1624         queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);
1625 }
1626 #endif
1627
1628 #ifdef CONFIG_VCODEC_MMU
1629 static struct device *rockchip_get_sysmmu_device_by_compatible(const char *compt)
1630 {
1631         struct device_node *dn = NULL;
1632         struct platform_device *pd = NULL;
1633         struct device *ret = NULL ;
1634
1635         dn = of_find_compatible_node(NULL,NULL,compt);
1636         if(!dn) {
1637                 printk("can't find device node %s \r\n",compt);
1638                 return NULL;
1639         }
1640
1641         pd = of_find_device_by_node(dn);
1642         if(!pd) {
1643                 printk("can't find platform device in device node %s\n",compt);
1644                 return  NULL;
1645         }
1646         ret = &pd->dev;
1647
1648         return ret;
1649
1650 }
1651 #ifdef CONFIG_IOMMU_API
1652 static inline void platform_set_sysmmu(struct device *iommu,
1653         struct device *dev)
1654 {
1655         dev->archdata.iommu = iommu;
1656 }
1657 #else
1658 static inline void platform_set_sysmmu(struct device *iommu,
1659         struct device *dev)
1660 {
1661 }
1662 #endif
1663
1664 int vcodec_sysmmu_fault_handler(struct device *dev,
1665                                 enum rk_iommu_inttype itype,
1666                                 unsigned long pgtable_base,
1667                                 unsigned long fault_addr, unsigned int status)
1668 {
1669         struct platform_device *pdev;
1670         struct vpu_service_info *pservice;
1671
1672         pr_info("%s in\n", __func__);
1673
1674         pdev = container_of(dev, struct platform_device, dev);
1675
1676         pservice = platform_get_drvdata(pdev);
1677
1678         if (pservice->reg_codec) {
1679                 struct vcodec_mem_region *mem, *n;
1680                 int i = 0;
1681                 pr_info("vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1682                 list_for_each_entry_safe(mem, n,
1683                                          &(*pservice->reg_codec)->mem_region_list,
1684                                          reg_lnk) {
1685                         pr_info("vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1686                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
1687                         i++;
1688                 }
1689
1690                 pr_alert("vcodec, page fault occur, reset hw\n");
1691                 (*pservice->reg_codec)->reg[101] = 1;
1692                 vpu_reset(pservice);
1693         }
1694
1695         return 0;
1696 }
1697 #endif
1698
1699 #if HEVC_TEST_ENABLE
1700 static int hevc_test_case0(vpu_service_info *pservice);
1701 #endif
1702 #if defined(CONFIG_ION_ROCKCHIP)
1703 extern struct ion_client *rockchip_ion_client_create(const char * name);
1704 #endif
1705 static int vcodec_probe(struct platform_device *pdev)
1706 {
1707         int ret = 0;
1708         struct resource *res = NULL;
1709         struct device *dev = &pdev->dev;
1710         void __iomem *regs = NULL;
1711         struct device_node *np = pdev->dev.of_node;
1712         struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
1713         char *prop = (char*)dev_name(dev);
1714         u32 config;
1715 #if defined(CONFIG_VCODEC_MMU)
1716         u32 iommu_en = 0;
1717         char mmu_dev_dts_name[40];
1718         of_property_read_u32(np, "iommu_enabled", &iommu_en);
1719 #endif
1720
1721         pr_info("probe device %s\n", dev_name(dev));
1722
1723         of_property_read_string(np, "name", (const char**)&prop);
1724         dev_set_name(dev, prop);
1725
1726         if (strcmp(dev_name(dev), "hevc_service") == 0) {
1727                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
1728                 g_combo.hevc_srv = pservice;
1729         } else if (strcmp(dev_name(dev), "vpu_service") == 0) {
1730                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
1731                 g_combo.vpu_srv = pservice;
1732         } else {
1733                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));
1734                 return -1;
1735         }
1736
1737         mutex_init(&g_mode_mutex);
1738         vcodec_enter_mode_nolock(pservice->dev_id, &config);
1739
1740         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
1741         if (cpu_is_rk3036() || cpu_is_rk312x()) {
1742                 pservice->waiting = &g_combo.waiting;
1743                 pservice->running = &g_combo.running;
1744                 pservice->lock = &g_combo.run_lock;
1745                 pservice->reg_codec = &g_combo.reg_codec;
1746         } else {
1747                 pservice->waiting = kzalloc(sizeof(struct list_head), GFP_KERNEL);
1748                 pservice->running = kzalloc(sizeof(struct list_head), GFP_KERNEL);
1749                 pservice->lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
1750                 pservice->reg_codec = kzalloc(sizeof(vpu_reg*), GFP_KERNEL);
1751                 INIT_LIST_HEAD(pservice->waiting);
1752                 INIT_LIST_HEAD(pservice->running);
1753                 mutex_init(pservice->lock);
1754         }
1755         INIT_LIST_HEAD(&pservice->done);
1756         INIT_LIST_HEAD(&pservice->session);
1757
1758         pservice->reg_pproc     = NULL;
1759         atomic_set(&pservice->total_running, 0);
1760         pservice->enabled = false;
1761 #if defined(CONFIG_VCODEC_MMU)
1762         pservice->mmu_dev = NULL;
1763 #endif
1764         pservice->dev = dev;
1765
1766         if (0 > vpu_get_clk(pservice))
1767                 goto err;
1768
1769         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
1770
1771         vpu_service_power_on(pservice);
1772
1773         mdelay(1);
1774
1775         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1776
1777         res->flags &= ~IORESOURCE_CACHEABLE;
1778
1779         regs = devm_ioremap_resource(pservice->dev, res);
1780         if (IS_ERR(regs)) {
1781                 ret = PTR_ERR(regs);
1782                 goto err;
1783         }
1784
1785         {
1786                 u32 offset = res->start;
1787                 if (cpu_is_rk3036()) {
1788                         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)
1789                                 offset += 0x400;
1790                 }
1791                 ret = vpu_service_check_hw(pservice, offset);
1792                 if (ret < 0) {
1793                         pr_err("error: hw info check faild\n");
1794                         goto err;
1795                 }
1796         }
1797
1798         /// define regs address.
1799         pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;
1800         pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;
1801
1802         pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);
1803
1804         pservice->reg_size   = pservice->dec_dev.iosize;
1805
1806         if (pservice->hw_info->hw_id != HEVC_ID && !cpu_is_rk3036()) {
1807                 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;
1808                 pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;
1809
1810                 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;
1811
1812                 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);
1813
1814                 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1815                 if (pservice->irq_enc < 0) {
1816                         dev_err(pservice->dev, "cannot find IRQ encoder\n");
1817                         ret = -ENXIO;
1818                         goto err;
1819                 }
1820
1821                 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, IRQF_DISABLED, dev_name(pservice->dev), (void *)pservice);
1822                 if (ret) {
1823                         dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);
1824                         goto err;
1825                 }
1826         }
1827
1828         pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1829         if (pservice->irq_dec < 0) {
1830                 dev_err(pservice->dev, "cannot find IRQ decoder\n");
1831                 ret = -ENXIO;
1832                 goto err;
1833         }
1834
1835         /* get the IRQ line */
1836         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);
1837         if (ret) {
1838                 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);
1839                 goto err;
1840         }
1841
1842         atomic_set(&pservice->dec_dev.irq_count_codec, 0);
1843         atomic_set(&pservice->dec_dev.irq_count_pp, 0);
1844         atomic_set(&pservice->enc_dev.irq_count_codec, 0);
1845         atomic_set(&pservice->enc_dev.irq_count_pp, 0);
1846
1847         /// create device
1848         ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));
1849         if (ret) {
1850                 dev_err(dev, "alloc dev_t failed\n");
1851                 goto err;
1852         }
1853
1854         cdev_init(&pservice->cdev, &vpu_service_fops);
1855
1856         pservice->cdev.owner = THIS_MODULE;
1857         pservice->cdev.ops = &vpu_service_fops;
1858
1859         ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);
1860
1861         if (ret) {
1862                 dev_err(dev, "add dev_t failed\n");
1863                 goto err;
1864         }
1865
1866         pservice->cls = class_create(THIS_MODULE, dev_name(dev));
1867
1868         if (IS_ERR(pservice->cls)) {
1869                 ret = PTR_ERR(pservice->cls);
1870                 dev_err(dev, "class_create err:%d\n", ret);
1871                 goto err;
1872         }
1873
1874         pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));
1875
1876         platform_set_drvdata(pdev, pservice);
1877
1878         get_hw_info(pservice);
1879
1880
1881 #ifdef CONFIG_DEBUG_FS
1882         pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
1883         if (pservice->debugfs_dir == NULL)
1884                 pr_err("create debugfs dir %s failed\n", dev_name(dev));
1885
1886         pservice->debugfs_file_regs =
1887                 debugfs_create_file("regs", 0664,
1888                                     pservice->debugfs_dir, pservice,
1889                                     &debug_vcodec_fops);
1890 #endif
1891
1892 #if defined(CONFIG_VCODEC_MMU)
1893         if (iommu_en) {
1894                 pservice->ion_client = rockchip_ion_client_create("vpu");
1895                 if (IS_ERR(pservice->ion_client)) {
1896                         dev_err(&pdev->dev, "failed to create ion client for vcodec");
1897                         return PTR_ERR(pservice->ion_client);
1898                 } else {
1899                         dev_info(&pdev->dev, "vcodec ion client create success!\n");
1900                 }
1901
1902                 if (pservice->hw_info->hw_id == HEVC_ID)
1903                         sprintf(mmu_dev_dts_name, HEVC_IOMMU_COMPATIBLE_NAME);
1904                 else
1905                         sprintf(mmu_dev_dts_name, VPU_IOMMU_COMPATIBLE_NAME);
1906
1907                 pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);
1908
1909                 if (pservice->mmu_dev) {
1910                         platform_set_sysmmu(pservice->mmu_dev, pservice->dev);
1911                         /*rockchip_iovmm_activate(pservice->dev);*/
1912                 }
1913
1914                 rockchip_iovmm_set_fault_handler(pservice->dev, vcodec_sysmmu_fault_handler);
1915         }
1916 #endif
1917         vcodec_exit_mode_nolock(pservice->dev_id, config);
1918         vpu_service_power_off(pservice);
1919
1920         pr_info("init success\n");
1921
1922 #if HEVC_SIM_ENABLE
1923         if (pservice->hw_info->hw_id == HEVC_ID)
1924                 simulate_init(pservice);
1925 #endif
1926
1927 #if HEVC_TEST_ENABLE
1928         hevc_test_case0(pservice);
1929 #endif
1930
1931         return 0;
1932
1933 err:
1934         pr_info("init failed\n");
1935         vcodec_exit_mode_nolock(pservice->dev_id, config);
1936         vpu_service_power_off(pservice);
1937         vpu_put_clk(pservice);
1938         wake_lock_destroy(&pservice->wake_lock);
1939
1940         if (res)
1941                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
1942         if (pservice->irq_enc > 0)
1943                 free_irq(pservice->irq_enc, (void *)pservice);
1944         if (pservice->irq_dec > 0)
1945                 free_irq(pservice->irq_dec, (void *)pservice);
1946
1947         if (pservice->child_dev) {
1948                 device_destroy(pservice->cls, pservice->dev_t);
1949                 cdev_del(&pservice->cdev);
1950                 unregister_chrdev_region(pservice->dev_t, 1);
1951         }
1952
1953         if (pservice->cls)
1954                 class_destroy(pservice->cls);
1955
1956         return ret;
1957 }
1958
1959 static int vcodec_remove(struct platform_device *pdev)
1960 {
1961         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
1962         struct resource *res;
1963
1964         device_destroy(pservice->cls, pservice->dev_t);
1965         class_destroy(pservice->cls);
1966         cdev_del(&pservice->cdev);
1967         unregister_chrdev_region(pservice->dev_t, 1);
1968
1969         free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);
1970         free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);
1971         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1972         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
1973         vpu_put_clk(pservice);
1974         wake_lock_destroy(&pservice->wake_lock);
1975
1976 #ifdef CONFIG_DEBUG_FS
1977         debugfs_remove(pservice->debugfs_file_regs);
1978         debugfs_remove(pservice->debugfs_dir);
1979 #endif
1980
1981         return 0;
1982 }
1983
1984 #if defined(CONFIG_OF)
1985 static const struct of_device_id vcodec_service_dt_ids[] = {
1986         {.compatible = "vpu_service",},
1987         {.compatible = "rockchip,hevc_service",},
1988         {},
1989 };
1990 #endif
1991
1992 static struct platform_driver vcodec_driver = {
1993         .probe = vcodec_probe,
1994         .remove = vcodec_remove,
1995         .driver = {
1996                 .name = "vcodec",
1997                 .owner = THIS_MODULE,
1998 #if defined(CONFIG_OF)
1999                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2000 #endif
2001         },
2002 };
2003
2004 static void get_hw_info(struct vpu_service_info *pservice)
2005 {
2006         VPUHwDecConfig_t *dec = &pservice->dec_config;
2007         VPUHwEncConfig_t *enc = &pservice->enc_config;
2008
2009         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {
2010                 u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];
2011                 u32 asicID      = pservice->dec_dev.hwregs[0];
2012
2013                 dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;
2014                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2015                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2016                         dec->jpegSupport = JPEG_PROGRESSIVE;
2017                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2018                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2019                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2020                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2021                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2022                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2023
2024                 if (soc_is_rk3190() || soc_is_rk3288())
2025                         dec->maxDecPicWidth = 4096;
2026                 else if (cpu_is_rk3036() || cpu_is_rk312x())
2027                         dec->maxDecPicWidth = 1920;
2028                 else
2029                         dec->maxDecPicWidth = configReg & 0x07FFU;
2030
2031                 /* 2nd Config register */
2032                 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];
2033                 if (dec->refBufSupport) {
2034                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2035                                 dec->refBufSupport |= 2;
2036                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2037                                 dec->refBufSupport |= 4;
2038                 }
2039                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2040                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2041                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2042                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2043
2044                 /* JPEG xtensions */
2045                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2046                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2047                 else
2048                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2049
2050                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2051                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2052                 else
2053                         dec->rvSupport = RV_NOT_SUPPORTED;
2054                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2055
2056                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2057                         dec->refBufSupport |= 8; /* enable HW support for offset */
2058
2059                 /// invalidate fuse register value in rk319x vpu and following.
2060                 if (!soc_is_rk3190() && !soc_is_rk3288() && !cpu_is_rk3036() && !cpu_is_rk312x()) {
2061                         VPUHwFuseStatus_t hwFuseSts;
2062                         /* Decoder fuse configuration */
2063                         u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2064
2065                         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
2066                         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
2067                         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
2068                         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
2069                         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
2070                         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
2071                         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
2072                         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
2073                         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
2074                         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
2075                         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
2076                         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
2077                         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
2078                         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
2079
2080                         /* check max. decoder output width */
2081
2082                         if (fuseReg & 0x8000U)
2083                                 hwFuseSts.maxDecPicWidthFuse = 1920;
2084                         else if (fuseReg & 0x4000U)
2085                                 hwFuseSts.maxDecPicWidthFuse = 1280;
2086                         else if (fuseReg & 0x2000U)
2087                                 hwFuseSts.maxDecPicWidthFuse = 720;
2088                         else if (fuseReg & 0x1000U)
2089                                 hwFuseSts.maxDecPicWidthFuse = 352;
2090                         else    /* remove warning */
2091                                 hwFuseSts.maxDecPicWidthFuse = 352;
2092
2093                         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
2094
2095                         /* Pp configuration */
2096                         configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
2097
2098                         if ((configReg >> DWL_PP_E) & 0x01U) {
2099                                 dec->ppSupport = 1;
2100                                 dec->maxPpOutPicWidth = configReg & 0x07FFU;
2101                                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
2102                                 dec->ppConfig = configReg;
2103                         } else {
2104                                 dec->ppSupport = 0;
2105                                 dec->maxPpOutPicWidth = 0;
2106                                 dec->ppConfig = 0;
2107                         }
2108
2109                         /* check the HW versio */
2110                         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
2111                                 /* Pp configuration */
2112                                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2113                                 if ((configReg >> DWL_PP_E) & 0x01U) {
2114                                         /* Pp fuse configuration */
2115                                         u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
2116
2117                                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
2118                                                 hwFuseSts.ppSupportFuse = 1;
2119                                                 /* check max. pp output width */
2120                                                 if (fuseRegPp & 0x8000U)
2121                                                         hwFuseSts.maxPpOutPicWidthFuse = 1920;
2122                                                 else if (fuseRegPp & 0x4000U)
2123                                                         hwFuseSts.maxPpOutPicWidthFuse = 1280;
2124                                                 else if (fuseRegPp & 0x2000U)
2125                                                         hwFuseSts.maxPpOutPicWidthFuse = 720;
2126                                                 else if (fuseRegPp & 0x1000U)
2127                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;
2128                                                 else
2129                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;
2130                                                 hwFuseSts.ppConfigFuse = fuseRegPp;
2131                                         } else {
2132                                                 hwFuseSts.ppSupportFuse = 0;
2133                                                 hwFuseSts.maxPpOutPicWidthFuse = 0;
2134                                                 hwFuseSts.ppConfigFuse = 0;
2135                                         }
2136                                 } else {
2137                                         hwFuseSts.ppSupportFuse = 0;
2138                                         hwFuseSts.maxPpOutPicWidthFuse = 0;
2139                                         hwFuseSts.ppConfigFuse = 0;
2140                                 }
2141
2142                                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
2143                                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
2144                                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
2145                                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
2146                                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
2147                                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
2148                                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
2149                                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
2150                                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
2151                                         dec->jpegSupport = JPEG_BASELINE;
2152                                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
2153                                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
2154                                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
2155                                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
2156                                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
2157                                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
2158
2159                                 /* check the pp config vs fuse status */
2160                                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
2161                                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
2162                                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
2163                                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
2164                                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
2165
2166                                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
2167                                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
2168                                 }
2169                                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
2170                                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
2171                                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;
2172                                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;
2173                                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;
2174                         }
2175                 }
2176
2177                 if (!cpu_is_rk3036()) {
2178                         configReg = pservice->enc_dev.hwregs[63];
2179                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2180                         enc->h264Enabled = (configReg >> 27) & 1;
2181                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2182                         enc->jpegEnabled = (configReg >> 25) & 1;
2183                         enc->vsEnabled = (configReg >> 24) & 1;
2184                         enc->rgbEnabled = (configReg >> 28) & 1;
2185                         /*enc->busType = (configReg >> 20) & 15;
2186                         enc->synthesisLanguage = (configReg >> 16) & 15;
2187                         enc->busWidth = (configReg >> 12) & 15;*/
2188                         enc->reg_size = pservice->reg_size;
2189                         enc->reserv[0] = enc->reserv[1] = 0;
2190                 }
2191
2192                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2193                 if (pservice->auto_freq) {
2194                         pr_info("vpu_service set to auto frequency mode\n");
2195                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2196                 }
2197
2198                 pservice->bug_dec_addr = cpu_is_rk30xx();
2199         } else {
2200                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2201                         dec->maxDecPicWidth = 1920;
2202                 else
2203                         dec->maxDecPicWidth = 4096;
2204                 /* disable frequency switch in hevc.*/
2205                 pservice->auto_freq = false;
2206         }
2207 }
2208
2209 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2210 {
2211         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2212         vpu_device *dev = &pservice->dec_dev;
2213         u32 raw_status;
2214         u32 irq_status;
2215
2216         vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);
2217
2218         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2219
2220         pr_debug("dec_irq\n");
2221
2222         if (irq_status & DEC_INTERRUPT_BIT) {
2223                 pr_debug("dec_isr dec %x\n", irq_status);
2224                 if ((irq_status & 0x40001) == 0x40001)
2225                 {
2226                         do {
2227                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2228                         } while ((irq_status & 0x40001) == 0x40001);
2229                 }
2230
2231                 /* clear dec IRQ */
2232                 if (pservice->hw_info->hw_id != HEVC_ID)
2233                         writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
2234                 else
2235                         writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2236                 atomic_add(1, &dev->irq_count_codec);
2237         }
2238
2239         if (pservice->hw_info->hw_id != HEVC_ID) {
2240                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2241                 if (irq_status & PP_INTERRUPT_BIT) {
2242                         pr_debug("vdpu_isr pp  %x\n", irq_status);
2243                         /* clear pp IRQ */
2244                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2245                         atomic_add(1, &dev->irq_count_pp);
2246                 }
2247         }
2248
2249         pservice->irq_status = raw_status;
2250
2251         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2252
2253         return IRQ_WAKE_THREAD;
2254 }
2255
2256 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2257 {
2258         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2259         vpu_device *dev = &pservice->dec_dev;
2260
2261         mutex_lock(pservice->lock);
2262         if (atomic_read(&dev->irq_count_codec)) {
2263 #if VPU_SERVICE_SHOW_TIME
2264                 do_gettimeofday(&dec_end);
2265                 pr_info("dec task: %ld ms\n",
2266                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2267                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2268 #endif
2269                 atomic_sub(1, &dev->irq_count_codec);
2270                 if (NULL == pservice->reg_codec) {
2271                         pr_err("error: dec isr with no task waiting\n");
2272                 } else {
2273                         reg_from_run_to_done(pservice, *pservice->reg_codec);
2274                 }
2275         }
2276
2277         if (atomic_read(&dev->irq_count_pp)) {
2278
2279 #if VPU_SERVICE_SHOW_TIME
2280                 do_gettimeofday(&pp_end);
2281                 printk("pp  task: %ld ms\n",
2282                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2283                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2284 #endif
2285
2286                 atomic_sub(1, &dev->irq_count_pp);
2287                 if (NULL == pservice->reg_pproc) {
2288                         pr_err("error: pp isr with no task waiting\n");
2289                 } else {
2290                         reg_from_run_to_done(pservice, pservice->reg_pproc);
2291                 }
2292         }
2293         try_set_reg(pservice);
2294         mutex_unlock(pservice->lock);
2295         return IRQ_HANDLED;
2296 }
2297
2298 static irqreturn_t vepu_irq(int irq, void *dev_id)
2299 {
2300         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2301         vpu_device *dev = &pservice->enc_dev;
2302         u32 irq_status;
2303
2304         vcodec_enter_mode_nolock(pservice->dev_id,  &pservice->reserved_mode);
2305         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2306
2307         pr_debug("vepu_irq irq status %x\n", irq_status);
2308
2309 #if VPU_SERVICE_SHOW_TIME
2310         do_gettimeofday(&enc_end);
2311         pr_info("enc task: %ld ms\n",
2312                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2313                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2314 #endif
2315         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2316                 /* clear enc IRQ */
2317                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2318                 atomic_add(1, &dev->irq_count_codec);
2319         }
2320
2321         pservice->irq_status = irq_status;
2322
2323         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2324
2325         return IRQ_WAKE_THREAD;
2326 }
2327
2328 static irqreturn_t vepu_isr(int irq, void *dev_id)
2329 {
2330         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2331         vpu_device *dev = &pservice->enc_dev;
2332
2333         mutex_lock(pservice->lock);
2334         if (atomic_read(&dev->irq_count_codec)) {
2335                 atomic_sub(1, &dev->irq_count_codec);
2336                 if (NULL == pservice->reg_codec) {
2337                         pr_err("error: enc isr with no task waiting\n");
2338                 } else {
2339                         reg_from_run_to_done(pservice, *pservice->reg_codec);
2340                 }
2341         }
2342         try_set_reg(pservice);
2343         mutex_unlock(pservice->lock);
2344         return IRQ_HANDLED;
2345 }
2346
2347 static int __init vcodec_service_init(void)
2348 {
2349         int ret;
2350
2351         g_combo.hevc_srv = NULL;
2352         g_combo.vpu_srv = NULL;
2353         INIT_LIST_HEAD(&g_combo.waiting);
2354         INIT_LIST_HEAD(&g_combo.running);
2355         mutex_init(&g_combo.run_lock);
2356         g_combo.reg_codec = NULL;
2357         g_combo.current_hw_mode = VCODEC_DEVICE_ID_VPU;
2358
2359         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2360                 pr_err("Platform device register failed (%d).\n", ret);
2361                 return ret;
2362         }
2363
2364 #ifdef CONFIG_DEBUG_FS
2365         vcodec_debugfs_init();
2366 #endif
2367
2368         return ret;
2369 }
2370
2371 static void __exit vcodec_service_exit(void)
2372 {
2373 #ifdef CONFIG_DEBUG_FS
2374         vcodec_debugfs_exit();
2375 #endif
2376
2377         platform_driver_unregister(&vcodec_driver);
2378 }
2379
2380 module_init(vcodec_service_init);
2381 module_exit(vcodec_service_exit);
2382
2383 #ifdef CONFIG_DEBUG_FS
2384 #include <linux/seq_file.h>
2385
2386 static int vcodec_debugfs_init()
2387 {
2388         parent = debugfs_create_dir("vcodec", NULL);
2389         if (!parent)
2390                 return -1;
2391
2392         return 0;
2393 }
2394
2395 static void vcodec_debugfs_exit()
2396 {
2397         debugfs_remove(parent);
2398 }
2399
2400 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2401 {
2402         return debugfs_create_dir(dirname, parent);
2403 }
2404
2405 static int debug_vcodec_show(struct seq_file *s, void *unused)
2406 {
2407         struct vpu_service_info *pservice = s->private;
2408         unsigned int i, n;
2409         vpu_reg *reg, *reg_tmp;
2410         vpu_session *session, *session_tmp;
2411
2412         mutex_lock(pservice->lock);
2413         vpu_service_power_on(pservice);
2414         if (pservice->hw_info->hw_id != HEVC_ID) {
2415                 seq_printf(s, "\nENC Registers:\n");
2416                 n = pservice->enc_dev.iosize >> 2;
2417                 for (i = 0; i < n; i++) {
2418                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));
2419                 }
2420         }
2421         seq_printf(s, "\nDEC Registers:\n");
2422         n = pservice->dec_dev.iosize >> 2;
2423         for (i = 0; i < n; i++)
2424                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2425
2426         seq_printf(s, "\nvpu service status:\n");
2427         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2428                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2429                 /*seq_printf(s, "waiting reg set %d\n");*/
2430                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2431                         seq_printf(s, "waiting register set\n");
2432                 }
2433                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2434                         seq_printf(s, "running register set\n");
2435                 }
2436                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2437                         seq_printf(s, "done    register set\n");
2438                 }
2439         }
2440         mutex_unlock(pservice->lock);
2441
2442         return 0;
2443 }
2444
2445 static int debug_vcodec_open(struct inode *inode, struct file *file)
2446 {
2447         return single_open(file, debug_vcodec_show, inode->i_private);
2448 }
2449
2450 #endif
2451
2452 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2453 #include "hevc_test_inc/pps_00.h"
2454 #include "hevc_test_inc/register_00.h"
2455 #include "hevc_test_inc/rps_00.h"
2456 #include "hevc_test_inc/scaling_list_00.h"
2457 #include "hevc_test_inc/stream_00.h"
2458
2459 #include "hevc_test_inc/pps_01.h"
2460 #include "hevc_test_inc/register_01.h"
2461 #include "hevc_test_inc/rps_01.h"
2462 #include "hevc_test_inc/scaling_list_01.h"
2463 #include "hevc_test_inc/stream_01.h"
2464
2465 #include "hevc_test_inc/cabac.h"
2466
2467 extern struct ion_client *rockchip_ion_client_create(const char * name);
2468
2469 static struct ion_client *ion_client = NULL;
2470 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2471 {
2472         int size = (len+15) & (~15);
2473         struct ion_handle *handle;
2474         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2475
2476         if (ion_client == NULL)
2477                 ion_client = rockchip_ion_client_create("vcodec");
2478
2479         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2480
2481         ptr = ion_map_kernel(ion_client, handle);
2482
2483         ion_phys(ion_client, handle, phy, &size);
2484
2485         memcpy(ptr, tbl, len);
2486
2487         return ptr;
2488 }
2489
2490 u8* get_align_ptr_no_copy(int len, u32 *phy)
2491 {
2492         int size = (len+15) & (~15);
2493         struct ion_handle *handle;
2494         u8 *ptr;
2495
2496         if (ion_client == NULL)
2497                 ion_client = rockchip_ion_client_create("vcodec");
2498
2499         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2500
2501         ptr = ion_map_kernel(ion_client, handle);
2502
2503         ion_phys(ion_client, handle, phy, &size);
2504
2505         return ptr;
2506 }
2507
2508 #define TEST_CNT    2
2509 static int hevc_test_case0(vpu_service_info *pservice)
2510 {
2511         vpu_session session;
2512         vpu_reg *reg;
2513         unsigned long size = 272;//sizeof(register_00); // registers array length
2514         int testidx = 0;
2515         int ret = 0;
2516
2517         u8 *pps_tbl[TEST_CNT];
2518         u8 *register_tbl[TEST_CNT];
2519         u8 *rps_tbl[TEST_CNT];
2520         u8 *scaling_list_tbl[TEST_CNT];
2521         u8 *stream_tbl[TEST_CNT];
2522
2523         int stream_size[2];
2524         int pps_size[2];
2525         int rps_size[2];
2526         int scl_size[2];
2527         int cabac_size[2];
2528
2529         u32 phy_pps;
2530         u32 phy_rps;
2531         u32 phy_scl;
2532         u32 phy_str;
2533         u32 phy_yuv;
2534         u32 phy_ref;
2535         u32 phy_cabac;
2536
2537         volatile u8 *stream_buf;
2538         volatile u8 *pps_buf;
2539         volatile u8 *rps_buf;
2540         volatile u8 *scl_buf;
2541         volatile u8 *yuv_buf;
2542         volatile u8 *cabac_buf;
2543         volatile u8 *ref_buf;
2544
2545         u8 *pps;
2546         u8 *yuv[2];
2547         int i;
2548
2549         pps_tbl[0] = pps_00;
2550         pps_tbl[1] = pps_01;
2551
2552         register_tbl[0] = register_00;
2553         register_tbl[1] = register_01;
2554
2555         rps_tbl[0] = rps_00;
2556         rps_tbl[1] = rps_01;
2557
2558         scaling_list_tbl[0] = scaling_list_00;
2559         scaling_list_tbl[1] = scaling_list_01;
2560
2561         stream_tbl[0] = stream_00;
2562         stream_tbl[1] = stream_01;
2563
2564         stream_size[0] = sizeof(stream_00);
2565         stream_size[1] = sizeof(stream_01);
2566
2567         pps_size[0] = sizeof(pps_00);
2568         pps_size[1] = sizeof(pps_01);
2569
2570         rps_size[0] = sizeof(rps_00);
2571         rps_size[1] = sizeof(rps_01);
2572
2573         scl_size[0] = sizeof(scaling_list_00);
2574         scl_size[1] = sizeof(scaling_list_01);
2575
2576         cabac_size[0] = sizeof(Cabac_table);
2577         cabac_size[1] = sizeof(Cabac_table);
2578
2579         /* create session */
2580         session.pid = current->pid;
2581         session.type = VPU_DEC;
2582         INIT_LIST_HEAD(&session.waiting);
2583         INIT_LIST_HEAD(&session.running);
2584         INIT_LIST_HEAD(&session.done);
2585         INIT_LIST_HEAD(&session.list_session);
2586         init_waitqueue_head(&session.wait);
2587         atomic_set(&session.task_running, 0);
2588         list_add_tail(&session.list_session, &pservice->session);
2589
2590         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2591         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2592
2593         while (testidx < TEST_CNT) {
2594                 /* create registers */
2595                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2596                 if (NULL == reg) {
2597                         pr_err("error: kmalloc fail in reg_init\n");
2598                         return -1;
2599                 }
2600
2601                 if (size > pservice->reg_size) {
2602                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2603                         size = pservice->reg_size;
2604                 }
2605                 reg->session = &session;
2606                 reg->type = session.type;
2607                 reg->size = size;
2608                 reg->freq = VPU_FREQ_DEFAULT;
2609                 reg->reg = (unsigned long *)&reg[1];
2610                 INIT_LIST_HEAD(&reg->session_link);
2611                 INIT_LIST_HEAD(&reg->status_link);
2612
2613                 /* TODO: stuff registers */
2614                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2615
2616                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2617                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2618                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2619                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2620                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2621
2622                 pps = pps_buf;
2623
2624                 /* TODO: replace reigster address */
2625                 for (i=0; i<64; i++) {
2626                         u32 scaling_offset;
2627                         u32 tmp;
2628
2629                         scaling_offset = (u32)pps[i*80+74];
2630                         scaling_offset += (u32)pps[i*80+75] << 8;
2631                         scaling_offset += (u32)pps[i*80+76] << 16;
2632                         scaling_offset += (u32)pps[i*80+77] << 24;
2633
2634                         tmp = phy_scl + scaling_offset;
2635
2636                         pps[i*80+74] = tmp & 0xff;
2637                         pps[i*80+75] = (tmp >> 8) & 0xff;
2638                         pps[i*80+76] = (tmp >> 16) & 0xff;
2639                         pps[i*80+77] = (tmp >> 24) & 0xff;
2640                 }
2641
2642                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2643                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2644
2645                 reg->reg[1] = 0x21;
2646                 reg->reg[4] = phy_str;
2647                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2648                 reg->reg[6] = phy_cabac;
2649                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2650                 reg->reg[42] = phy_pps;
2651                 reg->reg[43] = phy_rps;
2652                 for (i = 10; i <= 24; i++)
2653                         reg->reg[i] = phy_yuv;
2654
2655                 mutex_lock(pservice->lock);
2656                 list_add_tail(&reg->status_link, pservice->waiting);
2657                 list_add_tail(&reg->session_link, &session.waiting);
2658                 mutex_unlock(pservice->lock);
2659
2660                 printk("%s %d %p\n", __func__, __LINE__, pservice);
2661
2662                 /* stuff hardware */
2663                 try_set_reg(pservice);
2664
2665                 /* wait for result */
2666                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2667                 if (!list_empty(&session.done)) {
2668                         if (ret < 0)
2669                                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2670                         ret = 0;
2671                 } else {
2672                         if (unlikely(ret < 0)) {
2673                                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);
2674                         } else if (0 == ret) {
2675                                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2676                                 ret = -ETIMEDOUT;
2677                         }
2678                 }
2679                 if (ret < 0) {
2680                         int task_running = atomic_read(&session.task_running);
2681                         int n;
2682                         mutex_lock(pservice->lock);
2683                         vpu_service_dump(pservice);
2684                         if (task_running) {
2685                                 atomic_set(&session.task_running, 0);
2686                                 atomic_sub(task_running, &pservice->total_running);
2687                                 printk("%d task is running but not return, reset hardware...", task_running);
2688                                 vpu_reset(pservice);
2689                                 printk("done\n");
2690                         }
2691                         vpu_service_session_clear(pservice, &session);
2692                         mutex_unlock(pservice->lock);
2693
2694                         printk("\nDEC Registers:\n");
2695                         n = pservice->dec_dev.iosize >> 2;
2696                         for (i=0; i<n; i++)
2697                                 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2698
2699                         pr_err("test index %d failed\n", testidx);
2700                         break;
2701                 } else {
2702                         pr_info("test index %d success\n", testidx);
2703
2704                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2705
2706                         for (i=0; i<68; i++) {
2707                                 if (i % 4 == 0)
2708                                         printk("%02d: ", i);
2709                                 printk("%08x ", reg->reg[i]);
2710                                 if ((i+1) % 4 == 0)
2711                                         printk("\n");
2712                         }
2713
2714                         testidx++;
2715                 }
2716
2717                 reg_deinit(pservice, reg);
2718         }
2719
2720         return 0;
2721 }
2722
2723 #endif
2724