arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/clk.h>
  20 #include <linux/compat.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/fs.h>
  28 #include <linux/ioport.h>
  29 #include <linux/miscdevice.h>
  30 #include <linux/mm.h>
  31 #include <linux/poll.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/reset.h>
  34 #include <linux/sched.h>
  35 #include <linux/slab.h>
  36 #include <linux/wakelock.h>
  37 #include <linux/cdev.h>
  38 #include <linux/of.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/of_irq.h>
  41 #include <linux/rockchip/cpu.h>
  42 #include <linux/rockchip/cru.h>
  43 #include <linux/rockchip/pmu.h>
  44 #ifdef CONFIG_MFD_SYSCON
  45 #include <linux/regmap.h>
  46 #endif
  47 #include <linux/mfd/syscon.h>
  48
  49 #include <asm/cacheflush.h>
  50 #include <linux/uaccess.h>
  51 #include <linux/rockchip/grf.h>
  52
  53 #if defined(CONFIG_ION_ROCKCHIP)
  54 #include <linux/rockchip_ion.h>
  55 #endif
  56
  57 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  58 #define CONFIG_VCODEC_MMU
  59 #endif
  60
  61 #ifdef CONFIG_VCODEC_MMU
  62 #include <linux/rockchip-iovmm.h>
  63 #include <linux/dma-buf.h>
  64 #endif
  65
  66 #ifdef CONFIG_DEBUG_FS
  67 #include <linux/debugfs.h>
  68 #endif
  69
  70 #if defined(CONFIG_ARCH_RK319X)
  71 #include <mach/grf.h>
  72 #endif
  73
  74 #include "vcodec_service.h"
  75
  76 /*
  77  * debug flag usage:
  78  * +------+-------------------+
  79  * | 8bit |      24bit        |
  80  * +------+-------------------+
  81  *  0~23 bit is for different information type
  82  * 24~31 bit is for information print format
  83  */
  84
  85 #define DEBUG_POWER                             0x00000001
  86 #define DEBUG_CLOCK                             0x00000002
  87 #define DEBUG_IRQ_STATUS                        0x00000004
  88 #define DEBUG_IOMMU                             0x00000008
  89 #define DEBUG_IOCTL                             0x00000010
  90 #define DEBUG_FUNCTION                          0x00000020
  91 #define DEBUG_REGISTER                          0x00000040
  92 #define DEBUG_EXTRA_INFO                        0x00000080
  93 #define DEBUG_TIMING                            0x00000100
  94
  95 #define PRINT_FUNCTION                          0x80000000
  96 #define PRINT_LINE                              0x40000000
  97
  98 static int debug;
  99 module_param(debug, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(debug,
 101                  "Debug level - higher value produces more verbose messages");
 102
 103 #define HEVC_TEST_ENABLE        0
 104 #define VCODEC_CLOCK_ENABLE     1
 105
 106 typedef enum {
 107         VPU_DEC_ID_9190         = 0x6731,
 108         VPU_ID_8270             = 0x8270,
 109         VPU_ID_4831             = 0x4831,
 110         HEVC_ID                 = 0x6867,
 111 } VPU_HW_ID;
 112
 113 enum VPU_HW_SPEC {
 114         VPU_TYPE_VPU,
 115         VPU_TYPE_HEVC,
 116         VPU_TYPE_COMBO_NOENC,
 117         VPU_TYPE_COMBO
 118 };
 119
 120 typedef enum {
 121         VPU_DEC_TYPE_9190       = 0,
 122         VPU_ENC_TYPE_8270       = 0x100,
 123         VPU_ENC_TYPE_4831       ,
 124 } VPU_HW_TYPE_E;
 125
 126 typedef enum VPU_FREQ {
 127         VPU_FREQ_200M,
 128         VPU_FREQ_266M,
 129         VPU_FREQ_300M,
 130         VPU_FREQ_400M,
 131         VPU_FREQ_500M,
 132         VPU_FREQ_600M,
 133         VPU_FREQ_DEFAULT,
 134         VPU_FREQ_BUT,
 135 } VPU_FREQ;
 136
 137 typedef struct {
 138         VPU_HW_ID               hw_id;
 139         unsigned long           hw_addr;
 140         unsigned long           enc_offset;
 141         unsigned long           enc_reg_num;
 142         unsigned long           enc_io_size;
 143         unsigned long           dec_offset;
 144         unsigned long           dec_reg_num;
 145         unsigned long           dec_io_size;
 146 } VPU_HW_INFO_E;
 147
 148 struct extra_info_elem {
 149         u32 index;
 150         u32 offset;
 151 };
 152
 153 #define EXTRA_INFO_MAGIC        0x4C4A46
 154
 155 struct extra_info_for_iommu {
 156         u32 magic;
 157         u32 cnt;
 158         struct extra_info_elem elem[20];
 159 };
 160
 161 #define MHZ                                     (1000*1000)
 162
 163 #define REG_NUM_9190_DEC                        (60)
 164 #define REG_NUM_9190_PP                         (41)
 165 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 166
 167 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 168
 169 #define REG_NUM_ENC_8270                        (96)
 170 #define REG_SIZE_ENC_8270                       (0x200)
 171 #define REG_NUM_ENC_4831                        (164)
 172 #define REG_SIZE_ENC_4831                       (0x400)
 173
 174 #define REG_NUM_HEVC_DEC                        (68)
 175
 176 #define SIZE_REG(reg)                           ((reg)*4)
 177
 178 static VPU_HW_INFO_E vpu_hw_set[] = {
 179         [0] = {
 180                 .hw_id          = VPU_ID_8270,
 181                 .hw_addr        = 0,
 182                 .enc_offset     = 0x0,
 183                 .enc_reg_num    = REG_NUM_ENC_8270,
 184                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 185                 .dec_offset     = REG_SIZE_ENC_8270,
 186                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 187                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 188         },
 189         [1] = {
 190                 .hw_id          = VPU_ID_4831,
 191                 .hw_addr        = 0,
 192                 .enc_offset     = 0x0,
 193                 .enc_reg_num    = REG_NUM_ENC_4831,
 194                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 195                 .dec_offset     = REG_SIZE_ENC_4831,
 196                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 197                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 198         },
 199         [2] = {
 200                 .hw_id          = HEVC_ID,
 201                 .hw_addr        = 0,
 202                 .dec_offset     = 0x0,
 203                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 204                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 205         },
 206         [3] = {
 207                 .hw_id          = VPU_DEC_ID_9190,
 208                 .hw_addr        = 0,
 209                 .enc_offset     = 0x0,
 210                 .enc_reg_num    = 0,
 211                 .enc_io_size    = 0,
 212                 .dec_offset     = 0,
 213                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 214                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 215         },
 216 };
 217
 218 #ifndef BIT
 219 #define BIT(x)                                  (1<<(x))
 220 #endif
 221
 222 // interrupt and error status register
 223 #define DEC_INTERRUPT_REGISTER                  1
 224 #define DEC_INTERRUPT_BIT                       BIT(8)
 225 #define DEC_READY_BIT                           BIT(12)
 226 #define DEC_BUS_ERROR_BIT                       BIT(13)
 227 #define DEC_BUFFER_EMPTY_BIT                    BIT(14)
 228 #define DEC_ASO_ERROR_BIT                       BIT(15)
 229 #define DEC_STREAM_ERROR_BIT                    BIT(16)
 230 #define DEC_SLICE_DONE_BIT                      BIT(17)
 231 #define DEC_TIMEOUT_BIT                         BIT(18)
 232 #define DEC_ERR_MASK                            DEC_BUS_ERROR_BIT \
 233                                                 |DEC_BUFFER_EMPTY_BIT \
 234                                                 |DEC_STREAM_ERROR_BIT \
 235                                                 |DEC_TIMEOUT_BIT
 236
 237 #define PP_INTERRUPT_REGISTER                   60
 238 #define PP_INTERRUPT_BIT                        BIT(8)
 239 #define PP_READY_BIT                            BIT(12)
 240 #define PP_BUS_ERROR_BIT                        BIT(13)
 241 #define PP_ERR_MASK                             PP_BUS_ERROR_BIT
 242
 243 #define ENC_INTERRUPT_REGISTER                  1
 244 #define ENC_INTERRUPT_BIT                       BIT(0)
 245 #define ENC_READY_BIT                           BIT(2)
 246 #define ENC_BUS_ERROR_BIT                       BIT(3)
 247 #define ENC_BUFFER_FULL_BIT                     BIT(5)
 248 #define ENC_TIMEOUT_BIT                         BIT(6)
 249 #define ENC_ERR_MASK                            ENC_BUS_ERROR_BIT \
 250                                                 |ENC_BUFFER_FULL_BIT \
 251                                                 |ENC_TIMEOUT_BIT
 252
 253 #define HEVC_INTERRUPT_REGISTER                 1
 254 #define HEVC_DEC_INT_RAW_BIT                    BIT(9)
 255 #define HEVC_DEC_BUS_ERROR_BIT                  BIT(13)
 256 #define HEVC_DEC_STR_ERROR_BIT                  BIT(14)
 257 #define HEVC_DEC_TIMEOUT_BIT                    BIT(15)
 258 #define HEVC_DEC_BUFFER_EMPTY_BIT               BIT(16)
 259 #define HEVC_DEC_COLMV_ERROR_BIT                BIT(17)
 260 #define HEVC_DEC_ERR_MASK                       HEVC_DEC_BUS_ERROR_BIT \
 261                                                 |HEVC_DEC_STR_ERROR_BIT \
 262                                                 |HEVC_DEC_TIMEOUT_BIT \
 263                                                 |HEVC_DEC_BUFFER_EMPTY_BIT \
 264                                                 |HEVC_DEC_COLMV_ERROR_BIT
 265
 266
 267 // gating configuration set
 268 #define VPU_REG_EN_ENC                          14
 269 #define VPU_REG_ENC_GATE                        2
 270 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 271
 272 #define VPU_REG_EN_DEC                          1
 273 #define VPU_REG_DEC_GATE                        2
 274 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 275 #define VPU_REG_EN_PP                           0
 276 #define VPU_REG_PP_GATE                         1
 277 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 278 #define VPU_REG_EN_DEC_PP                       1
 279 #define VPU_REG_DEC_PP_GATE                     61
 280 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 281
 282 #define DEBUG
 283 #ifdef DEBUG
 284 #define vpu_debug_func(type, fmt, args...)                      \
 285         do {                                                    \
 286                 if (unlikely(debug & type)) {                   \
 287                         pr_info("%s:%d: " fmt,                  \
 288                                  __func__, __LINE__, ##args);   \
 289                 }                                               \
 290         } while (0)
 291 #define vpu_debug(type, fmt, args...)                           \
 292         do {                                                    \
 293                 if (unlikely(debug & type)) {                   \
 294                         pr_info(fmt, ##args);                   \
 295                 }                                               \
 296         } while (0)
 297 #else
 298 #define vpu_debug_func(level, fmt, args...)
 299 #define vpu_debug(level, fmt, args...)
 300 #endif
 301
 302 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
 303 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
 304
 305 #define vpu_err(fmt, args...)                           \
 306                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 307
 308 #if defined(CONFIG_VCODEC_MMU)
 309 static u8 addr_tbl_vpu_h264dec[] = {
 310         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 311         25, 26, 27, 28, 29, 40, 41
 312 };
 313
 314 static u8 addr_tbl_vpu_vp8dec[] = {
 315         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 316 };
 317
 318 static u8 addr_tbl_vpu_vp6dec[] = {
 319         12, 13, 14, 18, 27, 40
 320 };
 321
 322 static u8 addr_tbl_vpu_vc1dec[] = {
 323         12, 13, 14, 15, 16, 17, 27, 41
 324 };
 325
 326 static u8 addr_tbl_vpu_jpegdec[] = {
 327         12, 40, 66, 67
 328 };
 329
 330 static u8 addr_tbl_vpu_defaultdec[] = {
 331         12, 13, 14, 15, 16, 17, 40, 41
 332 };
 333
 334 static u8 addr_tbl_vpu_enc[] = {
 335         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 336 };
 337
 338 static u8 addr_tbl_hevc_dec[] = {
 339         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 340         21, 22, 23, 24, 42, 43
 341 };
 342 #endif
 343
 344 enum VPU_DEC_FMT {
 345         VPU_DEC_FMT_H264,
 346         VPU_DEC_FMT_MPEG4,
 347         VPU_DEC_FMT_H263,
 348         VPU_DEC_FMT_JPEG,
 349         VPU_DEC_FMT_VC1,
 350         VPU_DEC_FMT_MPEG2,
 351         VPU_DEC_FMT_MPEG1,
 352         VPU_DEC_FMT_VP6,
 353         VPU_DEC_FMT_RV,
 354         VPU_DEC_FMT_VP7,
 355         VPU_DEC_FMT_VP8,
 356         VPU_DEC_FMT_AVS,
 357         VPU_DEC_FMT_SVC,
 358         VPU_DEC_FMT_VC2,
 359         VPU_DEC_FMT_MVC,
 360         VPU_DEC_FMT_THEORA,
 361         VPU_DEC_FMT_RES
 362 };
 363
 364 /**
 365  * struct for process session which connect to vpu
 366  *
 367  * @author ChenHengming (2011-5-3)
 368  */
 369 typedef struct vpu_session {
 370         enum VPU_CLIENT_TYPE type;
 371         /* a linked list of data so we can access them for debugging */
 372         struct list_head list_session;
 373         /* a linked list of register data waiting for process */
 374         struct list_head waiting;
 375         /* a linked list of register data in processing */
 376         struct list_head running;
 377         /* a linked list of register data processed */
 378         struct list_head done;
 379         wait_queue_head_t wait;
 380         pid_t pid;
 381         atomic_t task_running;
 382 } vpu_session;
 383
 384 /**
 385  * struct for process register set
 386  *
 387  * @author ChenHengming (2011-5-4)
 388  */
 389 typedef struct vpu_reg {
 390         enum VPU_CLIENT_TYPE type;
 391         VPU_FREQ freq;
 392         vpu_session *session;
 393         struct vpu_subdev_data *data;
 394         struct list_head session_link;          /* link to vpu service session */
 395         struct list_head status_link;           /* link to register set list */
 396         unsigned long size;
 397 #if defined(CONFIG_VCODEC_MMU)
 398         struct list_head mem_region_list;
 399         u32 dec_base;
 400 #endif
 401         u32 *reg;
 402 } vpu_reg;
 403
 404 typedef struct vpu_device {
 405         atomic_t                irq_count_codec;
 406         atomic_t                irq_count_pp;
 407         unsigned long           iobaseaddr;
 408         unsigned int            iosize;
 409         volatile u32            *hwregs;
 410 } vpu_device;
 411
 412 enum vcodec_device_id {
 413         VCODEC_DEVICE_ID_VPU,
 414         VCODEC_DEVICE_ID_HEVC,
 415         VCODEC_DEVICE_ID_COMBO
 416 };
 417
 418 enum VCODEC_RUNNING_MODE {
 419         VCODEC_RUNNING_MODE_NONE = -1,
 420         VCODEC_RUNNING_MODE_VPU,
 421         VCODEC_RUNNING_MODE_HEVC,
 422 };
 423
 424 struct vcodec_mem_region {
 425         struct list_head srv_lnk;
 426         struct list_head reg_lnk;
 427         struct list_head session_lnk;
 428         unsigned long iova;     /* virtual address for iommu */
 429         unsigned long len;
 430         u32 reg_idx;
 431         struct ion_handle *hdl;
 432 };
 433
 434 enum vpu_ctx_state {
 435         MMU_ACTIVATED   = BIT(0)
 436 };
 437
 438 struct vpu_subdev_data {
 439         struct cdev cdev;
 440         dev_t dev_t;
 441         struct class *cls;
 442         struct device *child_dev;
 443
 444         int irq_enc;
 445         int irq_dec;
 446         struct vpu_service_info *pservice;
 447
 448         u32 *regs;
 449         enum VCODEC_RUNNING_MODE mode;
 450         struct list_head lnk_service;
 451
 452         struct device *dev;
 453
 454         vpu_device enc_dev;
 455         vpu_device dec_dev;
 456         VPU_HW_INFO_E *hw_info;
 457
 458         u32 reg_size;
 459         unsigned long state;
 460
 461 #ifdef CONFIG_DEBUG_FS
 462         struct dentry *debugfs_dir;
 463         struct dentry *debugfs_file_regs;
 464 #endif
 465
 466 #if defined(CONFIG_VCODEC_MMU)
 467         struct device *mmu_dev;
 468 #endif
 469 };
 470
 471 typedef struct vpu_service_info {
 472         struct wake_lock wake_lock;
 473         struct delayed_work power_off_work;
 474         struct mutex lock;
 475         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 476         struct list_head running;               /* link to link_reg in struct vpu_reg */
 477         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 478         struct list_head session;               /* link to list_session in struct vpu_session */
 479         atomic_t total_running;
 480         atomic_t enabled;
 481         atomic_t power_on_cnt;
 482         atomic_t power_off_cnt;
 483         vpu_reg *reg_codec;
 484         vpu_reg *reg_pproc;
 485         vpu_reg *reg_resev;
 486         struct vpu_dec_config dec_config;
 487         struct vpu_enc_config enc_config;
 488
 489         bool auto_freq;
 490         bool bug_dec_addr;
 491         atomic_t freq_status;
 492
 493         struct clk *aclk_vcodec;
 494         struct clk *hclk_vcodec;
 495         struct clk *clk_core;
 496         struct clk *clk_cabac;
 497         struct clk *pd_video;
 498
 499 #ifdef CONFIG_RESET_CONTROLLER
 500         struct reset_control *rst_a;
 501         struct reset_control *rst_h;
 502         struct reset_control *rst_v;
 503 #endif
 504         struct device *dev;
 505
 506         u32 irq_status;
 507         atomic_t reset_request;
 508 #if defined(CONFIG_VCODEC_MMU)
 509         struct ion_client *ion_client;
 510         struct list_head mem_region_list;
 511 #endif
 512
 513         enum vcodec_device_id dev_id;
 514
 515         enum VCODEC_RUNNING_MODE curr_mode;
 516         u32 prev_mode;
 517
 518         struct delayed_work simulate_work;
 519
 520         u32 mode_bit;
 521         u32 mode_ctrl;
 522         u32 *reg_base;
 523         u32 ioaddr;
 524 #ifdef CONFIG_MFD_SYSCON
 525         struct regmap *grf_base;
 526 #else
 527         u32 *grf_base;
 528 #endif
 529         char *name;
 530
 531         u32 subcnt;
 532         struct list_head subdev_list;
 533 } vpu_service_info;
 534
 535 struct vcodec_combo {
 536         struct vpu_service_info *vpu_srv;
 537         struct vpu_service_info *hevc_srv;
 538         struct list_head waiting;
 539         struct list_head running;
 540         struct mutex run_lock;
 541         vpu_reg *reg_codec;
 542         enum vcodec_device_id current_hw_mode;
 543 };
 544
 545 struct vpu_request {
 546         u32 *req;
 547         u32 size;
 548 };
 549
 550 #ifdef CONFIG_COMPAT
 551 struct compat_vpu_request {
 552         compat_uptr_t req;
 553         u32 size;
 554 };
 555 #endif
 556
 557 /* debugfs root directory for all device (vpu, hevc).*/
 558 static struct dentry *parent;
 559
 560 #ifdef CONFIG_DEBUG_FS
 561 static int vcodec_debugfs_init(void);
 562 static void vcodec_debugfs_exit(void);
 563 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 564 static int debug_vcodec_open(struct inode *inode, struct file *file);
 565
 566 static const struct file_operations debug_vcodec_fops = {
 567         .open = debug_vcodec_open,
 568         .read = seq_read,
 569         .llseek = seq_lseek,
 570         .release = single_release,
 571 };
 572 #endif
 573
 574 #define VDPU_SOFT_RESET_REG     101
 575 #define VDPU_CLEAN_CACHE_REG    516
 576 #define VEPU_CLEAN_CACHE_REG    772
 577 #define HEVC_CLEAN_CACHE_REG    260
 578
 579 #define VPU_REG_ENABLE(base, reg)       do { \
 580                                                 base[reg] = 1; \
 581                                         } while (0)
 582
 583 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 584 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 585 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 586 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 587
 588 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 589 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 590
 591 typedef struct {
 592         char *name;
 593         struct timeval start;
 594         struct timeval end;
 595         u32 error_mask;
 596 } task_info;
 597
 598 typedef enum {
 599         TASK_VPU_ENC,
 600         TASK_VPU_DEC,
 601         TASK_VPU_PP,
 602         TASK_RKDEC_HEVC,
 603         TASK_TYPE_BUTT,
 604 } TASK_TYPE;
 605
 606 task_info tasks[TASK_TYPE_BUTT] = {
 607         {
 608                 .name = "enc",
 609                 .error_mask = ENC_ERR_MASK
 610         },
 611         {
 612                 .name = "dec",
 613                 .error_mask = DEC_ERR_MASK
 614         },
 615         {
 616                 .name = "pp",
 617                 .error_mask = PP_ERR_MASK
 618         },
 619         {
 620                 .name = "hevc",
 621                 .error_mask = HEVC_DEC_ERR_MASK
 622         },
 623 };
 624
 625 static void time_record(task_info *task, int is_end)
 626 {
 627         if (unlikely(debug & DEBUG_TIMING)) {
 628                 do_gettimeofday((is_end)?(&task->end):(&task->start));
 629         }
 630 }
 631
 632 static void time_diff(task_info *task)
 633 {
 634         vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
 635                         (task->end.tv_sec  - task->start.tv_sec)  * 1000 +
 636                         (task->end.tv_usec - task->start.tv_usec) / 1000);
 637 }
 638
 639 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 640 {
 641         int bits;
 642         u32 raw = 0;
 643         struct vpu_service_info *pservice = data->pservice;
 644         struct vpu_subdev_data *subdata, *n;
 645         if (pservice->subcnt < 2) {
 646 #if defined(CONFIG_VCODEC_MMU)
 647                 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 648                         set_bit(MMU_ACTIVATED, &data->state);
 649                         if (atomic_read(&pservice->enabled))
 650                                 rockchip_iovmm_activate(data->dev);
 651                         else
 652                                 BUG_ON(!atomic_read(&pservice->enabled));
 653                 }
 654 #endif
 655                 return;
 656         }
 657
 658         if (pservice->curr_mode == data->mode)
 659                 return;
 660
 661         vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
 662 #if defined(CONFIG_VCODEC_MMU)
 663         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 664                 if (data != subdata && subdata->mmu_dev &&
 665                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 666                         clear_bit(MMU_ACTIVATED, &subdata->state);
 667                         rockchip_iovmm_deactivate(subdata->dev);
 668                 }
 669         }
 670 #endif
 671         bits = 1 << pservice->mode_bit;
 672 #ifdef CONFIG_MFD_SYSCON
 673         regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
 674
 675         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 676                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 677                         raw | bits | (bits << 16));
 678         else
 679                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 680                         (raw & (~bits)) | (bits << 16));
 681 #else
 682         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 683         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 684                 writel_relaxed(raw | bits | (bits << 16),
 685                         pservice->grf_base + pservice->mode_ctrl / 4);
 686         else
 687                 writel_relaxed((raw & (~bits)) | (bits << 16),
 688                         pservice->grf_base + pservice->mode_ctrl / 4);
 689 #endif
 690 #if defined(CONFIG_VCODEC_MMU)
 691         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 692                 set_bit(MMU_ACTIVATED, &data->state);
 693                 if (atomic_read(&pservice->enabled))
 694                         rockchip_iovmm_activate(data->dev);
 695                 else
 696                         BUG_ON(!atomic_read(&pservice->enabled));
 697         }
 698 #endif
 699         pservice->prev_mode = pservice->curr_mode;
 700         pservice->curr_mode = data->mode;
 701 }
 702
 703 static void vcodec_exit_mode(struct vpu_subdev_data *data)
 704 {
 705         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 706                 clear_bit(MMU_ACTIVATED, &data->state);
 707                 rockchip_iovmm_deactivate(data->dev);
 708                 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 709         }
 710 }
 711
 712 static int vpu_get_clk(struct vpu_service_info *pservice)
 713 {
 714 #if VCODEC_CLOCK_ENABLE
 715         switch (pservice->dev_id) {
 716         case VCODEC_DEVICE_ID_HEVC:
 717                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 718                 if (IS_ERR(pservice->pd_video)) {
 719                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 720                         return -1;
 721                 }
 722         case VCODEC_DEVICE_ID_COMBO:
 723                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 724                 if (IS_ERR(pservice->clk_cabac)) {
 725                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 726                         pservice->clk_cabac = NULL;
 727                 }
 728                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 729                 if (IS_ERR(pservice->clk_core)) {
 730                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 731                         return -1;
 732                 }
 733         case VCODEC_DEVICE_ID_VPU:
 734                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 735                 if (IS_ERR(pservice->aclk_vcodec)) {
 736                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 737                         return -1;
 738                 }
 739
 740                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 741                 if (IS_ERR(pservice->hclk_vcodec)) {
 742                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 743                         return -1;
 744                 }
 745                 if (pservice->pd_video == NULL) {
 746                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 747                         if (IS_ERR(pservice->pd_video)) {
 748                                 pservice->pd_video = NULL;
 749                                 dev_info(pservice->dev, "do not have pd_video\n");
 750                         }
 751                 }
 752                 break;
 753         default:
 754                 ;
 755         }
 756
 757         return 0;
 758 #else
 759         return 0;
 760 #endif
 761 }
 762
 763 static void vpu_put_clk(struct vpu_service_info *pservice)
 764 {
 765 #if VCODEC_CLOCK_ENABLE
 766         if (pservice->pd_video)
 767                 devm_clk_put(pservice->dev, pservice->pd_video);
 768         if (pservice->aclk_vcodec)
 769                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 770         if (pservice->hclk_vcodec)
 771                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 772         if (pservice->clk_core)
 773                 devm_clk_put(pservice->dev, pservice->clk_core);
 774         if (pservice->clk_cabac)
 775                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 776 #endif
 777 }
 778
 779 static void vpu_reset(struct vpu_subdev_data *data)
 780 {
 781         struct vpu_service_info *pservice = data->pservice;
 782         pr_info("%s: resetting...", dev_name(pservice->dev));
 783
 784 #if defined(CONFIG_ARCH_RK29)
 785         clk_disable(aclk_ddr_vepu);
 786         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 787         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 788         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 789         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 790         mdelay(10);
 791         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 792         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 793         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 794         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 795         clk_enable(aclk_ddr_vepu);
 796 #elif defined(CONFIG_ARCH_RK30)
 797         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 798         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 799         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 800         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 801         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 802         mdelay(1);
 803         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 804         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 805         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 806         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 807         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 808 #else
 809 #endif
 810         WARN_ON(pservice->reg_codec != NULL);
 811         WARN_ON(pservice->reg_pproc != NULL);
 812         WARN_ON(pservice->reg_resev != NULL);
 813         pservice->reg_codec = NULL;
 814         pservice->reg_pproc = NULL;
 815         pservice->reg_resev = NULL;
 816
 817         pr_info("for 3288/3368...");
 818 #ifdef CONFIG_RESET_CONTROLLER
 819         if (pservice->rst_a && pservice->rst_h) {
 820                 if (pservice->rst_v)
 821                         reset_control_assert(pservice->rst_v);
 822                 reset_control_assert(pservice->rst_a);
 823                 reset_control_assert(pservice->rst_h);
 824                 usleep_range(10, 20);
 825                 reset_control_deassert(pservice->rst_h);
 826                 reset_control_deassert(pservice->rst_a);
 827                 if (pservice->rst_v)
 828                         reset_control_deassert(pservice->rst_v);
 829         }
 830 #endif
 831
 832 #if defined(CONFIG_VCODEC_MMU)
 833         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 834                 clear_bit(MMU_ACTIVATED, &data->state);
 835                 if (atomic_read(&pservice->enabled))
 836                         rockchip_iovmm_deactivate(data->dev);
 837                 else
 838                         BUG_ON(!atomic_read(&pservice->enabled));
 839         }
 840 #endif
 841         atomic_set(&pservice->reset_request, 0);
 842         pr_info("done\n");
 843 }
 844
 845 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 846 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 847 {
 848         vpu_reg *reg, *n;
 849         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 850                 reg_deinit(data, reg);
 851         }
 852         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 853                 reg_deinit(data, reg);
 854         }
 855         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 856                 reg_deinit(data, reg);
 857         }
 858 }
 859
 860 static void vpu_service_dump(struct vpu_service_info *pservice)
 861 {
 862 }
 863
 864 static void vpu_service_power_off(struct vpu_service_info *pservice)
 865 {
 866         int total_running;
 867         struct vpu_subdev_data *data = NULL, *n;
 868         int ret = atomic_add_unless(&pservice->enabled, -1, 0);
 869         if (!ret)
 870                 return;
 871
 872         total_running = atomic_read(&pservice->total_running);
 873         if (total_running) {
 874                 pr_alert("alert: power off when %d task running!!\n", total_running);
 875                 mdelay(50);
 876                 pr_alert("alert: delay 50 ms for running task\n");
 877                 vpu_service_dump(pservice);
 878         }
 879
 880         pr_info("%s: power off...", dev_name(pservice->dev));
 881         udelay(10);
 882 #if defined(CONFIG_VCODEC_MMU)
 883         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 884                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 885                         clear_bit(MMU_ACTIVATED, &data->state);
 886                         rockchip_iovmm_deactivate(data->dev);
 887                 }
 888         }
 889         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 890 #endif
 891
 892 #if VCODEC_CLOCK_ENABLE
 893         if (pservice->pd_video)
 894                 clk_disable_unprepare(pservice->pd_video);
 895         if (pservice->hclk_vcodec)
 896                 clk_disable_unprepare(pservice->hclk_vcodec);
 897         if (pservice->aclk_vcodec)
 898                 clk_disable_unprepare(pservice->aclk_vcodec);
 899         if (pservice->clk_core)
 900                 clk_disable_unprepare(pservice->clk_core);
 901         if (pservice->clk_cabac)
 902                 clk_disable_unprepare(pservice->clk_cabac);
 903 #endif
 904
 905         atomic_add(1, &pservice->power_off_cnt);
 906         wake_unlock(&pservice->wake_lock);
 907         pr_info("done\n");
 908 }
 909
 910 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 911 {
 912         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 913 }
 914
 915 static void vpu_power_off_work(struct work_struct *work_s)
 916 {
 917         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 918         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 919
 920         if (mutex_trylock(&pservice->lock)) {
 921                 vpu_service_power_off(pservice);
 922                 mutex_unlock(&pservice->lock);
 923         } else {
 924                 /* Come back later if the device is busy... */
 925                 vpu_queue_power_off_work(pservice);
 926         }
 927 }
 928
 929 static void vpu_service_power_on(struct vpu_service_info *pservice)
 930 {
 931         int ret;
 932         static ktime_t last;
 933         ktime_t now = ktime_get();
 934         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 935                 cancel_delayed_work_sync(&pservice->power_off_work);
 936                 vpu_queue_power_off_work(pservice);
 937                 last = now;
 938         }
 939         ret = atomic_add_unless(&pservice->enabled, 1, 1);
 940         if (!ret)
 941                 return ;
 942
 943         pr_info("%s: power on\n", dev_name(pservice->dev));
 944
 945 #define BIT_VCODEC_CLK_SEL      (1<<10)
 946         if (cpu_is_rk312x())
 947                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 948                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 949                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 950
 951 #if VCODEC_CLOCK_ENABLE
 952         if (pservice->aclk_vcodec)
 953                 clk_prepare_enable(pservice->aclk_vcodec);
 954         if (pservice->hclk_vcodec)
 955                 clk_prepare_enable(pservice->hclk_vcodec);
 956         if (pservice->clk_core)
 957                 clk_prepare_enable(pservice->clk_core);
 958         if (pservice->clk_cabac)
 959                 clk_prepare_enable(pservice->clk_cabac);
 960         if (pservice->pd_video)
 961                 clk_prepare_enable(pservice->pd_video);
 962 #endif
 963
 964         udelay(10);
 965         atomic_add(1, &pservice->power_on_cnt);
 966         wake_lock(&pservice->wake_lock);
 967 }
 968
 969 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 970 {
 971         u32 type = (reg->reg[3] & 0xF0000000) >> 28;
 972         return ((type == 8) || (type == 4));
 973 }
 974
 975 static inline bool reg_check_interlace(vpu_reg *reg)
 976 {
 977         u32 type = (reg->reg[3] & (1 << 23));
 978         return (type > 0);
 979 }
 980
 981 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 982 {
 983         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 984         return type;
 985 }
 986
 987 static inline int reg_probe_width(vpu_reg *reg)
 988 {
 989         int width_in_mb = reg->reg[4] >> 23;
 990         return width_in_mb * 16;
 991 }
 992
 993 #if defined(CONFIG_VCODEC_MMU)
 994 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
 995 {
 996         struct vpu_service_info *pservice = data->pservice;
 997         struct ion_handle *hdl;
 998         int ret = 0;
 999         struct vcodec_mem_region *mem_region;
1000
1001         hdl = ion_import_dma_buf(pservice->ion_client, fd);
1002         if (IS_ERR(hdl)) {
1003                 vpu_err("import dma-buf from fd %d failed\n", fd);
1004                 return PTR_ERR(hdl);
1005         }
1006         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1007
1008         if (mem_region == NULL) {
1009                 vpu_err("allocate memory for iommu memory region failed\n");
1010                 ion_free(pservice->ion_client, hdl);
1011                 return -1;
1012         }
1013
1014         mem_region->hdl = hdl;
1015         ret = ion_map_iommu(data->dev, pservice->ion_client,
1016                 mem_region->hdl, &mem_region->iova, &mem_region->len);
1017
1018         if (ret < 0) {
1019                 vpu_err("ion map iommu failed\n");
1020                 kfree(mem_region);
1021                 ion_free(pservice->ion_client, hdl);
1022                 return ret;
1023         }
1024         INIT_LIST_HEAD(&mem_region->reg_lnk);
1025         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1026         return mem_region->iova;
1027 }
1028
1029 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
1030                                 int size, vpu_reg *reg,
1031                                 struct extra_info_for_iommu *ext_inf)
1032 {
1033         struct vpu_service_info *pservice = data->pservice;
1034         int i;
1035         int usr_fd = 0;
1036         int offset = 0;
1037
1038         if (tbl == NULL || size <= 0) {
1039                 dev_err(pservice->dev, "input arguments invalidate\n");
1040                 return -1;
1041         }
1042
1043         for (i = 0; i < size; i++) {
1044                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
1045
1046                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
1047                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
1048                         /* special for vpu dec num 41 regitster */
1049                         offset = reg->reg[tbl[i]] >> 10 << 4;
1050                 else
1051                         offset = reg->reg[tbl[i]] >> 10;
1052
1053                 if (usr_fd != 0) {
1054                         struct ion_handle *hdl;
1055                         int ret = 0;
1056                         struct vcodec_mem_region *mem_region;
1057
1058                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
1059                         if (IS_ERR(hdl)) {
1060                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
1061                                 return PTR_ERR(hdl);
1062                         }
1063
1064                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
1065                                 int i = 0;
1066                                 char *pps;
1067                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
1068                                 for (i=0; i<64; i++) {
1069                                         u32 scaling_offset;
1070                                         u32 tmp;
1071                                         int scaling_fd= 0;
1072                                         scaling_offset = (u32)pps[i*80+74];
1073                                         scaling_offset += (u32)pps[i*80+75] << 8;
1074                                         scaling_offset += (u32)pps[i*80+76] << 16;
1075                                         scaling_offset += (u32)pps[i*80+77] << 24;
1076                                         scaling_fd = scaling_offset&0x3ff;
1077                                         scaling_offset = scaling_offset >> 10;
1078                                         if(scaling_fd > 0) {
1079                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
1080                                                 tmp += scaling_offset;
1081                                                 pps[i*80+74] = tmp & 0xff;
1082                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
1083                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
1084                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
1085                                         }
1086                                 }
1087                         }
1088
1089                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1090
1091                         if (mem_region == NULL) {
1092                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
1093                                 ion_free(pservice->ion_client, hdl);
1094                                 return -1;
1095                         }
1096
1097                         mem_region->hdl = hdl;
1098                         mem_region->reg_idx = tbl[i];
1099                         ret = ion_map_iommu(data->dev,
1100                                             pservice->ion_client,
1101                                             mem_region->hdl,
1102                                             &mem_region->iova,
1103                                             &mem_region->len);
1104
1105                         if (ret < 0) {
1106                                 dev_err(pservice->dev, "ion map iommu failed\n");
1107                                 kfree(mem_region);
1108                                 ion_free(pservice->ion_client, hdl);
1109                                 return ret;
1110                         }
1111
1112                         /* special for vpu dec num 12: record decoded length
1113                            hacking for decoded length
1114                            NOTE: not a perfect fix, the fd is not recorded */
1115                         if (tbl[i] == 12 && data->hw_info->hw_id != HEVC_ID &&
1116                                         (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {
1117                                 reg->dec_base = mem_region->iova + offset;
1118                                 vpu_debug(DEBUG_REGISTER, "dec_set %08x\n", reg->dec_base);
1119                         }
1120
1121                         reg->reg[tbl[i]] = mem_region->iova + offset;
1122                         INIT_LIST_HEAD(&mem_region->reg_lnk);
1123                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1124                 }
1125         }
1126
1127         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1128                 for (i=0; i<ext_inf->cnt; i++) {
1129                         vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1130                                   ext_inf->elem[i].index,
1131                                   ext_inf->elem[i].offset);
1132                         reg->reg[ext_inf->elem[i].index] +=
1133                                 ext_inf->elem[i].offset;
1134                 }
1135         }
1136
1137         return 0;
1138 }
1139
1140 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1141                                         vpu_reg *reg,
1142                                         struct extra_info_for_iommu *ext_inf)
1143 {
1144         VPU_HW_ID hw_id;
1145         u8 *tbl;
1146         int size = 0;
1147
1148         hw_id = data->hw_info->hw_id;
1149
1150         if (hw_id == HEVC_ID) {
1151                 tbl = addr_tbl_hevc_dec;
1152                 size = sizeof(addr_tbl_hevc_dec);
1153         } else {
1154                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1155                         switch (reg_check_fmt(reg)) {
1156                         case VPU_DEC_FMT_H264:
1157                                 {
1158                                         tbl = addr_tbl_vpu_h264dec;
1159                                         size = sizeof(addr_tbl_vpu_h264dec);
1160                                         break;
1161                                 }
1162                         case VPU_DEC_FMT_VP8:
1163                         case VPU_DEC_FMT_VP7:
1164                                 {
1165                                         tbl = addr_tbl_vpu_vp8dec;
1166                                         size = sizeof(addr_tbl_vpu_vp8dec);
1167                                         break;
1168                                 }
1169
1170                         case VPU_DEC_FMT_VP6:
1171                                 {
1172                                         tbl = addr_tbl_vpu_vp6dec;
1173                                         size = sizeof(addr_tbl_vpu_vp6dec);
1174                                         break;
1175                                 }
1176                         case VPU_DEC_FMT_VC1:
1177                                 {
1178                                         tbl = addr_tbl_vpu_vc1dec;
1179                                         size = sizeof(addr_tbl_vpu_vc1dec);
1180                                         break;
1181                                 }
1182
1183                         case VPU_DEC_FMT_JPEG:
1184                                 {
1185                                         tbl = addr_tbl_vpu_jpegdec;
1186                                         size = sizeof(addr_tbl_vpu_jpegdec);
1187                                         break;
1188                                 }
1189                         default:
1190                                 tbl = addr_tbl_vpu_defaultdec;
1191                                 size = sizeof(addr_tbl_vpu_defaultdec);
1192                                 break;
1193                         }
1194                 } else if (reg->type == VPU_ENC) {
1195                         tbl = addr_tbl_vpu_enc;
1196                         size = sizeof(addr_tbl_vpu_enc);
1197                 }
1198         }
1199
1200         if (size != 0) {
1201                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1202         } else {
1203                 return -1;
1204         }
1205 }
1206 #endif
1207
1208 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1209         vpu_session *session, void __user *src, u32 size)
1210 {
1211         struct vpu_service_info *pservice = data->pservice;
1212         int extra_size = 0;
1213         struct extra_info_for_iommu extra_info;
1214         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1215
1216         vpu_debug_enter();
1217
1218         if (NULL == reg) {
1219                 vpu_err("error: kmalloc fail in reg_init\n");
1220                 return NULL;
1221         }
1222
1223         if (size > data->reg_size) {
1224                 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1225                   size, data->reg_size);*/
1226                 extra_size = size - data->reg_size;
1227                 size = data->reg_size;
1228         }
1229         reg->session = session;
1230         reg->data = data;
1231         reg->type = session->type;
1232         reg->size = size;
1233         reg->freq = VPU_FREQ_DEFAULT;
1234         reg->reg = (u32 *)&reg[1];
1235         INIT_LIST_HEAD(&reg->session_link);
1236         INIT_LIST_HEAD(&reg->status_link);
1237
1238 #if defined(CONFIG_VCODEC_MMU)
1239         if (data->mmu_dev)
1240                 INIT_LIST_HEAD(&reg->mem_region_list);
1241 #endif
1242
1243         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1244                 vpu_err("error: copy_from_user failed in reg_init\n");
1245                 kfree(reg);
1246                 return NULL;
1247         }
1248
1249         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1250                 vpu_err("error: copy_from_user failed in reg_init\n");
1251                 kfree(reg);
1252                 return NULL;
1253         }
1254
1255 #if defined(CONFIG_VCODEC_MMU)
1256         if (data->mmu_dev &&
1257             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1258                 vpu_err("error: translate reg address failed\n");
1259                 kfree(reg);
1260                 return NULL;
1261         }
1262 #endif
1263
1264         mutex_lock(&pservice->lock);
1265         list_add_tail(&reg->status_link, &pservice->waiting);
1266         list_add_tail(&reg->session_link, &session->waiting);
1267         mutex_unlock(&pservice->lock);
1268
1269         if (pservice->auto_freq) {
1270                 if (!soc_is_rk2928g()) {
1271                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1272                                 if (reg_check_rmvb_wmv(reg)) {
1273                                         reg->freq = VPU_FREQ_200M;
1274                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1275                                         if (reg_probe_width(reg) > 3200) {
1276                                                 /*raise frequency for 4k avc.*/
1277                                                 reg->freq = VPU_FREQ_600M;
1278                                         }
1279                                 } else {
1280                                         if (reg_check_interlace(reg)) {
1281                                                 reg->freq = VPU_FREQ_400M;
1282                                         }
1283                                 }
1284                         }
1285                         if (reg->type == VPU_PP) {
1286                                 reg->freq = VPU_FREQ_400M;
1287                         }
1288                 }
1289         }
1290         vpu_debug_leave();
1291         return reg;
1292 }
1293
1294 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1295 {
1296         struct vpu_service_info *pservice = data->pservice;
1297 #if defined(CONFIG_VCODEC_MMU)
1298         struct vcodec_mem_region *mem_region = NULL, *n;
1299 #endif
1300
1301         list_del_init(&reg->session_link);
1302         list_del_init(&reg->status_link);
1303         if (reg == pservice->reg_codec)
1304                 pservice->reg_codec = NULL;
1305         if (reg == pservice->reg_pproc)
1306                 pservice->reg_pproc = NULL;
1307
1308 #if defined(CONFIG_VCODEC_MMU)
1309         /* release memory region attach to this registers table. */
1310         if (data->mmu_dev) {
1311                 list_for_each_entry_safe(mem_region, n,
1312                         &reg->mem_region_list, reg_lnk) {
1313                         /* do not unmap iommu manually,
1314                            unmap will proccess when memory release */
1315                         /*vcodec_enter_mode(data);
1316                         ion_unmap_iommu(data->dev,
1317                                         pservice->ion_client,
1318                                         mem_region->hdl);
1319                         vcodec_exit_mode();*/
1320                         ion_free(pservice->ion_client, mem_region->hdl);
1321                         list_del_init(&mem_region->reg_lnk);
1322                         kfree(mem_region);
1323                 }
1324         }
1325 #endif
1326
1327         kfree(reg);
1328 }
1329
1330 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1331 {
1332         vpu_debug_enter();
1333         list_del_init(&reg->status_link);
1334         list_add_tail(&reg->status_link, &pservice->running);
1335
1336         list_del_init(&reg->session_link);
1337         list_add_tail(&reg->session_link, &reg->session->running);
1338         vpu_debug_leave();
1339 }
1340
1341 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1342 {
1343         int i;
1344         u32 *dst = (u32 *)&reg->reg[0];
1345         vpu_debug_enter();
1346         for (i = 0; i < count; i++)
1347                 *dst++ = *src++;
1348         vpu_debug_leave();
1349 }
1350
1351 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1352         vpu_reg *reg)
1353 {
1354         struct vpu_service_info *pservice = data->pservice;
1355         int irq_reg = -1;
1356
1357         vpu_debug_enter();
1358
1359         list_del_init(&reg->status_link);
1360         list_add_tail(&reg->status_link, &pservice->done);
1361
1362         list_del_init(&reg->session_link);
1363         list_add_tail(&reg->session_link, &reg->session->done);
1364
1365         /*vcodec_enter_mode(data);*/
1366         switch (reg->type) {
1367         case VPU_ENC : {
1368                 pservice->reg_codec = NULL;
1369                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1370                 irq_reg = ENC_INTERRUPT_REGISTER;
1371                 break;
1372         }
1373         case VPU_DEC : {
1374                 int reg_len = REG_NUM_9190_DEC;
1375                 pservice->reg_codec = NULL;
1376                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1377 #if defined(CONFIG_VCODEC_MMU)
1378                 /* revert hack for decoded length */
1379                 if (data->hw_info->hw_id != HEVC_ID) {
1380                         u32 dec_get = reg->reg[12];
1381                         s32 dec_length = dec_get - reg->dec_base;
1382                         vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1383                         reg->reg[12] = dec_length << 10;
1384                 }
1385 #endif
1386                 irq_reg = DEC_INTERRUPT_REGISTER;
1387                 break;
1388         }
1389         case VPU_PP : {
1390                 pservice->reg_pproc = NULL;
1391                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1392                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1393                 break;
1394         }
1395         case VPU_DEC_PP : {
1396                 pservice->reg_codec = NULL;
1397                 pservice->reg_pproc = NULL;
1398                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1399                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1400 #if defined(CONFIG_VCODEC_MMU)
1401                 /* revert hack for decoded length */
1402                 if (data->hw_info->hw_id != HEVC_ID) {
1403                         u32 dec_get = reg->reg[12];
1404                         s32 dec_length = dec_get - reg->dec_base;
1405                         vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1406                         reg->reg[12] = dec_length << 10;
1407                 }
1408 #endif
1409                 break;
1410         }
1411         default : {
1412                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1413                 break;
1414         }
1415         }
1416         vcodec_exit_mode(data);
1417
1418         if (irq_reg != -1)
1419                 reg->reg[irq_reg] = pservice->irq_status;
1420
1421         atomic_sub(1, &reg->session->task_running);
1422         atomic_sub(1, &pservice->total_running);
1423         wake_up(&reg->session->wait);
1424
1425         vpu_debug_leave();
1426 }
1427
1428 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1429 {
1430         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1431         if (curr == reg->freq)
1432                 return;
1433         atomic_set(&pservice->freq_status, reg->freq);
1434         switch (reg->freq) {
1435         case VPU_FREQ_200M : {
1436                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1437         } break;
1438         case VPU_FREQ_266M : {
1439                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1440         } break;
1441         case VPU_FREQ_300M : {
1442                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1443         } break;
1444         case VPU_FREQ_400M : {
1445                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1446         } break;
1447         case VPU_FREQ_500M : {
1448                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1449         } break;
1450         case VPU_FREQ_600M : {
1451                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1452         } break;
1453         default : {
1454                 if (soc_is_rk2928g())
1455                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1456                 else
1457                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1458         } break;
1459         }
1460 }
1461
1462 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1463 {
1464         struct vpu_service_info *pservice = data->pservice;
1465         int i;
1466         u32 *src = (u32 *)&reg->reg[0];
1467         vpu_debug_enter();
1468
1469         atomic_add(1, &pservice->total_running);
1470         atomic_add(1, &reg->session->task_running);
1471         if (pservice->auto_freq)
1472                 vpu_service_set_freq(pservice, reg);
1473
1474         vcodec_enter_mode(data);
1475
1476         switch (reg->type) {
1477         case VPU_ENC : {
1478                 int enc_count = data->hw_info->enc_reg_num;
1479                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1480
1481                 pservice->reg_codec = reg;
1482
1483                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1484
1485                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1486                         dst[i] = src[i];
1487
1488                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1489                         dst[i] = src[i];
1490
1491                 VEPU_CLEAN_CACHE(dst);
1492
1493                 dsb(sy);
1494
1495                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1496                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1497
1498                 time_record(&tasks[TASK_VPU_ENC], 0);
1499         } break;
1500         case VPU_DEC : {
1501                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1502
1503                 pservice->reg_codec = reg;
1504
1505                 if (data->hw_info->hw_id != HEVC_ID) {
1506                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1507                                 dst[i] = src[i];
1508                         VDPU_CLEAN_CACHE(dst);
1509                 } else {
1510                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1511                                 dst[i] = src[i];
1512                         HEVC_CLEAN_CACHE(dst);
1513                 }
1514
1515                 dsb(sy);
1516
1517                 if (data->hw_info->hw_id != HEVC_ID) {
1518                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1519                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1520                 } else {
1521                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1522                 }
1523                 dsb(sy);
1524                 dmb(sy);
1525
1526                 time_record(&tasks[TASK_VPU_DEC], 0);
1527         } break;
1528         case VPU_PP : {
1529                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1530                 pservice->reg_pproc = reg;
1531
1532                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1533
1534                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1535                         dst[i] = src[i];
1536
1537                 dsb(sy);
1538
1539                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1540
1541                 time_record(&tasks[TASK_VPU_PP], 0);
1542         } break;
1543         case VPU_DEC_PP : {
1544                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1545                 pservice->reg_codec = reg;
1546                 pservice->reg_pproc = reg;
1547
1548                 VDPU_SOFT_RESET(dst);
1549                 VDPU_CLEAN_CACHE(dst);
1550
1551                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1552                         dst[i] = src[i];
1553
1554                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1555                 dsb(sy);
1556
1557                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1558                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1559                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1560
1561                 time_record(&tasks[TASK_VPU_DEC], 0);
1562         } break;
1563         default : {
1564                 vpu_err("error: unsupport session type %d", reg->type);
1565                 atomic_sub(1, &pservice->total_running);
1566                 atomic_sub(1, &reg->session->task_running);
1567         } break;
1568         }
1569
1570         /*vcodec_exit_mode(data);*/
1571         vpu_debug_leave();
1572 }
1573
1574 static void try_set_reg(struct vpu_subdev_data *data)
1575 {
1576         struct vpu_service_info *pservice = data->pservice;
1577         vpu_debug_enter();
1578         if (!list_empty(&pservice->waiting)) {
1579                 int can_set = 0;
1580                 bool change_able = (NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc);
1581                 int reset_request = atomic_read(&pservice->reset_request);
1582                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1583
1584                 vpu_service_power_on(pservice);
1585
1586                 // first check can_set flag
1587                 if (change_able || !reset_request) {
1588                         switch (reg->type) {
1589                         case VPU_ENC : {
1590                                 if (change_able)
1591                                         can_set = 1;
1592                         } break;
1593                         case VPU_DEC : {
1594                                 if (NULL == pservice->reg_codec)
1595                                         can_set = 1;
1596                                 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1597                                         can_set = 0;
1598                         } break;
1599                         case VPU_PP : {
1600                                 if (NULL == pservice->reg_codec) {
1601                                         if (NULL == pservice->reg_pproc)
1602                                                 can_set = 1;
1603                                 } else {
1604                                         if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1605                                                 can_set = 1;
1606                                         /* can not charge frequency when vpu is working */
1607                                         if (pservice->auto_freq)
1608                                                 can_set = 0;
1609                                 }
1610                         } break;
1611                         case VPU_DEC_PP : {
1612                                 if (change_able)
1613                                         can_set = 1;
1614                                 } break;
1615                         default : {
1616                                 printk("undefined reg type %d\n", reg->type);
1617                         } break;
1618                         }
1619                 }
1620
1621                 // then check reset request
1622                 if (reset_request && !change_able)
1623                         reset_request = 0;
1624
1625                 // do reset before setting registers
1626                 if (reset_request)
1627                         vpu_reset(data);
1628
1629                 if (can_set) {
1630                         reg_from_wait_to_run(pservice, reg);
1631                         reg_copy_to_hw(reg->data, reg);
1632                 }
1633         }
1634         vpu_debug_leave();
1635 }
1636
1637 static int return_reg(struct vpu_subdev_data *data,
1638         vpu_reg *reg, u32 __user *dst)
1639 {
1640         int ret = 0;
1641         vpu_debug_enter();
1642         switch (reg->type) {
1643         case VPU_ENC : {
1644                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1645                         ret = -EFAULT;
1646                 break;
1647         }
1648         case VPU_DEC : {
1649                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1650                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1651                         ret = -EFAULT;
1652                 break;
1653         }
1654         case VPU_PP : {
1655                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1656                         ret = -EFAULT;
1657                 break;
1658         }
1659         case VPU_DEC_PP : {
1660                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1661                         ret = -EFAULT;
1662                 break;
1663         }
1664         default : {
1665                 ret = -EFAULT;
1666                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1667                 break;
1668         }
1669         }
1670         reg_deinit(data, reg);
1671         vpu_debug_leave();
1672         return ret;
1673 }
1674
1675 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1676         unsigned long arg)
1677 {
1678         struct vpu_subdev_data *data =
1679                 container_of(filp->f_dentry->d_inode->i_cdev,
1680                         struct vpu_subdev_data, cdev);
1681         struct vpu_service_info *pservice = data->pservice;
1682         vpu_session *session = (vpu_session *)filp->private_data;
1683         vpu_debug_enter();
1684         if (NULL == session)
1685                 return -EINVAL;
1686
1687         switch (cmd) {
1688         case VPU_IOC_SET_CLIENT_TYPE : {
1689                 session->type = (enum VPU_CLIENT_TYPE)arg;
1690                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1691                 break;
1692         }
1693         case VPU_IOC_GET_HW_FUSE_STATUS : {
1694                 struct vpu_request req;
1695                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1696                 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1697                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1698                         return -EFAULT;
1699                 } else {
1700                         if (VPU_ENC != session->type) {
1701                                 if (copy_to_user((void __user *)req.req,
1702                                         &pservice->dec_config,
1703                                         sizeof(struct vpu_dec_config))) {
1704                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1705                                                 session->type);
1706                                         return -EFAULT;
1707                                 }
1708                         } else {
1709                                 if (copy_to_user((void __user *)req.req,
1710                                         &pservice->enc_config,
1711                                         sizeof(struct vpu_enc_config ))) {
1712                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1713                                                 session->type);
1714                                         return -EFAULT;
1715                                 }
1716                         }
1717                 }
1718
1719                 break;
1720         }
1721         case VPU_IOC_SET_REG : {
1722                 struct vpu_request req;
1723                 vpu_reg *reg;
1724                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1725                 if (copy_from_user(&req, (void __user *)arg,
1726                         sizeof(struct vpu_request))) {
1727                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1728                         return -EFAULT;
1729                 }
1730                 reg = reg_init(data, session,
1731                         (void __user *)req.req, req.size);
1732                 if (NULL == reg) {
1733                         return -EFAULT;
1734                 } else {
1735                         mutex_lock(&pservice->lock);
1736                         try_set_reg(data);
1737                         mutex_unlock(&pservice->lock);
1738                 }
1739
1740                 break;
1741         }
1742         case VPU_IOC_GET_REG : {
1743                 struct vpu_request req;
1744                 vpu_reg *reg;
1745                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1746                 if (copy_from_user(&req, (void __user *)arg,
1747                         sizeof(struct vpu_request))) {
1748                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1749                         return -EFAULT;
1750                 } else {
1751                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1752                         if (!list_empty(&session->done)) {
1753                                 if (ret < 0) {
1754                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1755                                 }
1756                                 ret = 0;
1757                         } else {
1758                                 if (unlikely(ret < 0)) {
1759                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1760                                 } else if (0 == ret) {
1761                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1762                                         ret = -ETIMEDOUT;
1763                                 }
1764                         }
1765                         if (ret < 0) {
1766                                 int task_running = atomic_read(&session->task_running);
1767                                 mutex_lock(&pservice->lock);
1768                                 vpu_service_dump(pservice);
1769                                 if (task_running) {
1770                                         atomic_set(&session->task_running, 0);
1771                                         atomic_sub(task_running, &pservice->total_running);
1772                                         printk("%d task is running but not return, reset hardware...", task_running);
1773                                         vpu_reset(data);
1774                                         printk("done\n");
1775                                 }
1776                                 vpu_service_session_clear(data, session);
1777                                 mutex_unlock(&pservice->lock);
1778                                 return ret;
1779                         }
1780                 }
1781                 mutex_lock(&pservice->lock);
1782                 reg = list_entry(session->done.next, vpu_reg, session_link);
1783                 return_reg(data, reg, (u32 __user *)req.req);
1784                 mutex_unlock(&pservice->lock);
1785                 break;
1786         }
1787         case VPU_IOC_PROBE_IOMMU_STATUS: {
1788                 int iommu_enable = 0;
1789
1790                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1791
1792 #if defined(CONFIG_VCODEC_MMU)
1793                 iommu_enable = data->mmu_dev ? 1 : 0;
1794 #endif
1795
1796                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1797                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1798                         return -EFAULT;
1799                 }
1800                 break;
1801         }
1802         default : {
1803                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1804                 break;
1805         }
1806         }
1807         vpu_debug_leave();
1808         return 0;
1809 }
1810
1811 #ifdef CONFIG_COMPAT
1812 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1813         unsigned long arg)
1814 {
1815         struct vpu_subdev_data *data =
1816                 container_of(filp->f_dentry->d_inode->i_cdev,
1817                         struct vpu_subdev_data, cdev);
1818         struct vpu_service_info *pservice = data->pservice;
1819         vpu_session *session = (vpu_session *)filp->private_data;
1820         vpu_debug_enter();
1821         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1822                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1823         if (NULL == session)
1824                 return -EINVAL;
1825
1826         switch (cmd) {
1827         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1828                 session->type = (enum VPU_CLIENT_TYPE)arg;
1829                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1830                 break;
1831         }
1832         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1833                 struct compat_vpu_request req;
1834                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1835                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1836                                    sizeof(struct compat_vpu_request))) {
1837                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1838                                 " copy_from_user failed\n");
1839                         return -EFAULT;
1840                 } else {
1841                         if (VPU_ENC != session->type) {
1842                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1843                                                  &pservice->dec_config,
1844                                                  sizeof(struct vpu_dec_config))) {
1845                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1846                                                 "copy_to_user failed type %d\n",
1847                                                 session->type);
1848                                         return -EFAULT;
1849                                 }
1850                         } else {
1851                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1852                                                  &pservice->enc_config,
1853                                                  sizeof(struct vpu_enc_config ))) {
1854                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1855                                                 " copy_to_user failed type %d\n",
1856                                                 session->type);
1857                                         return -EFAULT;
1858                                 }
1859                         }
1860                 }
1861
1862                 break;
1863         }
1864         case COMPAT_VPU_IOC_SET_REG : {
1865                 struct compat_vpu_request req;
1866                 vpu_reg *reg;
1867                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1868                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1869                                    sizeof(struct compat_vpu_request))) {
1870                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1871                         return -EFAULT;
1872                 }
1873                 reg = reg_init(data, session,
1874                                compat_ptr((compat_uptr_t)req.req), req.size);
1875                 if (NULL == reg) {
1876                         return -EFAULT;
1877                 } else {
1878                         mutex_lock(&pservice->lock);
1879                         try_set_reg(data);
1880                         mutex_unlock(&pservice->lock);
1881                 }
1882
1883                 break;
1884         }
1885         case COMPAT_VPU_IOC_GET_REG : {
1886                 struct compat_vpu_request req;
1887                 vpu_reg *reg;
1888                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1889                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1890                                    sizeof(struct compat_vpu_request))) {
1891                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1892                         return -EFAULT;
1893                 } else {
1894                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1895                         if (!list_empty(&session->done)) {
1896                                 if (ret < 0) {
1897                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1898                                 }
1899                                 ret = 0;
1900                         } else {
1901                                 if (unlikely(ret < 0)) {
1902                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1903                                 } else if (0 == ret) {
1904                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1905                                         ret = -ETIMEDOUT;
1906                                 }
1907                         }
1908                         if (ret < 0) {
1909                                 int task_running = atomic_read(&session->task_running);
1910                                 mutex_lock(&pservice->lock);
1911                                 vpu_service_dump(pservice);
1912                                 if (task_running) {
1913                                         atomic_set(&session->task_running, 0);
1914                                         atomic_sub(task_running, &pservice->total_running);
1915                                         printk("%d task is running but not return, reset hardware...", task_running);
1916                                         vpu_reset(data);
1917                                         printk("done\n");
1918                                 }
1919                                 vpu_service_session_clear(data, session);
1920                                 mutex_unlock(&pservice->lock);
1921                                 return ret;
1922                         }
1923                 }
1924                 mutex_lock(&pservice->lock);
1925                 reg = list_entry(session->done.next, vpu_reg, session_link);
1926                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1927                 mutex_unlock(&pservice->lock);
1928                 break;
1929         }
1930         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1931                 int iommu_enable = 0;
1932
1933                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1934 #if defined(CONFIG_VCODEC_MMU)
1935                 iommu_enable = data->mmu_dev ? 1 : 0;
1936 #endif
1937
1938                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1939                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1940                         return -EFAULT;
1941                 }
1942                 break;
1943         }
1944         default : {
1945                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1946                 break;
1947         }
1948         }
1949         vpu_debug_leave();
1950         return 0;
1951 }
1952 #endif
1953
1954 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1955 {
1956         int ret = -EINVAL, i = 0;
1957         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1958         u32 enc_id = *tmp;
1959
1960         enc_id = (enc_id >> 16) & 0xFFFF;
1961         pr_info("checking hw id %x\n", enc_id);
1962         data->hw_info = NULL;
1963         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1964                 if (enc_id == vpu_hw_set[i].hw_id) {
1965                         data->hw_info = &vpu_hw_set[i];
1966                         ret = 0;
1967                         break;
1968                 }
1969         }
1970         iounmap((void *)tmp);
1971         return ret;
1972 }
1973
1974 static int vpu_service_open(struct inode *inode, struct file *filp)
1975 {
1976         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1977         struct vpu_service_info *pservice = data->pservice;
1978         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1979
1980         vpu_debug_enter();
1981
1982         if (NULL == session) {
1983                 vpu_err("error: unable to allocate memory for vpu_session.");
1984                 return -ENOMEM;
1985         }
1986
1987         session->type   = VPU_TYPE_BUTT;
1988         session->pid    = current->pid;
1989         INIT_LIST_HEAD(&session->waiting);
1990         INIT_LIST_HEAD(&session->running);
1991         INIT_LIST_HEAD(&session->done);
1992         INIT_LIST_HEAD(&session->list_session);
1993         init_waitqueue_head(&session->wait);
1994         atomic_set(&session->task_running, 0);
1995         mutex_lock(&pservice->lock);
1996         list_add_tail(&session->list_session, &pservice->session);
1997         filp->private_data = (void *)session;
1998         mutex_unlock(&pservice->lock);
1999
2000         pr_debug("dev opened\n");
2001         vpu_debug_leave();
2002         return nonseekable_open(inode, filp);
2003 }
2004
2005 static int vpu_service_release(struct inode *inode, struct file *filp)
2006 {
2007         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
2008         struct vpu_service_info *pservice = data->pservice;
2009         int task_running;
2010         vpu_session *session = (vpu_session *)filp->private_data;
2011         vpu_debug_enter();
2012         if (NULL == session)
2013                 return -EINVAL;
2014
2015         task_running = atomic_read(&session->task_running);
2016         if (task_running) {
2017                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
2018                 msleep(50);
2019         }
2020         wake_up(&session->wait);
2021
2022         mutex_lock(&pservice->lock);
2023         /* remove this filp from the asynchronusly notified filp's */
2024         list_del_init(&session->list_session);
2025         vpu_service_session_clear(data, session);
2026         kfree(session);
2027         filp->private_data = NULL;
2028         mutex_unlock(&pservice->lock);
2029
2030         pr_debug("dev closed\n");
2031         vpu_debug_leave();
2032         return 0;
2033 }
2034
2035 static const struct file_operations vpu_service_fops = {
2036         .unlocked_ioctl = vpu_service_ioctl,
2037         .open           = vpu_service_open,
2038         .release        = vpu_service_release,
2039 #ifdef CONFIG_COMPAT
2040         .compat_ioctl   = compat_vpu_service_ioctl,
2041 #endif
2042 };
2043
2044 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2045 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2046 static irqreturn_t vepu_irq(int irq, void *dev_id);
2047 static irqreturn_t vepu_isr(int irq, void *dev_id);
2048 static void get_hw_info(struct vpu_subdev_data *data);
2049
2050 #ifdef CONFIG_VCODEC_MMU
2051 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2052 {
2053         struct device_node *dn = NULL;
2054         struct platform_device *pd = NULL;
2055         struct device *ret = NULL ;
2056
2057         dn = of_find_compatible_node(NULL,NULL,compt);
2058         if(!dn) {
2059                 printk("can't find device node %s \r\n",compt);
2060                 return NULL;
2061         }
2062
2063         pd = of_find_device_by_node(dn);
2064         if(!pd) {
2065                 printk("can't find platform device in device node %s\n",compt);
2066                 return  NULL;
2067         }
2068         ret = &pd->dev;
2069
2070         return ret;
2071
2072 }
2073 #ifdef CONFIG_IOMMU_API
2074 static inline void platform_set_sysmmu(struct device *iommu,
2075         struct device *dev)
2076 {
2077         dev->archdata.iommu = iommu;
2078 }
2079 #else
2080 static inline void platform_set_sysmmu(struct device *iommu,
2081         struct device *dev)
2082 {
2083 }
2084 #endif
2085
2086 int vcodec_sysmmu_fault_hdl(struct device *dev,
2087                                 enum rk_iommu_inttype itype,
2088                                 unsigned long pgtable_base,
2089                                 unsigned long fault_addr, unsigned int status)
2090 {
2091         struct platform_device *pdev;
2092         struct vpu_subdev_data *data;
2093         struct vpu_service_info *pservice;
2094
2095         vpu_debug_enter();
2096
2097         pdev = container_of(dev, struct platform_device, dev);
2098
2099         data = platform_get_drvdata(pdev);
2100         pservice = data->pservice;
2101
2102         if (pservice->reg_codec) {
2103                 struct vcodec_mem_region *mem, *n;
2104                 int i = 0;
2105                 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
2106                 list_for_each_entry_safe(mem, n,
2107                                          &pservice->reg_codec->mem_region_list,
2108                                          reg_lnk) {
2109                         vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
2110                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
2111                         i++;
2112                 }
2113
2114                 pr_alert("vcodec, page fault occur, reset hw\n");
2115                 pservice->reg_codec->reg[101] = 1;
2116                 vpu_reset(data);
2117         }
2118
2119         return 0;
2120 }
2121 #endif
2122
2123 #if HEVC_TEST_ENABLE
2124 static int hevc_test_case0(vpu_service_info *pservice);
2125 #endif
2126 #if defined(CONFIG_ION_ROCKCHIP)
2127 extern struct ion_client *rockchip_ion_client_create(const char * name);
2128 #endif
2129
2130 static int vcodec_subdev_probe(struct platform_device *pdev,
2131         struct vpu_service_info *pservice)
2132 {
2133         int ret = 0;
2134         struct resource *res = NULL;
2135         u32 ioaddr = 0;
2136         struct device *dev = &pdev->dev;
2137         char *name = (char*)dev_name(dev);
2138         struct device_node *np = pdev->dev.of_node;
2139         struct vpu_subdev_data *data =
2140                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2141 #if defined(CONFIG_VCODEC_MMU)
2142         u32 iommu_en = 0;
2143         char mmu_dev_dts_name[40];
2144         of_property_read_u32(np, "iommu_enabled", &iommu_en);
2145 #endif
2146         pr_info("probe device %s\n", dev_name(dev));
2147
2148         data->pservice = pservice;
2149         data->dev = dev;
2150
2151         of_property_read_string(np, "name", (const char**)&name);
2152         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2153         /*dev_set_name(dev, name);*/
2154
2155         if (pservice->reg_base == 0) {
2156                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2157                 data->regs = devm_ioremap_resource(dev, res);
2158                 if (IS_ERR(data->regs)) {
2159                         ret = PTR_ERR(data->regs);
2160                         goto err;
2161                 }
2162                 ioaddr = res->start;
2163         } else {
2164                 data->regs = pservice->reg_base;
2165                 ioaddr = pservice->ioaddr;
2166         }
2167
2168         clear_bit(MMU_ACTIVATED, &data->state);
2169         vcodec_enter_mode(data);
2170         ret = vpu_service_check_hw(data, ioaddr);
2171         if (ret < 0) {
2172                 vpu_err("error: hw info check faild\n");
2173                 goto err;
2174         }
2175
2176         data->dec_dev.iosize = data->hw_info->dec_io_size;
2177         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2178         data->reg_size = data->dec_dev.iosize;
2179
2180         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2181                 data->enc_dev.iosize = data->hw_info->enc_io_size;
2182                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2183                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2184         }
2185
2186         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2187         if (data->irq_enc > 0) {
2188                 ret = devm_request_threaded_irq(dev,
2189                         data->irq_enc, vepu_irq, vepu_isr,
2190                         IRQF_SHARED, dev_name(dev),
2191                         (void *)data);
2192                 if (ret) {
2193                         dev_err(dev,
2194                                 "error: can't request vepu irq %d\n",
2195                                 data->irq_enc);
2196                         goto err;
2197                 }
2198         }
2199         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2200         if (data->irq_dec > 0) {
2201                 ret = devm_request_threaded_irq(dev,
2202                         data->irq_dec, vdpu_irq, vdpu_isr,
2203                         IRQF_SHARED, dev_name(dev),
2204                         (void *)data);
2205                 if (ret) {
2206                         dev_err(dev,
2207                                 "error: can't request vdpu irq %d\n",
2208                                 data->irq_dec);
2209                         goto err;
2210                 }
2211         }
2212         atomic_set(&data->dec_dev.irq_count_codec, 0);
2213         atomic_set(&data->dec_dev.irq_count_pp, 0);
2214         atomic_set(&data->enc_dev.irq_count_codec, 0);
2215         atomic_set(&data->enc_dev.irq_count_pp, 0);
2216 #if defined(CONFIG_VCODEC_MMU)
2217         if (iommu_en) {
2218                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2219                         sprintf(mmu_dev_dts_name,
2220                                 HEVC_IOMMU_COMPATIBLE_NAME);
2221                 else
2222                         sprintf(mmu_dev_dts_name,
2223                                 VPU_IOMMU_COMPATIBLE_NAME);
2224
2225                 data->mmu_dev =
2226                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2227
2228                 if (data->mmu_dev)
2229                         platform_set_sysmmu(data->mmu_dev, dev);
2230
2231                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2232         }
2233 #endif
2234         get_hw_info(data);
2235         pservice->auto_freq = true;
2236
2237         vcodec_exit_mode(data);
2238         /* create device node */
2239         ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2240         if (ret) {
2241                 dev_err(dev, "alloc dev_t failed\n");
2242                 goto err;
2243         }
2244
2245         cdev_init(&data->cdev, &vpu_service_fops);
2246
2247         data->cdev.owner = THIS_MODULE;
2248         data->cdev.ops = &vpu_service_fops;
2249
2250         ret = cdev_add(&data->cdev, data->dev_t, 1);
2251
2252         if (ret) {
2253                 dev_err(dev, "add dev_t failed\n");
2254                 goto err;
2255         }
2256
2257         data->cls = class_create(THIS_MODULE, name);
2258
2259         if (IS_ERR(data->cls)) {
2260                 ret = PTR_ERR(data->cls);
2261                 dev_err(dev, "class_create err:%d\n", ret);
2262                 goto err;
2263         }
2264
2265         data->child_dev = device_create(data->cls, dev,
2266                 data->dev_t, NULL, name);
2267
2268         platform_set_drvdata(pdev, data);
2269
2270         INIT_LIST_HEAD(&data->lnk_service);
2271         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2272
2273 #ifdef CONFIG_DEBUG_FS
2274         data->debugfs_dir =
2275                 vcodec_debugfs_create_device_dir((char*)name, parent);
2276         if (data->debugfs_dir == NULL)
2277                 vpu_err("create debugfs dir %s failed\n", name);
2278
2279         data->debugfs_file_regs =
2280                 debugfs_create_file("regs", 0664,
2281                                     data->debugfs_dir, data,
2282                                     &debug_vcodec_fops);
2283 #endif
2284         return 0;
2285 err:
2286         if (data->irq_enc > 0)
2287                 free_irq(data->irq_enc, (void *)data);
2288         if (data->irq_dec > 0)
2289                 free_irq(data->irq_dec, (void *)data);
2290
2291         if (data->child_dev) {
2292                 device_destroy(data->cls, data->dev_t);
2293                 cdev_del(&data->cdev);
2294                 unregister_chrdev_region(data->dev_t, 1);
2295         }
2296
2297         if (data->cls)
2298                 class_destroy(data->cls);
2299         return -1;
2300 }
2301
2302 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2303 {
2304         device_destroy(data->cls, data->dev_t);
2305         class_destroy(data->cls);
2306         cdev_del(&data->cdev);
2307         unregister_chrdev_region(data->dev_t, 1);
2308
2309         free_irq(data->irq_enc, (void *)&data);
2310         free_irq(data->irq_dec, (void *)&data);
2311
2312 #ifdef CONFIG_DEBUG_FS
2313         debugfs_remove_recursive(data->debugfs_dir);
2314 #endif
2315 }
2316
2317 static void vcodec_read_property(struct device_node *np,
2318         struct vpu_service_info *pservice)
2319 {
2320         pservice->mode_bit = 0;
2321         pservice->mode_ctrl = 0;
2322         pservice->subcnt = 0;
2323
2324         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2325
2326         if (pservice->subcnt > 1) {
2327                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2328                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2329         }
2330 #ifdef CONFIG_MFD_SYSCON
2331         pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2332 #else
2333         pservice->grf_base = (u32*)RK_GRF_VIRT;
2334 #endif
2335         if (IS_ERR(pservice->grf_base)) {
2336 #ifdef CONFIG_ARM
2337                 pservice->grf_base = RK_GRF_VIRT;
2338 #else
2339                 vpu_err("can't find vpu grf property\n");
2340                 return;
2341 #endif
2342         }
2343
2344 #ifdef CONFIG_RESET_CONTROLLER
2345         pservice->rst_a = devm_reset_control_get(pservice->dev, "video_a");
2346         pservice->rst_h = devm_reset_control_get(pservice->dev, "video_h");
2347         pservice->rst_v = devm_reset_control_get(pservice->dev, "video");
2348
2349         if (IS_ERR_OR_NULL(pservice->rst_a)) {
2350                 pr_warn("No reset resource define\n");
2351                 pservice->rst_a = NULL;
2352         }
2353
2354         if (IS_ERR_OR_NULL(pservice->rst_h)) {
2355                 pr_warn("No reset resource define\n");
2356                 pservice->rst_h = NULL;
2357         }
2358
2359         if (IS_ERR_OR_NULL(pservice->rst_v)) {
2360                 pr_warn("No reset resource define\n");
2361                 pservice->rst_v = NULL;
2362         }
2363 #endif
2364
2365         of_property_read_string(np, "name", (const char**)&pservice->name);
2366 }
2367
2368 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2369 {
2370         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2371         pservice->curr_mode = -1;
2372
2373         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2374         INIT_LIST_HEAD(&pservice->waiting);
2375         INIT_LIST_HEAD(&pservice->running);
2376         mutex_init(&pservice->lock);
2377
2378         INIT_LIST_HEAD(&pservice->done);
2379         INIT_LIST_HEAD(&pservice->session);
2380         INIT_LIST_HEAD(&pservice->subdev_list);
2381
2382         pservice->reg_pproc     = NULL;
2383         atomic_set(&pservice->total_running, 0);
2384         atomic_set(&pservice->enabled,       0);
2385         atomic_set(&pservice->power_on_cnt,  0);
2386         atomic_set(&pservice->power_off_cnt, 0);
2387         atomic_set(&pservice->reset_request, 0);
2388
2389         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2390
2391         pservice->ion_client = rockchip_ion_client_create("vpu");
2392         if (IS_ERR(pservice->ion_client)) {
2393                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2394                         PTR_ERR(pservice->ion_client));
2395         } else {
2396                 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2397         }
2398 }
2399
2400 static int vcodec_probe(struct platform_device *pdev)
2401 {
2402         int i;
2403         int ret = 0;
2404         struct resource *res = NULL;
2405         struct device *dev = &pdev->dev;
2406         struct device_node *np = pdev->dev.of_node;
2407         struct vpu_service_info *pservice =
2408                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2409
2410         pr_info("probe device %s\n", dev_name(dev));
2411
2412         pservice->dev = dev;
2413
2414         vcodec_read_property(np, pservice);
2415         vcodec_init_drvdata(pservice);
2416
2417         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2418                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2419         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2420                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2421         else
2422                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2423
2424         if (0 > vpu_get_clk(pservice))
2425                 goto err;
2426
2427         vpu_service_power_on(pservice);
2428
2429         if (of_property_read_bool(np, "reg")) {
2430                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2431
2432                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2433                 if (IS_ERR(pservice->reg_base)) {
2434                         vpu_err("ioremap registers base failed\n");
2435                         ret = PTR_ERR(pservice->reg_base);
2436                         goto err;
2437                 }
2438                 pservice->ioaddr = res->start;
2439         } else {
2440                 pservice->reg_base = 0;
2441         }
2442
2443         if (of_property_read_bool(np, "subcnt")) {
2444                 for (i = 0; i<pservice->subcnt; i++) {
2445                         struct device_node *sub_np;
2446                         struct platform_device *sub_pdev;
2447                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2448                         sub_pdev = of_find_device_by_node(sub_np);
2449
2450                         vcodec_subdev_probe(sub_pdev, pservice);
2451                 }
2452         } else {
2453                 vcodec_subdev_probe(pdev, pservice);
2454         }
2455         platform_set_drvdata(pdev, pservice);
2456
2457         vpu_service_power_off(pservice);
2458
2459         pr_info("init success\n");
2460
2461         return 0;
2462
2463 err:
2464         pr_info("init failed\n");
2465         vpu_service_power_off(pservice);
2466         vpu_put_clk(pservice);
2467         wake_lock_destroy(&pservice->wake_lock);
2468
2469         if (res)
2470                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2471
2472         return ret;
2473 }
2474
2475 static int vcodec_remove(struct platform_device *pdev)
2476 {
2477         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2478         struct resource *res;
2479         struct vpu_subdev_data *data, *n;
2480
2481         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2482                 vcodec_subdev_remove(data);
2483         }
2484
2485         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2486         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2487         vpu_put_clk(pservice);
2488         wake_lock_destroy(&pservice->wake_lock);
2489
2490         return 0;
2491 }
2492
2493 #if defined(CONFIG_OF)
2494 static const struct of_device_id vcodec_service_dt_ids[] = {
2495         {.compatible = "vpu_service",},
2496         {.compatible = "rockchip,hevc_service",},
2497         {.compatible = "rockchip,vpu_combo",},
2498         {},
2499 };
2500 #endif
2501
2502 static struct platform_driver vcodec_driver = {
2503         .probe = vcodec_probe,
2504         .remove = vcodec_remove,
2505         .driver = {
2506                 .name = "vcodec",
2507                 .owner = THIS_MODULE,
2508 #if defined(CONFIG_OF)
2509                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2510 #endif
2511         },
2512 };
2513
2514 static void get_hw_info(struct vpu_subdev_data *data)
2515 {
2516         struct vpu_service_info *pservice = data->pservice;
2517         struct vpu_dec_config *dec = &pservice->dec_config;
2518         struct vpu_enc_config *enc = &pservice->enc_config;
2519         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2520                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2521                 u32 asicID      = data->dec_dev.hwregs[0];
2522
2523                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2524                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2525                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2526                         dec->jpegSupport = JPEG_PROGRESSIVE;
2527                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2528                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2529                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2530                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2531                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2532                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2533
2534                 dec->maxDecPicWidth = 4096;
2535
2536                 /* 2nd Config register */
2537                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2538                 if (dec->refBufSupport) {
2539                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2540                                 dec->refBufSupport |= 2;
2541                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2542                                 dec->refBufSupport |= 4;
2543                 }
2544                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2545                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2546                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2547                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2548
2549                 /* JPEG xtensions */
2550                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2551                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2552                 else
2553                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2554
2555                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2556                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2557                 else
2558                         dec->rvSupport = RV_NOT_SUPPORTED;
2559                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2560
2561                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2562                         dec->refBufSupport |= 8; /* enable HW support for offset */
2563
2564                 if (!cpu_is_rk3036()) {
2565                         configReg = data->enc_dev.hwregs[63];
2566                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2567                         enc->h264Enabled = (configReg >> 27) & 1;
2568                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2569                         enc->jpegEnabled = (configReg >> 25) & 1;
2570                         enc->vsEnabled = (configReg >> 24) & 1;
2571                         enc->rgbEnabled = (configReg >> 28) & 1;
2572                         enc->reg_size = data->reg_size;
2573                         enc->reserv[0] = enc->reserv[1] = 0;
2574                 }
2575                 pservice->auto_freq = true;
2576                 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2577                 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2578
2579                 pservice->bug_dec_addr = cpu_is_rk30xx();
2580         } else {
2581                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2582                         dec->maxDecPicWidth = 1920;
2583                 else
2584                         dec->maxDecPicWidth = 4096;
2585                 /* disable frequency switch in hevc.*/
2586                 pservice->auto_freq = false;
2587         }
2588 }
2589
2590 static bool check_irq_err(task_info *task, u32 irq_status)
2591 {
2592         return (task->error_mask & irq_status) ? true : false;
2593 }
2594
2595 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2596 {
2597         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2598         struct vpu_service_info *pservice = data->pservice;
2599         vpu_device *dev = &data->dec_dev;
2600         u32 raw_status;
2601         u32 dec_status;
2602
2603         /*vcodec_enter_mode(data);*/
2604
2605         dec_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2606
2607         if (dec_status & DEC_INTERRUPT_BIT) {
2608                 time_record(&tasks[TASK_VPU_DEC], 1);
2609                 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", dec_status);
2610                 if ((dec_status & 0x40001) == 0x40001) {
2611                         do {
2612                                 dec_status =
2613                                         readl(dev->hwregs +
2614                                                 DEC_INTERRUPT_REGISTER);
2615                         } while ((dec_status & 0x40001) == 0x40001);
2616                 }
2617
2618                 if (check_irq_err((data->hw_info->hw_id == HEVC_ID)?
2619                                         (&tasks[TASK_RKDEC_HEVC]) : (&tasks[TASK_VPU_DEC]),
2620                                         dec_status)) {
2621                         atomic_add(1, &pservice->reset_request);
2622                 }
2623
2624                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2625                 atomic_add(1, &dev->irq_count_codec);
2626                 time_diff(&tasks[TASK_VPU_DEC]);
2627         }
2628
2629         if (data->hw_info->hw_id != HEVC_ID) {
2630                 u32 pp_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2631                 if (pp_status & PP_INTERRUPT_BIT) {
2632                         time_record(&tasks[TASK_VPU_PP], 1);
2633                         vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", pp_status);
2634
2635                         if (check_irq_err(&tasks[TASK_VPU_PP], dec_status))
2636                                 atomic_add(1, &pservice->reset_request);
2637
2638                         /* clear pp IRQ */
2639                         writel(pp_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2640                         atomic_add(1, &dev->irq_count_pp);
2641                         time_diff(&tasks[TASK_VPU_PP]);
2642                 }
2643         }
2644
2645         pservice->irq_status = raw_status;
2646
2647         /*vcodec_exit_mode(pservice);*/
2648
2649         if (atomic_read(&dev->irq_count_pp) ||
2650             atomic_read(&dev->irq_count_codec))
2651                 return IRQ_WAKE_THREAD;
2652         else
2653                 return IRQ_NONE;
2654 }
2655
2656 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2657 {
2658         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2659         struct vpu_service_info *pservice = data->pservice;
2660         vpu_device *dev = &data->dec_dev;
2661
2662         mutex_lock(&pservice->lock);
2663         if (atomic_read(&dev->irq_count_codec)) {
2664                 atomic_sub(1, &dev->irq_count_codec);
2665                 if (NULL == pservice->reg_codec) {
2666                         vpu_err("error: dec isr with no task waiting\n");
2667                 } else {
2668                         reg_from_run_to_done(data, pservice->reg_codec);
2669                         /* avoid vpu timeout and can't recover problem */
2670                         VDPU_SOFT_RESET(data->regs);
2671                 }
2672         }
2673
2674         if (atomic_read(&dev->irq_count_pp)) {
2675                 atomic_sub(1, &dev->irq_count_pp);
2676                 if (NULL == pservice->reg_pproc) {
2677                         vpu_err("error: pp isr with no task waiting\n");
2678                 } else {
2679                         reg_from_run_to_done(data, pservice->reg_pproc);
2680                 }
2681         }
2682         try_set_reg(data);
2683         mutex_unlock(&pservice->lock);
2684         return IRQ_HANDLED;
2685 }
2686
2687 static irqreturn_t vepu_irq(int irq, void *dev_id)
2688 {
2689         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2690         struct vpu_service_info *pservice = data->pservice;
2691         vpu_device *dev = &data->enc_dev;
2692         u32 irq_status;
2693
2694         /*vcodec_enter_mode(data);*/
2695         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2696
2697         vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2698
2699         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2700                 time_record(&tasks[TASK_VPU_ENC], 1);
2701
2702                 if (check_irq_err(&tasks[TASK_VPU_ENC], irq_status))
2703                         atomic_add(1, &pservice->reset_request);
2704
2705                 /* clear enc IRQ */
2706                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2707                 atomic_add(1, &dev->irq_count_codec);
2708                 time_diff(&tasks[TASK_VPU_ENC]);
2709         }
2710
2711         pservice->irq_status = irq_status;
2712
2713         /*vcodec_exit_mode(pservice);*/
2714
2715         if (atomic_read(&dev->irq_count_codec))
2716                 return IRQ_WAKE_THREAD;
2717         else
2718                 return IRQ_NONE;
2719 }
2720
2721 static irqreturn_t vepu_isr(int irq, void *dev_id)
2722 {
2723         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2724         struct vpu_service_info *pservice = data->pservice;
2725         vpu_device *dev = &data->enc_dev;
2726
2727         mutex_lock(&pservice->lock);
2728         if (atomic_read(&dev->irq_count_codec)) {
2729                 atomic_sub(1, &dev->irq_count_codec);
2730                 if (NULL == pservice->reg_codec) {
2731                         vpu_err("error: enc isr with no task waiting\n");
2732                 } else {
2733                         reg_from_run_to_done(data, pservice->reg_codec);
2734                 }
2735         }
2736         try_set_reg(data);
2737         mutex_unlock(&pservice->lock);
2738         return IRQ_HANDLED;
2739 }
2740
2741 static int __init vcodec_service_init(void)
2742 {
2743         int ret;
2744
2745         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2746                 vpu_err("Platform device register failed (%d).\n", ret);
2747                 return ret;
2748         }
2749
2750 #ifdef CONFIG_DEBUG_FS
2751         vcodec_debugfs_init();
2752 #endif
2753
2754         return ret;
2755 }
2756
2757 static void __exit vcodec_service_exit(void)
2758 {
2759 #ifdef CONFIG_DEBUG_FS
2760         vcodec_debugfs_exit();
2761 #endif
2762
2763         platform_driver_unregister(&vcodec_driver);
2764 }
2765
2766 module_init(vcodec_service_init);
2767 module_exit(vcodec_service_exit);
2768
2769 #ifdef CONFIG_DEBUG_FS
2770 #include <linux/seq_file.h>
2771
2772 static int vcodec_debugfs_init()
2773 {
2774         parent = debugfs_create_dir("vcodec", NULL);
2775         if (!parent)
2776                 return -1;
2777
2778         return 0;
2779 }
2780
2781 static void vcodec_debugfs_exit()
2782 {
2783         debugfs_remove(parent);
2784 }
2785
2786 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2787 {
2788         return debugfs_create_dir(dirname, parent);
2789 }
2790
2791 static int debug_vcodec_show(struct seq_file *s, void *unused)
2792 {
2793         struct vpu_subdev_data *data = s->private;
2794         struct vpu_service_info *pservice = data->pservice;
2795         unsigned int i, n;
2796         vpu_reg *reg, *reg_tmp;
2797         vpu_session *session, *session_tmp;
2798
2799         mutex_lock(&pservice->lock);
2800         vpu_service_power_on(pservice);
2801         if (data->hw_info->hw_id != HEVC_ID) {
2802                 seq_printf(s, "\nENC Registers:\n");
2803                 n = data->enc_dev.iosize >> 2;
2804                 for (i = 0; i < n; i++)
2805                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2806         }
2807         seq_printf(s, "\nDEC Registers:\n");
2808         n = data->dec_dev.iosize >> 2;
2809         for (i = 0; i < n; i++)
2810                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2811
2812         seq_printf(s, "\nvpu service status:\n");
2813         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2814                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2815                 /*seq_printf(s, "waiting reg set %d\n");*/
2816                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2817                         seq_printf(s, "waiting register set\n");
2818                 }
2819                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2820                         seq_printf(s, "running register set\n");
2821                 }
2822                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2823                         seq_printf(s, "done    register set\n");
2824                 }
2825         }
2826
2827         seq_printf(s, "\npower counter: on %d off %d\n",
2828                         atomic_read(&pservice->power_on_cnt),
2829                         atomic_read(&pservice->power_off_cnt));
2830         mutex_unlock(&pservice->lock);
2831         vpu_service_power_off(pservice);
2832
2833         return 0;
2834 }
2835
2836 static int debug_vcodec_open(struct inode *inode, struct file *file)
2837 {
2838         return single_open(file, debug_vcodec_show, inode->i_private);
2839 }
2840
2841 #endif
2842
2843 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2844 #include "hevc_test_inc/pps_00.h"
2845 #include "hevc_test_inc/register_00.h"
2846 #include "hevc_test_inc/rps_00.h"
2847 #include "hevc_test_inc/scaling_list_00.h"
2848 #include "hevc_test_inc/stream_00.h"
2849
2850 #include "hevc_test_inc/pps_01.h"
2851 #include "hevc_test_inc/register_01.h"
2852 #include "hevc_test_inc/rps_01.h"
2853 #include "hevc_test_inc/scaling_list_01.h"
2854 #include "hevc_test_inc/stream_01.h"
2855
2856 #include "hevc_test_inc/cabac.h"
2857
2858 extern struct ion_client *rockchip_ion_client_create(const char * name);
2859
2860 static struct ion_client *ion_client = NULL;
2861 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2862 {
2863         int size = (len+15) & (~15);
2864         struct ion_handle *handle;
2865         u8 *ptr;
2866
2867         if (ion_client == NULL)
2868                 ion_client = rockchip_ion_client_create("vcodec");
2869
2870         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2871
2872         ptr = ion_map_kernel(ion_client, handle);
2873
2874         ion_phys(ion_client, handle, phy, &size);
2875
2876         memcpy(ptr, tbl, len);
2877
2878         return ptr;
2879 }
2880
2881 u8* get_align_ptr_no_copy(int len, u32 *phy)
2882 {
2883         int size = (len+15) & (~15);
2884         struct ion_handle *handle;
2885         u8 *ptr;
2886
2887         if (ion_client == NULL)
2888                 ion_client = rockchip_ion_client_create("vcodec");
2889
2890         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2891
2892         ptr = ion_map_kernel(ion_client, handle);
2893
2894         ion_phys(ion_client, handle, phy, &size);
2895
2896         return ptr;
2897 }
2898
2899 #define TEST_CNT    2
2900 static int hevc_test_case0(vpu_service_info *pservice)
2901 {
2902         vpu_session session;
2903         vpu_reg *reg;
2904         unsigned long size = 272;
2905         int testidx = 0;
2906         int ret = 0;
2907         u8 *pps_tbl[TEST_CNT];
2908         u8 *register_tbl[TEST_CNT];
2909         u8 *rps_tbl[TEST_CNT];
2910         u8 *scaling_list_tbl[TEST_CNT];
2911         u8 *stream_tbl[TEST_CNT];
2912
2913         int stream_size[2];
2914         int pps_size[2];
2915         int rps_size[2];
2916         int scl_size[2];
2917         int cabac_size[2];
2918
2919         u32 phy_pps;
2920         u32 phy_rps;
2921         u32 phy_scl;
2922         u32 phy_str;
2923         u32 phy_yuv;
2924         u32 phy_ref;
2925         u32 phy_cabac;
2926
2927         volatile u8 *stream_buf;
2928         volatile u8 *pps_buf;
2929         volatile u8 *rps_buf;
2930         volatile u8 *scl_buf;
2931         volatile u8 *yuv_buf;
2932         volatile u8 *cabac_buf;
2933         volatile u8 *ref_buf;
2934
2935         u8 *pps;
2936         u8 *yuv[2];
2937         int i;
2938
2939         pps_tbl[0] = pps_00;
2940         pps_tbl[1] = pps_01;
2941
2942         register_tbl[0] = register_00;
2943         register_tbl[1] = register_01;
2944
2945         rps_tbl[0] = rps_00;
2946         rps_tbl[1] = rps_01;
2947
2948         scaling_list_tbl[0] = scaling_list_00;
2949         scaling_list_tbl[1] = scaling_list_01;
2950
2951         stream_tbl[0] = stream_00;
2952         stream_tbl[1] = stream_01;
2953
2954         stream_size[0] = sizeof(stream_00);
2955         stream_size[1] = sizeof(stream_01);
2956
2957         pps_size[0] = sizeof(pps_00);
2958         pps_size[1] = sizeof(pps_01);
2959
2960         rps_size[0] = sizeof(rps_00);
2961         rps_size[1] = sizeof(rps_01);
2962
2963         scl_size[0] = sizeof(scaling_list_00);
2964         scl_size[1] = sizeof(scaling_list_01);
2965
2966         cabac_size[0] = sizeof(Cabac_table);
2967         cabac_size[1] = sizeof(Cabac_table);
2968
2969         /* create session */
2970         session.pid = current->pid;
2971         session.type = VPU_DEC;
2972         INIT_LIST_HEAD(&session.waiting);
2973         INIT_LIST_HEAD(&session.running);
2974         INIT_LIST_HEAD(&session.done);
2975         INIT_LIST_HEAD(&session.list_session);
2976         init_waitqueue_head(&session.wait);
2977         atomic_set(&session.task_running, 0);
2978         list_add_tail(&session.list_session, &pservice->session);
2979
2980         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2981         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2982
2983         while (testidx < TEST_CNT) {
2984                 /* create registers */
2985                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2986                 if (NULL == reg) {
2987                         vpu_err("error: kmalloc fail in reg_init\n");
2988                         return -1;
2989                 }
2990
2991                 if (size > pservice->reg_size) {
2992                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2993                         size = pservice->reg_size;
2994                 }
2995                 reg->session = &session;
2996                 reg->type = session.type;
2997                 reg->size = size;
2998                 reg->freq = VPU_FREQ_DEFAULT;
2999                 reg->reg = (unsigned long *)&reg[1];
3000                 INIT_LIST_HEAD(&reg->session_link);
3001                 INIT_LIST_HEAD(&reg->status_link);
3002
3003                 /* TODO: stuff registers */
3004                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
3005
3006                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
3007                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
3008                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
3009                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
3010                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
3011
3012                 pps = pps_buf;
3013
3014                 /* TODO: replace reigster address */
3015                 for (i=0; i<64; i++) {
3016                         u32 scaling_offset;
3017                         u32 tmp;
3018
3019                         scaling_offset = (u32)pps[i*80+74];
3020                         scaling_offset += (u32)pps[i*80+75] << 8;
3021                         scaling_offset += (u32)pps[i*80+76] << 16;
3022                         scaling_offset += (u32)pps[i*80+77] << 24;
3023
3024                         tmp = phy_scl + scaling_offset;
3025
3026                         pps[i*80+74] = tmp & 0xff;
3027                         pps[i*80+75] = (tmp >> 8) & 0xff;
3028                         pps[i*80+76] = (tmp >> 16) & 0xff;
3029                         pps[i*80+77] = (tmp >> 24) & 0xff;
3030                 }
3031
3032                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
3033                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
3034
3035                 reg->reg[1] = 0x21;
3036                 reg->reg[4] = phy_str;
3037                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
3038                 reg->reg[6] = phy_cabac;
3039                 reg->reg[7] = testidx?phy_ref:phy_yuv;
3040                 reg->reg[42] = phy_pps;
3041                 reg->reg[43] = phy_rps;
3042                 for (i = 10; i <= 24; i++)
3043                         reg->reg[i] = phy_yuv;
3044
3045                 mutex_lock(pservice->lock);
3046                 list_add_tail(&reg->status_link, &pservice->waiting);
3047                 list_add_tail(&reg->session_link, &session.waiting);
3048                 mutex_unlock(pservice->lock);
3049
3050                 /* stuff hardware */
3051                 try_set_reg(data);
3052
3053                 /* wait for result */
3054                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
3055                 if (!list_empty(&session.done)) {
3056                         if (ret < 0)
3057                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
3058                         ret = 0;
3059                 } else {
3060                         if (unlikely(ret < 0)) {
3061                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
3062                         } else if (0 == ret) {
3063                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
3064                                 ret = -ETIMEDOUT;
3065                         }
3066                 }
3067                 if (ret < 0) {
3068                         int task_running = atomic_read(&session.task_running);
3069                         int n;
3070                         mutex_lock(pservice->lock);
3071                         vpu_service_dump(pservice);
3072                         if (task_running) {
3073                                 atomic_set(&session.task_running, 0);
3074                                 atomic_sub(task_running, &pservice->total_running);
3075                                 printk("%d task is running but not return, reset hardware...", task_running);
3076                                 vpu_reset(data);
3077                                 printk("done\n");
3078                         }
3079                         vpu_service_session_clear(pservice, &session);
3080                         mutex_unlock(pservice->lock);
3081
3082                         printk("\nDEC Registers:\n");
3083                         n = data->dec_dev.iosize >> 2;
3084                         for (i=0; i<n; i++)
3085                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
3086
3087                         vpu_err("test index %d failed\n", testidx);
3088                         break;
3089                 } else {
3090                         vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
3091
3092                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
3093
3094                         for (i=0; i<68; i++) {
3095                                 if (i % 4 == 0)
3096                                         printk("%02d: ", i);
3097                                 printk("%08x ", reg->reg[i]);
3098                                 if ((i+1) % 4 == 0)
3099                                         printk("\n");
3100                         }
3101
3102                         testidx++;
3103                 }
3104
3105                 reg_deinit(data, reg);
3106         }
3107
3108         return 0;
3109 }
3110
3111 #endif
3112