arch/arm/mach-rockchip/rk3288_ddr_suspend.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Chris Zhong<zyw@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/regmap.h>
  22
  23 #include "pm.h"
  24 #include "embedded/rk3288_ddr.h"
  25 #include "embedded/rk3288_resume.h"
  26
  27 void __iomem *rk3288_regulator_pwm_addr;
  28 void __iomem *rk3288_ddr_ctrl_addr[RK3288_NUM_DDR_PORTS];
  29 void __iomem *rk3288_phy_addr[RK3288_NUM_DDR_PORTS];
  30 void __iomem *rk3288_msch_addr[RK3288_NUM_DDR_PORTS];
  31
  32 static const char * const rk3288_ddr_clk_names[] = {
  33         "pclk_ddrupctl0",
  34         "pclk_publ0",
  35         "pclk_ddrupctl1",
  36         "pclk_publ1",
  37         "aclk_dmac1",
  38 };
  39 #define NUM_DDR_CLK_NAMES ARRAY_SIZE(rk3288_ddr_clk_names)
  40
  41 static struct clk *rk3288_ddr_clks[NUM_DDR_CLK_NAMES];
  42
  43 static const u32 rk3288_pwm_reg[] = {
  44         0x4,    /* PERIOD */
  45         0x8,    /* DUTY */
  46         0xc,    /* CTRL */
  47 };
  48 #define NUM_PWM_REGS ARRAY_SIZE(rk3288_pwm_reg)
  49
  50 static const u32 rk3288_ddr_phy_dll_reg[] = {
  51         DDR_PUBL_DLLGCR,
  52         DDR_PUBL_ACDLLCR,
  53         DDR_PUBL_DX0DLLCR,
  54         DDR_PUBL_DX1DLLCR,
  55         DDR_PUBL_DX2DLLCR,
  56         DDR_PUBL_DX3DLLCR,
  57         DDR_PUBL_PIR,
  58 };
  59 #define NUM_DDR_PHY_DLL_REGS ARRAY_SIZE(rk3288_ddr_phy_dll_reg)
  60
  61 static const u32 rk3288_ddr_ctrl_reg[] = {
  62         DDR_PCTL_TOGCNT1U,
  63         DDR_PCTL_TINIT,
  64         DDR_PCTL_TEXSR,
  65         DDR_PCTL_TINIT,
  66         DDR_PCTL_TRSTH,
  67         DDR_PCTL_TOGCNT100N,
  68         DDR_PCTL_TREFI,
  69         DDR_PCTL_TMRD,
  70         DDR_PCTL_TRFC,
  71         DDR_PCTL_TRP,
  72         DDR_PCTL_TRTW,
  73         DDR_PCTL_TAL,
  74         DDR_PCTL_TCL,
  75         DDR_PCTL_TCWL,
  76         DDR_PCTL_TRAS,
  77         DDR_PCTL_TRC,
  78         DDR_PCTL_TRCD,
  79         DDR_PCTL_TRRD,
  80         DDR_PCTL_TRTP,
  81         DDR_PCTL_TWR,
  82         DDR_PCTL_TWTR,
  83         DDR_PCTL_TEXSR,
  84         DDR_PCTL_TXP,
  85         DDR_PCTL_TXPDLL,
  86         DDR_PCTL_TZQCS,
  87         DDR_PCTL_TZQCSI,
  88         DDR_PCTL_TDQS,
  89         DDR_PCTL_TCKSRE,
  90         DDR_PCTL_TCKSRX,
  91         DDR_PCTL_TCKE,
  92         DDR_PCTL_TMOD,
  93         DDR_PCTL_TRSTL,
  94         DDR_PCTL_TZQCL,
  95         DDR_PCTL_TMRR,
  96         DDR_PCTL_TCKESR,
  97         DDR_PCTL_TDPD,
  98         DDR_PCTL_SCFG,
  99         DDR_PCTL_CMDTSTATEN,
 100         DDR_PCTL_MCFG1,
 101         DDR_PCTL_MCFG,
 102         DDR_PCTL_DFITCTRLDELAY,
 103         DDR_PCTL_DFIODTCFG,
 104         DDR_PCTL_DFIODTCFG1,
 105         DDR_PCTL_DFIODTRANKMAP,
 106         DDR_PCTL_DFITPHYWRDATA,
 107         DDR_PCTL_DFITPHYWRLAT,
 108         DDR_PCTL_DFITRDDATAEN,
 109         DDR_PCTL_DFITPHYRDLAT,
 110         DDR_PCTL_DFITPHYUPDTYPE0,
 111         DDR_PCTL_DFITPHYUPDTYPE1,
 112         DDR_PCTL_DFITPHYUPDTYPE2,
 113         DDR_PCTL_DFITPHYUPDTYPE3,
 114         DDR_PCTL_DFITCTRLUPDMIN,
 115         DDR_PCTL_DFITCTRLUPDMAX,
 116         DDR_PCTL_DFITCTRLUPDDLY,
 117         DDR_PCTL_DFIUPDCFG,
 118         DDR_PCTL_DFITREFMSKI,
 119         DDR_PCTL_DFITCTRLUPDI,
 120         DDR_PCTL_DFISTCFG0,
 121         DDR_PCTL_DFISTCFG1,
 122         DDR_PCTL_DFITDRAMCLKEN,
 123         DDR_PCTL_DFITDRAMCLKDIS,
 124         DDR_PCTL_DFISTCFG2,
 125         DDR_PCTL_DFILPCFG0,
 126 };
 127 #define NUM_DDR_CTRL_REGS ARRAY_SIZE(rk3288_ddr_ctrl_reg)
 128
 129 static const u32 rk3288_ddr_phy_reg[] = {
 130         DDR_PUBL_DTPR0,
 131         DDR_PUBL_DTPR1,
 132         DDR_PUBL_DTPR2,
 133         DDR_PUBL_MR0,
 134         DDR_PUBL_MR1,
 135         DDR_PUBL_MR2,
 136         DDR_PUBL_MR3,
 137         DDR_PUBL_PGCR,
 138         DDR_PUBL_PTR0,
 139         DDR_PUBL_PTR1,
 140         DDR_PUBL_PTR2,
 141         DDR_PUBL_ACIOCR,
 142         DDR_PUBL_DXCCR,
 143         DDR_PUBL_DSGCR,
 144         DDR_PUBL_DCR,
 145         DDR_PUBL_ODTCR,
 146         DDR_PUBL_DTAR,
 147         DDR_PUBL_DX0GCR,
 148         DDR_PUBL_DX1GCR,
 149         DDR_PUBL_DX2GCR,
 150         DDR_PUBL_DX3GCR,
 151         DDR_PUBL_DX0DQTR,
 152         DDR_PUBL_DX0DQSTR,
 153         DDR_PUBL_DX1DQTR,
 154         DDR_PUBL_DX1DQSTR,
 155         DDR_PUBL_DX2DQTR,
 156         DDR_PUBL_DX2DQSTR,
 157         DDR_PUBL_DX3DQTR,
 158         DDR_PUBL_DX3DQSTR,
 159 };
 160 #define NUM_DDR_PHY_REGS ARRAY_SIZE(rk3288_ddr_phy_reg)
 161
 162 static const u32 rk3288_ddr_msch_reg[] = {
 163         DDR_MSCH_DDRCONF,
 164         DDR_MSCH_DDRTIMING,
 165         DDR_MSCH_DDRMODE,
 166         DDR_MSCH_READLATENCY,
 167         DDR_MSCH_ACTIVATE,
 168         DDR_MSCH_DEVTODEV,
 169 };
 170 #define NUM_DDR_MSCH_REGS ARRAY_SIZE(rk3288_ddr_msch_reg)
 171
 172 static const u32 rk3288_ddr_phy_zqcr_reg[] = {
 173         DDR_PUBL_ZQ0CR0,
 174         DDR_PUBL_ZQ1CR0,
 175 };
 176 #define NUM_DDR_PHY_ZQCR_REGS ARRAY_SIZE(rk3288_ddr_phy_zqcr_reg)
 177
 178 static void rk3288_ddr_reg_save(void __iomem *regbase, const u32 reg_list[],
 179                                 int num_reg, u32 *vals)
 180 {
 181         int i;
 182
 183         for (i = 0; i < num_reg; i++)
 184                 vals[i] = readl_relaxed(regbase + reg_list[i]);
 185 }
 186
 187 static void rk3288_ddr_save_offsets(u32 *dst_offsets, const u32 *src_offsets,
 188                                     int num_offsets, int max_offsets)
 189 {
 190         memcpy(dst_offsets, src_offsets, sizeof(*dst_offsets) * num_offsets);
 191
 192         /*
 193          * Bytes are precious in the restore code, so we don't actually store
 194          * a count.  We just put a 0xffffffff if num >= max.
 195          */
 196         if (num_offsets < max_offsets)
 197                 dst_offsets[num_offsets] = RK3288_BOGUS_OFFSET;
 198 }
 199
 200 int rk3288_ddr_suspend(struct rk3288_ddr_save_data *ddr_save)
 201 {
 202         int ret;
 203         int i;
 204
 205         for (i = 0; i < ARRAY_SIZE(rk3288_ddr_clk_names); i++) {
 206                 ret = clk_enable(rk3288_ddr_clks[i]);
 207                 if (ret) {
 208                         pr_err("%s: Couldn't enable clock %s\n", __func__,
 209                                rk3288_ddr_clk_names[i]);
 210                         goto err;
 211                 }
 212         }
 213
 214         if (rk3288_regulator_pwm_addr)
 215                 rk3288_ddr_reg_save(rk3288_regulator_pwm_addr, rk3288_pwm_reg,
 216                                 NUM_PWM_REGS, ddr_save->pwm_vals);
 217
 218         rk3288_ddr_reg_save(rk3288_ddr_ctrl_addr[0], rk3288_ddr_ctrl_reg,
 219                             NUM_DDR_CTRL_REGS, ddr_save->ctrl_vals);
 220
 221         /* TODO: need to support only one channel of DDR? */
 222         for (i = 0; i < RK3288_NUM_DDR_PORTS; i++) {
 223                 rk3288_ddr_reg_save(rk3288_phy_addr[i], rk3288_ddr_phy_reg,
 224                                     NUM_DDR_PHY_REGS, ddr_save->phy_vals[i]);
 225                 rk3288_ddr_reg_save(rk3288_phy_addr[i], rk3288_ddr_phy_dll_reg,
 226                                     NUM_DDR_PHY_DLL_REGS,
 227                                     ddr_save->phy_dll_vals[i]);
 228                 rk3288_ddr_reg_save(rk3288_msch_addr[i], rk3288_ddr_msch_reg,
 229                                     NUM_DDR_MSCH_REGS, ddr_save->msch_vals[i]);
 230         }
 231
 232         rk3288_ddr_reg_save(rk3288_phy_addr[0], rk3288_ddr_phy_zqcr_reg,
 233                             NUM_DDR_PHY_ZQCR_REGS, ddr_save->phy_zqcr_vals);
 234
 235         return 0;
 236
 237 err:
 238         for (; i > 0; i--)
 239                 clk_disable(rk3288_ddr_clks[i - 1]);
 240
 241         return ret;
 242 }
 243
 244 void rk3288_ddr_resume(void)
 245 {
 246         int i;
 247
 248         for (i = NUM_DDR_CLK_NAMES; i > 0; i--)
 249                 clk_disable(rk3288_ddr_clks[i - 1]);
 250 }
 251
 252 /**
 253  * rk3288_get_regulator_pwm_np - Get the PWM regulator node, if present
 254  *
 255  * It's common (but not required) that an rk3288 board uses one of the
 256  * PWMs on the rk3288 as a regulator.  We'll see if we're in that case.  If we
 257  * are we'll return a "np" for the PWM to save.  If not, we'll return NULL.
 258  * If we have an unexpected error we'll return an ERR_PTR.
 259  *
 260  * NOTE: this whole concept of needing to restore the voltage immediately after
 261  * resume only makes sense for the PWMs built into rk3288.  Any external
 262  * regulators or external PWMs ought to keep their state.
 263  */
 264 static struct device_node * __init rk3288_get_regulator_pwm_np(
 265         struct device_node *dmc_np)
 266 {
 267         struct device_node *np;
 268         struct of_phandle_args args;
 269         int ret;
 270
 271         /* Look for the supply to the memory controller; OK if not there */
 272         np = of_parse_phandle(dmc_np, "logic-supply", 0);
 273         if (!np)
 274                 return NULL;
 275
 276         /* Check to see if it's a PWM regulator; OK if it's not */
 277         if (!of_device_is_compatible(np, "pwm-regulator")) {
 278                 of_node_put(np);
 279                 return NULL;
 280         }
 281
 282         /* If it's a PWM regulator, we'd better be able to get the PWM */
 283         ret = of_parse_phandle_with_args(np, "pwms", "#pwm-cells", 0, &args);
 284         of_node_put(np);
 285         if (ret) {
 286                 pr_err("%s(): can't parse \"pwms\" property\n", __func__);
 287                 return ERR_PTR(ret);
 288         }
 289
 290         /*
 291          * It seems highly unlikely that we'd have a PWM supplying a PWM
 292          * regulator on an rk3288 that isn't a rk3288 PWM.  In such a case
 293          * it's unlikely that the PWM will lose its state.  We'll throw up a
 294          * warning just because this is so strange, but we won't treat it as
 295          * an error.
 296          */
 297         if (!of_device_is_compatible(args.np, "rockchip,rk3288-pwm")) {
 298                 pr_warn("%s(): unexpected PWM for regulator\n", __func__);
 299                 of_node_put(args.np);
 300                 return NULL;
 301         }
 302
 303         return args.np;
 304 }
 305
 306 int __init rk3288_ddr_suspend_init(struct rk3288_ddr_save_data *ddr_save)
 307 {
 308         struct device_node *dmc_np = NULL, *noc_np = NULL, *pwm_np = NULL;
 309         int ret;
 310         int i;
 311
 312         dmc_np = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-dmc");
 313         if (!dmc_np) {
 314                 pr_err("%s: could not find dmc dt node\n", __func__);
 315                 ret = -ENODEV;
 316                 goto err;
 317         }
 318
 319         noc_np = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-noc");
 320         if (!noc_np) {
 321                 pr_err("%s: could not find noc node\n", __func__);
 322                 ret = -ENODEV;
 323                 goto err;
 324         }
 325
 326         pwm_np = rk3288_get_regulator_pwm_np(dmc_np);
 327         if (IS_ERR(pwm_np)) {
 328                 ret = PTR_ERR(pwm_np);
 329                 goto err;
 330         }
 331
 332         /* Do the offsets and saving of the PWM together */
 333         if (pwm_np) {
 334                 struct resource res;
 335
 336                 rk3288_regulator_pwm_addr = of_iomap(pwm_np, 0);
 337                 if (!rk3288_regulator_pwm_addr) {
 338                         pr_err("%s: could not map PWM\n", __func__);
 339                         ret = -ENOMEM;
 340                         goto err;
 341                 }
 342
 343                 ret = of_address_to_resource(pwm_np, 0, &res);
 344                 if (ret) {
 345                         pr_err("%s: could not get PWM phy addr\n", __func__);
 346                         goto err;
 347                 }
 348
 349                 BUILD_BUG_ON(NUM_PWM_REGS > RK3288_MAX_PWM_REGS);
 350                 rk3288_ddr_save_offsets(ddr_save->pwm_addrs,
 351                                         rk3288_pwm_reg,
 352                                         NUM_PWM_REGS,
 353                                         RK3288_MAX_PWM_REGS);
 354
 355                 /* Adjust to store full address, since there are many PWMs */
 356                 for (i = 0; i < NUM_PWM_REGS; i++)
 357                         ddr_save->pwm_addrs[i] += res.start;
 358         }
 359
 360         /* Copy offsets in */
 361         BUILD_BUG_ON(NUM_DDR_PHY_DLL_REGS > RK3288_MAX_DDR_PHY_DLL_REGS);
 362         rk3288_ddr_save_offsets(ddr_save->phy_dll_offsets,
 363                                 rk3288_ddr_phy_dll_reg,
 364                                 NUM_DDR_PHY_DLL_REGS,
 365                                 RK3288_MAX_DDR_PHY_DLL_REGS);
 366
 367         BUILD_BUG_ON(NUM_DDR_CTRL_REGS > RK3288_MAX_DDR_CTRL_REGS);
 368         rk3288_ddr_save_offsets(ddr_save->ctrl_offsets,
 369                                 rk3288_ddr_ctrl_reg,
 370                                 NUM_DDR_CTRL_REGS,
 371                                 RK3288_MAX_DDR_CTRL_REGS);
 372
 373         BUILD_BUG_ON(NUM_DDR_PHY_REGS > RK3288_MAX_DDR_PHY_REGS);
 374         rk3288_ddr_save_offsets(ddr_save->phy_offsets,
 375                                 rk3288_ddr_phy_reg,
 376                                 NUM_DDR_PHY_REGS,
 377                                 RK3288_MAX_DDR_PHY_REGS);
 378
 379         BUILD_BUG_ON(ARRAY_SIZE(rk3288_ddr_msch_reg) >
 380                      RK3288_MAX_DDR_MSCH_REGS);
 381         rk3288_ddr_save_offsets(ddr_save->msch_offsets,
 382                                 rk3288_ddr_msch_reg,
 383                                 NUM_DDR_MSCH_REGS,
 384                                 RK3288_MAX_DDR_MSCH_REGS);
 385
 386         BUILD_BUG_ON(NUM_DDR_PHY_ZQCR_REGS > RK3288_MAX_DDR_PHY_ZQCR_REGS);
 387         rk3288_ddr_save_offsets(ddr_save->phy_zqcr_offsets,
 388                                 rk3288_ddr_phy_zqcr_reg,
 389                                 NUM_DDR_PHY_ZQCR_REGS,
 390                                 RK3288_MAX_DDR_PHY_ZQCR_REGS);
 391
 392         for (i = 0; i < RK3288_NUM_DDR_PORTS; i++) {
 393                 rk3288_ddr_ctrl_addr[i] = of_iomap(dmc_np, i * 2);
 394                 if (!rk3288_ddr_ctrl_addr[i]) {
 395                         pr_err("%s: could not map ddr ctrl\n", __func__);
 396                         ret = -ENOMEM;
 397                         goto err;
 398                 }
 399
 400                 rk3288_phy_addr[i] = of_iomap(dmc_np, i * 2 + 1);
 401                 if (!rk3288_phy_addr[i]) {
 402                         pr_err("%s: could not map phy\n", __func__);
 403                         ret = -ENOMEM;
 404                         goto err;
 405                 }
 406         }
 407
 408         for (i = 0; i < NUM_DDR_CLK_NAMES; i++) {
 409                 rk3288_ddr_clks[i] =
 410                         of_clk_get_by_name(dmc_np, rk3288_ddr_clk_names[i]);
 411
 412                 if (IS_ERR(rk3288_ddr_clks[i])) {
 413                         pr_err("%s: couldn't get clock %s\n", __func__,
 414                                rk3288_ddr_clk_names[i]);
 415                         ret = PTR_ERR(rk3288_ddr_clks[i]);
 416                         goto err;
 417                 }
 418
 419                 ret = clk_prepare(rk3288_ddr_clks[i]);
 420                 if (ret) {
 421                         pr_err("%s: couldn't prepare clock %s\n", __func__,
 422                                rk3288_ddr_clk_names[i]);
 423                         clk_put(rk3288_ddr_clks[i]);
 424                         rk3288_ddr_clks[i] = NULL;
 425                         goto err;
 426                 }
 427         }
 428
 429         rk3288_msch_addr[0] = of_iomap(noc_np, 0);
 430         if (!rk3288_msch_addr[0]) {
 431                 pr_err("%s: could not map msch base\n", __func__);
 432                 ret = -ENOMEM;
 433                 goto err;
 434         }
 435         rk3288_msch_addr[1] = rk3288_msch_addr[0] + 0x80;
 436
 437         ret = 0;
 438         goto exit_of;
 439
 440 err:
 441         if (rk3288_msch_addr[0]) {
 442                 iounmap(rk3288_msch_addr[0]);
 443                 rk3288_msch_addr[0] = NULL;
 444         }
 445
 446         for (i = 0; i < NUM_DDR_CLK_NAMES; i++)
 447                 if (!IS_ERR_OR_NULL(rk3288_ddr_clks[i])) {
 448                         clk_unprepare(rk3288_ddr_clks[i]);
 449                         clk_put(rk3288_ddr_clks[i]);
 450                         rk3288_ddr_clks[i] = NULL;
 451                 }
 452
 453         for (i = 0; i < RK3288_NUM_DDR_PORTS; i++) {
 454                 if (rk3288_phy_addr[i]) {
 455                         iounmap(rk3288_phy_addr[i]);
 456                         rk3288_phy_addr[i] = NULL;
 457                 }
 458                 if (rk3288_ddr_ctrl_addr[i]) {
 459                         iounmap(rk3288_ddr_ctrl_addr[i]);
 460                         rk3288_ddr_ctrl_addr[i] = NULL;
 461                 }
 462         }
 463
 464         if (rk3288_regulator_pwm_addr) {
 465                 iounmap(rk3288_regulator_pwm_addr);
 466                 rk3288_regulator_pwm_addr = NULL;
 467         }
 468
 469 exit_of:
 470         if (pwm_np)
 471                 of_node_put(pwm_np);
 472         if (noc_np)
 473                 of_node_put(noc_np);
 474         if (dmc_np)
 475                 of_node_put(dmc_np);
 476
 477         return ret;
 478 }