2 * Device Tree support for Rockchip RK3288
4 * Copyright (C) 2014 ROCKCHIP, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clocksource.h>
19 #include <linux/cpuidle.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/irqchip.h>
23 #include <linux/kernel.h>
24 #include <linux/of_address.h>
25 #include <linux/of_platform.h>
26 #include <linux/rockchip/common.h>
27 #include <linux/rockchip/cpu.h>
28 #include <linux/rockchip/cru.h>
29 #include <linux/rockchip/dvfs.h>
30 #include <linux/rockchip/grf.h>
31 #include <linux/rockchip/iomap.h>
32 #include <linux/rockchip/pmu.h>
33 #include <asm/cpuidle.h>
34 #include <asm/cputype.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
43 #define RK3288_DEVICE(name) \
45 .virtual = (unsigned long) RK_##name##_VIRT, \
46 .pfn = __phys_to_pfn(RK3288_##name##_PHYS), \
47 .length = RK3288_##name##_SIZE, \
51 #define RK3288_SERVICE_DEVICE(name) \
52 RK_DEVICE(RK3288_SERVICE_##name##_VIRT, RK3288_SERVICE_##name##_PHYS, RK3288_SERVICE_##name##_SIZE)
54 #define RK3288_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
55 #define RK3288_TIMER7_VIRT (RK_TIMER_VIRT + 0x20)
57 static struct map_desc rk3288_io_desc[] __initdata = {
64 RK3288_SERVICE_DEVICE(CORE),
65 RK3288_SERVICE_DEVICE(DMAC),
66 RK3288_SERVICE_DEVICE(GPU),
67 RK3288_SERVICE_DEVICE(PERI),
68 RK3288_SERVICE_DEVICE(VIO),
69 RK3288_SERVICE_DEVICE(VIDEO),
70 RK3288_SERVICE_DEVICE(HEVC),
71 RK3288_SERVICE_DEVICE(BUS),
72 RK_DEVICE(RK_DDR_VIRT, RK3288_DDR_PCTL0_PHYS, RK3288_DDR_PCTL_SIZE),
73 RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE, RK3288_DDR_PUBL0_PHYS, RK3288_DDR_PUBL_SIZE),
74 RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PCTL1_PHYS, RK3288_DDR_PCTL_SIZE),
75 RK_DEVICE(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PUBL1_PHYS, RK3288_DDR_PUBL_SIZE),
76 RK_DEVICE(RK_GPIO_VIRT(0), RK3288_GPIO0_PHYS, RK3288_GPIO_SIZE),
77 RK_DEVICE(RK_GPIO_VIRT(1), RK3288_GPIO1_PHYS, RK3288_GPIO_SIZE),
78 RK_DEVICE(RK_GPIO_VIRT(2), RK3288_GPIO2_PHYS, RK3288_GPIO_SIZE),
79 RK_DEVICE(RK_GPIO_VIRT(3), RK3288_GPIO3_PHYS, RK3288_GPIO_SIZE),
80 RK_DEVICE(RK_GPIO_VIRT(4), RK3288_GPIO4_PHYS, RK3288_GPIO_SIZE),
81 RK_DEVICE(RK_GPIO_VIRT(5), RK3288_GPIO5_PHYS, RK3288_GPIO_SIZE),
82 RK_DEVICE(RK_GPIO_VIRT(6), RK3288_GPIO6_PHYS, RK3288_GPIO_SIZE),
83 RK_DEVICE(RK_GPIO_VIRT(7), RK3288_GPIO7_PHYS, RK3288_GPIO_SIZE),
84 RK_DEVICE(RK_GPIO_VIRT(8), RK3288_GPIO8_PHYS, RK3288_GPIO_SIZE),
85 RK_DEVICE(RK_DEBUG_UART_VIRT, RK3288_UART_DBG_PHYS, RK3288_UART_SIZE),
86 RK_DEVICE(RK_GIC_VIRT, RK3288_GIC_DIST_PHYS, RK3288_GIC_DIST_SIZE),
87 RK_DEVICE(RK_GIC_VIRT + RK3288_GIC_DIST_SIZE, RK3288_GIC_CPU_PHYS, RK3288_GIC_CPU_SIZE),
88 RK_DEVICE(RK_BOOTRAM_VIRT, RK3288_BOOTRAM_PHYS, RK3288_BOOTRAM_SIZE),
89 RK_DEVICE(RK3288_IMEM_VIRT, RK3288_IMEM_PHYS, SZ_4K),
90 RK_DEVICE(RK_TIMER_VIRT, RK3288_TIMER6_PHYS, RK3288_TIMER_SIZE),
93 static void __init rk3288_boot_mode_init(void)
95 u32 flag = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG0);
96 u32 mode = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG1);
97 u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_ST);
99 if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
100 mode = BOOT_MODE_RECOVERY;
101 if (rst_st & ((1 << 4) | (1 << 5)))
102 mode = BOOT_MODE_WATCHDOG;
103 else if (rst_st & ((1 << 2) | (1 << 3)))
104 mode = BOOT_MODE_TSADC;
105 rockchip_boot_mode_init(flag, mode);
108 static void usb_uart_init(void)
112 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
113 soc_status2 = (readl_relaxed(RK_GRF_VIRT + RK3288_GRF_SOC_STATUS2));
115 #ifdef CONFIG_RK_USB_UART
116 if (!(soc_status2 & (1<<14)) && (soc_status2 & (1<<17))) {
117 /* software control usb phy enable */
118 writel_relaxed(0x00040004, RK_GRF_VIRT + RK3288_GRF_UOC0_CON2);
119 /* usb phy enter suspend */
120 writel_relaxed(0x003f002a, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
121 writel_relaxed(0x00c000c0, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
126 extern void secondary_startup(void);
128 static void __init rk3288_dt_map_io(void)
132 rockchip_soc_id = ROCKCHIP_SOC_RK3288;
134 iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
138 /* pmu reset by second global soft reset */
139 v = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
142 writel_relaxed(v, RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
144 /* rkpwm is used instead of old pwm */
145 writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
147 /* disable address remap */
148 writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
150 /* enable timer7 for core */
151 writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
153 writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
154 writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
156 writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
159 /* power up/down GPU domain wait 1us */
160 writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRDWN_CNT);
161 writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRUP_CNT);
163 rk3288_boot_mode_init();
166 static const u8 pmu_st_map[] = {
180 static bool rk3288_pmu_power_domain_is_on(enum pmu_power_domain pd)
182 /* 1'b0: power on, 1'b1: power off */
183 return !(readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
186 static DEFINE_SPINLOCK(pmu_idle_lock);
188 static const u8 pmu_idle_map[] = {
192 [IDLE_REQ_VIDEO] = 3,
195 [IDLE_REQ_ALIVE] = 6,
201 static int rk3288_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
203 u32 bit = pmu_idle_map[req];
204 u32 idle_mask = BIT(bit) | BIT(bit + 16);
205 u32 idle_target = (idle << bit) | (idle << (bit + 16));
210 spin_lock_irqsave(&pmu_idle_lock, flags);
211 val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
216 writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
219 while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_ST) & idle_mask) != idle_target)
221 spin_unlock_irqrestore(&pmu_idle_lock, flags);
226 static const u8 pmu_pd_map[] = {
240 static DEFINE_SPINLOCK(pmu_pd_lock);
242 static noinline void rk3288_do_pmu_set_power_domain(enum pmu_power_domain domain, bool on)
244 u8 pd = pmu_pd_map[domain];
245 u32 val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
250 writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
253 while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
257 static u32 gpu_r_qos[CPU_AXI_QOS_NUM_REGS];
258 static u32 gpu_w_qos[CPU_AXI_QOS_NUM_REGS];
259 static u32 vio0_iep_qos[CPU_AXI_QOS_NUM_REGS];
260 static u32 vio0_vip_qos[CPU_AXI_QOS_NUM_REGS];
261 static u32 vio0_vop_qos[CPU_AXI_QOS_NUM_REGS];
262 static u32 vio1_isp_r_qos[CPU_AXI_QOS_NUM_REGS];
263 static u32 vio1_isp_w0_qos[CPU_AXI_QOS_NUM_REGS];
264 static u32 vio1_isp_w1_qos[CPU_AXI_QOS_NUM_REGS];
265 static u32 vio1_vop_qos[CPU_AXI_QOS_NUM_REGS];
266 static u32 vio2_rga_r_qos[CPU_AXI_QOS_NUM_REGS];
267 static u32 vio2_rga_w_qos[CPU_AXI_QOS_NUM_REGS];
268 static u32 video_qos[CPU_AXI_QOS_NUM_REGS];
269 static u32 hevc_r_qos[CPU_AXI_QOS_NUM_REGS];
270 static u32 hevc_w_qos[CPU_AXI_QOS_NUM_REGS];
272 #define SAVE_QOS(array, NAME) CPU_AXI_SAVE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
273 #define RESTORE_QOS(array, NAME) CPU_AXI_RESTORE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
275 static int rk3288_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
279 spin_lock_irqsave(&pmu_pd_lock, flags);
280 if (rk3288_pmu_power_domain_is_on(pd) == on)
284 /* if power down, idle request to NIU first */
286 SAVE_QOS(vio0_iep_qos, VIO0_IEP);
287 SAVE_QOS(vio0_vip_qos, VIO0_VIP);
288 SAVE_QOS(vio0_vop_qos, VIO0_VOP);
289 SAVE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
290 SAVE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
291 SAVE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
292 SAVE_QOS(vio1_vop_qos, VIO1_VOP);
293 SAVE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
294 SAVE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
295 rk3288_pmu_set_idle_request(IDLE_REQ_VIO, true);
296 } else if (pd == PD_VIDEO) {
297 SAVE_QOS(video_qos, VIDEO);
298 rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
299 } else if (pd == PD_GPU) {
300 SAVE_QOS(gpu_r_qos, GPU_R);
301 SAVE_QOS(gpu_w_qos, GPU_W);
302 rk3288_pmu_set_idle_request(IDLE_REQ_GPU, true);
303 } else if (pd == PD_HEVC) {
304 SAVE_QOS(hevc_r_qos, HEVC_R);
305 SAVE_QOS(hevc_w_qos, HEVC_W);
306 rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, true);
307 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
308 writel_relaxed(0x20002 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
311 else if (pd == PD_PERI) {
312 rk3288_pmu_set_idle_request(IDLE_REQ_PERI, true);
317 rk3288_do_pmu_set_power_domain(pd, on);
320 /* if power up, idle request release to NIU */
322 rk3288_pmu_set_idle_request(IDLE_REQ_VIO, false);
323 RESTORE_QOS(vio0_iep_qos, VIO0_IEP);
324 RESTORE_QOS(vio0_vip_qos, VIO0_VIP);
325 RESTORE_QOS(vio0_vop_qos, VIO0_VOP);
326 RESTORE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
327 RESTORE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
328 RESTORE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
329 RESTORE_QOS(vio1_vop_qos, VIO1_VOP);
330 RESTORE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
331 RESTORE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
332 } else if (pd == PD_VIDEO) {
333 rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
334 RESTORE_QOS(video_qos, VIDEO);
335 } else if (pd == PD_GPU) {
336 rk3288_pmu_set_idle_request(IDLE_REQ_GPU, false);
337 RESTORE_QOS(gpu_r_qos, GPU_R);
338 RESTORE_QOS(gpu_w_qos, GPU_W);
339 } else if (pd == PD_HEVC) {
340 rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, false);
341 RESTORE_QOS(hevc_r_qos, HEVC_R);
342 RESTORE_QOS(hevc_w_qos, HEVC_W);
343 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
345 writel_relaxed(0x20000 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
348 writel_relaxed(virt_to_phys(secondary_startup), RK3288_IMEM_VIRT + 8);
349 writel_relaxed(0xDEADBEAF, RK3288_IMEM_VIRT + 4);
353 else if (pd == PD_PERI) {
354 rk3288_pmu_set_idle_request(IDLE_REQ_PERI, false);
359 spin_unlock_irqrestore(&pmu_pd_lock, flags);
363 static int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on)
365 u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT];
366 u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT];
369 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
370 clks_save[i] = cru_readl(RK3288_CRU_CLKGATES_CON(i));
371 clks_ungating[i] = 0;
377 clks_ungating[5] = 1 << 7;
379 clks_ungating[18] = 1 << 0;
382 /* aclk_vdpu_src hclk_vpu aclk_vepu_src */
383 clks_ungating[3] = 1 << 11 | 1 << 10 | 1 << 9;
384 /* hclk_video aclk_video */
385 clks_ungating[9] = 1 << 1 | 1 << 0;
388 /* aclk_lcdc0/1_src dclk_lcdc0/1_src rga_core aclk_rga_src */
389 /* edp_24m edp isp isp_jpeg */
391 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 |
392 1 << 12 | 1 << 13 | 1 << 14 | 1 << 15;
393 clks_ungating[15] = 0xffff;
394 clks_ungating[16] = 0x0fff;
397 /* hevc_core hevc_cabac aclk_hevc */
398 clks_ungating[13] = 1 << 15 | 1 << 14 | 1 << 13;
402 clks_ungating[12] = 1 << 11 | 1 < 10 | 1 << 9 | 1 << 8;
409 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
410 if (clks_ungating[i])
411 cru_writel(clks_ungating[i] << 16, RK3288_CRU_CLKGATES_CON(i));
414 ret = rk3288_pmu_set_power_domain(pd, on);
416 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
417 if (clks_ungating[i])
418 cru_writel(clks_save[i] | 0xffff0000, RK3288_CRU_CLKGATES_CON(i));
424 static void __init rk3288_dt_init_timer(void)
426 rockchip_pmu_ops.set_power_domain = rk3288_sys_set_power_domain;
427 rockchip_pmu_ops.power_domain_is_on = rk3288_pmu_power_domain_is_on;
428 rockchip_pmu_ops.set_idle_request = rk3288_pmu_set_idle_request;
430 clocksource_of_init();
434 static void __init rk3288_reserve(void)
436 /* reserve memory for ION */
437 rockchip_ion_reserve();
440 static const char * const rk3288_dt_compat[] __initconst = {
445 static void rk3288_restart(char mode, const char *cmd)
447 u32 boot_flag, boot_mode;
449 rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
451 writel_relaxed(boot_flag, RK_PMU_VIRT + RK3288_PMU_SYS_REG0); // for loader
452 writel_relaxed(boot_mode, RK_PMU_VIRT + RK3288_PMU_SYS_REG1); // for linux
455 /* pll enter slow mode */
456 writel_relaxed(0xf3030000, RK_CRU_VIRT + RK3288_CRU_MODE_CON);
458 writel_relaxed(0xeca8, RK_CRU_VIRT + RK3288_CRU_GLB_SRST_SND_VALUE);
462 static struct cpuidle_driver rk3288_cpuidle_driver = {
463 .name = "rk3288_cpuidle",
464 .owner = THIS_MODULE,
465 .states[0] = ARM_CPUIDLE_WFI_STATE,
469 static int rk3288_cpuidle_enter(struct cpuidle_device *dev,
470 struct cpuidle_driver *drv, int index)
472 void *sel = RK_CRU_VIRT + RK3288_CRU_CLKSELS_CON(36);
473 u32 con = readl_relaxed(sel);
474 u32 cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0);
475 writel_relaxed(0x70007 << (cpu << 2), sel);
477 writel_relaxed((0x70000 << (cpu << 2)) | con, sel);
482 static void __init rk3288_init_cpuidle(void)
486 if (!rockchip_jtag_enabled)
487 rk3288_cpuidle_driver.states[0].enter = rk3288_cpuidle_enter;
488 ret = cpuidle_register(&rk3288_cpuidle_driver, NULL);
490 pr_err("%s: failed to register cpuidle driver: %d\n", __func__, ret);
493 static void __init rk3288_init_suspend(void);
495 static void __init rk3288_init_late(void)
498 rk3288_init_suspend();
500 #ifdef CONFIG_CPU_IDLE
501 rk3288_init_cpuidle();
503 if (rockchip_jtag_enabled)
504 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
507 DT_MACHINE_START(RK3288_DT, "Rockchip RK3288 (Flattened Device Tree)")
508 .smp = smp_ops(rockchip_smp_ops),
509 .map_io = rk3288_dt_map_io,
510 .init_time = rk3288_dt_init_timer,
511 .dt_compat = rk3288_dt_compat,
512 .init_late = rk3288_init_late,
513 .reserve = rk3288_reserve,
514 .restart = rk3288_restart,
517 char PIE_DATA(sram_stack)[1024];
518 EXPORT_PIE_SYMBOL(DATA(sram_stack));
520 static int __init rk3288_pie_init(void)
523 if (!cpu_is_rk3288())
526 err = rockchip_pie_init();
530 rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3288);
531 if (IS_ERR(rockchip_pie_chunk)) {
532 err = PTR_ERR(rockchip_pie_chunk);
533 pr_err("%s: failed to load section %d\n", __func__, err);
534 rockchip_pie_chunk = NULL;
538 rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
539 rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *) DATA(sram_stack) + sizeof(DATA(sram_stack)));
543 arch_initcall(rk3288_pie_init);
545 #include "pm-rk3288.c"
547 static u32 rk_pmu_pwrdn_st;
548 static inline void rk_pm_soc_pd_suspend(void)
550 rk_pmu_pwrdn_st = pmu_readl(RK3288_PMU_PWRDN_ST);
552 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
553 rk3288_sys_set_power_domain(PD_GPU, false);
555 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
556 rk3288_sys_set_power_domain(PD_HEVC, false);
558 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
559 rk3288_sys_set_power_domain(PD_VIO, false);
561 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
562 rk3288_sys_set_power_domain(PD_VIDEO, false);
564 rkpm_ddr_printascii("pd state:");
565 rkpm_ddr_printhex(rk_pmu_pwrdn_st);
566 rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
567 rkpm_ddr_printascii("\n");
570 static inline void rk_pm_soc_pd_resume(void)
572 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
573 rk3288_sys_set_power_domain(PD_GPU, true);
575 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
576 rk3288_sys_set_power_domain(PD_HEVC, true);
578 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
579 rk3288_sys_set_power_domain(PD_VIO, true);
581 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
582 rk3288_sys_set_power_domain(PD_VIDEO, true);
585 rkpm_ddr_printascii("pd state:");
586 rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
587 rkpm_ddr_printascii("\n");
590 void inline rkpm_periph_pd_dn(bool on)
592 rk3288_sys_set_power_domain(PD_PERI, on);
595 static void __init rk3288_init_suspend(void)
597 printk("%s\n",__FUNCTION__);
598 rockchip_suspend_init();
600 rk3288_suspend_init();
601 rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend,rk_pm_soc_pd_resume);
605 extern bool console_suspend_enabled;
607 static int __init rk3288_pm_dbg(void)
610 console_suspend_enabled=0;
612 pm_suspend(PM_SUSPEND_MEM);
620 //late_initcall_sync(rk3288_pm_dbg);
625 #define sram_printascii(s) do {} while (0) /* FIXME */
626 #include "ddr_rk32.c"
628 static int __init rk3288_ddr_init(void)
632 ddr_change_freq = _ddr_change_freq;
633 ddr_round_rate = _ddr_round_rate;
634 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
636 ddr_init(DDR3_DEFAULT, 300);
641 arch_initcall_sync(rk3288_ddr_init);