1 #include <linux/linkage.h>
2 #include <asm/assembler.h>
3 #include <asm/memory.h>
5 #define _RKPM_SEELP_S_INCLUDE_
9 ENTRY(rk312x_pm_slp_cpu_while_tst)
10 stmfd sp!, { r3 - r12, lr }
15 ldmfd sp!, { r3 - r12, pc }
19 ENTRY(rk312x_pm_slp_cpu_resume)
27 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
37 WFENE // ; wait if it.s locked
38 B cpu1loop // ; if any failure, loop
43 adr r1,9b // boot ram base
44 ldr r5,8f // resume data offset ,from ram base
45 add r5,r5,r1 // resume data addr
47 ldr r3 ,[r5,#(RKPM_BOOTDATA_ARM_ERRATA_818325_F*4)]
48 ldr r4, = 0x200080b4 // armvoltage pwm resume
52 ldr r2, = 0x00100010 //pwm0
58 ldr r2, = 0x00400040 //pwm1
64 ldr r2, = 0x01000100//pwm2
68 ldr sp,[r5,#(RKPM_BOOTDATA_CPUSP*4)] //sp
70 ldr r3,[r5,#(RKPM_BOOTDATA_DDR_F*4)]
71 //get SLP_DDR_NEED_RES ,if it is 1 ,ddr need to reusme
74 ldr r1,[r5,#(RKPM_BOOTDATA_DDRCODE*4)] // ddr resume code
75 ldr r0,[r5,#(RKPM_BOOTDATA_DDRDATA*4)] //ddr resume data
80 /*****************************************************************************/
83 mov r2,#0x20000000 ;/*cru PA*/
86 str r3,[r2,#0x14];/*PLL no power-down*/
94 tst r3,#400;/*DPLL lock*/
98 ldr r3,=0x00100010;/*DPLL normal mode*/
103 str r3,[r2,#0xd0];/*enable DDR PHY clock*/
115 orr r3, r3, #0xc;/*phy soft de-reset*/
117 sub r2, r2, #0x2000; /*0x20008000*/
121 /*move to access status*/
122 sub r2, r2, #0x4000;/*0x20004000*/
124 str r3,[r2,#0x4];/*wake up */
134 ldr r4, = 0x100a000c //printk
135 mov r1, #0x0e //msch ce xiao
138 ldr r4, = 0x100a0010 //printk
139 mov r1, #0x0e //msch ce xiao
141 ldr pc, [r5,#(RKPM_BOOTDATA_CPUCODE*4)]
142 8: .long (0x00+0x700)//RKPM_BOOT_CODE_OFFSET+RKPM_BOOT_CODE_SIZE
143 ENDPROC(rk312x_pm_slp_cpu_resume)