arch/arm/mach-rockchip/rk312x.c

   1 /*
   2  * Device Tree support for Rockchip RK3288
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/rockchip/common.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/cru.h>
  29 #include <linux/rockchip/dvfs.h>
  30 #include <linux/rockchip/grf.h>
  31 #include <linux/rockchip/iomap.h>
  32 #include <linux/rockchip/pmu.h>
  33 /*#include <asm/cpuidle.h>*/
  34 #include <asm/cputype.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include "cpu_axi.h"
  38 #include "loader.h"
  39 #define CPU 312x
  40 #include "sram.h"
  41 #include "pm.h"
  42 #include "pm-rk312x.c"
  43 #define RK312X_DEVICE(name) \
  44         { \
  45                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  46                 .pfn            = __phys_to_pfn(RK312X_##name##_PHYS), \
  47                 .length         = RK312X_##name##_SIZE, \
  48                 .type           = MT_DEVICE, \
  49         }
  50
  51 static const char * const rk3126_dt_compat[] __initconst = {
  52         "rockchip,rk3126",
  53         NULL,
  54 };
  55
  56 static const char * const rk3128_dt_compat[] __initconst = {
  57         "rockchip,rk3128",
  58         NULL,
  59 };
  60
  61 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  62 #define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  63
  64 static struct map_desc rk312x_io_desc[] __initdata = {
  65         RK312X_DEVICE(CRU),
  66         RK312X_DEVICE(GRF),
  67         RK312X_DEVICE(ROM),
  68         RK312X_DEVICE(PMU),
  69         RK312X_DEVICE(EFUSE),
  70         RK312X_DEVICE(TIMER),
  71         RK312X_DEVICE(CPU_AXI_BUS),
  72         RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE),
  73         RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE),
  74         RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE),
  75         RK_DEVICE(RK_GPIO_VIRT(0), RK312X_GPIO0_PHYS, RK312X_GPIO_SIZE),
  76         RK_DEVICE(RK_GPIO_VIRT(1), RK312X_GPIO1_PHYS, RK312X_GPIO_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(2), RK312X_GPIO2_PHYS, RK312X_GPIO_SIZE),
  78         RK_DEVICE(RK_GPIO_VIRT(3), RK312X_GPIO3_PHYS, RK312X_GPIO_SIZE),
  79         RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
  80         RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
  81         RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
  82 };
  83 static void usb_uart_init(void)
  84 {
  85 #ifdef CONFIG_RK_USB_UART
  86         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_STATUS0);
  87 #endif
  88         writel_relaxed(0x34000000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
  89 #ifdef CONFIG_RK_USB_UART
  90         if (!(soc_status0 & (1 << 5)) && (soc_status0 & (1 << 8))) {
  91                 /* software control usb phy enable */
  92                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK312X_GRF_UOC0_CON0);
  93                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
  94         }
  95 #endif
  96
  97         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
  98         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
  99         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 100         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 101         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 102         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 103 }
 104
 105 static void __init rk312x_dt_map_io(void)
 106 {
 107         iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc));
 108         debug_ll_io_init();
 109         usb_uart_init();
 110
 111         /* enable timer5 for core */
 112         writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10);
 113         dsb();
 114         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00);
 115         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04);
 116         dsb();
 117         writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10);
 118         dsb();
 119 }
 120
 121 static void __init rk3126_dt_map_io(void)
 122 {
 123         rockchip_soc_id = ROCKCHIP_SOC_RK3126;
 124
 125         rk312x_dt_map_io();
 126 }
 127
 128 static void __init rk3128_dt_map_io(void)
 129 {
 130         rockchip_soc_id = ROCKCHIP_SOC_RK3128;
 131
 132         rk312x_dt_map_io();
 133 }
 134 static DEFINE_SPINLOCK(pmu_idle_lock);
 135 static const u8 pmu_idle_map[] = {
 136         [IDLE_REQ_PERI] = 0,
 137         [IDLE_REQ_VIDEO] = 1,
 138         [IDLE_REQ_VIO] = 2,
 139         [IDLE_REQ_GPU] = 3,
 140         [IDLE_REQ_CORE] = 4,
 141         [IDLE_REQ_SYS] = 5,
 142         [IDLE_REQ_MSCH] = 6,
 143         [IDLE_REQ_CRYPTO] = 7,
 144
 145 };
 146 static int rk312x_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 147 {
 148         u32 val;
 149         unsigned long flags;
 150         u32 bit = pmu_idle_map[req];
 151         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 152         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 153         u32 mask = BIT(bit);
 154
 155         spin_lock_irqsave(&pmu_idle_lock, flags);
 156         val = pmu_readl(RK312X_PMU_IDLE_REQ);
 157         if (idle)
 158                 val |= mask;
 159         else
 160                 val &= ~mask;
 161         pmu_writel(val, RK312X_PMU_IDLE_REQ);
 162         dsb();
 163
 164         while (((pmu_readl(RK312X_PMU_IDLE_ST) & idle_mask) != idle_target))
 165                 ;
 166         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 167         return 0;
 168 }
 169 static const u8 pmu_pd_map[] = {
 170         [PD_GPU] = 1,
 171         [PD_VIDEO] = 2,
 172         [PD_VIO] = 3,
 173 };
 174
 175 static const u8 pmu_st_map[] = {
 176         [PD_GPU] = 1,
 177         [PD_VIDEO] = 2,
 178         [PD_VIO] = 3,
 179 };
 180
 181 static noinline void rk312x_do_pmu_set_power_domain(enum pmu_power_domain domain
 182         , bool on)
 183 {
 184         u8 pd = pmu_pd_map[domain];
 185         u32 val = pmu_readl(RK312X_PMU_PWRDN_CON);
 186
 187         if (on)
 188                 val &= ~BIT(pd);
 189         else
 190                 val |=  BIT(pd);
 191         pmu_writel(val, RK312X_PMU_PWRDN_CON);
 192         dsb();
 193
 194         while ((pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 195                 ;
 196 }
 197
 198 static bool rk312x_pmu_power_domain_is_on(enum pmu_power_domain pd)
 199 {
 200         /*1"b0: power on, 1'b1: power off*/
 201         return !(pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 202 }
 203 static DEFINE_SPINLOCK(pmu_pd_lock);
 204 static u32 rga_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 205 static u32 ebc_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 206 static u32 iep_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 207 static u32 lcdc0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 208 static u32 vip0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 209 static u32 gpu_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 210 static u32 video_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 211
 212 #define SAVE_QOS(array, NAME) RK312X_CPU_AXI_SAVE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 213 #define RESTORE_QOS(array, NAME) RK312X_CPU_AXI_RESTORE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 214
 215 static int rk312x_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 216 {
 217         unsigned long flags;
 218
 219         spin_lock_irqsave(&pmu_pd_lock, flags);
 220         if (rk312x_pmu_power_domain_is_on(pd) == on)
 221                 goto out;
 222         if (!on) {
 223                 if (pd == PD_GPU) {
 224                         SAVE_QOS(gpu_qos, GPU);
 225                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, true);
 226                 } else if (pd == PD_VIO) {
 227                         SAVE_QOS(rga_qos, VIO_RGA);
 228                         SAVE_QOS(ebc_qos, VIO_EBC);
 229                         SAVE_QOS(iep_qos, VIO_IEP);
 230                         SAVE_QOS(lcdc0_qos, VIO_LCDC0);
 231                         SAVE_QOS(vip0_qos, VIO_VIP0);
 232                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, true);
 233                 } else if (pd == PD_VIDEO) {
 234                         SAVE_QOS(video_qos, VIDEO);
 235                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 236                 }
 237         }
 238
 239         rk312x_do_pmu_set_power_domain(pd, on);
 240
 241         if (on) {
 242                 if (pd == PD_GPU) {
 243                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, false);
 244                         RESTORE_QOS(gpu_qos, GPU);
 245                 } else if (pd == PD_VIO) {
 246                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, false);
 247                         RESTORE_QOS(rga_qos, VIO_RGA);
 248                         RESTORE_QOS(ebc_qos, VIO_EBC);
 249                         RESTORE_QOS(iep_qos, VIO_IEP);
 250                         RESTORE_QOS(lcdc0_qos, VIO_LCDC0);
 251                         RESTORE_QOS(vip0_qos, VIO_VIP0);
 252                 } else if (pd == PD_VIDEO) {
 253                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 254                         RESTORE_QOS(video_qos, VIDEO);
 255                 }
 256         }
 257 out:
 258         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 259
 260         return 0;
 261 }
 262 extern void secondary_startup(void);
 263 static int rk312x_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 264 {
 265         u32 clks_save[RK312X_CRU_CLKGATES_CON_CNT];
 266         u32 clks_ungating[RK312X_CRU_CLKGATES_CON_CNT];
 267         u32 i, ret = 0;
 268
 269         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 270                 clks_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 271                 clks_ungating[i] = 0;
 272         }
 273         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 274                 cru_writel(0xffff0000, RK312X_CRU_CLKGATES_CON(i));
 275
 276         if (on) {
 277 #ifdef CONFIG_SMP
 278                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 279                         writel_relaxed(0x20000 << (pd - PD_CPU_1),
 280                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 281                         dsb();
 282                         udelay(10);
 283                         writel_relaxed(virt_to_phys(secondary_startup),
 284                                        RK312X_IMEM_VIRT + 8);
 285                         writel_relaxed(0xDEADBEAF, RK312X_IMEM_VIRT + 4);
 286                         dsb_sev();
 287                 }
 288 #endif
 289         } else {
 290 #ifdef CONFIG_SMP
 291                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 292                         writel_relaxed(0x20002 << (pd - PD_CPU_1),
 293                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 294                         dsb();
 295                 }
 296 #endif
 297         }
 298
 299         if (((pd == PD_GPU) || (pd == PD_VIO) || (pd == PD_VIDEO)))
 300                 ret = rk312x_pmu_set_power_domain(pd, on);
 301
 302         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 303                 cru_writel(clks_save[i] | 0xffff0000
 304                         , RK312X_CRU_CLKGATES_CON(i));
 305         }
 306
 307         return ret;
 308 }
 309
 310 static void __init rk312x_dt_init_timer(void)
 311 {
 312         rockchip_pmu_ops.set_power_domain = rk312x_sys_set_power_domain;
 313         rockchip_pmu_ops.power_domain_is_on = rk312x_pmu_power_domain_is_on;
 314         rockchip_pmu_ops.set_idle_request = rk312x_pmu_set_idle_request;
 315         of_clk_init(NULL);
 316         clocksource_of_init();
 317         of_dvfs_init();
 318 }
 319
 320 static void __init rk312x_reserve(void)
 321 {
 322         /* reserve memory for ION */
 323         rockchip_ion_reserve();
 324 }
 325 #ifdef CONFIG_PM
 326 static void __init rk321x_init_suspend(void);
 327 #endif
 328 static void __init rk312x_init_late(void)
 329 {
 330 #ifdef CONFIG_PM
 331         rk321x_init_suspend();
 332 #endif
 333 }
 334
 335 static void rk312x_restart(char mode, const char *cmd)
 336 {
 337         u32 boot_flag, boot_mode;
 338
 339         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 340
 341         /* for loader */
 342         writel_relaxed(boot_flag, RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
 343         /* for linux */
 344         writel_relaxed(boot_mode, RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
 345
 346         dsb();
 347
 348         /* pll enter slow mode */
 349         writel_relaxed(0x30110000, RK_CRU_VIRT + RK312X_CRU_MODE_CON);
 350         dsb();
 351         writel_relaxed(0xeca8, RK_CRU_VIRT + RK312X_CRU_GLB_SRST_SND_VALUE);
 352         dsb();
 353 }
 354
 355 DT_MACHINE_START(RK3126_DT, "Rockchip RK3126")
 356         .smp            = smp_ops(rockchip_smp_ops),
 357         .map_io         = rk3126_dt_map_io,
 358         .init_time      = rk312x_dt_init_timer,
 359         .dt_compat      = rk3126_dt_compat,
 360         .init_late      = rk312x_init_late,
 361         .reserve        = rk312x_reserve,
 362         .restart        = rk312x_restart,
 363 MACHINE_END
 364
 365 DT_MACHINE_START(RK3128_DT, "Rockchip RK3128")
 366         .smp            = smp_ops(rockchip_smp_ops),
 367         .map_io         = rk3128_dt_map_io,
 368         .init_time      = rk312x_dt_init_timer,
 369         .dt_compat      = rk3128_dt_compat,
 370         .init_late      = rk312x_init_late,
 371         .reserve        = rk312x_reserve,
 372         .restart        = rk312x_restart,
 373 MACHINE_END
 374
 375
 376 char PIE_DATA(sram_stack)[1024];
 377 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 378
 379 static int __init rk312x_pie_init(void)
 380 {
 381         int err;
 382
 383         if (!cpu_is_rk312x())
 384                 return 0;
 385
 386         err = rockchip_pie_init();
 387         if (err)
 388                 return err;
 389
 390         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk312x);
 391         if (IS_ERR(rockchip_pie_chunk)) {
 392                 err = PTR_ERR(rockchip_pie_chunk);
 393                 pr_err("%s: failed to load section %d\n", __func__, err);
 394                 rockchip_pie_chunk = NULL;
 395                 return err;
 396         }
 397
 398         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 399         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 400
 401         return 0;
 402 }
 403 arch_initcall(rk312x_pie_init);
 404
 405 #include "ddr_rk3126.c"
 406 static int __init rk312x_ddr_init(void)
 407 {
 408         if (cpu_is_rk312x()) {
 409                 ddr_change_freq = _ddr_change_freq;
 410                 ddr_round_rate = _ddr_round_rate;
 411                 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 412                 ddr_init(DDR3_DEFAULT, 300);
 413                 }
 414         return 0;
 415 }
 416 arch_initcall_sync(rk312x_ddr_init);
 417
 418 #ifdef CONFIG_PM
 419 static u32 rk_pmu_pwrdn_st;
 420 static inline void rk_pm_soc_pd_suspend(void)
 421 {
 422         rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST);
 423         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 424                 rk312x_sys_set_power_domain(PD_GPU, false);
 425
 426         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 427                 rk312x_sys_set_power_domain(PD_VIO, false);
 428
 429         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 430                 rk312x_sys_set_power_domain(PD_VIDEO, false);
 431 }
 432 static inline void rk_pm_soc_pd_resume(void)
 433 {
 434         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 435                 rk312x_sys_set_power_domain(PD_VIDEO, true);
 436
 437         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 438                 rk312x_sys_set_power_domain(PD_VIO, true);
 439
 440         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 441                 rk312x_sys_set_power_domain(PD_GPU, true);
 442 }
 443 static void __init rk321x_init_suspend(void)
 444 {
 445         pr_info("%s\n", __func__);
 446         rockchip_suspend_init();
 447         rk312x_suspend_init();
 448         rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume);
 449 }
 450 #endif