arch/arm/mach-rockchip/rk312x.c

   1 /*
   2  * Device Tree support for Rockchip RK3288
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/rockchip/common.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/cru.h>
  29 #include <linux/rockchip/dvfs.h>
  30 #include <linux/rockchip/grf.h>
  31 #include <linux/rockchip/iomap.h>
  32 #include <linux/rockchip/pmu.h>
  33 /*#include <asm/cpuidle.h>*/
  34 #include <asm/cputype.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include "cpu_axi.h"
  38 #include "loader.h"
  39 #define CPU 312x
  40 #include "sram.h"
  41 #include "pm.h"
  42 #include "pm-rk312x.c"
  43 #define RK312X_DEVICE(name) \
  44         { \
  45                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  46                 .pfn            = __phys_to_pfn(RK312X_##name##_PHYS), \
  47                 .length         = RK312X_##name##_SIZE, \
  48                 .type           = MT_DEVICE, \
  49         }
  50
  51 static const char * const rk3126_dt_compat[] __initconst = {
  52         "rockchip,rk3126",
  53         NULL,
  54 };
  55
  56 static const char * const rk3128_dt_compat[] __initconst = {
  57         "rockchip,rk3128",
  58         NULL,
  59 };
  60
  61 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  62 #define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  63
  64 static struct map_desc rk312x_io_desc[] __initdata = {
  65         RK312X_DEVICE(CRU),
  66         RK312X_DEVICE(GRF),
  67         RK312X_DEVICE(ROM),
  68         RK312X_DEVICE(PMU),
  69         RK312X_DEVICE(EFUSE),
  70         RK312X_DEVICE(TIMER),
  71         RK312X_DEVICE(CPU_AXI_BUS),
  72         RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE),
  73         RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE),
  74         RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE),
  75         RK_DEVICE(RK_GPIO_VIRT(0), RK312X_GPIO0_PHYS, RK312X_GPIO_SIZE),
  76         RK_DEVICE(RK_GPIO_VIRT(1), RK312X_GPIO1_PHYS, RK312X_GPIO_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(2), RK312X_GPIO2_PHYS, RK312X_GPIO_SIZE),
  78         RK_DEVICE(RK_GPIO_VIRT(3), RK312X_GPIO3_PHYS, RK312X_GPIO_SIZE),
  79         RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
  80         RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
  81         RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
  82 };
  83 static void usb_uart_init(void)
  84 {
  85 #ifdef CONFIG_RK_USB_UART
  86         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_STATUS0);
  87 #endif
  88         writel_relaxed(0x34000000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
  89 #ifdef CONFIG_RK_USB_UART
  90         if (!(soc_status0 & (1 << 5)) && (soc_status0 & (1 << 8))) {
  91                 /* software control usb phy enable */
  92                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK312X_GRF_UOC0_CON0);
  93                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
  94         }
  95 #endif
  96
  97         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
  98         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
  99         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 100         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 101         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 102         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 103 }
 104
 105 static void __init rk312x_dt_map_io(void)
 106 {
 107         u32 v;
 108
 109         iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc));
 110         debug_ll_io_init();
 111         usb_uart_init();
 112
 113         /* pmu reset by second global soft reset */
 114         v = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 115         v &= ~(3 << 12);
 116         v |= 1 << 12;
 117         writel_relaxed(v, RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 118
 119         /* enable timer5 for core */
 120         writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10);
 121         dsb();
 122         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00);
 123         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04);
 124         dsb();
 125         writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10);
 126         dsb();
 127         writel_relaxed(0x80000000, RK_CRU_VIRT + RK312X_CRU_MISC_CON);
 128         dsb();
 129
 130 }
 131
 132 static void __init rk3126_dt_map_io(void)
 133 {
 134         rockchip_soc_id = ROCKCHIP_SOC_RK3126;
 135
 136         rk312x_dt_map_io();
 137 }
 138
 139 static void __init rk3128_dt_map_io(void)
 140 {
 141         rockchip_soc_id = ROCKCHIP_SOC_RK3128;
 142
 143         rk312x_dt_map_io();
 144 }
 145 static DEFINE_SPINLOCK(pmu_idle_lock);
 146 static const u8 pmu_idle_map[] = {
 147         [IDLE_REQ_PERI] = 0,
 148         [IDLE_REQ_VIDEO] = 1,
 149         [IDLE_REQ_VIO] = 2,
 150         [IDLE_REQ_GPU] = 3,
 151         [IDLE_REQ_CORE] = 4,
 152         [IDLE_REQ_SYS] = 5,
 153         [IDLE_REQ_MSCH] = 6,
 154         [IDLE_REQ_CRYPTO] = 7,
 155
 156 };
 157 static int rk312x_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 158 {
 159         u32 val;
 160         unsigned long flags;
 161         u32 bit = pmu_idle_map[req];
 162         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 163         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 164         u32 mask = BIT(bit);
 165
 166         spin_lock_irqsave(&pmu_idle_lock, flags);
 167         val = pmu_readl(RK312X_PMU_IDLE_REQ);
 168         if (idle)
 169                 val |= mask;
 170         else
 171                 val &= ~mask;
 172         pmu_writel(val, RK312X_PMU_IDLE_REQ);
 173         dsb();
 174
 175         while (((pmu_readl(RK312X_PMU_IDLE_ST) & idle_mask) != idle_target))
 176                 ;
 177         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 178         return 0;
 179 }
 180 static const u8 pmu_pd_map[] = {
 181         [PD_GPU] = 1,
 182         [PD_VIDEO] = 2,
 183         [PD_VIO] = 3,
 184 };
 185
 186 static const u8 pmu_st_map[] = {
 187         [PD_GPU] = 1,
 188         [PD_VIDEO] = 2,
 189         [PD_VIO] = 3,
 190 };
 191
 192 static noinline void rk312x_do_pmu_set_power_domain(enum pmu_power_domain domain
 193         , bool on)
 194 {
 195         u8 pd = pmu_pd_map[domain];
 196         u32 val = pmu_readl(RK312X_PMU_PWRDN_CON);
 197
 198         if (on)
 199                 val &= ~BIT(pd);
 200         else
 201                 val |=  BIT(pd);
 202         pmu_writel(val, RK312X_PMU_PWRDN_CON);
 203         dsb();
 204
 205         while ((pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 206                 ;
 207 }
 208
 209 static bool rk312x_pmu_power_domain_is_on(enum pmu_power_domain pd)
 210 {
 211         /*1"b0: power on, 1'b1: power off*/
 212         return !(pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 213 }
 214 static DEFINE_SPINLOCK(pmu_pd_lock);
 215 static u32 rga_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 216 static u32 ebc_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 217 static u32 iep_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 218 static u32 lcdc0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 219 static u32 vip0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 220 static u32 gpu_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 221 static u32 video_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 222
 223 #define SAVE_QOS(array, NAME) RK312X_CPU_AXI_SAVE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 224 #define RESTORE_QOS(array, NAME) RK312X_CPU_AXI_RESTORE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 225
 226 static int rk312x_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 227 {
 228         unsigned long flags;
 229
 230         spin_lock_irqsave(&pmu_pd_lock, flags);
 231         if (rk312x_pmu_power_domain_is_on(pd) == on)
 232                 goto out;
 233         if (!on) {
 234                 if (pd == PD_GPU) {
 235                         SAVE_QOS(gpu_qos, GPU);
 236                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, true);
 237                 } else if (pd == PD_VIO) {
 238                         SAVE_QOS(rga_qos, VIO_RGA);
 239                         SAVE_QOS(ebc_qos, VIO_EBC);
 240                         SAVE_QOS(iep_qos, VIO_IEP);
 241                         SAVE_QOS(lcdc0_qos, VIO_LCDC0);
 242                         SAVE_QOS(vip0_qos, VIO_VIP0);
 243                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, true);
 244                 } else if (pd == PD_VIDEO) {
 245                         SAVE_QOS(video_qos, VIDEO);
 246                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 247                 }
 248         }
 249
 250         rk312x_do_pmu_set_power_domain(pd, on);
 251
 252         if (on) {
 253                 if (pd == PD_GPU) {
 254                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, false);
 255                         RESTORE_QOS(gpu_qos, GPU);
 256                 } else if (pd == PD_VIO) {
 257                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, false);
 258                         RESTORE_QOS(rga_qos, VIO_RGA);
 259                         RESTORE_QOS(ebc_qos, VIO_EBC);
 260                         RESTORE_QOS(iep_qos, VIO_IEP);
 261                         RESTORE_QOS(lcdc0_qos, VIO_LCDC0);
 262                         RESTORE_QOS(vip0_qos, VIO_VIP0);
 263                 } else if (pd == PD_VIDEO) {
 264                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 265                         RESTORE_QOS(video_qos, VIDEO);
 266                 }
 267         }
 268 out:
 269         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 270
 271         return 0;
 272 }
 273 extern void secondary_startup(void);
 274 static int rk312x_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 275 {
 276         u32 clks_save[RK312X_CRU_CLKGATES_CON_CNT];
 277         u32 clks_ungating[RK312X_CRU_CLKGATES_CON_CNT];
 278         u32 i, ret = 0;
 279
 280         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 281                 clks_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 282                 clks_ungating[i] = 0;
 283         }
 284         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 285                 cru_writel(0xffff0000, RK312X_CRU_CLKGATES_CON(i));
 286
 287         if (on) {
 288 #ifdef CONFIG_SMP
 289                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 290                         writel_relaxed(0x20000 << (pd - PD_CPU_1),
 291                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 292                         dsb();
 293                         udelay(10);
 294                         writel_relaxed(virt_to_phys(secondary_startup),
 295                                        RK312X_IMEM_VIRT + 8);
 296                         writel_relaxed(0xDEADBEAF, RK312X_IMEM_VIRT + 4);
 297                         dsb_sev();
 298                 }
 299 #endif
 300         } else {
 301 #ifdef CONFIG_SMP
 302                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 303                         writel_relaxed(0x20002 << (pd - PD_CPU_1),
 304                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 305                         dsb();
 306                 }
 307 #endif
 308         }
 309
 310         if (((pd == PD_GPU) || (pd == PD_VIO) || (pd == PD_VIDEO)))
 311                 ret = rk312x_pmu_set_power_domain(pd, on);
 312
 313         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 314                 cru_writel(clks_save[i] | 0xffff0000
 315                         , RK312X_CRU_CLKGATES_CON(i));
 316         }
 317
 318         return ret;
 319 }
 320
 321 static void __init rk312x_dt_init_timer(void)
 322 {
 323         rockchip_pmu_ops.set_power_domain = rk312x_sys_set_power_domain;
 324         rockchip_pmu_ops.power_domain_is_on = rk312x_pmu_power_domain_is_on;
 325         rockchip_pmu_ops.set_idle_request = rk312x_pmu_set_idle_request;
 326         of_clk_init(NULL);
 327         clocksource_of_init();
 328         of_dvfs_init();
 329 }
 330
 331 static void __init rk312x_reserve(void)
 332 {
 333         /* reserve memory for ION */
 334         rockchip_ion_reserve();
 335 }
 336 #ifdef CONFIG_PM
 337 static void __init rk321x_init_suspend(void);
 338 #endif
 339 static void __init rk312x_init_late(void)
 340 {
 341 #ifdef CONFIG_PM
 342         rk321x_init_suspend();
 343 #endif
 344 }
 345
 346 static void rk312x_restart(char mode, const char *cmd)
 347 {
 348         u32 boot_flag, boot_mode;
 349
 350         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 351
 352         /* for loader */
 353         writel_relaxed(boot_flag, RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
 354         /* for linux */
 355         writel_relaxed(boot_mode, RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
 356
 357         dsb();
 358
 359         /* pll enter slow mode */
 360         writel_relaxed(0x11010000, RK_CRU_VIRT + RK312X_CRU_MODE_CON);
 361         dsb();
 362         writel_relaxed(0xeca8, RK_CRU_VIRT + RK312X_CRU_GLB_SRST_SND_VALUE);
 363         dsb();
 364 }
 365
 366 DT_MACHINE_START(RK3126_DT, "Rockchip RK3126")
 367         .smp            = smp_ops(rockchip_smp_ops),
 368         .map_io         = rk3126_dt_map_io,
 369         .init_time      = rk312x_dt_init_timer,
 370         .dt_compat      = rk3126_dt_compat,
 371         .init_late      = rk312x_init_late,
 372         .reserve        = rk312x_reserve,
 373         .restart        = rk312x_restart,
 374 MACHINE_END
 375
 376 DT_MACHINE_START(RK3128_DT, "Rockchip RK3128")
 377         .smp            = smp_ops(rockchip_smp_ops),
 378         .map_io         = rk3128_dt_map_io,
 379         .init_time      = rk312x_dt_init_timer,
 380         .dt_compat      = rk3128_dt_compat,
 381         .init_late      = rk312x_init_late,
 382         .reserve        = rk312x_reserve,
 383         .restart        = rk312x_restart,
 384 MACHINE_END
 385
 386
 387 char PIE_DATA(sram_stack)[1024];
 388 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 389
 390 static int __init rk312x_pie_init(void)
 391 {
 392         int err;
 393
 394         if (!cpu_is_rk312x())
 395                 return 0;
 396
 397         err = rockchip_pie_init();
 398         if (err)
 399                 return err;
 400
 401         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk312x);
 402         if (IS_ERR(rockchip_pie_chunk)) {
 403                 err = PTR_ERR(rockchip_pie_chunk);
 404                 pr_err("%s: failed to load section %d\n", __func__, err);
 405                 rockchip_pie_chunk = NULL;
 406                 return err;
 407         }
 408
 409         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 410         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 411
 412         return 0;
 413 }
 414 arch_initcall(rk312x_pie_init);
 415
 416 #include "ddr_rk3126.c"
 417 static int __init rk312x_ddr_init(void)
 418 {
 419         if (cpu_is_rk312x()) {
 420                 ddr_change_freq = _ddr_change_freq;
 421                 ddr_round_rate = _ddr_round_rate;
 422                 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 423                 ddr_bandwidth_get = _ddr_bandwidth_get;
 424                 ddr_init(DDR3_DEFAULT, 300);
 425                 }
 426         return 0;
 427 }
 428 arch_initcall_sync(rk312x_ddr_init);
 429
 430 #ifdef CONFIG_PM
 431 static u32 rk_pmu_pwrdn_st;
 432 static inline void rk_pm_soc_pd_suspend(void)
 433 {
 434         rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST);
 435         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 436                 rk312x_sys_set_power_domain(PD_GPU, false);
 437
 438         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 439                 rk312x_sys_set_power_domain(PD_VIO, false);
 440
 441         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 442                 rk312x_sys_set_power_domain(PD_VIDEO, false);
 443 }
 444 static inline void rk_pm_soc_pd_resume(void)
 445 {
 446         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 447                 rk312x_sys_set_power_domain(PD_VIDEO, true);
 448
 449         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 450                 rk312x_sys_set_power_domain(PD_VIO, true);
 451
 452         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 453                 rk312x_sys_set_power_domain(PD_GPU, true);
 454 }
 455 static void __init rk321x_init_suspend(void)
 456 {
 457         pr_info("%s\n", __func__);
 458         rockchip_suspend_init();
 459         rkpm_pie_init();
 460         rk312x_suspend_init();
 461         rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume);
 462 }
 463 #endif