arch/arm/mach-rockchip/rk312x.c

   1 /*
   2  * Device Tree support for Rockchip RK3288
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/rockchip/common.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/cru.h>
  29 #include <linux/rockchip/dvfs.h>
  30 #include <linux/rockchip/grf.h>
  31 #include <linux/rockchip/iomap.h>
  32 #include <linux/rockchip/pmu.h>
  33 /*#include <asm/cpuidle.h>*/
  34 #include <asm/cputype.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include "cpu_axi.h"
  38 #include "loader.h"
  39 #define CPU 312x
  40 #include "sram.h"
  41 #include "pm.h"
  42 #include "pm-rk312x.c"
  43 #define RK312X_DEVICE(name) \
  44         { \
  45                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  46                 .pfn            = __phys_to_pfn(RK312X_##name##_PHYS), \
  47                 .length         = RK312X_##name##_SIZE, \
  48                 .type           = MT_DEVICE, \
  49         }
  50
  51 static const char * const rk3126_dt_compat[] __initconst = {
  52         "rockchip,rk3126",
  53         NULL,
  54 };
  55
  56 static const char * const rk3128_dt_compat[] __initconst = {
  57         "rockchip,rk3128",
  58         NULL,
  59 };
  60
  61 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  62 #define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  63
  64 static struct map_desc rk312x_io_desc[] __initdata = {
  65         RK312X_DEVICE(CRU),
  66         RK312X_DEVICE(GRF),
  67         RK312X_DEVICE(ROM),
  68         RK312X_DEVICE(PMU),
  69         RK312X_DEVICE(EFUSE),
  70         RK312X_DEVICE(TIMER),
  71         RK312X_DEVICE(CPU_AXI_BUS),
  72         RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE),
  73         RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE),
  74         RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE),
  75         RK_DEVICE(RK_GPIO_VIRT(0), RK312X_GPIO0_PHYS, RK312X_GPIO_SIZE),
  76         RK_DEVICE(RK_GPIO_VIRT(1), RK312X_GPIO1_PHYS, RK312X_GPIO_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(2), RK312X_GPIO2_PHYS, RK312X_GPIO_SIZE),
  78         RK_DEVICE(RK_GPIO_VIRT(3), RK312X_GPIO3_PHYS, RK312X_GPIO_SIZE),
  79         RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
  80         RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
  81         RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
  82         RK_DEVICE(RK_PWM_VIRT, RK312X_PWM_PHYS, RK312X_PWM_SIZE),
  83 };
  84
  85 static void __init rk312x_boot_mode_init(void)
  86 {
  87         u32 flag = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
  88         u32 mode = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
  89         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_RST_ST);
  90
  91         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  92                 mode = BOOT_MODE_RECOVERY;
  93         if (rst_st & ((1 << 2) | (1 << 3)))
  94                 mode = BOOT_MODE_WATCHDOG;
  95
  96         rockchip_boot_mode_init(flag, mode);
  97 }
  98
  99 static void usb_uart_init(void)
 100 {
 101 #ifdef CONFIG_RK_USB_UART
 102         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_STATUS0);
 103 #endif
 104         writel_relaxed(0x34000000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 105 #ifdef CONFIG_RK_USB_UART
 106         if (!(soc_status0 & (1 << 5)) && (soc_status0 & (1 << 8))) {
 107                 /* software control usb phy enable */
 108                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK312X_GRF_UOC0_CON0);
 109                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 110         }
 111 #endif
 112
 113         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
 114         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 115         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 116         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 117         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 118         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 119 }
 120
 121 static void __init rk312x_dt_map_io(void)
 122 {
 123         u32 v;
 124
 125         iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc));
 126         debug_ll_io_init();
 127         usb_uart_init();
 128
 129         /* pmu reset by second global soft reset */
 130         v = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 131         v &= ~(3 << 12);
 132         v |= 1 << 12;
 133         writel_relaxed(v, RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 134
 135         /* enable timer5 for core */
 136         writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10);
 137         dsb();
 138         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00);
 139         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04);
 140         dsb();
 141         writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10);
 142         dsb();
 143         writel_relaxed(0x80000000, RK_CRU_VIRT + RK312X_CRU_MISC_CON);
 144         dsb();
 145
 146         rk312x_boot_mode_init();
 147         rockchip_efuse_init();
 148 }
 149
 150 static void __init rk3126_dt_map_io(void)
 151 {
 152         rockchip_soc_id = ROCKCHIP_SOC_RK3126;
 153
 154         rk312x_dt_map_io();
 155 }
 156
 157 static void __init rk3128_dt_map_io(void)
 158 {
 159         rockchip_soc_id = ROCKCHIP_SOC_RK3128;
 160
 161         rk312x_dt_map_io();
 162 }
 163 static DEFINE_SPINLOCK(pmu_idle_lock);
 164 static const u8 pmu_idle_map[] = {
 165         [IDLE_REQ_PERI] = 0,
 166         [IDLE_REQ_VIDEO] = 1,
 167         [IDLE_REQ_VIO] = 2,
 168         [IDLE_REQ_GPU] = 3,
 169         [IDLE_REQ_CORE] = 4,
 170         [IDLE_REQ_SYS] = 5,
 171         [IDLE_REQ_MSCH] = 6,
 172         [IDLE_REQ_CRYPTO] = 7,
 173
 174 };
 175 static int rk312x_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 176 {
 177         u32 val;
 178         unsigned long flags;
 179         u32 bit = pmu_idle_map[req];
 180         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 181         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 182         u32 mask = BIT(bit);
 183
 184         spin_lock_irqsave(&pmu_idle_lock, flags);
 185         val = pmu_readl(RK312X_PMU_IDLE_REQ);
 186         if (idle)
 187                 val |= mask;
 188         else
 189                 val &= ~mask;
 190         pmu_writel(val, RK312X_PMU_IDLE_REQ);
 191         dsb();
 192
 193         while (((pmu_readl(RK312X_PMU_IDLE_ST) & idle_mask) != idle_target))
 194                 ;
 195         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 196         return 0;
 197 }
 198 static const u8 pmu_pd_map[] = {
 199         [PD_GPU] = 1,
 200         [PD_VIDEO] = 2,
 201         [PD_VIO] = 3,
 202 };
 203
 204 static const u8 pmu_st_map[] = {
 205         [PD_GPU] = 1,
 206         [PD_VIDEO] = 2,
 207         [PD_VIO] = 3,
 208 };
 209
 210 static noinline void rk312x_do_pmu_set_power_domain(enum pmu_power_domain domain
 211         , bool on)
 212 {
 213         u8 pd = pmu_pd_map[domain];
 214         u32 val = pmu_readl(RK312X_PMU_PWRDN_CON);
 215
 216         if (on)
 217                 val &= ~BIT(pd);
 218         else
 219                 val |=  BIT(pd);
 220         pmu_writel(val, RK312X_PMU_PWRDN_CON);
 221         dsb();
 222
 223         while ((pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 224                 ;
 225 }
 226
 227 static bool rk312x_pmu_power_domain_is_on(enum pmu_power_domain pd)
 228 {
 229         /*1"b0: power on, 1'b1: power off*/
 230         return !(pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 231 }
 232 static DEFINE_SPINLOCK(pmu_pd_lock);
 233 static u32 rga_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 234 static u32 ebc_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 235 static u32 iep_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 236 static u32 lcdc0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 237 static u32 vip0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 238 static u32 gpu_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 239 static u32 video_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 240
 241 #define SAVE_QOS(array, NAME) RK312X_CPU_AXI_SAVE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 242 #define RESTORE_QOS(array, NAME) RK312X_CPU_AXI_RESTORE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 243
 244 static int rk312x_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 245 {
 246         unsigned long flags;
 247
 248         spin_lock_irqsave(&pmu_pd_lock, flags);
 249         if (rk312x_pmu_power_domain_is_on(pd) == on)
 250                 goto out;
 251         if (!on) {
 252                 if (pd == PD_GPU) {
 253                         SAVE_QOS(gpu_qos, GPU);
 254                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, true);
 255                 } else if (pd == PD_VIO) {
 256                         SAVE_QOS(rga_qos, VIO_RGA);
 257                         SAVE_QOS(ebc_qos, VIO_EBC);
 258                         SAVE_QOS(iep_qos, VIO_IEP);
 259                         SAVE_QOS(lcdc0_qos, VIO_LCDC0);
 260                         SAVE_QOS(vip0_qos, VIO_VIP0);
 261                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, true);
 262                 } else if (pd == PD_VIDEO) {
 263                         SAVE_QOS(video_qos, VIDEO);
 264                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 265                 }
 266         }
 267
 268         rk312x_do_pmu_set_power_domain(pd, on);
 269
 270         if (on) {
 271                 if (pd == PD_GPU) {
 272                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, false);
 273                         RESTORE_QOS(gpu_qos, GPU);
 274                 } else if (pd == PD_VIO) {
 275                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, false);
 276                         RESTORE_QOS(rga_qos, VIO_RGA);
 277                         RESTORE_QOS(ebc_qos, VIO_EBC);
 278                         RESTORE_QOS(iep_qos, VIO_IEP);
 279                         RESTORE_QOS(lcdc0_qos, VIO_LCDC0);
 280                         RESTORE_QOS(vip0_qos, VIO_VIP0);
 281                 } else if (pd == PD_VIDEO) {
 282                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 283                         RESTORE_QOS(video_qos, VIDEO);
 284                 }
 285         }
 286 out:
 287         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 288
 289         return 0;
 290 }
 291 extern void secondary_startup(void);
 292 static int rk312x_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 293 {
 294         u32 clks_save[RK312X_CRU_CLKGATES_CON_CNT];
 295         u32 clks_ungating[RK312X_CRU_CLKGATES_CON_CNT];
 296         u32 i, ret = 0;
 297
 298         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 299                 clks_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 300                 clks_ungating[i] = 0;
 301         }
 302         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 303                 cru_writel(0xffff0000, RK312X_CRU_CLKGATES_CON(i));
 304
 305         if (on) {
 306 #ifdef CONFIG_SMP
 307                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 308                         writel_relaxed(0x20000 << (pd - PD_CPU_1),
 309                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 310                         dsb();
 311                         udelay(10);
 312                         writel_relaxed(virt_to_phys(secondary_startup),
 313                                        RK312X_IMEM_VIRT + 8);
 314                         writel_relaxed(0xDEADBEAF, RK312X_IMEM_VIRT + 4);
 315                         dsb_sev();
 316                 }
 317 #endif
 318         } else {
 319 #ifdef CONFIG_SMP
 320                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 321                         writel_relaxed(0x20002 << (pd - PD_CPU_1),
 322                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 323                         dsb();
 324                 }
 325 #endif
 326         }
 327
 328         if (((pd == PD_GPU) || (pd == PD_VIO) || (pd == PD_VIDEO)))
 329                 ret = rk312x_pmu_set_power_domain(pd, on);
 330
 331         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 332                 cru_writel(clks_save[i] | 0xffff0000
 333                         , RK312X_CRU_CLKGATES_CON(i));
 334         }
 335
 336         return ret;
 337 }
 338
 339 static void __init rk312x_dt_init_timer(void)
 340 {
 341         rockchip_pmu_ops.set_power_domain = rk312x_sys_set_power_domain;
 342         rockchip_pmu_ops.power_domain_is_on = rk312x_pmu_power_domain_is_on;
 343         rockchip_pmu_ops.set_idle_request = rk312x_pmu_set_idle_request;
 344         of_clk_init(NULL);
 345         clocksource_of_init();
 346         of_dvfs_init();
 347 }
 348
 349 static void __init rk312x_reserve(void)
 350 {
 351         /* reserve memory for ION */
 352         rockchip_ion_reserve();
 353 }
 354 #ifdef CONFIG_PM
 355 static void __init rk321x_init_suspend(void);
 356 #endif
 357 static void __init rk312x_init_late(void)
 358 {
 359 #ifdef CONFIG_PM
 360         rk321x_init_suspend();
 361 #endif
 362         if (rockchip_jtag_enabled)
 363                 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
 364 }
 365
 366 static void rk312x_restart(char mode, const char *cmd)
 367 {
 368         u32 boot_flag, boot_mode;
 369
 370         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 371
 372         /* for loader */
 373         writel_relaxed(boot_flag, RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
 374         /* for linux */
 375         writel_relaxed(boot_mode, RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
 376
 377         dsb();
 378
 379         /* pll enter slow mode */
 380         writel_relaxed(0x11010000, RK_CRU_VIRT + RK312X_CRU_MODE_CON);
 381         dsb();
 382         writel_relaxed(0xeca8, RK_CRU_VIRT + RK312X_CRU_GLB_SRST_SND_VALUE);
 383         dsb();
 384 }
 385
 386 DT_MACHINE_START(RK3126_DT, "Rockchip RK3126")
 387         .smp            = smp_ops(rockchip_smp_ops),
 388         .map_io         = rk3126_dt_map_io,
 389         .init_time      = rk312x_dt_init_timer,
 390         .dt_compat      = rk3126_dt_compat,
 391         .init_late      = rk312x_init_late,
 392         .reserve        = rk312x_reserve,
 393         .restart        = rk312x_restart,
 394 MACHINE_END
 395
 396 DT_MACHINE_START(RK3128_DT, "Rockchip RK3128")
 397         .smp            = smp_ops(rockchip_smp_ops),
 398         .map_io         = rk3128_dt_map_io,
 399         .init_time      = rk312x_dt_init_timer,
 400         .dt_compat      = rk3128_dt_compat,
 401         .init_late      = rk312x_init_late,
 402         .reserve        = rk312x_reserve,
 403         .restart        = rk312x_restart,
 404 MACHINE_END
 405
 406
 407 char PIE_DATA(sram_stack)[1024];
 408 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 409
 410 static int __init rk312x_pie_init(void)
 411 {
 412         int err;
 413
 414         if (!cpu_is_rk312x())
 415                 return 0;
 416
 417         err = rockchip_pie_init();
 418         if (err)
 419                 return err;
 420
 421         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk312x);
 422         if (IS_ERR(rockchip_pie_chunk)) {
 423                 err = PTR_ERR(rockchip_pie_chunk);
 424                 pr_err("%s: failed to load section %d\n", __func__, err);
 425                 rockchip_pie_chunk = NULL;
 426                 return err;
 427         }
 428
 429         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 430         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 431
 432         return 0;
 433 }
 434 arch_initcall(rk312x_pie_init);
 435
 436 #include "ddr_rk3126.c"
 437 static int __init rk312x_ddr_init(void)
 438 {
 439         if (cpu_is_rk312x()) {
 440                 ddr_change_freq = _ddr_change_freq;
 441                 ddr_round_rate = _ddr_round_rate;
 442                 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 443                 ddr_bandwidth_get = _ddr_bandwidth_get;
 444                 ddr_init(DDR3_DEFAULT, 300);
 445                 }
 446         return 0;
 447 }
 448 arch_initcall_sync(rk312x_ddr_init);
 449
 450 #ifdef CONFIG_PM
 451 static u32 rk_pmu_pwrdn_st;
 452 static inline void rk_pm_soc_pd_suspend(void)
 453 {
 454         rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST);
 455         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 456                 rk312x_sys_set_power_domain(PD_GPU, false);
 457
 458         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 459                 rk312x_sys_set_power_domain(PD_VIO, false);
 460
 461         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 462                 rk312x_sys_set_power_domain(PD_VIDEO, false);
 463 }
 464 static inline void rk_pm_soc_pd_resume(void)
 465 {
 466         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 467                 rk312x_sys_set_power_domain(PD_VIDEO, true);
 468
 469         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 470                 rk312x_sys_set_power_domain(PD_VIO, true);
 471
 472         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 473                 rk312x_sys_set_power_domain(PD_GPU, true);
 474 }
 475 static void __init rk321x_init_suspend(void)
 476 {
 477         pr_info("%s\n", __func__);
 478         rockchip_suspend_init();
 479         rkpm_pie_init();
 480         rk312x_suspend_init();
 481         rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume);
 482 }
 483 #endif