arch/arm/mach-rockchip/rk312x.c

   1 /*
   2  * Device Tree support for Rockchip RK3288
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/rockchip/common.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/cru.h>
  29 #include <linux/rockchip/dvfs.h>
  30 #include <linux/rockchip/grf.h>
  31 #include <linux/rockchip/iomap.h>
  32 #include <linux/rockchip/pmu.h>
  33 /*#include <asm/cpuidle.h>*/
  34 #include <asm/cputype.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include "cpu_axi.h"
  38 #include "loader.h"
  39 #define CPU 312x
  40 #include "sram.h"
  41 #include "pm.h"
  42 #include "pm-rk312x.c"
  43 #define RK312X_DEVICE(name) \
  44         { \
  45                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  46                 .pfn            = __phys_to_pfn(RK312X_##name##_PHYS), \
  47                 .length         = RK312X_##name##_SIZE, \
  48                 .type           = MT_DEVICE, \
  49         }
  50
  51 static const char * const rk3126_dt_compat[] __initconst = {
  52         "rockchip,rk3126",
  53         NULL,
  54 };
  55
  56 static const char * const rk3128_dt_compat[] __initconst = {
  57         "rockchip,rk3128",
  58         NULL,
  59 };
  60
  61 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  62 #define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  63
  64 static struct map_desc rk312x_io_desc[] __initdata = {
  65         RK312X_DEVICE(CRU),
  66         RK312X_DEVICE(GRF),
  67         RK312X_DEVICE(ROM),
  68         RK312X_DEVICE(PMU),
  69         RK312X_DEVICE(EFUSE),
  70         RK312X_DEVICE(TIMER),
  71         RK312X_DEVICE(CPU_AXI_BUS),
  72         RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE),
  73         RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE),
  74         RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE),
  75         RK_DEVICE(RK_GPIO_VIRT(0), RK312X_GPIO0_PHYS, RK312X_GPIO_SIZE),
  76         RK_DEVICE(RK_GPIO_VIRT(1), RK312X_GPIO1_PHYS, RK312X_GPIO_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(2), RK312X_GPIO2_PHYS, RK312X_GPIO_SIZE),
  78         RK_DEVICE(RK_GPIO_VIRT(3), RK312X_GPIO3_PHYS, RK312X_GPIO_SIZE),
  79         RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
  80         RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
  81         RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
  82 };
  83
  84 static void __init rk312x_boot_mode_init(void)
  85 {
  86         u32 flag = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
  87         u32 mode = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
  88         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_RST_ST);
  89
  90         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  91                 mode = BOOT_MODE_RECOVERY;
  92         if (rst_st & ((1 << 2) | (1 << 3)))
  93                 mode = BOOT_MODE_WATCHDOG;
  94
  95         rockchip_boot_mode_init(flag, mode);
  96 }
  97
  98 static void usb_uart_init(void)
  99 {
 100 #ifdef CONFIG_RK_USB_UART
 101         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_STATUS0);
 102 #endif
 103         writel_relaxed(0x34000000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 104 #ifdef CONFIG_RK_USB_UART
 105         if (!(soc_status0 & (1 << 5)) && (soc_status0 & (1 << 8))) {
 106                 /* software control usb phy enable */
 107                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK312X_GRF_UOC0_CON0);
 108                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 109         }
 110 #endif
 111
 112         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
 113         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 114         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 115         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 116         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 117         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 118 }
 119
 120 static void __init rk312x_dt_map_io(void)
 121 {
 122         u32 v;
 123
 124         iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc));
 125         debug_ll_io_init();
 126         usb_uart_init();
 127
 128         /* pmu reset by second global soft reset */
 129         v = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 130         v &= ~(3 << 12);
 131         v |= 1 << 12;
 132         writel_relaxed(v, RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 133
 134         /* enable timer5 for core */
 135         writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10);
 136         dsb();
 137         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00);
 138         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04);
 139         dsb();
 140         writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10);
 141         dsb();
 142         writel_relaxed(0x80000000, RK_CRU_VIRT + RK312X_CRU_MISC_CON);
 143         dsb();
 144
 145         rk312x_boot_mode_init();
 146 }
 147
 148 static void __init rk3126_dt_map_io(void)
 149 {
 150         rockchip_soc_id = ROCKCHIP_SOC_RK3126;
 151
 152         rk312x_dt_map_io();
 153 }
 154
 155 static void __init rk3128_dt_map_io(void)
 156 {
 157         rockchip_soc_id = ROCKCHIP_SOC_RK3128;
 158
 159         rk312x_dt_map_io();
 160 }
 161 static DEFINE_SPINLOCK(pmu_idle_lock);
 162 static const u8 pmu_idle_map[] = {
 163         [IDLE_REQ_PERI] = 0,
 164         [IDLE_REQ_VIDEO] = 1,
 165         [IDLE_REQ_VIO] = 2,
 166         [IDLE_REQ_GPU] = 3,
 167         [IDLE_REQ_CORE] = 4,
 168         [IDLE_REQ_SYS] = 5,
 169         [IDLE_REQ_MSCH] = 6,
 170         [IDLE_REQ_CRYPTO] = 7,
 171
 172 };
 173 static int rk312x_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 174 {
 175         u32 val;
 176         unsigned long flags;
 177         u32 bit = pmu_idle_map[req];
 178         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 179         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 180         u32 mask = BIT(bit);
 181
 182         spin_lock_irqsave(&pmu_idle_lock, flags);
 183         val = pmu_readl(RK312X_PMU_IDLE_REQ);
 184         if (idle)
 185                 val |= mask;
 186         else
 187                 val &= ~mask;
 188         pmu_writel(val, RK312X_PMU_IDLE_REQ);
 189         dsb();
 190
 191         while (((pmu_readl(RK312X_PMU_IDLE_ST) & idle_mask) != idle_target))
 192                 ;
 193         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 194         return 0;
 195 }
 196 static const u8 pmu_pd_map[] = {
 197         [PD_GPU] = 1,
 198         [PD_VIDEO] = 2,
 199         [PD_VIO] = 3,
 200 };
 201
 202 static const u8 pmu_st_map[] = {
 203         [PD_GPU] = 1,
 204         [PD_VIDEO] = 2,
 205         [PD_VIO] = 3,
 206 };
 207
 208 static noinline void rk312x_do_pmu_set_power_domain(enum pmu_power_domain domain
 209         , bool on)
 210 {
 211         u8 pd = pmu_pd_map[domain];
 212         u32 val = pmu_readl(RK312X_PMU_PWRDN_CON);
 213
 214         if (on)
 215                 val &= ~BIT(pd);
 216         else
 217                 val |=  BIT(pd);
 218         pmu_writel(val, RK312X_PMU_PWRDN_CON);
 219         dsb();
 220
 221         while ((pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 222                 ;
 223 }
 224
 225 static bool rk312x_pmu_power_domain_is_on(enum pmu_power_domain pd)
 226 {
 227         /*1"b0: power on, 1'b1: power off*/
 228         return !(pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 229 }
 230 static DEFINE_SPINLOCK(pmu_pd_lock);
 231 static u32 rga_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 232 static u32 ebc_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 233 static u32 iep_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 234 static u32 lcdc0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 235 static u32 vip0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 236 static u32 gpu_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 237 static u32 video_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 238
 239 #define SAVE_QOS(array, NAME) RK312X_CPU_AXI_SAVE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 240 #define RESTORE_QOS(array, NAME) RK312X_CPU_AXI_RESTORE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 241
 242 static int rk312x_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 243 {
 244         unsigned long flags;
 245
 246         spin_lock_irqsave(&pmu_pd_lock, flags);
 247         if (rk312x_pmu_power_domain_is_on(pd) == on)
 248                 goto out;
 249         if (!on) {
 250                 if (pd == PD_GPU) {
 251                         SAVE_QOS(gpu_qos, GPU);
 252                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, true);
 253                 } else if (pd == PD_VIO) {
 254                         SAVE_QOS(rga_qos, VIO_RGA);
 255                         SAVE_QOS(ebc_qos, VIO_EBC);
 256                         SAVE_QOS(iep_qos, VIO_IEP);
 257                         SAVE_QOS(lcdc0_qos, VIO_LCDC0);
 258                         SAVE_QOS(vip0_qos, VIO_VIP0);
 259                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, true);
 260                 } else if (pd == PD_VIDEO) {
 261                         SAVE_QOS(video_qos, VIDEO);
 262                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 263                 }
 264         }
 265
 266         rk312x_do_pmu_set_power_domain(pd, on);
 267
 268         if (on) {
 269                 if (pd == PD_GPU) {
 270                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, false);
 271                         RESTORE_QOS(gpu_qos, GPU);
 272                 } else if (pd == PD_VIO) {
 273                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, false);
 274                         RESTORE_QOS(rga_qos, VIO_RGA);
 275                         RESTORE_QOS(ebc_qos, VIO_EBC);
 276                         RESTORE_QOS(iep_qos, VIO_IEP);
 277                         RESTORE_QOS(lcdc0_qos, VIO_LCDC0);
 278                         RESTORE_QOS(vip0_qos, VIO_VIP0);
 279                 } else if (pd == PD_VIDEO) {
 280                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 281                         RESTORE_QOS(video_qos, VIDEO);
 282                 }
 283         }
 284 out:
 285         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 286
 287         return 0;
 288 }
 289 extern void secondary_startup(void);
 290 static int rk312x_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 291 {
 292         u32 clks_save[RK312X_CRU_CLKGATES_CON_CNT];
 293         u32 clks_ungating[RK312X_CRU_CLKGATES_CON_CNT];
 294         u32 i, ret = 0;
 295
 296         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 297                 clks_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 298                 clks_ungating[i] = 0;
 299         }
 300         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 301                 cru_writel(0xffff0000, RK312X_CRU_CLKGATES_CON(i));
 302
 303         if (on) {
 304 #ifdef CONFIG_SMP
 305                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 306                         writel_relaxed(0x20000 << (pd - PD_CPU_1),
 307                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 308                         dsb();
 309                         udelay(10);
 310                         writel_relaxed(virt_to_phys(secondary_startup),
 311                                        RK312X_IMEM_VIRT + 8);
 312                         writel_relaxed(0xDEADBEAF, RK312X_IMEM_VIRT + 4);
 313                         dsb_sev();
 314                 }
 315 #endif
 316         } else {
 317 #ifdef CONFIG_SMP
 318                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 319                         writel_relaxed(0x20002 << (pd - PD_CPU_1),
 320                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 321                         dsb();
 322                 }
 323 #endif
 324         }
 325
 326         if (((pd == PD_GPU) || (pd == PD_VIO) || (pd == PD_VIDEO)))
 327                 ret = rk312x_pmu_set_power_domain(pd, on);
 328
 329         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 330                 cru_writel(clks_save[i] | 0xffff0000
 331                         , RK312X_CRU_CLKGATES_CON(i));
 332         }
 333
 334         return ret;
 335 }
 336
 337 static void __init rk312x_dt_init_timer(void)
 338 {
 339         rockchip_pmu_ops.set_power_domain = rk312x_sys_set_power_domain;
 340         rockchip_pmu_ops.power_domain_is_on = rk312x_pmu_power_domain_is_on;
 341         rockchip_pmu_ops.set_idle_request = rk312x_pmu_set_idle_request;
 342         of_clk_init(NULL);
 343         clocksource_of_init();
 344         of_dvfs_init();
 345 }
 346
 347 static void __init rk312x_reserve(void)
 348 {
 349         /* reserve memory for ION */
 350         rockchip_ion_reserve();
 351 }
 352 #ifdef CONFIG_PM
 353 static void __init rk321x_init_suspend(void);
 354 #endif
 355 static void __init rk312x_init_late(void)
 356 {
 357 #ifdef CONFIG_PM
 358         rk321x_init_suspend();
 359 #endif
 360 }
 361
 362 static void rk312x_restart(char mode, const char *cmd)
 363 {
 364         u32 boot_flag, boot_mode;
 365
 366         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 367
 368         /* for loader */
 369         writel_relaxed(boot_flag, RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
 370         /* for linux */
 371         writel_relaxed(boot_mode, RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
 372
 373         dsb();
 374
 375         /* pll enter slow mode */
 376         writel_relaxed(0x11010000, RK_CRU_VIRT + RK312X_CRU_MODE_CON);
 377         dsb();
 378         writel_relaxed(0xeca8, RK_CRU_VIRT + RK312X_CRU_GLB_SRST_SND_VALUE);
 379         dsb();
 380 }
 381
 382 DT_MACHINE_START(RK3126_DT, "Rockchip RK3126")
 383         .smp            = smp_ops(rockchip_smp_ops),
 384         .map_io         = rk3126_dt_map_io,
 385         .init_time      = rk312x_dt_init_timer,
 386         .dt_compat      = rk3126_dt_compat,
 387         .init_late      = rk312x_init_late,
 388         .reserve        = rk312x_reserve,
 389         .restart        = rk312x_restart,
 390 MACHINE_END
 391
 392 DT_MACHINE_START(RK3128_DT, "Rockchip RK3128")
 393         .smp            = smp_ops(rockchip_smp_ops),
 394         .map_io         = rk3128_dt_map_io,
 395         .init_time      = rk312x_dt_init_timer,
 396         .dt_compat      = rk3128_dt_compat,
 397         .init_late      = rk312x_init_late,
 398         .reserve        = rk312x_reserve,
 399         .restart        = rk312x_restart,
 400 MACHINE_END
 401
 402
 403 char PIE_DATA(sram_stack)[1024];
 404 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 405
 406 static int __init rk312x_pie_init(void)
 407 {
 408         int err;
 409
 410         if (!cpu_is_rk312x())
 411                 return 0;
 412
 413         err = rockchip_pie_init();
 414         if (err)
 415                 return err;
 416
 417         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk312x);
 418         if (IS_ERR(rockchip_pie_chunk)) {
 419                 err = PTR_ERR(rockchip_pie_chunk);
 420                 pr_err("%s: failed to load section %d\n", __func__, err);
 421                 rockchip_pie_chunk = NULL;
 422                 return err;
 423         }
 424
 425         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 426         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 427
 428         return 0;
 429 }
 430 arch_initcall(rk312x_pie_init);
 431
 432 #include "ddr_rk3126.c"
 433 static int __init rk312x_ddr_init(void)
 434 {
 435         if (cpu_is_rk312x()) {
 436                 ddr_change_freq = _ddr_change_freq;
 437                 ddr_round_rate = _ddr_round_rate;
 438                 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 439                 ddr_bandwidth_get = _ddr_bandwidth_get;
 440                 ddr_init(DDR3_DEFAULT, 300);
 441                 }
 442         return 0;
 443 }
 444 arch_initcall_sync(rk312x_ddr_init);
 445
 446 #ifdef CONFIG_PM
 447 static u32 rk_pmu_pwrdn_st;
 448 static inline void rk_pm_soc_pd_suspend(void)
 449 {
 450         rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST);
 451         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 452                 rk312x_sys_set_power_domain(PD_GPU, false);
 453
 454         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 455                 rk312x_sys_set_power_domain(PD_VIO, false);
 456
 457         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 458                 rk312x_sys_set_power_domain(PD_VIDEO, false);
 459 }
 460 static inline void rk_pm_soc_pd_resume(void)
 461 {
 462         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 463                 rk312x_sys_set_power_domain(PD_VIDEO, true);
 464
 465         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 466                 rk312x_sys_set_power_domain(PD_VIO, true);
 467
 468         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 469                 rk312x_sys_set_power_domain(PD_GPU, true);
 470 }
 471 static void __init rk321x_init_suspend(void)
 472 {
 473         pr_info("%s\n", __func__);
 474         rockchip_suspend_init();
 475         rkpm_pie_init();
 476         rk312x_suspend_init();
 477         rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume);
 478 }
 479 #endif