arch/arm/mach-rockchip/rk312x.c

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/clocksource.h>
  17 #include <linux/cpuidle.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/irqchip.h>
  21 #include <linux/kernel.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/rockchip/common.h>
  25 #include <linux/rockchip/cpu.h>
  26 #include <linux/rockchip/cru.h>
  27 #include <linux/rockchip/dvfs.h>
  28 #include <linux/rockchip/grf.h>
  29 #include <linux/rockchip/iomap.h>
  30 #include <linux/rockchip/pmu.h>
  31 /*#include <asm/cpuidle.h>*/
  32 #include <asm/cputype.h>
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35 #include "cpu_axi.h"
  36 #include "loader.h"
  37 #include "rk3126b.h"
  38 #define CPU 312x
  39 #include "sram.h"
  40 #include "pm.h"
  41 #include "pm-rk312x.c"
  42 #define RK312X_DEVICE(name) \
  43         { \
  44                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  45                 .pfn            = __phys_to_pfn(RK312X_##name##_PHYS), \
  46                 .length         = RK312X_##name##_SIZE, \
  47                 .type           = MT_DEVICE, \
  48         }
  49
  50 static const char * const rk3126_dt_compat[] __initconst = {
  51         "rockchip,rk3126",
  52         NULL,
  53 };
  54
  55 static const char * const rk3128_dt_compat[] __initconst = {
  56         "rockchip,rk3128",
  57         NULL,
  58 };
  59
  60 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  61 #define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  62
  63 static struct map_desc rk312x_io_desc[] __initdata = {
  64         RK312X_DEVICE(CRU),
  65         RK312X_DEVICE(GRF),
  66         RK312X_DEVICE(ROM),
  67         RK312X_DEVICE(PMU),
  68         RK312X_DEVICE(EFUSE),
  69         RK312X_DEVICE(TIMER),
  70         RK312X_DEVICE(CPU_AXI_BUS),
  71         RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE),
  72         RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE),
  73         RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE),
  74         RK_DEVICE(RK_GPIO_VIRT(0), RK312X_GPIO0_PHYS, RK312X_GPIO_SIZE),
  75         RK_DEVICE(RK_GPIO_VIRT(1), RK312X_GPIO1_PHYS, RK312X_GPIO_SIZE),
  76         RK_DEVICE(RK_GPIO_VIRT(2), RK312X_GPIO2_PHYS, RK312X_GPIO_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(3), RK312X_GPIO3_PHYS, RK312X_GPIO_SIZE),
  78         RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
  79         RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
  80         RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
  81         RK_DEVICE(RK_PWM_VIRT, RK312X_PWM_PHYS, RK312X_PWM_SIZE),
  82 };
  83
  84 static void __init rk312x_boot_mode_init(void)
  85 {
  86         u32 flag = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
  87         u32 mode = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
  88         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_RST_ST);
  89
  90         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  91                 mode = BOOT_MODE_RECOVERY;
  92         if (rst_st & ((1 << 2) | (1 << 3)))
  93                 mode = BOOT_MODE_WATCHDOG;
  94
  95         rockchip_boot_mode_init(flag, mode);
  96 }
  97
  98 static void usb_uart_init(void)
  99 {
 100 #ifdef CONFIG_RK_USB_UART
 101         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_STATUS0);
 102 #endif
 103         writel_relaxed(0x34000000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 104 #ifdef CONFIG_RK_USB_UART
 105         if (!(soc_status0 & (1 << 5)) && (soc_status0 & (1 << 8))) {
 106                 /* software control usb phy enable */
 107                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK312X_GRF_UOC0_CON0);
 108                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 109         }
 110 #endif
 111
 112         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
 113         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 114         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 115         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 116         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 117         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 118 }
 119
 120 static void __init rk312x_dt_map_io(void)
 121 {
 122         u32 v;
 123
 124         iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc));
 125         debug_ll_io_init();
 126         usb_uart_init();
 127
 128         /* pmu reset by second global soft reset */
 129         v = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 130         v &= ~(3 << 12);
 131         v |= 1 << 12;
 132         writel_relaxed(v, RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 133
 134         /* enable timer5 for core */
 135         writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10);
 136         dsb();
 137         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00);
 138         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04);
 139         dsb();
 140         writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10);
 141         dsb();
 142         writel_relaxed(0x80000000, RK_CRU_VIRT + RK312X_CRU_MISC_CON);
 143         dsb();
 144
 145         rk312x_boot_mode_init();
 146         rockchip_efuse_init();
 147 }
 148
 149 static void __init rk3126_dt_map_io(void)
 150 {
 151         rockchip_soc_id = ROCKCHIP_SOC_RK3126;
 152
 153         rk312x_dt_map_io();
 154
 155         if (readl_relaxed(RK_GRF_VIRT + RK312X_GRF_CHIP_TAG) == 0x3136)
 156                 rockchip_soc_id = ROCKCHIP_SOC_RK3126B;
 157 }
 158
 159 static void __init rk3128_dt_map_io(void)
 160 {
 161         rockchip_soc_id = ROCKCHIP_SOC_RK3128;
 162
 163         rk312x_dt_map_io();
 164 }
 165 static DEFINE_SPINLOCK(pmu_idle_lock);
 166 static const u8 pmu_idle_map[] = {
 167         [IDLE_REQ_PERI] = 0,
 168         [IDLE_REQ_VIDEO] = 1,
 169         [IDLE_REQ_VIO] = 2,
 170         [IDLE_REQ_GPU] = 3,
 171         [IDLE_REQ_CORE] = 4,
 172         [IDLE_REQ_SYS] = 5,
 173         [IDLE_REQ_MSCH] = 6,
 174         [IDLE_REQ_CRYPTO] = 7,
 175
 176 };
 177 static int rk312x_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 178 {
 179         u32 val;
 180         unsigned long flags;
 181         u32 bit = pmu_idle_map[req];
 182         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 183         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 184         u32 mask = BIT(bit);
 185
 186         spin_lock_irqsave(&pmu_idle_lock, flags);
 187         val = pmu_readl(RK312X_PMU_IDLE_REQ);
 188         if (idle)
 189                 val |= mask;
 190         else
 191                 val &= ~mask;
 192         pmu_writel(val, RK312X_PMU_IDLE_REQ);
 193         dsb();
 194
 195         while (((pmu_readl(RK312X_PMU_IDLE_ST) & idle_mask) != idle_target))
 196                 ;
 197         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 198         return 0;
 199 }
 200 static const u8 pmu_pd_map[] = {
 201         [PD_GPU] = 1,
 202         [PD_VIDEO] = 2,
 203         [PD_VIO] = 3,
 204 };
 205
 206 static const u8 pmu_st_map[] = {
 207         [PD_GPU] = 1,
 208         [PD_VIDEO] = 2,
 209         [PD_VIO] = 3,
 210 };
 211
 212 static noinline void rk312x_do_pmu_set_power_domain(enum pmu_power_domain domain
 213         , bool on)
 214 {
 215         u8 pd = pmu_pd_map[domain];
 216         u32 val = pmu_readl(RK312X_PMU_PWRDN_CON);
 217
 218         if (on)
 219                 val &= ~BIT(pd);
 220         else
 221                 val |=  BIT(pd);
 222         pmu_writel(val, RK312X_PMU_PWRDN_CON);
 223         dsb();
 224
 225         while ((pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 226                 ;
 227 }
 228
 229 static bool rk312x_pmu_power_domain_is_on(enum pmu_power_domain pd)
 230 {
 231         /*1"b0: power on, 1'b1: power off*/
 232         return !(pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 233 }
 234 static DEFINE_SPINLOCK(pmu_pd_lock);
 235 static u32 rga_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 236 static u32 ebc_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 237 static u32 iep_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 238 static u32 lcdc0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 239 static u32 vip0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 240 static u32 gpu_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 241 static u32 video_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 242
 243 #define SAVE_QOS(array, NAME) RK312X_CPU_AXI_SAVE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 244 #define RESTORE_QOS(array, NAME) RK312X_CPU_AXI_RESTORE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 245
 246 static int rk312x_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 247 {
 248         unsigned long flags;
 249
 250         spin_lock_irqsave(&pmu_pd_lock, flags);
 251         if (rk312x_pmu_power_domain_is_on(pd) == on)
 252                 goto out;
 253         if (!on) {
 254                 if (pd == PD_GPU) {
 255                         SAVE_QOS(gpu_qos, GPU);
 256                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, true);
 257                 } else if (pd == PD_VIO) {
 258                         SAVE_QOS(rga_qos, VIO_RGA);
 259                         SAVE_QOS(ebc_qos, VIO_EBC);
 260                         SAVE_QOS(iep_qos, VIO_IEP);
 261                         SAVE_QOS(lcdc0_qos, VIO_LCDC0);
 262                         SAVE_QOS(vip0_qos, VIO_VIP0);
 263                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, true);
 264                 } else if (pd == PD_VIDEO) {
 265                         SAVE_QOS(video_qos, VIDEO);
 266                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 267                 }
 268         }
 269
 270         rk312x_do_pmu_set_power_domain(pd, on);
 271
 272         if (on) {
 273                 if (pd == PD_GPU) {
 274                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, false);
 275                         RESTORE_QOS(gpu_qos, GPU);
 276                 } else if (pd == PD_VIO) {
 277                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, false);
 278                         RESTORE_QOS(rga_qos, VIO_RGA);
 279                         RESTORE_QOS(ebc_qos, VIO_EBC);
 280                         RESTORE_QOS(iep_qos, VIO_IEP);
 281                         RESTORE_QOS(lcdc0_qos, VIO_LCDC0);
 282                         RESTORE_QOS(vip0_qos, VIO_VIP0);
 283                 } else if (pd == PD_VIDEO) {
 284                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 285                         RESTORE_QOS(video_qos, VIDEO);
 286                 }
 287         }
 288 out:
 289         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 290
 291         return 0;
 292 }
 293 extern void secondary_startup(void);
 294 static int rk312x_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 295 {
 296         u32 clks_save[RK312X_CRU_CLKGATES_CON_CNT];
 297         u32 clks_ungating[RK312X_CRU_CLKGATES_CON_CNT];
 298         u32 i, ret = 0;
 299
 300         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 301                 clks_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 302                 clks_ungating[i] = 0;
 303         }
 304         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 305                 cru_writel(0xffff0000, RK312X_CRU_CLKGATES_CON(i));
 306
 307         if (on) {
 308 #ifdef CONFIG_SMP
 309                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 310                         writel_relaxed(0x20000 << (pd - PD_CPU_1),
 311                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 312                         dsb();
 313                         udelay(10);
 314                         writel_relaxed(virt_to_phys(secondary_startup),
 315                                        RK312X_IMEM_VIRT + 8);
 316                         writel_relaxed(0xDEADBEAF, RK312X_IMEM_VIRT + 4);
 317                         dsb_sev();
 318                 }
 319 #endif
 320         } else {
 321 #ifdef CONFIG_SMP
 322                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 323                         writel_relaxed(0x20002 << (pd - PD_CPU_1),
 324                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 325                         dsb();
 326                 }
 327 #endif
 328         }
 329
 330         if (((pd == PD_GPU) || (pd == PD_VIO) || (pd == PD_VIDEO)))
 331                 ret = rk312x_pmu_set_power_domain(pd, on);
 332
 333         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 334                 cru_writel(clks_save[i] | 0xffff0000
 335                         , RK312X_CRU_CLKGATES_CON(i));
 336         }
 337
 338         return ret;
 339 }
 340
 341 static void __init rk312x_dt_init_timer(void)
 342 {
 343         rockchip_pmu_ops.set_power_domain = rk312x_sys_set_power_domain;
 344         rockchip_pmu_ops.power_domain_is_on = rk312x_pmu_power_domain_is_on;
 345         rockchip_pmu_ops.set_idle_request = rk312x_pmu_set_idle_request;
 346         of_clk_init(NULL);
 347         clocksource_of_init();
 348         of_dvfs_init();
 349 }
 350
 351 static void __init rk312x_reserve(void)
 352 {
 353         /* reserve memory for ION */
 354         rockchip_ion_reserve();
 355 }
 356
 357 #ifdef CONFIG_PM
 358 static u32 rk_pmu_pwrdn_st;
 359
 360 static void rk_pm_soc_pd_suspend(void)
 361 {
 362         rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST);
 363         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 364                 rk312x_sys_set_power_domain(PD_GPU, false);
 365
 366         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 367                 rk312x_sys_set_power_domain(PD_VIO, false);
 368
 369         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 370                 rk312x_sys_set_power_domain(PD_VIDEO, false);
 371 }
 372
 373 static void rk_pm_soc_pd_resume(void)
 374 {
 375         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 376                 rk312x_sys_set_power_domain(PD_VIDEO, true);
 377
 378         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 379                 rk312x_sys_set_power_domain(PD_VIO, true);
 380
 381         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 382                 rk312x_sys_set_power_domain(PD_GPU, true);
 383 }
 384
 385 static void __init rk312x_init_suspend(void)
 386 {
 387         pr_info("%s\n", __func__);
 388         rkpm_pie_init();
 389         rk312x_suspend_init();
 390 }
 391 #endif
 392
 393 static void __init rk312x_init_late(void)
 394 {
 395 #ifdef CONFIG_PM
 396         rockchip_suspend_init();
 397         if (soc_is_rk3126b())
 398                 rk3126b_init_suspend();
 399         else
 400                 rk312x_init_suspend();
 401         rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume);
 402 #endif
 403         if (rockchip_jtag_enabled)
 404                 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
 405 }
 406
 407 static void rk312x_restart(char mode, const char *cmd)
 408 {
 409         u32 boot_flag, boot_mode;
 410
 411         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 412
 413         /* for loader */
 414         writel_relaxed(boot_flag, RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
 415         /* for linux */
 416         writel_relaxed(boot_mode, RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
 417
 418         dsb();
 419
 420         /* pll enter slow mode */
 421         writel_relaxed(0x11010000, RK_CRU_VIRT + RK312X_CRU_MODE_CON);
 422         dsb();
 423         writel_relaxed(0xeca8, RK_CRU_VIRT + RK312X_CRU_GLB_SRST_SND_VALUE);
 424         dsb();
 425 }
 426
 427 DT_MACHINE_START(RK3126_DT, "Rockchip RK3126")
 428         .smp            = smp_ops(rockchip_smp_ops),
 429         .map_io         = rk3126_dt_map_io,
 430         .init_time      = rk312x_dt_init_timer,
 431         .dt_compat      = rk3126_dt_compat,
 432         .init_late      = rk312x_init_late,
 433         .reserve        = rk312x_reserve,
 434         .restart        = rk312x_restart,
 435 MACHINE_END
 436
 437 DT_MACHINE_START(RK3128_DT, "Rockchip RK3128")
 438         .smp            = smp_ops(rockchip_smp_ops),
 439         .map_io         = rk3128_dt_map_io,
 440         .init_time      = rk312x_dt_init_timer,
 441         .dt_compat      = rk3128_dt_compat,
 442         .init_late      = rk312x_init_late,
 443         .reserve        = rk312x_reserve,
 444         .restart        = rk312x_restart,
 445 MACHINE_END
 446
 447
 448 char PIE_DATA(sram_stack)[1024];
 449 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 450
 451 static int __init rk312x_pie_init(void)
 452 {
 453         int err;
 454
 455         if (!cpu_is_rk312x())
 456                 return 0;
 457         if (soc_is_rk3126b())
 458                 return 0;
 459
 460         err = rockchip_pie_init();
 461         if (err)
 462                 return err;
 463
 464         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk312x);
 465         if (IS_ERR(rockchip_pie_chunk)) {
 466                 err = PTR_ERR(rockchip_pie_chunk);
 467                 pr_err("%s: failed to load section %d\n", __func__, err);
 468                 rockchip_pie_chunk = NULL;
 469                 return err;
 470         }
 471
 472         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 473         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 474
 475         return 0;
 476 }
 477 arch_initcall(rk312x_pie_init);
 478
 479 #include "ddr_rk3126.c"
 480 static int __init rk312x_ddr_init(void)
 481 {
 482         if (soc_is_rk3128() || soc_is_rk3126()) {
 483                 ddr_change_freq = _ddr_change_freq;
 484                 ddr_round_rate = _ddr_round_rate;
 485                 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 486                 ddr_bandwidth_get = _ddr_bandwidth_get;
 487                 ddr_init(DDR3_DEFAULT, 300);
 488                 }
 489         return 0;
 490 }
 491 arch_initcall_sync(rk312x_ddr_init);