arch/arm/mach-rockchip/rk3036.c

   1 /*
   2  * Device Tree support for Rockchip RK3036
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/wakeup_reason.h>
  27 #include <linux/rockchip/common.h>
  28 #include <linux/rockchip/cpu.h>
  29 #include <linux/rockchip/cru.h>
  30 #include <linux/rockchip/dvfs.h>
  31 #include <linux/rockchip/grf.h>
  32 #include <linux/rockchip/iomap.h>
  33 #include <linux/rockchip/pmu.h>
  34 #include <asm/cpuidle.h>
  35 #include <asm/cputype.h>
  36 #include <asm/mach/arch.h>
  37 #include <asm/mach/map.h>
  38 #include "cpu_axi.h"
  39 #include "loader.h"
  40 #define CPU 3036
  41 #include "sram.h"
  42 #include "pm.h"
  43
  44 #define RK3036_DEVICE(name) \
  45         { \
  46                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  47                 .pfn            = __phys_to_pfn(RK3036_##name##_PHYS), \
  48                 .length         = RK3036_##name##_SIZE, \
  49                 .type           = MT_DEVICE, \
  50         }
  51
  52 #define RK3036_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  53 #define RK3036_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  54
  55 static struct map_desc rk3036_io_desc[] __initdata = {
  56         RK3036_DEVICE(CRU),
  57         RK3036_DEVICE(GRF),
  58         RK3036_DEVICE(ROM),
  59         RK3036_DEVICE(EFUSE),
  60         RK3036_DEVICE(CPU_AXI_BUS),
  61         RK_DEVICE(RK_DDR_VIRT, RK3036_DDR_PCTL_PHYS, RK3036_DDR_PCTL_SIZE),
  62         RK_DEVICE(RK_DDR_VIRT + RK3036_DDR_PCTL_SIZE, RK3036_DDR_PHY_PHYS,
  63                   RK3036_DDR_PHY_SIZE),
  64         RK_DEVICE(RK_GPIO_VIRT(0), RK3036_GPIO0_PHYS, RK3036_GPIO_SIZE),
  65         RK_DEVICE(RK_GPIO_VIRT(1), RK3036_GPIO1_PHYS, RK3036_GPIO_SIZE),
  66         RK_DEVICE(RK_GPIO_VIRT(2), RK3036_GPIO2_PHYS, RK3036_GPIO_SIZE),
  67         RK_DEVICE(RK_DEBUG_UART_VIRT, RK3036_UART2_PHYS, RK3036_UART_SIZE),
  68         RK_DEVICE(RK_GIC_VIRT, RK3036_GIC_DIST_PHYS, RK3036_GIC_DIST_SIZE),
  69         RK_DEVICE(RK_GIC_VIRT + RK3036_GIC_DIST_SIZE, RK3036_GIC_CPU_PHYS,
  70                   RK3036_GIC_CPU_SIZE),
  71         RK_DEVICE(RK3036_IMEM_VIRT, RK3036_IMEM_PHYS, SZ_4K),
  72         RK_DEVICE(RK_TIMER_VIRT, RK3036_TIMER_PHYS, RK3036_TIMER_SIZE),
  73 };
  74
  75 static void __init rk3036_boot_mode_init(void)
  76 {
  77         u32 flag = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG4);
  78         u32 mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG5);
  79         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3036_CRU_RST_ST);
  80
  81         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  82                 mode = BOOT_MODE_RECOVERY;
  83         if (rst_st & ((1 << 2) | (1 << 3)))
  84                 mode = BOOT_MODE_WATCHDOG;
  85         rockchip_boot_mode_init(flag, mode);
  86 }
  87
  88 static void usb_uart_init(void)
  89 {
  90 #ifdef CONFIG_RK_USB_UART
  91         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_STATUS0);
  92 #endif
  93         writel_relaxed(0x34000000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
  94 #ifdef CONFIG_RK_USB_UART
  95         if (!(soc_status0 & (1 << 14)) && (soc_status0 & (1 << 17))) {
  96                 /* software control usb phy enable */
  97                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK3036_GRF_UOC0_CON5);
  98                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
  99         }
 100 #endif
 101
 102         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
 103         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 104         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 105         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 106         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 107         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 108 }
 109
 110 static void __init rk3036_dt_map_io(void)
 111 {
 112         rockchip_soc_id = ROCKCHIP_SOC_RK3036;
 113
 114         iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
 115         debug_ll_io_init();
 116         usb_uart_init();
 117
 118         /* enable timer5 for core */
 119         writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
 120         dsb();
 121         writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
 122         writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
 123         dsb();
 124         writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
 125         dsb();
 126
 127         rk3036_boot_mode_init();
 128 }
 129
 130 extern void secondary_startup(void);
 131 static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 132 {
 133         if (on) {
 134 #ifdef CONFIG_SMP
 135                 if (PD_CPU_1 == pd) {
 136                         writel_relaxed(0x20000
 137                                 , RK_CRU_VIRT + RK3036_CRU_SOFTRST0_CON);
 138                         dsb();
 139                         udelay(10);
 140                         writel_relaxed(virt_to_phys(secondary_startup),
 141                                            RK3036_IMEM_VIRT + 8);
 142                         writel_relaxed(0xDEADBEAF, RK3036_IMEM_VIRT + 4);
 143                         dsb_sev();
 144                 }
 145 #endif
 146         } else {
 147 #ifdef CONFIG_SMP
 148                 if (PD_CPU_1 == pd) {
 149                         writel_relaxed(0x20002
 150                                 , RK_CRU_VIRT + RK3036_CRU_SOFTRST0_CON);
 151                         dsb();
 152                 }
 153 #endif
 154         }
 155
 156         return 0;
 157 }
 158
 159 static bool rk3036_pmu_power_domain_is_on(enum pmu_power_domain pd)
 160 {
 161         return 1;
 162 }
 163
 164 static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 165 {
 166         return 0;
 167 }
 168
 169 static void __init rk3036_dt_init_timer(void)
 170 {
 171         rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
 172         rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
 173         rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
 174         of_clk_init(NULL);
 175         clocksource_of_init();
 176 }
 177
 178 #ifdef CONFIG_PM
 179 static inline void rk3036_uart_printch(char byte)
 180 {
 181 write_uart:
 182         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
 183         dsb();
 184
 185         /* loop check LSR[6], Transmitter Empty bit */
 186         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
 187                 barrier();
 188
 189         if (byte == '\n') {
 190                 byte = '\r';
 191                 goto write_uart;
 192         }
 193 }
 194
 195 static void rk3036_ddr_printch(char byte)
 196 {
 197         rk3036_uart_printch(byte);
 198
 199         rk_last_log_text(&byte, 1);
 200
 201         if (byte == '\n') {
 202                 byte = '\r';
 203                 rk_last_log_text(&byte, 1);
 204         }
 205 }
 206
 207 enum rk_plls_id {
 208         APLL_ID = 0,
 209         DPLL_ID,
 210         GPLL_ID,
 211         RK3036_END_PLL_ID,
 212 };
 213
 214 #define GPIO_INTEN 0x30
 215 #define GPIO_INT_STATUS 0x40
 216 #define GIC_DIST_PENDING_SET 0x200
 217 static void rk3036_pm_dump_irq(void)
 218 {
 219         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT
 220                 + GIC_DIST_PENDING_SET + 8) >> 4) & 7;
 221         u32 irq[4];
 222         int i;
 223
 224         for (i = 0; i < ARRAY_SIZE(irq); i++) {
 225                 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET +
 226                                            (1 + i) * 4);
 227                 if (irq[i])
 228                         log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
 229         }
 230         pr_info("wakeup irq: %08x %08x %08x %08x\n",
 231                 irq[0], irq[1], irq[2], irq[3]);
 232         for (i = 0; i <= 2; i++) {
 233                 if (irq_gpio & (1 << i))
 234                         pr_info("wakeup gpio%d: %08x\n", i,
 235                                 readl_relaxed(RK_GPIO_VIRT(i) +
 236                                                   GPIO_INT_STATUS));
 237         }
 238 }
 239
 240 #define DUMP_GPIO_INTEN(ID) \
 241         do { \
 242                 u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
 243                 if (en) { \
 244                         pr_info("GPIO%d_INTEN: %08x\n", ID, en); \
 245                 } \
 246         } while (0)
 247
 248 static void rk3036_pm_dump_inten(void)
 249 {
 250         DUMP_GPIO_INTEN(0);
 251         DUMP_GPIO_INTEN(1);
 252         DUMP_GPIO_INTEN(2);
 253 }
 254
 255 static u32 clk_ungt_msk[RK3036_CRU_CLKGATES_CON_CNT];
 256 /*first clk gating setting*/
 257
 258 static u32 clk_ungt_msk_1[RK3036_CRU_CLKGATES_CON_CNT];
 259 /* first clk gating setting*/
 260
 261 static u32 clk_ungt_save[RK3036_CRU_CLKGATES_CON_CNT];
 262 /*first clk gating value saveing*/
 263
 264 static u32 *p_rkpm_clkgt_last_set;
 265 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
 266 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
 267
 268 static void gtclks_suspend(void)
 269 {
 270         int i;
 271
 272         for (i = 0; i < RK3036_CRU_CLKGATES_CON_CNT; i++) {
 273                 clk_ungt_save[i] = cru_readl(RK3036_CRU_CLKGATES_CON(i));
 274                 if (i != 10)
 275                         CLK_MSK_UNGATING(clk_ungt_msk[i]
 276                         , RK3036_CRU_CLKGATES_CON(i));
 277                 else
 278                         cru_writel(clk_ungt_msk[i], RK3036_CRU_CLKGATES_CON(i));
 279         }
 280
 281         /*gpio0_a1 clk gate should be disable for volt adjust*/
 282         if (cru_readl(RK3036_CRU_CLKGATES_CON(8)) & 0x200)
 283                 cru_writel(0x02000000, RK3036_CRU_CLKGATES_CON(8));
 284 }
 285
 286 static void gtclks_resume(void)
 287 {
 288         int i;
 289
 290         for (i = 0; i < RK3036_CRU_CLKGATES_CON_CNT; i++) {
 291                 if (i != 10)
 292                         cru_writel(clk_ungt_save[i] | 0xffff0000
 293                                 , RK3036_CRU_CLKGATES_CON(i));
 294                 else
 295                         cru_writel(clk_ungt_save[i]
 296                                 , RK3036_CRU_CLKGATES_CON(i));
 297         }
 298 }
 299
 300 static void clks_gating_suspend_init(void)
 301 {
 302         p_rkpm_clkgt_last_set = &clk_ungt_msk_1[0];
 303         if (clk_suspend_clkgt_info_get(clk_ungt_msk, p_rkpm_clkgt_last_set
 304                 , RK3036_CRU_CLKGATES_CON_CNT) == RK3036_CRU_CLKGATES_CON(0))
 305                 rkpm_set_ops_gtclks(gtclks_suspend, gtclks_resume);
 306 }
 307
 308 #define RK3036_PLL_BYPASS CRU_W_MSK_SETBITS(1, 0xF, 0x01)
 309 #define RK3036_PLL_NOBYPASS CRU_W_MSK_SETBITS(0, 0xF, 0x01)
 310 #define RK3036_PLL_POWERDOWN CRU_W_MSK_SETBITS(1, 0xD, 0x01)
 311 #define RK3036_PLL_POWERON CRU_W_MSK_SETBITS(0, 0xD, 0x01)
 312
 313 #define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + offset)
 314 #define grf_writel(v, offset) do { writel_relaxed(v, \
 315         RK_GRF_VIRT + offset); dsb(); } while (0)
 316
 317 #define gpio0_readl(offset) readl_relaxed(RK_GPIO_VIRT(0) + offset)
 318 #define gpio0_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(0) \
 319         + offset); dsb(); } while (0)
 320
 321 static u32 plls_con0_save[RK3036_END_PLL_ID];
 322 static u32 plls_con1_save[RK3036_END_PLL_ID];
 323 static u32 plls_con2_save[RK3036_END_PLL_ID];
 324
 325 static u32 cru_mode_con;
 326 static u32 clk_sel0, clk_sel1, clk_sel10;
 327 static int goio0_pin_iomux, gpio0_pin_data, gpio0_pin_dir;
 328
 329 static void pm_pll_wait_lock(u32 pll_idx)
 330 {
 331         u32 delay = 600000U;
 332
 333         dsb();
 334         dsb();
 335         dsb();
 336         dsb();
 337         dsb();
 338         dsb();
 339         while (delay > 0) {
 340                 if ((cru_readl(RK3036_PLL_CONS(pll_idx, 1)) & (0x1 << 10)))
 341                         break;
 342                 delay--;
 343         }
 344         if (delay == 0) {
 345                 rkpm_ddr_printascii("unlock-pll:");
 346                 rkpm_ddr_printhex(pll_idx);
 347                 rkpm_ddr_printch('\n');
 348         }
 349 }
 350
 351 static void pll_udelay(u32 udelay)
 352 {
 353         u32 mode;
 354
 355         mode = cru_readl(RK3036_CRU_MODE_CON);
 356         cru_writel(RK3036_PLL_MODE_SLOW(APLL_ID), RK3036_CRU_MODE_CON);
 357         rkpm_udelay(udelay * 5);
 358         cru_writel(mode|(RK3036_PLL_MODE_MSK(APLL_ID)
 359                 << 16), RK3036_CRU_MODE_CON);
 360 }
 361
 362 static inline void plls_suspend(u32 pll_id)
 363 {
 364         plls_con0_save[pll_id] = cru_readl(RK3036_PLL_CONS((pll_id), 0));
 365         plls_con1_save[pll_id] = cru_readl(RK3036_PLL_CONS((pll_id), 1));
 366         plls_con2_save[pll_id] = cru_readl(RK3036_PLL_CONS((pll_id), 2));
 367
 368         /*cru_writel(RK3036_PLL_BYPASS, RK3036_PLL_CONS((pll_id), 0));*/
 369         cru_writel(RK3036_PLL_POWERDOWN, RK3036_PLL_CONS((pll_id), 1));
 370 }
 371 static inline void plls_resume(u32 pll_id)
 372 {
 373         u32 pllcon0, pllcon1, pllcon2;
 374
 375         pllcon0 = plls_con0_save[pll_id];
 376         pllcon1 = plls_con1_save[pll_id];
 377         pllcon2 = plls_con2_save[pll_id];
 378 /*
 379         cru_writel(pllcon0 | 0xffff0000, RK3036_PLL_CONS(pll_id, 0));
 380         cru_writel(pllcon1 | 0xf5ff0000, RK3036_PLL_CONS(pll_id, 1));
 381         cru_writel(pllcon2, RK3036_PLL_CONS(pll_id, 2));
 382 */
 383         cru_writel(RK3036_PLL_POWERON, RK3036_PLL_CONS((pll_id), 1));
 384
 385         pll_udelay(5);
 386
 387         pll_udelay(168);
 388         pm_pll_wait_lock(pll_id);
 389 }
 390
 391 static void pm_plls_suspend(void)
 392 {
 393         cru_mode_con  = cru_readl(RK3036_CRU_MODE_CON);
 394
 395         clk_sel0 = cru_readl(RK3036_CRU_CLKSELS_CON(0));
 396         clk_sel1 = cru_readl(RK3036_CRU_CLKSELS_CON(1));
 397         clk_sel10 = cru_readl(RK3036_CRU_CLKSELS_CON(10));
 398
 399         cru_writel(RK3036_PLL_MODE_SLOW(GPLL_ID), RK3036_CRU_MODE_CON);
 400         cru_writel(0
 401                                                 |CRU_W_MSK_SETBITS(0, 0, 0x1f)
 402                                                 |CRU_W_MSK_SETBITS(0, 8, 0x3)
 403                                                 |CRU_W_MSK_SETBITS(0, 12, 0x3)
 404                                                 , RK3036_CRU_CLKSELS_CON(10));
 405         plls_suspend(GPLL_ID);
 406
 407
 408         cru_writel(RK3036_PLL_MODE_SLOW(APLL_ID), RK3036_CRU_MODE_CON);
 409
 410         cru_writel(0
 411                                                 |CRU_W_MSK_SETBITS(0, 0, 0x1f)
 412                                                 |CRU_W_MSK_SETBITS(0, 8, 0x1f)
 413                                           , RK3036_CRU_CLKSELS_CON(0));
 414
 415         cru_writel(0
 416                                                 |CRU_W_MSK_SETBITS(0, 0, 0xf)
 417                                                 |CRU_W_MSK_SETBITS(0, 4, 0x7)
 418                                                 |CRU_W_MSK_SETBITS(0, 8, 0x3)
 419                                                 |CRU_W_MSK_SETBITS(0, 12, 0x7)
 420                                          , RK3036_CRU_CLKSELS_CON(1));
 421
 422         plls_suspend(APLL_ID);
 423
 424         goio0_pin_iomux = grf_readl(0xa8);
 425         grf_writel(0x000c0000, 0xa8);
 426
 427         gpio0_pin_data = gpio0_readl(0x0);
 428         gpio0_pin_dir = gpio0_readl(0x04);
 429
 430         gpio0_writel(gpio0_pin_dir | 0x2, 0x04);
 431         gpio0_writel(gpio0_pin_data | 0x2, 0x00);
 432 }
 433
 434 static void pm_plls_resume(void)
 435 {
 436         gpio0_writel(gpio0_pin_dir, 0x04);
 437         gpio0_writel(gpio0_pin_data, 0x00);
 438         grf_writel(0x000c0008, 0xa8);
 439
 440         plls_resume(APLL_ID);
 441         cru_writel(clk_sel0 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x1f))
 442                 , RK3036_CRU_CLKSELS_CON(0));
 443         cru_writel(clk_sel1 | (CRU_W_MSK(0, 0xf) | CRU_W_MSK(4, 0x7)
 444                 |CRU_W_MSK(8, 0x3) | CRU_W_MSK(12, 0x7))
 445                 , RK3036_CRU_CLKSELS_CON(1));
 446         cru_writel(cru_mode_con | (RK3036_PLL_MODE_MSK(APLL_ID) << 16)
 447                 , RK3036_CRU_MODE_CON);
 448
 449         plls_resume(GPLL_ID);
 450         cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
 451                 | CRU_W_MSK(12, 0x3)), RK3036_CRU_CLKSELS_CON(10));
 452         cru_writel(cru_mode_con | (RK3036_PLL_MODE_MSK(GPLL_ID)
 453                 << 16), RK3036_CRU_MODE_CON);
 454 }
 455
 456 #include "ddr_rk3036.c"
 457 #include "pm-pie.c"
 458
 459 char PIE_DATA(sram_stack)[1024];
 460 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 461
 462 static int __init rk3036_pie_init(void)
 463 {
 464         int err;
 465
 466         if (!cpu_is_rk3036())
 467                 return 0;
 468
 469         err = rockchip_pie_init();
 470         if (err)
 471                 return err;
 472
 473         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3036);
 474         if (IS_ERR(rockchip_pie_chunk)) {
 475                 err = PTR_ERR(rockchip_pie_chunk);
 476                 pr_err("%s: failed to load section %d\n", __func__, err);
 477                 rockchip_pie_chunk = NULL;
 478                 return err;
 479         }
 480
 481         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk
 482                 , &__pie_common_start[0]);
 483         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk
 484                 , (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 485
 486         return 0;
 487 }
 488 arch_initcall(rk3036_pie_init);
 489
 490 static void reg_pread(void)
 491 {
 492         volatile u32 n;
 493         int i;
 494
 495         volatile u32 *temp = (volatile unsigned int *)rockchip_sram_virt;
 496
 497         flush_cache_all();
 498         outer_flush_all();
 499         local_flush_tlb_all();
 500
 501         for (i = 0; i < 2; i++) {
 502                 n = temp[1024 * i];
 503                 barrier();
 504         }
 505
 506         n = readl_relaxed(RK_GPIO_VIRT(0));
 507         n = readl_relaxed(RK_GPIO_VIRT(1));
 508         n = readl_relaxed(RK_GPIO_VIRT(2));
 509
 510         n = readl_relaxed(RK_DEBUG_UART_VIRT);
 511         n = readl_relaxed(RK_CPU_AXI_BUS_VIRT);
 512         n = readl_relaxed(RK_DDR_VIRT);
 513         n = readl_relaxed(RK_GRF_VIRT);
 514         n = readl_relaxed(RK_CRU_VIRT);
 515 }
 516
 517 #define RK3036_CRU_UNGATING_OPS(id) cru_writel(\
 518         CRU_W_MSK_SETBITS(0,  (id), 0x1), RK3036_CRU_UART_GATE)
 519 #define RK3036_CRU_GATING_OPS(id) cru_writel(\
 520         CRU_W_MSK_SETBITS(1, (id), 0x1), RK3036_CRU_UART_GATE)
 521
 522 static inline void  uart_printch(char bbyte)
 523 {
 524         u32 reg_save;
 525         u32 u_clk_id = (RK3036_CLKGATE_UART0_SRC + CONFIG_RK_DEBUG_UART * 2);
 526         u32 u_pclk_id = (RK3036_CLKGATE_UART0_PCLK + CONFIG_RK_DEBUG_UART * 2);
 527
 528         reg_save = cru_readl(RK3036_CRU_UART_GATE);
 529         RK3036_CRU_UNGATING_OPS(u_clk_id);
 530         RK3036_CRU_UNGATING_OPS(u_pclk_id);
 531         rkpm_udelay(1);
 532
 533
 534 write_uart:
 535         writel_relaxed(bbyte, RK_DEBUG_UART_VIRT);
 536         dsb();
 537
 538         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
 539                 barrier();
 540
 541         if (bbyte == '\n') {
 542                 bbyte = '\r';
 543                 goto write_uart;
 544         }
 545
 546         cru_writel(reg_save | CRU_W_MSK(u_clk_id
 547                 , 0x1), RK3036_CRU_UART_GATE);
 548         cru_writel(reg_save | CRU_W_MSK(u_pclk_id
 549                 , 0x1), RK3036_CRU_UART_GATE);
 550
 551
 552         if (0) {
 553 write_uart1:
 554                 writel_relaxed(bbyte, RK_DEBUG_UART_VIRT);
 555                 dsb();
 556
 557                 while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
 558                         barrier();
 559         if (bbyte == '\n') {
 560                 bbyte = '\r';
 561                 goto write_uart1;
 562                 }
 563         }
 564 }
 565
 566
 567 void PIE_FUNC(sram_printch)(char byte)
 568 {
 569         uart_printch(byte);
 570 }
 571
 572 static void __init rk3036_suspend_init(void)
 573 {
 574         struct device_node *parent;
 575         u32 pm_ctrbits;
 576
 577         PM_LOG("%s enter\n", __func__);
 578
 579         parent = of_find_node_by_name(NULL, "rockchip_suspend");
 580
 581         if (IS_ERR_OR_NULL(parent)) {
 582                 PM_ERR("%s dev node err\n", __func__);
 583                 return;
 584         }
 585
 586         if (of_property_read_u32_array(parent, "rockchip,ctrbits"
 587                 , &pm_ctrbits, 1)) {
 588                         PM_ERR("%s:get pm ctr error\n", __func__);
 589                         return;
 590         }
 591         PM_LOG("%s: pm_ctrbits =%x\n", __func__, pm_ctrbits);
 592         rkpm_set_ctrbits(pm_ctrbits);
 593
 594         clks_gating_suspend_init();
 595         rkpm_set_ops_plls(pm_plls_suspend, pm_plls_resume);
 596
 597         rkpm_set_ops_regs_pread(reg_pread);
 598         rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk
 599                 , &FUNC(ddr_suspend))
 600                 , fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)));
 601
 602         rkpm_set_ops_prepare_finish(rk3036_pm_dump_inten
 603                 , rk3036_pm_dump_irq);
 604
 605         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk
 606                 , &FUNC(sram_printch)));
 607         rkpm_set_ops_printch(rk3036_ddr_printch);
 608 }
 609 #endif
 610
 611 static void __init rk3036_init_suspend(void)
 612 {
 613         pr_info("%s\n", __func__);
 614         rockchip_suspend_init();
 615         rkpm_pie_init();
 616         rk3036_suspend_init();
 617 }
 618
 619 static void __init rk3036_init_late(void)
 620 {
 621 #ifdef CONFIG_PM
 622         rk3036_init_suspend();
 623 #endif
 624 }
 625
 626 static void __init rk3036_reserve(void)
 627 {
 628         /* reserve memory for ION */
 629         rockchip_ion_reserve();
 630 }
 631
 632 static void rk3036_restart(char mode, const char *cmd)
 633 {
 634         u32 boot_flag, boot_mode;
 635
 636         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 637         /* for loader */
 638         writel_relaxed(boot_flag, RK_GRF_VIRT + RK3036_GRF_OS_REG4);
 639         /* for linux */
 640         writel_relaxed(boot_mode, RK_GRF_VIRT + RK3036_GRF_OS_REG5);
 641         dsb();
 642
 643         /* pll enter slow mode */
 644         writel_relaxed(0x30110000, RK_CRU_VIRT + RK3036_CRU_MODE_CON);
 645         dsb();
 646         writel_relaxed(0xeca8, RK_CRU_VIRT + RK3036_CRU_GLB_SRST_SND_VALUE);
 647         dsb();
 648 }
 649
 650 static const char *const rk3036_dt_compat[] __initconst = {
 651         "rockchip,rk3036",
 652         NULL,
 653 };
 654
 655 DT_MACHINE_START(RK3036_DT, "Rockchip RK3036")
 656         .dt_compat      = rk3036_dt_compat,
 657         .smp            = smp_ops(rockchip_smp_ops),
 658         .reserve        = rk3036_reserve,
 659         .map_io         = rk3036_dt_map_io,
 660         .init_time      = rk3036_dt_init_timer,
 661         .init_late      = rk3036_init_late,
 662         .reserve        = rk3036_reserve,
 663         .restart        = rk3036_restart,
 664 MACHINE_END