arch/arm/mach-rockchip/pm-rk312x.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <asm/cacheflush.h>
   4 #include <asm/tlbflush.h>
   5 #include <asm/hardware/cache-l2x0.h>
   6 #include <linux/module.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/wakeup_reason.h>
   9 #include <linux/pm.h>
  10 #include <linux/suspend.h>
  11 #include <linux/of.h>
  12 #include <linux/io.h>
  13 #include <linux/of_address.h>
  14 #include <linux/rockchip/cpu.h>
  15 #include <linux/rockchip/grf.h>
  16 #include <linux/rockchip/iomap.h>
  17 #include "pm.h"
  18 #include <linux/irqchip/arm-gic.h>
  19 #include "pm-pie.c"
  20
  21 __weak void rk_usb_power_down(void);
  22 __weak void rk_usb_power_up(void);
  23
  24 #define GPIO_INTEN 0x30
  25 #define GPIO_INT_STATUS 0x40
  26 #define GIC_DIST_PENDING_SET 0x200
  27 #define DUMP_GPIO_INTEN(ID)\
  28 do { \
  29         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN);\
  30         if (en) {\
  31                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
  32                 rkpm_ddr_printhex(en); \
  33                 rkpm_ddr_printch('\n'); \
  34         } \
  35 } while (0)
  36 #define RK312X_CRU_UNGATING_OPS(id) cru_writel(\
  37         CRU_W_MSK_SETBITS(0,  (id) % 16, 0x1), RK312X_CRU_GATEID_CONS((id)))
  38 #define RK312X_CRU_GATING_OPS(id) cru_writel(\
  39         CRU_W_MSK_SETBITS(1, (id) % 16, 0x1), RK312X_CRU_GATEID_CONS((id)))
  40
  41 enum rk_plls_id {
  42         APLL_ID = 0,
  43         DPLL_ID,
  44         CPLL_ID,
  45         GPLL_ID,
  46         END_PLL_ID,
  47 };
  48
  49 static inline void  uart_printch(char bbyte)
  50 {
  51         u32 reg_save[2];
  52         u32 u_clk_id = (RK312X_CLKGATE_UART0_SRC + CONFIG_RK_DEBUG_UART * 2);
  53         u32 u_pclk_id = (RK312X_CLKGATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART);
  54
  55         reg_save[0] = cru_readl(RK312X_CRU_GATEID_CONS(u_clk_id));
  56         reg_save[1] = cru_readl(RK312X_CRU_GATEID_CONS(u_pclk_id));
  57         RK312X_CRU_UNGATING_OPS(u_clk_id);
  58         RK312X_CRU_UNGATING_OPS(u_pclk_id);
  59         rkpm_udelay(1);
  60
  61 write_uart:
  62         writel_relaxed(bbyte, RK_DEBUG_UART_VIRT);
  63         dsb();
  64
  65         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
  66                 barrier();
  67
  68         if (bbyte == '\n') {
  69                 bbyte = '\r';
  70                 goto write_uart;
  71         }
  72
  73         cru_writel(reg_save[0] | CRU_W_MSK(u_clk_id
  74                 % 16, 0x1), RK312X_CRU_GATEID_CONS(u_clk_id));
  75         cru_writel(reg_save[1] | CRU_W_MSK(u_pclk_id
  76                 % 16, 0x1), RK312X_CRU_GATEID_CONS(u_pclk_id));
  77
  78         if (0) {
  79 write_uart1:
  80                 writel_relaxed(bbyte, RK_DEBUG_UART_VIRT);
  81                 dsb();
  82
  83                 while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
  84                         barrier();
  85         if (bbyte == '\n') {
  86                 bbyte = '\r';
  87                 goto write_uart1;
  88                 }
  89         }
  90 }
  91
  92 void PIE_FUNC(sram_printch)(char byte)
  93 {
  94         uart_printch(byte);
  95 }
  96 static void pll_udelay(u32 udelay)
  97 {
  98         u32 mode;
  99
 100         mode = cru_readl(RK312X_CRU_MODE_CON);
 101         cru_writel(RK312X_PLL_MODE_SLOW(APLL_ID), RK312X_CRU_MODE_CON);
 102         rkpm_udelay(udelay * 5);
 103         cru_writel(mode|(RK312X_PLL_MODE_MSK(APLL_ID)
 104                 << 16), RK312X_CRU_MODE_CON);
 105 }
 106
 107 #define RK312X_PLL_PWR_DN_MSK (0x01 << 1)
 108 #define RK312X_PLL_BYPASS CRU_W_MSK_SETBITS(1, 0xF, 0x01)
 109 #define RK312X_PLL_NOBYPASS CRU_W_MSK_SETBITS(0, 0xF, 0x01)
 110 #define RK312X_PLL_RESET CRU_W_MSK_SETBITS(1, 14, 0x01)
 111 #define RK312X_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0, 14, 0x01)
 112 #define RK312X_PLL_POWERDOWN CRU_W_MSK_SETBITS(1, 0xD, 0x01)
 113 #define RK312X_PLL_POWERON CRU_W_MSK_SETBITS(0, 0xD, 0x01)
 114
 115 static u32 plls_con0_save[END_PLL_ID];
 116 static u32 plls_con1_save[END_PLL_ID];
 117 static u32 plls_con2_save[END_PLL_ID];
 118 static u32 cru_mode_con;
 119
 120 static void pm_pll_wait_lock(u32 pll_idx)
 121 {
 122         u32 delay = 600000U;
 123
 124         dsb();
 125         dsb();
 126         dsb();
 127         dsb();
 128         dsb();
 129         dsb();
 130         while (delay > 0) {
 131                 if ((cru_readl(RK312X_PLL_CONS(pll_idx, 1)) & (0x1 << 10)))
 132                         break;
 133                 delay--;
 134         }
 135         if (delay == 0) {
 136                 rkpm_ddr_printascii("unlock-pll:");
 137                 rkpm_ddr_printhex(pll_idx);
 138                 rkpm_ddr_printch('\n');
 139         }
 140 }
 141
 142 static inline void plls_suspend(u32 pll_id)
 143 {
 144         plls_con0_save[pll_id] = cru_readl(RK312X_PLL_CONS((pll_id), 0));
 145         plls_con1_save[pll_id] = cru_readl(RK312X_PLL_CONS((pll_id), 1));
 146         plls_con2_save[pll_id] = cru_readl(RK312X_PLL_CONS((pll_id), 2));
 147
 148         /*cru_writel(RK312X_PLL_BYPASS, RK312X_PLL_CONS((pll_id), 0));*/
 149         cru_writel(RK312X_PLL_POWERDOWN, RK312X_PLL_CONS((pll_id), 1));
 150 }
 151 static inline void plls_resume(u32 pll_id)
 152 {
 153         u32 pllcon0, pllcon1, pllcon2;
 154
 155         cru_writel(RK312X_PLL_MODE_SLOW(pll_id), RK312X_CRU_MODE_CON);
 156         /*cru_writel(RK312X_PLL_NOBYPASS, RK312x_PLL_CONS((pll_id), 0));*/
 157
 158         pllcon0 = plls_con0_save[pll_id];
 159         /*cru_readl(RK312x_PLL_CONS((pll_id),0));*/
 160         pllcon1 = plls_con1_save[pll_id];
 161         /*cru_readl(RK12x_PLL_CONS((pll_id),1));*/
 162         pllcon2 = plls_con2_save[pll_id];
 163         /*cru_readl(RK312x_PLL_CONS((pll_id),2));*/
 164
 165         cru_writel(RK312X_PLL_POWERON, RK312X_PLL_CONS((pll_id), 1));
 166
 167         pll_udelay(5);
 168
 169         /*return form rest*/
 170         /*cru_writel(RK312X_PLL_RESET_RESUME, RK312X_PLL_CONS(pll_id, 1));*/
 171
 172         /*wating lock state*/
 173         pll_udelay(168);
 174         pm_pll_wait_lock(pll_id);
 175
 176 }
 177 static u32 clk_sel0, clk_sel1, clk_sel10, clk_sel24, clk_sel29;
 178 static void pm_plls_suspend(void)
 179 {
 180         clk_sel0 = cru_readl(RK312X_CRU_CLKSELS_CON(0));
 181         clk_sel1 = cru_readl(RK312X_CRU_CLKSELS_CON(1));
 182         clk_sel10 = cru_readl(RK312X_CRU_CLKSELS_CON(10));
 183         clk_sel24 = cru_readl(RK312X_CRU_CLKSELS_CON(24));
 184         clk_sel29 = cru_readl(RK312X_CRU_CLKSELS_CON(29));
 185
 186         cru_mode_con = cru_readl(RK312X_CRU_MODE_CON);
 187
 188         /*CPLL*/
 189         cru_writel(RK312X_PLL_MODE_SLOW(CPLL_ID), RK312X_CRU_MODE_CON);
 190
 191         /*GPLL*/
 192         cru_writel(RK312X_PLL_MODE_SLOW(GPLL_ID), RK312X_CRU_MODE_CON);
 193
 194         /*crypto*/
 195         cru_writel(CRU_W_MSK_SETBITS(3, 0, 0x3), RK312X_CRU_CLKSELS_CON(24));
 196
 197         /* peri aclk hclk pclk*/
 198         cru_writel(0
 199                 |CRU_W_MSK_SETBITS(0, 0, 0x1f)/*1 aclk*/
 200                 |CRU_W_MSK_SETBITS(0, 8, 0x3)/*2   hclk 0 1:1,1 2:1 ,2 4:1*/
 201                 |CRU_W_MSK_SETBITS(0, 12, 0x3)/* 2     0~3  1 2 4 8 div*/
 202                 , RK312X_CRU_CLKSELS_CON(10));
 203
 204         /* pmu*/
 205         cru_writel(CRU_W_MSK_SETBITS(0, 8, 0x1f), RK312X_CRU_CLKSELS_CON(29));
 206         plls_suspend(CPLL_ID);
 207         plls_suspend(GPLL_ID);
 208
 209         /*apll*/
 210         cru_writel(RK312X_PLL_MODE_SLOW(APLL_ID), RK312X_CRU_MODE_CON);
 211         /*a7_core*/
 212         cru_writel(0 | CRU_W_MSK_SETBITS(0, 0, 0x1f)
 213         , RK312X_CRU_CLKSELS_CON(0));
 214
 215         /*pclk_dbg*/
 216         cru_writel(0 | CRU_W_MSK_SETBITS(3, 0, 0x7)
 217         , RK312X_CRU_CLKSELS_CON(1));
 218         plls_suspend(APLL_ID);
 219 }
 220
 221 static void pm_plls_resume(void)
 222 {
 223         cru_writel(clk_sel0 | CRU_W_MSK(0, 0x1f), RK312X_CRU_CLKSELS_CON(0));
 224         cru_writel(clk_sel1 | CRU_W_MSK(0, 0x7), RK312X_CRU_CLKSELS_CON(1));
 225
 226         plls_resume(APLL_ID);
 227         cru_writel(cru_mode_con
 228                 |(RK312X_PLL_MODE_MSK(APLL_ID) << 16), RK312X_CRU_MODE_CON);
 229
 230
 231         /*peri aclk hclk pclk*/
 232         cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
 233         | CRU_W_MSK(12, 0x3)), RK312X_CRU_CLKSELS_CON(10));
 234
 235         /* crypto*/
 236         cru_writel(clk_sel24 | CRU_W_MSK(0, 0x3), RK312X_CRU_CLKSELS_CON(24));
 237
 238         cru_writel(clk_sel29 | CRU_W_MSK(8, 0x1f), RK312X_CRU_CLKSELS_CON(29));
 239
 240         /* pmu alive */
 241         plls_resume(GPLL_ID);
 242         cru_writel(cru_mode_con | (RK312X_PLL_MODE_MSK(GPLL_ID) << 16)
 243                 , RK312X_CRU_MODE_CON);
 244
 245         plls_resume(CPLL_ID);
 246         cru_writel(cru_mode_con | (RK312X_PLL_MODE_MSK(CPLL_ID) << 16)
 247                 , RK312X_CRU_MODE_CON);
 248 }
 249 #ifdef CONFIG_RK_LAST_LOG
 250 extern void rk_last_log_text(char *text, size_t size);
 251 #endif
 252
 253 static void  ddr_printch(char byte)
 254 {
 255         uart_printch(byte);
 256 #ifdef CONFIG_RK_LAST_LOG
 257         rk_last_log_text(&byte, 1);
 258
 259         if (byte == '\n') {
 260                 byte = '\r';
 261                 rk_last_log_text(&byte, 1);
 262         }
 263 #endif
 264         pll_udelay(2);
 265 }
 266
 267 static noinline void rk312x_pm_dump_inten(void)
 268 {
 269         DUMP_GPIO_INTEN(0);
 270         DUMP_GPIO_INTEN(1);
 271         DUMP_GPIO_INTEN(2);
 272         DUMP_GPIO_INTEN(3);
 273 }
 274 static noinline void rk312x_pm_dump_irq(void)
 275 {
 276         u32 irq[4];
 277         int i;
 278
 279         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT +
 280 GIC_DIST_PENDING_SET + 8) >> 4) & 0x0F;
 281
 282         for (i = 0; i < ARRAY_SIZE(irq); i++)
 283                 irq[i] = readl_relaxed(RK_GIC_VIRT +
 284 GIC_DIST_PENDING_SET + (1 + i) * 4);
 285         for (i = 0; i < ARRAY_SIZE(irq); i++) {
 286                 if (irq[i])
 287                         log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
 288         }
 289         for (i = 0; i <= 3; i++) {
 290                 if (irq_gpio & (1 << i)) {
 291                         pr_debug("wakeup gpio%d: %08x\n", i
 292                                 , readl_relaxed(RK_GPIO_VIRT(i)
 293                                 + GPIO_INT_STATUS));
 294                         rkpm_ddr_printascii("wakeup gpio");
 295                         rkpm_ddr_printhex(i);
 296                         rkpm_ddr_printascii(":");
 297                         rkpm_ddr_printhex(readl_relaxed(RK_GPIO_VIRT(i)
 298                                 + GPIO_INT_STATUS));
 299                         rkpm_ddr_printch('\n');
 300                 }
 301         }
 302 }
 303
 304 static void rkpm_prepare(void)
 305 {
 306         rk312x_pm_dump_inten();
 307 }
 308 static void rkpm_finish(void)
 309 {
 310         rk312x_pm_dump_irq();
 311 }
 312 enum rk312x_pwr_mode_con {
 313         pmu_power_mode_en = 0,
 314         pmu_clk_core_src_gate_en,
 315         pmu_clk_bus_src_gate_en,
 316         pmu_global_int_disable,
 317
 318         pmu_core_pd_en,
 319         pmu_use_if,
 320         pmu_wait_osc_24m,
 321         pmu_sref_enter_en,
 322
 323         pmu_ddr_gating_en,
 324         pmu_int_en,
 325         pmu_ddr0io_ret_de_req,
 326
 327         pmu_clr_crypto = 16,
 328         pmu_clr_msch,
 329         pmu_clr_sys,
 330         pmu_clr_core,
 331
 332         pmu_clr_gpu,
 333         pmu_clr_vio,
 334         pmu_clr_video,
 335         pmu_clr_peri,
 336 };
 337 #define SOC_REMAP 12
 338 #define GRF_SOC_CON0 0x140
 339
 340 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
 341 #define RKPM_BOOTRAM_PHYS (RK312X_IMEM_PHYS)
 342 #define RKPM_BOOTRAM_BASE (RK312X_IMEM_VIRT)
 343 #define RKPM_BOOTRAM_SIZE (RK312X_IMEM_SIZE)
 344
 345 /*sys resume code in boot ram*/
 346 #define  RKPM_BOOT_CODE_PHY  (RKPM_BOOTRAM_PHYS + RKPM_BOOT_CODE_OFFSET)
 347 #define  RKPM_BOOT_CODE_BASE  (RKPM_BOOTRAM_BASE + RKPM_BOOT_CODE_OFFSET)
 348
 349
 350 /*sys resume data in boot ram*/
 351 #define  RKPM_BOOT_DATA_PHY  (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DATA_OFFSET)
 352 #define  RKPM_BOOT_DATA_BASE  (RKPM_BOOTRAM_BASE + RKPM_BOOT_DATA_OFFSET)
 353
 354 /*ddr resume data in boot ram*/
 355 #define  RKPM_BOOT_DDRCODE_PHY   (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
 356 #define  RKPM_BOOT_DDRCODE_BASE  (RKPM_BOOTRAM_BASE + RKPM_BOOT_DDRCODE_OFFSET)
 357
 358 /*#define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))*/
 359 #define RKPM_BOOT_CPUSP_PHY (0x00 + ((RKPM_BOOTRAM_SIZE - 1) & (~(0x7))))
 360
 361 /*the value is used to control cpu resume flow*/
 362 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
 363 static char *resume_data_base = (char *)(RKPM_BOOT_DATA_BASE);
 364 /*static char *resume_data_phy=  (char *)( RKPM_BOOT_DATA_PHY);*/
 365
 366 /*****save boot sram**********************/
 367 #define BOOT_RAM_SAVE_SIZE (RKPM_BOOTRAM_SIZE + 4 * 10)
 368 #define INT_RAM_SIZE (64 * 1024)
 369 static char boot_ram_data[BOOT_RAM_SAVE_SIZE];/*8K + 40byte*/
 370 static char int_ram_data[INT_RAM_SIZE];
 371 /******resume code *****************
 372 #define RKPM_BOOT_CODE_OFFSET (0x00)
 373 #define RKPM_BOOT_CODE_PHY (RKPM_BOOTRAM_PHYS + PM_BOOT_CODE_OFFSET)
 374 #define RKPM_BOOT_CODE_BASE (RKPM_BOOTRAM_BASE + PM_BOOT_CODE_OFFSET)
 375 #define RKPM_BOOT_CODE_SIZE (0x100)
 376 **************************************************/
 377 extern void rkpm_slp_cpu_resume(void);
 378
 379 static void sram_data_for_sleep(char *boot_save, char *int_save, u32 flag)
 380 {
 381         char *addr_base, *addr_phy, *data_src, *data_dst;
 382         u32 sr_size, data_size;
 383
 384         addr_base = (char *)RKPM_BOOTRAM_BASE;
 385         addr_phy = (char *)RKPM_BOOTRAM_PHYS;
 386         sr_size = RKPM_BOOTRAM_SIZE;  /*SZ8k*/
 387         /**********save boot sarm***********************************/
 388         if (boot_save)
 389                 memcpy(boot_save, addr_base, sr_size);
 390         /**********move  resume code and data to boot sram*************/
 391         data_dst = (char *)RKPM_BOOT_CODE_BASE;
 392         data_src = (char *)rkpm_slp_cpu_resume;
 393         data_size = RKPM_BOOT_CODE_SIZE;
 394
 395         memcpy(data_dst, data_src, data_size);
 396         data_dst = (char *)resume_data_base;
 397         data_src = (char *)sleep_resume_data;
 398         data_size = sizeof(sleep_resume_data);
 399         memcpy((char *)data_dst, (char *)data_src, data_size);
 400 }
 401 static u32 rk312x_powermode;
 402 static u32 pmu_pwrmode_con;
 403 static u32 gpio_pmic_sleep_mode;
 404 static u32 grf_soc_con0;
 405 static u32 pmu_wakeup_conf;
 406 static u32 pmic_sleep_gpio;
 407
 408 static u32 rkpm_slp_mode_set(u32 ctrbits)
 409 {
 410         u32 pwr_mode_config;
 411
 412         if ((RKPM_CTR_ARMOFF_LPMD & ctrbits) == 0)
 413                 return 0;
 414
 415         pmu_wakeup_conf = pmu_readl(RK312X_PMU_WAKEUP_CFG);
 416         /*grf_soc_con0 = grf_readl(GRF_SOC_CON0);*/
 417         /*grf_writel((1 << SOC_REMAP)
 418         | (1 << (SOC_REMAP + 16)), GRF_SOC_CON0);*/
 419         /*grf_gpio1a_iomux = grf_readl(0x00b8);*/
 420         /*grf_writel(0x00030003, 0xb8);*/
 421
 422         pmu_writel(0x01, RK312X_PMU_WAKEUP_CFG);
 423         /* arm interrupt wake-up enable*/
 424         /*grf_writel((1 << SOC_REMAP)
 425         | (1 << (SOC_REMAP + 16)), GRF_SOC_CON0);*/
 426         /*remap bit control, when soc_remap = 1, the bootrom is mapped to
 427          address 0x10100000,and internal memory is mapped to address 0x0.*/
 428
 429         /*grf_writel(0X00030002, 0xb4);
 430         rk3126 GPIO1A1 : RK3128 GPIO3C1 iomux pmic-sleep*/
 431         if ((pmic_sleep_gpio == 0) || (pmic_sleep_gpio == 0x1a10)) {
 432                 gpio_pmic_sleep_mode = grf_readl(0xb8);
 433                 grf_writel(0X000C000C, 0xb8);
 434         }
 435         /*rk3126 GPIO1A1 : RK3128 GPIO3C1 iomux pmic-sleep*/
 436         if (pmic_sleep_gpio == 0x3c10) {
 437                 gpio_pmic_sleep_mode = grf_readl(0xe4);
 438                 grf_writel(0X000C0004, 0xe4);
 439         }
 440         /*rk3126 GPIO3C1 : RK3128 GPIO3C1 iomux pmic-sleep*/
 441
 442         pwr_mode_config = BIT(pmu_power_mode_en) | BIT(pmu_global_int_disable);
 443         pmu_pwrmode_con = pmu_readl(RK312X_PMU_PWRMODE_CON);
 444         if (rkpm_chk_val_ctrbits(ctrbits, RKPM_CTR_IDLEAUTO_MD)) {
 445                 rkpm_ddr_printascii("-autoidle-");
 446                 pwr_mode_config |= BIT(pmu_clk_core_src_gate_en);
 447         } else if (rkpm_chk_val_ctrbits(ctrbits, RKPM_CTR_ARMDP_LPMD)) {
 448                 rkpm_ddr_printascii("-armdp-");
 449                 pwr_mode_config |= BIT(pmu_core_pd_en);
 450         } else if (rkpm_chk_val_ctrbits(ctrbits, RKPM_CTR_ARMOFF_LPMD)) {
 451                 rkpm_ddr_printascii("-armoff-");
 452                 /*arm power off */
 453                 pwr_mode_config |= 0
 454                                 |BIT(pmu_clk_core_src_gate_en)
 455                                 |BIT(pmu_clk_bus_src_gate_en)
 456                                 | BIT(pmu_core_pd_en)
 457                         /*      | BIT(pmu_use_if)//aaa*/
 458                                 | BIT(pmu_sref_enter_en)
 459                                 |BIT(pmu_int_en)
 460                         /*      | BIT(pmu_wait_osc_24m)*/
 461                                 | BIT(pmu_ddr_gating_en)
 462                                 | BIT(pmu_ddr0io_ret_de_req)
 463                                 | BIT(pmu_clr_core)
 464                                 | BIT(pmu_clr_crypto)
 465                                 | BIT(pmu_clr_sys)
 466                                 /*| BIT(pmu_clr_vio)*/
 467                                 /*| BIT(pmu_clr_video)*/
 468                                 | BIT(pmu_clr_peri)
 469                                 | BIT(pmu_clr_msch)
 470                                 /*| BIT(pmu_clr_gpu) */
 471                                 ;
 472         }
 473         pmu_writel(32 * 30, RK312X_PMU_OSC_CNT);
 474         pmu_writel(pwr_mode_config, RK312X_PMU_PWRMODE_CON);
 475         rk312x_powermode = pwr_mode_config;
 476         return pmu_readl(RK312X_PMU_PWRMODE_CON);
 477 }
 478
 479 static void sram_code_data_save(u32 pwrmode)
 480 {
 481         sleep_resume_data[RKPM_BOOTDATA_L2LTY_F] = 0;
 482         sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F] = 0;
 483         sleep_resume_data[RKPM_BOOTDATA_DDR_F] = 0;
 484         sleep_resume_data[RKPM_BOOTDATA_CPUSP] = RKPM_BOOT_CPUSP_PHY;
 485         /*in sys resume ,ddr is need resume*/
 486         sleep_resume_data[RKPM_BOOTDATA_CPUCODE] = virt_to_phys(cpu_resume);
 487         /*in sys resume ,ddr is need resume*/
 488
 489         sram_data_for_sleep(boot_ram_data, int_ram_data, 1);
 490         flush_cache_all();
 491         outer_flush_all();
 492         local_flush_tlb_all();
 493 }
 494
 495 #define  RK_GICD_BASE (RK_GIC_VIRT)
 496 #define RK_GICC_BASE (RK_GIC_VIRT+RK312X_GIC_DIST_SIZE)
 497 #define PM_IRQN_START 32
 498 #define PM_IRQN_END     107
 499 #define gic_reg_dump(a, b, c)  {}
 500 static u32 slp_gic_save[260+50];
 501
 502 static void rkpm_gic_dist_save(u32 *context)
 503 {
 504         int i = 0, j, irqstart = 0;
 505         unsigned int gic_irqs;
 506
 507         gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 508         gic_irqs = (gic_irqs + 1) * 32;
 509         if (gic_irqs > 1020)
 510                 gic_irqs = 1020;
 511
 512         irqstart = PM_IRQN_START;
 513
 514         i = 0;
 515
 516         for (j = irqstart; j < gic_irqs; j += 16)
 517                 context[i++] = readl_relaxed(RK_GICD_BASE
 518                 + GIC_DIST_CONFIG + (j * 4) / 16);
 519         gic_reg_dump("gic level", j, RK_GICD_BASE + GIC_DIST_CONFIG);
 520
 521         /*
 522         * Set all global interrupts to this CPU only.
 523         */
 524         for (j = 0; j < gic_irqs; j += 4)
 525                 context[i++] = readl_relaxed(RK_GICD_BASE
 526                 + GIC_DIST_TARGET +     (j * 4) / 4);
 527         gic_reg_dump("gic trig", j, RK_GICD_BASE + GIC_DIST_TARGET);
 528
 529         for (j = 0; j < gic_irqs; j += 4)
 530                 context[i++] = readl_relaxed(RK_GICD_BASE
 531                 + GIC_DIST_PRI + (j * 4) / 4);
 532         gic_reg_dump("gic pri", j, RK_GICD_BASE + GIC_DIST_PRI);
 533
 534         for (j = 0; j < gic_irqs; j += 32)
 535                 context[i++] = readl_relaxed(RK_GICD_BASE
 536                 + GIC_DIST_IGROUP + (j * 4) / 32);
 537         gic_reg_dump("gic secure", j, RK_GICD_BASE + 0x80);
 538
 539         for (j = irqstart; j < gic_irqs; j += 32)
 540                 context[i++] = readl_relaxed(RK_GICD_BASE
 541                 + GIC_DIST_PENDING_SET + (j * 4) / 32);
 542         gic_reg_dump("gic PENDING",  j,  RK_GICD_BASE
 543                 + GIC_DIST_PENDING_SET);
 544
 545         for (j = 0; j < gic_irqs; j += 32)
 546                 context[i++] = readl_relaxed(RK_GICD_BASE
 547                 + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 548         gic_reg_dump("gic en", j, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 549         gic_reg_dump("gicc", 0x1c, RK_GICC_BASE);
 550         gic_reg_dump("giccfc", 0,  RK_GICC_BASE + 0xfc);
 551
 552         context[i++] = readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 553         context[i++] = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 554         context[i++] = readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 555         /*
 556         context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
 557         context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 558         context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
 559         context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 560         context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 561         */
 562         for (j = irqstart; j < gic_irqs; j += 32) {
 563                 writel_relaxed(0xffffffff, RK_GICD_BASE
 564                         + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 565                 dsb();
 566         }
 567         writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 568         writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 569
 570         writel_relaxed(0, RK_GICC_BASE + GIC_CPU_CTRL);
 571         writel_relaxed(0, RK_GICD_BASE + GIC_DIST_CTRL);
 572 }
 573 static void  rkpm_peri_save(u32 power_mode)
 574 {
 575         rkpm_gic_dist_save(&slp_gic_save[0]);
 576 }
 577
 578 static void rkpm_save_setting(u32 ctrbits)
 579 {
 580         u32 pd_cpu;
 581
 582         if ((RKPM_CTR_ARMOFF_LPMD & ctrbits) == 0)
 583                 return;
 584
 585         rkpm_slp_mode_set(ctrbits);
 586         if (rk312x_powermode & BIT(pmu_power_mode_en)) {
 587                 sram_code_data_save(rk312x_powermode);
 588                 rkpm_peri_save(rk312x_powermode);
 589         }
 590         grf_soc_con0 = grf_readl(GRF_SOC_CON0);
 591
 592         grf_writel((1 << SOC_REMAP) | (1 << (SOC_REMAP + 16)), GRF_SOC_CON0);
 593
 594         for (pd_cpu = PD_CPU_1; pd_cpu <= PD_CPU_3; pd_cpu++) {
 595                 writel_relaxed(0x20000 << (pd_cpu - PD_CPU_1),
 596                                RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 597                 dsb();
 598                 udelay(10);
 599         }
 600 }
 601
 602 #define UART_DLL        0       /* Out: Divisor Latch Low */
 603 #define UART_DLM        1       /* Out: Divisor Latch High */
 604 #define UART_IER        1
 605 #define UART_FCR        2
 606 #define UART_LCR        3       /* Out: Line Control Register */
 607 #define UART_MCR        4
 608
 609 void slp312x_uartdbg_resume(void)
 610 {
 611         void __iomem *b_addr = RK_DEBUG_UART_VIRT;
 612         u32 pclk_id = RK312X_CLKGATE_PCLK_UART2;
 613         u32 clk_id = (RK312X_CLKGATE_UART0_SRC + 2 * 2);
 614         u32 gate_reg[2];
 615         u32 rfl_reg, lsr_reg;
 616
 617         gate_reg[0] = cru_readl(RK312X_CRU_GATEID_CONS(pclk_id));
 618         gate_reg[1] = cru_readl(RK312X_CRU_GATEID_CONS(clk_id));
 619
 620         RK312X_CRU_UNGATING_OPS(pclk_id);
 621         grf_writel(0x00f00000, 0x00c0);
 622
 623         do {
 624                 cru_writel(CRU_W_MSK_SETBITS(0x2, 8, 0x3)
 625                         , RK312X_CRU_CLKSELS_CON(16));
 626                 cru_writel(0|CRU_W_MSK_SETBITS(1, 9, 0x1)
 627                         , RK312X_CRU_SOFTRSTS_CON(2));
 628                 dsb();
 629                 dsb();
 630                 rkpm_udelay(10);
 631                 cru_writel(0 | CRU_W_MSK_SETBITS(0, 9, 0x1)
 632                         , RK312X_CRU_SOFTRSTS_CON(2));
 633
 634                 reg_writel(0x83, b_addr + UART_LCR*4);
 635
 636                 reg_writel(0xd, b_addr + UART_DLL*4);
 637                 reg_writel(0x0, b_addr + UART_DLM*4);
 638
 639                 reg_writel(0x3, b_addr + UART_LCR*4);
 640
 641                 reg_writel(0x5, b_addr + UART_IER*4);
 642                 reg_writel(0xc1, b_addr + UART_FCR*4);
 643
 644                 rfl_reg = readl_relaxed(b_addr + 0x84);
 645                 lsr_reg = readl_relaxed(b_addr + 0x14);
 646         } while ((rfl_reg & 0x1f) || (lsr_reg & 0xf));
 647
 648         cru_writel(CRU_W_MSK_SETBITS(0x2, 8, 0x3), RK312X_CRU_CLKSELS_CON(16));
 649
 650         grf_writel(0x00f000a0, 0x00c0);
 651
 652         cru_writel(gate_reg[0] | CRU_W_MSK(pclk_id % 16, 0x1)
 653                 , RK312X_CRU_GATEID_CONS(pclk_id));
 654         cru_writel(gate_reg[1] | CRU_W_MSK(clk_id % 16, 0x1)
 655                 , RK312X_CRU_GATEID_CONS(clk_id));
 656 }
 657
 658 static void rkpm_gic_dist_resume(u32 *context)
 659 {
 660         int i = 0, j, irqstart = 0;
 661         unsigned int gic_irqs;
 662
 663         gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 664         gic_irqs = (gic_irqs + 1) * 32;
 665         if (gic_irqs > 1020)
 666                 gic_irqs = 1020;
 667
 668         irqstart = PM_IRQN_START;
 669
 670         writel_relaxed(0, RK_GICC_BASE + GIC_CPU_CTRL);
 671         dsb();
 672         writel_relaxed(0, RK_GICD_BASE + GIC_DIST_CTRL);
 673         dsb();
 674         for (j = irqstart; j < gic_irqs; j += 32) {
 675                 writel_relaxed(0xffffffff, RK_GICD_BASE
 676                         + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 677                 dsb();
 678         }
 679
 680         i = 0;
 681
 682         for (j = irqstart; j < gic_irqs; j += 16) {
 683                 writel_relaxed(context[i++], RK_GICD_BASE
 684                         + GIC_DIST_CONFIG + j * 4 / 16);
 685                 dsb();
 686         }
 687         gic_reg_dump("gic level",  j,  RK_GICD_BASE + GIC_DIST_CONFIG);
 688
 689         /*
 690         * Set all global interrupts to this CPU only.
 691         */
 692         for (j = 0; j < gic_irqs; j += 4) {
 693                 writel_relaxed(context[i++], RK_GICD_BASE
 694                         + GIC_DIST_TARGET +  (j * 4) / 4);
 695                 dsb();
 696         }
 697         gic_reg_dump("gic target", j, RK_GICD_BASE + GIC_DIST_TARGET);
 698
 699         for (j = 0; j < gic_irqs; j += 4) {
 700                 writel_relaxed(context[i++], RK_GICD_BASE
 701                         + GIC_DIST_PRI + (j * 4) / 4);
 702                 dsb();
 703         }
 704         gic_reg_dump("gic pri",  j,  RK_GICD_BASE + GIC_DIST_PRI);
 705
 706         for (j = 0; j < gic_irqs; j += 32) {
 707                 writel_relaxed(context[i++], RK_GICD_BASE
 708                         + GIC_DIST_IGROUP + (j * 4) / 32);
 709                 dsb();
 710         }
 711         gic_reg_dump("gic secu",  j, RK_GICD_BASE + 0x80);
 712
 713         for (j = irqstart; j < gic_irqs; j += 32) {
 714                 /*writel_relaxed(context[i++],
 715                 RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);*/
 716                 i++;
 717                 dsb();
 718         }
 719
 720         gic_reg_dump("gic pending",  j,  RK_GICD_BASE + GIC_DIST_PENDING_SET);
 721
 722         if (0) {
 723                 for (j = 0; j < gic_irqs; j += 32) {
 724                         writel_relaxed(context[i++], RK_GICD_BASE
 725                                 + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 726                         dsb();
 727                 }
 728                 gic_reg_dump("gic disable", j, RK_GICD_BASE
 729                         + GIC_DIST_ENABLE_CLEAR);
 730         } else {
 731                 for (j = irqstart; j < gic_irqs; j += 32)
 732                         writel_relaxed(0xffffffff, RK_GICD_BASE
 733                         + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 734                 writel_relaxed(0xffff0000,  RK_GICD_BASE
 735                         + GIC_DIST_ENABLE_CLEAR);
 736                 writel_relaxed(0x0000ffff,  RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 737         }
 738
 739         /*enable*/
 740         for (j = 0; j < gic_irqs; j += 32) {
 741                 writel_relaxed(context[i++], RK_GICD_BASE
 742                         + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 743                 dsb();
 744         }
 745
 746         gic_reg_dump("gic enable", j, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 747
 748         writel_relaxed(context[i++], RK_GICC_BASE + GIC_CPU_PRIMASK);
 749         writel_relaxed(context[i++], RK_GICD_BASE + GIC_DIST_CTRL);
 750         writel_relaxed(context[i++], RK_GICC_BASE + GIC_CPU_CTRL);
 751
 752         gic_reg_dump("gicc", 0x1c, RK_GICC_BASE);
 753         gic_reg_dump("giccfc", 0, RK_GICC_BASE + 0xfc);
 754 }
 755
 756 static void sram_data_resume(char *boot_save, char *int_save, u32 flag)
 757 {
 758         char *addr_base, *addr_phy;
 759         u32 sr_size;
 760
 761         addr_base = (char *)RKPM_BOOTRAM_BASE;
 762         addr_phy = (char *)RKPM_BOOTRAM_PHYS;
 763         sr_size = RKPM_BOOTRAM_SIZE;
 764         /* save boot sram*/
 765         if (boot_save)
 766                 memcpy(addr_base, boot_save,  sr_size);
 767
 768         flush_icache_range((unsigned long)addr_base
 769                 , (unsigned long)addr_base + sr_size);
 770         outer_clean_range((phys_addr_t) addr_phy
 771                 , (phys_addr_t)addr_phy+sr_size);
 772 }
 773
 774 static inline void sram_code_data_resume(u32 pwrmode)
 775 {
 776         sram_data_resume(boot_ram_data
 777                 , int_ram_data, sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
 778 }
 779
 780 static inline void  rkpm_slp_mode_set_resume(void)
 781 {
 782         u32 pd_cpu;
 783
 784         pmu_writel(pmu_wakeup_conf, RK312X_PMU_WAKEUP_CFG);
 785         /* arm interrupt wake-up enable*/
 786         pmu_writel(pmu_pwrmode_con, RK312X_PMU_PWRMODE_CON);
 787
 788         for (pd_cpu = PD_CPU_1; pd_cpu <= PD_CPU_3; pd_cpu++) {
 789                 writel_relaxed(0x20002 << (pd_cpu - PD_CPU_1),
 790                                RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 791                 dsb();
 792                 udelay(10);
 793         }
 794
 795         grf_writel(grf_soc_con0 | (1 << (SOC_REMAP + 16)), GRF_SOC_CON0);
 796
 797         if ((pmic_sleep_gpio == 0) || (pmic_sleep_gpio == 0x1a10))
 798                 grf_writel(0X000C000C | gpio_pmic_sleep_mode, 0xb8);
 799         /*rk3126 GPIO1A1 : RK3128 GPIO3C1 iomux pmic-sleep*/
 800         if (pmic_sleep_gpio == 0x3c10)
 801                 grf_writel(0X000C0004 | gpio_pmic_sleep_mode, 0xe4);
 802 }
 803
 804 void fiq_glue_resume(void);
 805
 806 static inline void  rkpm_peri_resume(u32 power_mode)
 807 {
 808         rkpm_gic_dist_resume(&slp_gic_save[0]);
 809         fiq_glue_resume();
 810 }
 811
 812 static void rkpm_save_setting_resume(void)
 813 {
 814         if (rk312x_powermode == 0)
 815                 return;
 816
 817         rkpm_slp_mode_set_resume();
 818         if (rk312x_powermode & BIT(pmu_power_mode_en)) {
 819                 rkpm_peri_resume(rk312x_powermode);
 820                 sram_code_data_resume(rk312x_powermode);
 821         }
 822 }
 823 static inline void  rkpm_peri_resume_first(u32 power_mode)
 824 {
 825         slp312x_uartdbg_resume();
 826 }
 827 static void rkpm_slp_setting(void)
 828 {
 829         rk_usb_power_down();
 830 }
 831 static void rkpm_save_setting_resume_first(void)
 832 {
 833         rk_usb_power_up();
 834         rkpm_peri_resume_first(pmu_pwrmode_con);
 835 }
 836 static u32 clk_ungt_msk[RK312X_CRU_CLKGATES_CON_CNT];
 837 /*first clk gating setting*/
 838
 839 static u32 clk_ungt_msk_1[RK312X_CRU_CLKGATES_CON_CNT];
 840 /* first clk gating setting*/
 841
 842 static u32 clk_ungt_save[RK312X_CRU_CLKGATES_CON_CNT];
 843 /*first clk gating value saveing*/
 844
 845 static u32 *p_rkpm_clkgt_last_set;
 846 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
 847 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
 848
 849 static void gtclks_suspend(void)
 850 {
 851         int i;
 852
 853         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 854                 clk_ungt_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 855                 CLK_MSK_UNGATING(clk_ungt_msk[i], RK312X_CRU_CLKGATES_CON(i));
 856         }
 857 }
 858
 859 static void gtclks_resume(void)
 860 {
 861         int i;
 862
 863         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 864                 cru_writel(clk_ungt_save[i] | 0xffff0000
 865                 , RK312X_CRU_CLKGATES_CON(i));
 866 }
 867 static void clks_gating_suspend_init(void)
 868 {
 869         p_rkpm_clkgt_last_set = &clk_ungt_msk_1[0];
 870         if (clk_suspend_clkgt_info_get(clk_ungt_msk, p_rkpm_clkgt_last_set
 871                 , RK312X_CRU_CLKGATES_CON_CNT) == RK312X_CRU_CLKGATES_CON(0))
 872                 rkpm_set_ops_gtclks(gtclks_suspend, gtclks_resume);
 873 }
 874 static void pmic_sleep_gpio_get_dts_info(struct device_node *parent)
 875 {
 876         struct property *prop;
 877
 878         prop = of_find_property(parent, "rockchip,pmic-suspend_gpios", NULL);
 879         if (!prop)
 880                 return;
 881         if (!prop->value)
 882                 return;
 883
 884         of_property_read_u32_array(parent, "rockchip,pmic-suspend_gpios"
 885                 , &pmic_sleep_gpio, 1);
 886 }
 887
 888 #define SRAM_LOOPS_PER_USEC     24
 889 #define SRAM_LOOP(loops)       \
 890         do {\
 891                 unsigned int i = (loops);\
 892                 if (i < 7)\
 893                         i = 7;\
 894         barrier();\
 895         asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));\
 896         } while (0)
 897 /* delay on slow mode */
 898 #define sram_udelay(usecs)      SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
 899 /* delay on deep slow mode */
 900 #define sram_32k_udelay(usecs)  SRAM_LOOP(((usecs)*\
 901         SRAM_LOOPS_PER_USEC)/(24000000/32768))
 902
 903 void PIE_FUNC(ddr_suspend)(void);
 904 void PIE_FUNC(ddr_resume)(void);
 905
 906 void PIE_FUNC(pwm_regulator_suspend)(void)
 907 {
 908         int gpio0_inout;
 909         int gpio0_ddr;
 910         int clk_gates8;
 911
 912         clk_gates8 = cru_readl(0xf0);
 913         cru_writel(0x1e000000, 0xf0);
 914         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
 915                 grf_writel(0x00100000, 0xb4);/*iomux  gpio0d2*/
 916                 gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
 917                 gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
 918                 writel_relaxed(gpio0_inout | 0x04000000
 919                         , RK_GPIO_VIRT(0) + 0x04);
 920                 dsb();
 921                 writel_relaxed(gpio0_ddr | 0x04000000, RK_GPIO_VIRT(0));
 922         }
 923
 924         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
 925                 grf_writel(0x00400000, 0xb4);/*iomux  gpio0d3*/
 926                 gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
 927                 gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
 928                 writel_relaxed(gpio0_inout | 0x08000000
 929                         , RK_GPIO_VIRT(0) + 0x04);
 930                 dsb();
 931                 writel_relaxed(gpio0_ddr | 0x08000000, RK_GPIO_VIRT(0));
 932         }
 933
 934         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
 935                 grf_writel(0x01000000, 0xb4);/*iomux  gpio0d2*/
 936                 gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
 937                 gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
 938                 writel_relaxed(gpio0_inout | 0x08000000, RK_GPIO_VIRT(0) + 0x04);
 939                 dsb();
 940                 writel_relaxed(gpio0_ddr | 0x08000000, RK_GPIO_VIRT(0));
 941         }
 942         cru_writel(0x1e000000 | clk_gates8, 0xf0);
 943         sram_udelay(30);
 944 }
 945
 946 void PIE_FUNC(pwm_regulator_resume)(void)
 947 {
 948         int gpio0_inout;
 949         int gpio0_ddr;
 950         int clk_gates8;
 951
 952         clk_gates8 = cru_readl(0xf0);
 953         cru_writel(0x1e000000, 0xf0);
 954         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
 955                 gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
 956                 gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
 957                 writel_relaxed(gpio0_inout | 0x04000000, RK_GPIO_VIRT(0)
 958                         + 0x04);
 959                 dsb();
 960                 writel_relaxed(gpio0_ddr &  ~0x04000000, RK_GPIO_VIRT(0));
 961                 grf_writel(0x00100010, 0xb4);/*iomux  gpio0d2*/
 962         }
 963
 964         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
 965                 grf_writel(0x00400040, 0xb4);/*iomux  gpio0d3*/
 966                 gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
 967                 gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
 968                 writel_relaxed(gpio0_inout | 0x08000000, RK_GPIO_VIRT(0)
 969                         + 0x04);
 970                 dsb();
 971                 writel_relaxed(gpio0_ddr | ~0x08000000, RK_GPIO_VIRT(0));
 972         }
 973
 974         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
 975                 gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
 976                 gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
 977                 writel_relaxed(gpio0_inout | 0x08000000, RK_GPIO_VIRT(0)
 978                         + 0x04);
 979                 dsb();
 980                 writel_relaxed(gpio0_ddr | ~0x08000000, RK_GPIO_VIRT(0));
 981                 grf_writel(0x01001000, 0xb4);/*iomux  gpio0d2*/
 982         }
 983         cru_writel(0x1e000000 | clk_gates8, 0xf0);
 984         sram_udelay(30);
 985 }
 986 static void reg_pread(void)
 987 {
 988         int i;
 989         volatile u32 n;
 990
 991         volatile u32 *temp = (volatile unsigned int *)rockchip_sram_virt;
 992
 993         flush_cache_all();
 994         outer_flush_all();
 995         local_flush_tlb_all();
 996
 997         for (i = 0; i < 2; i++) {
 998                 n = temp[1024 * i];
 999                 barrier();
1000         }
1001
1002         n = readl_relaxed(RK_GPIO_VIRT(0));
1003         n = readl_relaxed(RK_GPIO_VIRT(1));
1004         n = readl_relaxed(RK_GPIO_VIRT(1) + 4);
1005
1006         n = readl_relaxed(RK_GPIO_VIRT(2));
1007         n = readl_relaxed(RK_GPIO_VIRT(3));
1008
1009         n = readl_relaxed(RK_DEBUG_UART_VIRT);
1010         n = readl_relaxed(RK_CPU_AXI_BUS_VIRT);
1011         n = readl_relaxed(RK_DDR_VIRT);
1012         n = readl_relaxed(RK_GRF_VIRT);
1013         n = readl_relaxed(RK_CRU_VIRT);
1014         n = readl_relaxed(RK_PMU_VIRT);
1015 }
1016
1017 static void __init rk312x_suspend_init(void)
1018 {
1019         struct device_node *parent;
1020         u32 pm_ctrbits;
1021
1022         pr_info("%s\n", __func__);
1023         parent = of_find_node_by_name(NULL, "rockchip_suspend");
1024
1025         if (IS_ERR_OR_NULL(parent)) {
1026                 PM_ERR("%s dev node err\n",  __func__);
1027                 return;
1028         }
1029
1030         if (of_property_read_u32_array(parent
1031                 , "rockchip,ctrbits", &pm_ctrbits, 1)) {
1032                 PM_ERR("%s:get pm ctr error\n", __func__);
1033         return;
1034         }
1035         pmic_sleep_gpio_get_dts_info(parent);
1036         rkpm_set_ctrbits(pm_ctrbits);
1037         clks_gating_suspend_init();
1038         rkpm_set_ops_prepare_finish(rkpm_prepare, rkpm_finish);
1039         rkpm_set_ops_plls(pm_plls_suspend, pm_plls_resume);
1040         rkpm_set_ops_save_setting(rkpm_save_setting
1041                 , rkpm_save_setting_resume);
1042         rkpm_set_ops_regs_sleep(rkpm_slp_setting
1043                 , rkpm_save_setting_resume_first);
1044         rkpm_set_ops_regs_pread(reg_pread);
1045         rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk
1046                 , &FUNC(ddr_suspend))
1047                 , fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)));
1048         rkpm_set_sram_ops_volt(fn_to_pie(rockchip_pie_chunk
1049                 , &FUNC(pwm_regulator_suspend))
1050                 , fn_to_pie(rockchip_pie_chunk, &FUNC(pwm_regulator_resume)));
1051         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk
1052                 , &FUNC(sram_printch)));
1053         rkpm_set_ops_printch(ddr_printch);
1054 }