2 * Copyright (C) 2013-2015 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
12 #include <linux/platform_device.h>
13 #include <linux/rockchip/cpu.h>
14 #include <linux/rockchip/iomap.h>
15 #include <asm/compiler.h>
17 #include <asm/system_info.h>
21 #define efuse_readl(offset) readl_relaxed(RK_EFUSE_VIRT + offset)
22 #define efuse_writel(val, offset) writel_relaxed(val, RK_EFUSE_VIRT + offset)
25 static u8 efuse_buf[32] = {};
27 struct rockchip_efuse {
28 int (*get_leakage)(int ch);
29 int (*get_temp)(int ch);
34 static struct rockchip_efuse efuse;
37 /****************************secure reg access****************************/
39 #define SEC_REG_RW_SHT (0x0)
40 #define SEC_REG_RD (0x0)
41 #define SEC_REG_WR (0x1)
43 #define SEC_REG_BITS_SHT (0x1)
44 #define SEC_REG_32 (0x0)
45 #define SEC_REG_64 (0x2)
47 #define SEC_REG_RD_32 (SEC_REG_RD | SEC_REG_32)
48 #define SEC_REG_RD_64 (SEC_REG_RD | SEC_REG_64)
49 #define SEC_REG_WR_32 (SEC_REG_WR | SEC_REG_32)
50 #define SEC_REG_WR_64 (SEC_REG_WR | SEC_REG_64)
52 #define PSCI_SIP_ACCESS_REG (0x82000002)
53 #define PSCI_SIP_RKTF_VER (0x82000001)
55 static phys_addr_t efuse_phys;
58 * arg2: rd/wr control, bit[0] 0-rd 1-rt, bit[1] 0-32bit, 1-64bit
60 * arg0: read or write val
61 * function_id: return fail/succes
63 static u32 reg_wr_fn_smc(u64 function_id, u64 arg0, u64 arg1, u64 arg2)
71 : "+r" (function_id), "+r" (arg0)
72 : "r" (arg1), "r" (arg2));
77 static u32 reg_rd_fn_smc(u64 function_id, u64 arg0, u64 arg1, u64 arg2,
86 : "+r" (function_id), "+r" (arg0)
87 : "r" (arg1), "r" (arg2));
94 static u32 (*reg_wr_fn)(u64, u64, u64, u64) = reg_wr_fn_smc;
95 static u32 (*reg_rd_fn)(u64, u64, u64, u64, u64 *) = reg_rd_fn_smc;
97 static u32 secure_regs_rd_32(u64 addr_phy)
101 reg_rd_fn(PSCI_SIP_ACCESS_REG, 0, addr_phy, SEC_REG_RD_32, &val);
105 static u32 secure_regs_wr_32(u64 addr_phy, u32 val)
109 return reg_wr_fn(PSCI_SIP_ACCESS_REG, val_64, addr_phy, SEC_REG_WR_32);
112 static u32 efuse_readl(u32 offset)
114 return secure_regs_rd_32(efuse_phys + offset);
117 static void efuse_writel(u32 val, u32 offset)
119 secure_regs_wr_32(efuse_phys + offset, val);
122 #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
123 #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
125 #define RKTF_VLDVER_MAJOR (1)
126 #define RKTF_VLDVER_MINOR (3)
129 static int __init rockchip_tf_ver_check(void)
134 ver_val = reg_rd_fn(PSCI_SIP_RKTF_VER, 0, 0, 0, &val);
135 if (ver_val == 0xffffffff)
138 if ((RKTF_VER_MAJOR(ver_val) >= RKTF_VLDVER_MAJOR) &&
139 (RKTF_VER_MINOR(ver_val) >= RKTF_VLDVER_MINOR))
144 pr_err("read tf version 0x%x!\n", ver_val);
148 pr_err("trusted firmware need to update to(%d.%d) or is invaild!\n",
149 RKTF_VLDVER_MAJOR, RKTF_VLDVER_MINOR);
154 device_initcall_sync(rockchip_tf_ver_check);
157 static int rk3288_efuse_readregs(u32 addr, u32 length, u8 *buf)
166 efuse_writel(EFUSE_CSB, REG_EFUSE_CTRL);
167 efuse_writel(EFUSE_LOAD | EFUSE_PGENB, REG_EFUSE_CTRL);
170 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
171 (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), REG_EFUSE_CTRL);
172 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
173 ((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT),
176 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
177 EFUSE_STROBE, REG_EFUSE_CTRL);
179 *buf = efuse_readl(REG_EFUSE_DOUT);
180 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
181 (~EFUSE_STROBE), REG_EFUSE_CTRL);
187 efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_CSB, REG_EFUSE_CTRL);
193 static int __init rk3288_get_efuse_version(void)
195 int ret = efuse_buf[4] & (~(0x1 << 3));
199 static int __init rk3288_get_process_version(void)
201 int ret = efuse_buf[6]&0x0f;
206 static int rk3288_get_leakage(int ch)
208 if ((ch < 0) || (ch > 2))
211 return efuse_buf[23+ch];
215 static void __init rk3288_set_system_serial(void)
220 for (i = 0; i < 8; i++) {
221 buf[i] = efuse_buf[8 + (i << 1)];
222 buf[i + 8] = efuse_buf[7 + (i << 1)];
225 system_serial_low = crc32(0, buf, 8);
226 system_serial_high = crc32(system_serial_low, buf + 8, 8);
229 static inline void __init rk3288_set_system_serial(void) {}
232 int rk312x_efuse_readregs(u32 addr, u32 length, u8 *buf)
239 efuse_writel(EFUSE_LOAD, REG_EFUSE_CTRL);
242 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
243 (~(EFUSE_A_MASK << RK312X_EFUSE_A_SHIFT)),
245 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
246 ((addr & EFUSE_A_MASK) << RK312X_EFUSE_A_SHIFT),
249 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
250 EFUSE_STROBE, REG_EFUSE_CTRL);
252 *buf = efuse_readl(REG_EFUSE_DOUT);
253 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
254 (~EFUSE_STROBE), REG_EFUSE_CTRL);
260 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
261 (~EFUSE_LOAD) , REG_EFUSE_CTRL);
267 int rockchip_efuse_version(void)
269 return efuse.efuse_version;
272 int rockchip_process_version(void)
274 return efuse.process_version;
277 int rockchip_get_leakage(int ch)
281 if (efuse.get_leakage) {
282 return efuse.get_leakage(ch);
284 ret = rk3288_efuse_readregs(0, 32, efuse_buf);
286 return efuse_buf[23+ch];
291 int rockchip_efuse_get_temp_adjust(int ch)
295 if (efuse_buf[31] & 0x80)
296 temp = -(efuse_buf[31] & 0x7f);
298 temp = efuse_buf[31];
303 static void __init rk3288_efuse_init(void)
307 ret = rk3288_efuse_readregs(0, 32, efuse_buf);
309 efuse.get_leakage = rk3288_get_leakage;
310 efuse.efuse_version = rk3288_get_efuse_version();
311 efuse.process_version = rk3288_get_process_version();
312 rockchip_set_cpu_version((efuse_buf[6] >> 4) & 3);
313 rk3288_set_system_serial();
315 pr_err("failed to read eFuse, return %d\n", ret);
319 void __init rockchip_efuse_init(void)
323 if (cpu_is_rk3288()) {
325 } else if (cpu_is_rk312x()) {
326 ret = rk312x_efuse_readregs(0, 32, efuse_buf);
328 efuse.get_leakage = rk3288_get_leakage;
330 pr_err("failed to read eFuse, return %d\n", ret);
335 static int __init rockchip_efuse_probe(struct platform_device *pdev)
337 struct resource *regs;
339 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 dev_err(&pdev->dev, "failed to get I/O memory\n");
344 efuse_phys = regs->start;
350 static const struct of_device_id rockchip_efuse_of_match[] = {
351 { .compatible = "rockchip,rk3368-efuse-256", .data = NULL, },
355 static struct platform_driver rockchip_efuse_driver = {
358 .owner = THIS_MODULE,
359 .of_match_table = of_match_ptr(rockchip_efuse_of_match),
363 static int __init rockchip_efuse_module_init(void)
365 return platform_driver_probe(&rockchip_efuse_driver,
366 rockchip_efuse_probe);
368 arch_initcall_sync(rockchip_efuse_module_init);