2 * Copyright (C) 2013-2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
11 #include <linux/rockchip/cpu.h>
12 #include <linux/rockchip/iomap.h>
13 #include <asm/system_info.h>
16 #define efuse_readl(offset) readl_relaxed(RK_EFUSE_VIRT + offset)
17 #define efuse_writel(val, offset) writel_relaxed(val, RK_EFUSE_VIRT + offset)
19 static u8 efuse_buf[32] = {};
21 struct rockchip_efuse {
22 int (*get_leakage)(int ch);
27 static struct rockchip_efuse efuse;
29 static int __init rk3288_efuse_readregs(u32 addr, u32 length, u8 *buf)
38 efuse_writel(EFUSE_CSB, REG_EFUSE_CTRL);
39 efuse_writel(EFUSE_LOAD | EFUSE_PGENB, REG_EFUSE_CTRL);
42 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
43 (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), REG_EFUSE_CTRL);
44 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
45 ((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT),
48 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
49 EFUSE_STROBE, REG_EFUSE_CTRL);
51 *buf = efuse_readl(REG_EFUSE_DOUT);
52 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
53 (~EFUSE_STROBE), REG_EFUSE_CTRL);
59 efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_CSB, REG_EFUSE_CTRL);
65 static int __init rk3288_get_efuse_version(void)
67 int ret = efuse_buf[4] & (~(0x1 << 3));
71 static int __init rk3288_get_process_version(void)
73 int ret = efuse_buf[6]&0x0f;
78 static int rk3288_get_leakage(int ch)
80 if ((ch < 0) || (ch > 2))
83 return efuse_buf[23+ch];
86 static void __init rk3288_set_system_serial(void)
91 for (i = 0; i < 8; i++) {
92 buf[i] = efuse_buf[8 + (i << 1)];
93 buf[i + 8] = efuse_buf[7 + (i << 1)];
96 system_serial_low = crc32(0, buf, 8);
97 system_serial_high = crc32(system_serial_low, buf + 8, 8);
100 int rk312x_efuse_readregs(u32 addr, u32 length, u8 *buf)
107 efuse_writel(EFUSE_LOAD, REG_EFUSE_CTRL);
110 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
111 (~(EFUSE_A_MASK << RK312X_EFUSE_A_SHIFT)),
113 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
114 ((addr & EFUSE_A_MASK) << RK312X_EFUSE_A_SHIFT),
117 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
118 EFUSE_STROBE, REG_EFUSE_CTRL);
120 *buf = efuse_readl(REG_EFUSE_DOUT);
121 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
122 (~EFUSE_STROBE), REG_EFUSE_CTRL);
128 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
129 (~EFUSE_LOAD) , REG_EFUSE_CTRL);
135 int rockchip_efuse_version(void)
137 return efuse.efuse_version;
140 int rockchip_process_version(void)
142 return efuse.process_version;
145 int rockchip_get_leakage(int ch)
147 if (efuse.get_leakage)
148 return efuse.get_leakage(ch);
152 void __init rockchip_efuse_init(void)
156 if (cpu_is_rk3288()) {
157 ret = rk3288_efuse_readregs(0, 32, efuse_buf);
159 efuse.get_leakage = rk3288_get_leakage;
160 efuse.efuse_version = rk3288_get_efuse_version();
161 efuse.process_version = rk3288_get_process_version();
162 rockchip_set_cpu_version((efuse_buf[6] >> 4) & 3);
163 rk3288_set_system_serial();
165 pr_err("failed to read eFuse, return %d\n", ret);
167 } else if (cpu_is_rk312x()) {
168 ret = rk312x_efuse_readregs(0, 32, efuse_buf);
170 efuse.get_leakage = rk3288_get_leakage;
172 pr_err("failed to read eFuse, return %d\n", ret);