arch/arm/mach-rockchip/ddr_rk32.c

   1 /*
   2  * Function Driver for DDR controller
   3  *
   4  * Copyright (C) 2011-2014 Fuzhou Rockchip Electronics Co.,Ltd
   5  * Author:
   6  * hcy@rock-chips.com
   7  * yk@rock-chips.com
   8  *
   9  * v1.00
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/tlbflush.h>
  19 #include <linux/cpu.h>
  20 #include <dt-bindings/clock/ddr.h>
  21 #include <linux/rockchip/cru.h>
  22 #include <linux/rk_fb.h>
  23 #include "cpu_axi.h"
  24
  25 typedef uint32_t uint32;
  26
  27 #define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
  28 /***********************************
  29  * Global Control Macro
  30  ***********************************/
  31 //#define ENABLE_DDR_CLCOK_GPLL_PATH  //for RK3188
  32
  33 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)
  34 #define DDR3_DDR2_DLL_DISABLE_FREQ    (333)
  35 #define SR_IDLE                       (0x3)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
  36 #define PD_IDLE                       (0X40)  //unit:DDR clk cycle, and 0 for disable auto power-down
  37
  38 //#if (DDR3_DDR2_ODT_DISABLE_FREQ > DDR3_DDR2_DLL_DISABLE_FREQ)
  39 //#error
  40 //#endif
  41
  42 #define ddr_print(x...) printk( "DDR DEBUG: " x )
  43
  44 /***********************************
  45  * ARCH Relative Macro and Struction
  46  ***********************************/
  47 #define SRAM_CODE_OFFSET        rockchip_sram_virt
  48 #define SRAM_SIZE               rockchip_sram_size
  49
  50 /*
  51  * PMU
  52  */
  53 //PMU_PWRDN_ST
  54 #define pd_scu_pwr_st       (1<<11)
  55 #define pd_hevc_pwr_st      (1<<10)
  56 #define pd_gpu_pwr_st       (1<<9)
  57 #define pd_video_pwr_st     (1<<8)
  58 #define pd_vio_pwr_st       (1<<7)
  59 #define pd_peri_pwr_st      (1<<6)
  60 #define pd_bus_pwr_st      (1<<5)
  61 //PMU_IDLE_REQ
  62 #define idle_req_hevc_cfg   (1<<9)
  63 #define idle_req_cpup_cfg   (1<<8)
  64 #define idle_req_dma_cfg    (1<<7)
  65 #define idle_req_alive_cfg  (1<<6)
  66 #define idle_req_core_cfg   (1<<5)
  67 #define idle_req_vio_cfg    (1<<4)
  68 #define idle_req_video_cfg  (1<<3)
  69 #define idle_req_gpu_cfg    (1<<2)
  70 #define idle_req_peri_cfg   (1<<1)
  71 #define idle_req_bus_cfg    (1<<0)
  72
  73 //PMU_IDLE_ST
  74 #define idle_ack_hevc     (1<<25)
  75 #define idle_ack_cpup     (1<<24)
  76 #define idle_ack_dma      (1<<23)
  77 #define idle_ack_alive    (1<<22)
  78 #define idle_ack_core     (1<<21)
  79 #define idle_ack_vio      (1<<20)
  80 #define idle_ack_video    (1<<19)
  81 #define idle_ack_gpu      (1<<18)
  82 #define idle_ack_peir     (1<<17)
  83 #define idle_ack_bus      (1<<16)
  84
  85 #define idle_hevc   (1<<9)
  86 #define idle_cpup   (1<<8)
  87 #define idle_dma    (1<<7)
  88 #define idle_alive  (1<<6)
  89 #define idle_core   (1<<5)
  90 #define idle_vio    (1<<4)
  91 #define idle_video  (1<<3)
  92 #define idle_gpu    (1<<2)
  93 #define idle_peri   (1<<1)
  94 #define idle_bus    (1<<0)
  95
  96 //PMU_PWRMODE_CON
  97 /* ch=0, channel a
  98    ch=1, channel b
  99  */
 100 #define ddrio_ret_de_req(ch)  (1<<(21+(ch)))
 101 #define ddrc_gating_en(ch)    (1<<(19+(ch)))
 102 #define ddrio_ret_en(ch)      (1<<(17+(ch)))
 103 #define sref_enter_en(ch)     (1<<(15+(ch)))
 104
 105 //PMU_PWR_STATE
 106 #define SREF_EXIT             (1<<26)
 107 #define DDR_IO_PWRUP          (1<<25)
 108
 109 //PMU registers
 110 typedef volatile struct tagPMU_FILE
 111 {
 112     uint32 PMU_WAKEUP_CFG[2];
 113     uint32 PMU_PWRDN_CON;
 114     uint32 PMU_PWRDN_ST;
 115     uint32 PMU_IDLE_REQ;
 116     uint32 PMU_IDLE_ST;
 117     uint32 PMU_PWRMODE_CON;
 118     uint32 PMU_PWR_STATE;
 119     uint32 PMU_OSC_CNT;
 120     uint32 PMU_PLL_CNT;
 121     uint32 PMU_STABL_CNT;
 122     uint32 PMU_DDR0IO_PWRON_CNT;
 123     uint32 PMU_DDR1IO_PWRON_CNT;
 124     uint32 PMU_CORE_PWRDN_CNT;
 125     uint32 PMU_CORE_PWRUP_CNT;
 126     uint32 PMU_GPU_PWRDWN_CNT;
 127     uint32 PMU_GPU_PWRUP_CNT;
 128     uint32 PMU_WAKEUP_RST_CLR_CNT;
 129     uint32 PMU_SFT_CON;
 130     uint32 PMU_DDR_SREF_ST;
 131     uint32 PMU_INT_CON;
 132     uint32 PMU_INT_ST;
 133     uint32 PMU_BOOT_ADDR_SEL;
 134     uint32 PMU_GRF_CON;
 135     uint32 PMU_GPIO_SR;
 136     uint32 PMU_GPIO0_A_PULL;
 137     uint32 PMU_GPIO0_B_PULL;
 138     uint32 PMU_GPIO0_C_PULL;
 139     uint32 PMU_GPIO0_A_DRV;
 140     uint32 PMU_GPIO0_B_DRV;
 141     uint32 PMU_GPIO0_C_DRV;
 142     uint32 PMU_GPIO_OP;
 143     uint32 PMU_GPIO0_SEL18;
 144     uint32 PMU_GPIO0_A_IOMUX;
 145     uint32 PMU_GPIO0_B_IOMUX;
 146     uint32 PMU_GPIO0_C_IOMUX;
 147     uint32 PMU_GPIO0_D_IOMUX;
 148     uint32 PMU_PMU_SYS_REG[4];
 149 }PMU_FILE, *pPMU_FILE;
 150
 151 /*
 152  * CRU
 153  */
 154 typedef enum PLL_ID_Tag
 155 {
 156     APLL=0,
 157     DPLL,
 158     CPLL,
 159     GPLL,
 160     PLL_MAX
 161 }PLL_ID;
 162
 163 #define PLL_RESET  (((0x1<<5)<<16) | (0x1<<5))
 164 #define PLL_DE_RESET  (((0x1<<5)<<16) | (0x0<<5))
 165 #define NR(n)      ((0x3F<<(8+16)) | (((n)-1)<<8))
 166 #define NO(n)      ((0xF<<16) | ((n)-1))
 167 #define NF(n)      ((0x1FFF<<16) | ((n)-1))
 168 #define NB(n)      ((0xFFF<<16) | ((n)-1))
 169
 170  //CRU Registers
 171 typedef volatile struct tagCRU_STRUCT
 172 {
 173     uint32 CRU_PLL_CON[5][4];
 174     uint32 CRU_MODE_CON;
 175     uint32 reserved1[(0x60-0x54)/4];
 176     uint32 CRU_CLKSEL_CON[43];
 177     uint32 reserved2[(0x160-0x10c)/4];
 178     uint32 CRU_CLKGATE_CON[19];
 179     uint32 reserved3[(0x1b0-0x1ac)/4];
 180     uint32 CRU_GLB_SRST_FST_VALUE;
 181     uint32 CRU_GLB_SRST_SND_VALUE;
 182     uint32 CRU_SOFTRST_CON[12];
 183     uint32 CRU_MISC_CON;
 184     uint32 CRU_GLB_CNT_TH;
 185     uint32 CRU_TSADC_RST_CON;
 186     uint32 reserved4[(0x200-0x1f4)/4];
 187     uint32 CRU_SDMMC_CON[2];
 188     uint32 CRU_SDIO0_CON[2];
 189     uint32 CRU_SDIO1_CON[2];
 190     uint32 CRU_EMMC_CON[2];
 191     // other regigster unused in boot
 192 } CRU_REG, *pCRU_REG;
 193
 194 /*
 195  * GRF
 196  */
 197 //REG FILE registers
 198 typedef volatile struct tagREG_FILE
 199 {
 200     uint32 GRF_GPIO1A_IOMUX;
 201     uint32 GRF_GPIO1B_IOMUX;
 202     uint32 GRF_GPIO1C_IOMUX;
 203     uint32 GRF_GPIO1D_IOMUX;
 204     uint32 GRF_GPIO2A_IOMUX;
 205     uint32 GRF_GPIO2B_IOMUX;
 206     uint32 GRF_GPIO2C_IOMUX;
 207     uint32 GRF_GPIO2D_IOMUX;
 208     uint32 GRF_GPIO3A_IOMUX;
 209     uint32 GRF_GPIO3B_IOMUX;
 210     uint32 GRF_GPIO3C_IOMUX;
 211     uint32 GRF_GPIO3DL_IOMUX;
 212     uint32 GRF_GPIO3DH_IOMUX;
 213     uint32 GRF_GPIO4AL_IOMUX;
 214     uint32 GRF_GPIO4AH_IOMUX;
 215     uint32 GRF_GPIO4BL_IOMUX;
 216     uint32 GRF_GPIO4BH_IOMUX;
 217     uint32 GRF_GPIO4C_IOMUX;
 218     uint32 GRF_GPIO4D_IOMUX;
 219     uint32 GRF_GPIO5A_IOMUX;
 220     uint32 GRF_GPIO5B_IOMUX;
 221     uint32 GRF_GPIO5C_IOMUX;
 222     uint32 GRF_GPIO5D_IOMUX;
 223     uint32 GRF_GPIO6A_IOMUX;
 224     uint32 GRF_GPIO6B_IOMUX;
 225     uint32 GRF_GPIO6C_IOMUX;
 226     uint32 GRF_GPIO6D_IOMUX;
 227     uint32 GRF_GPIO7A_IOMUX;
 228     uint32 GRF_GPIO7B_IOMUX;
 229     uint32 GRF_GPIO7CL_IOMUX;
 230     uint32 GRF_GPIO7CH_IOMUX;
 231     uint32 GRF_GPIO7D_IOMUX;
 232     uint32 GRF_GPIO8A_IOMUX;
 233     uint32 GRF_GPIO8B_IOMUX;
 234     uint32 GRF_GPIO8C_IOMUX;
 235     uint32 GRF_GPIO8D_IOMUX;
 236     uint32 reserved1[(0x100-0x90)/4];
 237     uint32 GRF_GPIO1L_SR;
 238     uint32 GRF_GPIO1H_SR;
 239     uint32 GRF_GPIO2L_SR;
 240     uint32 GRF_GPIO2H_SR;
 241     uint32 GRF_GPIO3L_SR;
 242     uint32 GRF_GPIO3H_SR;
 243     uint32 GRF_GPIO4L_SR;
 244     uint32 GRF_GPIO4H_SR;
 245     uint32 GRF_GPIO5L_SR;
 246     uint32 GRF_GPIO5H_SR;
 247     uint32 GRF_GPIO6L_SR;
 248     uint32 GRF_GPIO6H_SR;
 249     uint32 GRF_GPIO7L_SR;
 250     uint32 GRF_GPIO7H_SR;
 251     uint32 GRF_GPIO8L_SR;
 252     uint32 GRF_GPIO8H_SR;
 253     uint32 GRF_GPIO1A_P;
 254     uint32 GRF_GPIO1B_P;
 255     uint32 GRF_GPIO1C_P;
 256     uint32 GRF_GPIO1D_P;
 257     uint32 GRF_GPIO2A_P;
 258     uint32 GRF_GPIO2B_P;
 259     uint32 GRF_GPIO2C_P;
 260     uint32 GRF_GPIO2D_P;
 261     uint32 GRF_GPIO3A_P;
 262     uint32 GRF_GPIO3B_P;
 263     uint32 GRF_GPIO3C_P;
 264     uint32 GRF_GPIO3D_P;
 265     uint32 GRF_GPIO4A_P;
 266     uint32 GRF_GPIO4B_P;
 267     uint32 GRF_GPIO4C_P;
 268     uint32 GRF_GPIO4D_P;
 269     uint32 GRF_GPIO5A_P;
 270     uint32 GRF_GPIO5B_P;
 271     uint32 GRF_GPIO5C_P;
 272     uint32 GRF_GPIO5D_P;
 273     uint32 GRF_GPIO6A_P;
 274     uint32 GRF_GPIO6B_P;
 275     uint32 GRF_GPIO6C_P;
 276     uint32 GRF_GPIO6D_P;
 277     uint32 GRF_GPIO7A_P;
 278     uint32 GRF_GPIO7B_P;
 279     uint32 GRF_GPIO7C_P;
 280     uint32 GRF_GPIO7D_P;
 281     uint32 GRF_GPIO8A_P;
 282     uint32 GRF_GPIO8B_P;
 283     uint32 GRF_GPIO8C_P;
 284     uint32 GRF_GPIO8D_P;
 285     uint32 GRF_GPIO1A_E;
 286     uint32 GRF_GPIO1B_E;
 287     uint32 GRF_GPIO1C_E;
 288     uint32 GRF_GPIO1D_E;
 289     uint32 GRF_GPIO2A_E;
 290     uint32 GRF_GPIO2B_E;
 291     uint32 GRF_GPIO2C_E;
 292     uint32 GRF_GPIO2D_E;
 293     uint32 GRF_GPIO3A_E;
 294     uint32 GRF_GPIO3B_E;
 295     uint32 GRF_GPIO3C_E;
 296     uint32 GRF_GPIO3D_E;
 297     uint32 GRF_GPIO4A_E;
 298     uint32 GRF_GPIO4B_E;
 299     uint32 GRF_GPIO4C_E;
 300     uint32 GRF_GPIO4D_E;
 301     uint32 GRF_GPIO5A_E;
 302     uint32 GRF_GPIO5B_E;
 303     uint32 GRF_GPIO5C_E;
 304     uint32 GRF_GPIO5D_E;
 305     uint32 GRF_GPIO6A_E;
 306     uint32 GRF_GPIO6B_E;
 307     uint32 GRF_GPIO6C_E;
 308     uint32 GRF_GPIO6D_E;
 309     uint32 GRF_GPIO7A_E;
 310     uint32 GRF_GPIO7B_E;
 311     uint32 GRF_GPIO7C_E;
 312     uint32 GRF_GPIO7D_E;
 313     uint32 GRF_GPIO8A_E;
 314     uint32 GRF_GPIO8B_E;
 315     uint32 GRF_GPIO8C_E;
 316     uint32 GRF_GPIO8D_E;
 317     uint32 GRF_GPIO_SMT;
 318     uint32 GRF_SOC_CON[15];
 319     uint32 GRF_SOC_STATUS[23];
 320     uint32 reserved2[(0x2e0-0x2dc)/4];
 321     uint32 GRF_DMAC2_CON[4];
 322     uint32 GRF_DDRC0_CON0;
 323     uint32 GRF_DDRC1_CON0;
 324     uint32 GRF_CPU_CON[5];
 325     uint32 reserved3[(0x318-0x30c)/4];
 326     uint32 GRF_CPU_STATUS0;
 327     uint32 reserved4[(0x320-0x31c)/4];
 328     uint32 GRF_UOC0_CON[5];
 329     uint32 GRF_UOC1_CON[5];
 330     uint32 GRF_UOC2_CON[4];
 331     uint32 GRF_UOC3_CON[2];
 332     uint32 GRF_UOC4_CON[2];
 333     uint32 GRF_DLL_CON[3];
 334     uint32 GRF_DLL_STATUS[3];
 335     uint32 GRF_IO_VSEL;
 336     uint32 GRF_SARADC_TESTBIT;
 337     uint32 GRF_TSADC_TESTBIT_L;
 338     uint32 GRF_TSADC_TESTBIT_H;
 339     uint32 GRF_OS_REG[4];
 340     uint32 GRF_FAST_BOOT_ADDR;
 341     uint32 GRF_SOC_CON15;
 342     uint32 GRF_SOC_CON16;
 343 } REG_FILE, *pREG_FILE;
 344
 345 /*
 346  * PCTL
 347  */
 348 //SCTL
 349 #define INIT_STATE                     (0)
 350 #define CFG_STATE                      (1)
 351 #define GO_STATE                       (2)
 352 #define SLEEP_STATE                    (3)
 353 #define WAKEUP_STATE                   (4)
 354
 355 //STAT
 356 #define Init_mem                       (0)
 357 #define Config                         (1)
 358 #define Config_req                     (2)
 359 #define Access                         (3)
 360 #define Access_req                     (4)
 361 #define Low_power                      (5)
 362 #define Low_power_entry_req            (6)
 363 #define Low_power_exit_req             (7)
 364
 365 //MCFG
 366 #define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
 367 #define pd_idle(n)                     ((n)<<8)
 368 #define mddr_en                        (2<<22)
 369 #define lpddr2_en                      (3<<22)
 370 #define ddr2_en                        (0<<5)
 371 #define ddr3_en                        (1<<5)
 372 #define lpddr2_s2                      (0<<6)
 373 #define lpddr2_s4                      (1<<6)
 374 #define mddr_lpddr2_bl_2               (0<<20)
 375 #define mddr_lpddr2_bl_4               (1<<20)
 376 #define mddr_lpddr2_bl_8               (2<<20)
 377 #define mddr_lpddr2_bl_16              (3<<20)
 378 #define ddr2_ddr3_bl_4                 (0)
 379 #define ddr2_ddr3_bl_8                 (1)
 380 #define tfaw_cfg(n)                    (((n)-4)<<18)
 381 #define pd_exit_slow                   (0<<17)
 382 #define pd_exit_fast                   (1<<17)
 383 #define pd_type(n)                     ((n)<<16)
 384 #define two_t_en(n)                    ((n)<<3)
 385 #define bl8int_en(n)                   ((n)<<2)
 386 #define cke_or_en(n)                   ((n)<<1)
 387
 388 //POWCTL
 389 #define power_up_start                 (1<<0)
 390
 391 //POWSTAT
 392 #define power_up_done                  (1<<0)
 393
 394 //DFISTSTAT0
 395 #define dfi_init_complete              (1<<0)
 396
 397 //CMDTSTAT
 398 #define cmd_tstat                      (1<<0)
 399
 400 //CMDTSTATEN
 401 #define cmd_tstat_en                   (1<<1)
 402
 403 //MCMD
 404 #define Deselect_cmd                   (0)
 405 #define PREA_cmd                       (1)
 406 #define REF_cmd                        (2)
 407 #define MRS_cmd                        (3)
 408 #define ZQCS_cmd                       (4)
 409 #define ZQCL_cmd                       (5)
 410 #define RSTL_cmd                       (6)
 411 #define MRR_cmd                        (8)
 412 #define DPDE_cmd                       (9)
 413
 414 #define lpddr2_op(n)                   ((n)<<12)
 415 #define lpddr2_ma(n)                   ((n)<<4)
 416
 417 #define bank_addr(n)                   ((n)<<17)
 418 #define cmd_addr(n)                    ((n)<<4)
 419
 420 #define start_cmd                      (1u<<31)
 421
 422 typedef union STAT_Tag
 423 {
 424     uint32 d32;
 425     struct
 426     {
 427         unsigned ctl_stat : 3;
 428         unsigned reserved3 : 1;
 429         unsigned lp_trig : 3;
 430         unsigned reserved7_31 : 25;
 431     }b;
 432 }STAT_T;
 433
 434 typedef union SCFG_Tag
 435 {
 436     uint32 d32;
 437     struct
 438     {
 439         unsigned hw_low_power_en : 1;
 440         unsigned reserved1_5 : 5;
 441         unsigned nfifo_nif1_dis : 1;
 442         unsigned reserved7 : 1;
 443         unsigned bbflags_timing : 4;
 444         unsigned reserved12_31 : 20;
 445     } b;
 446 }SCFG_T;
 447
 448 /* DDR Controller register struct */
 449 typedef volatile struct DDR_REG_Tag
 450 {
 451     //Operational State, Control, and Status Registers
 452     SCFG_T SCFG;                   //State Configuration Register
 453     volatile uint32 SCTL;                   //State Control Register
 454     STAT_T STAT;                   //State Status Register
 455     volatile uint32 INTRSTAT;               //Interrupt Status Register
 456     uint32 reserved0[(0x40-0x10)/4];
 457     //Initailization Control and Status Registers
 458     volatile uint32 MCMD;                   //Memory Command Register
 459     volatile uint32 POWCTL;                 //Power Up Control Registers
 460     volatile uint32 POWSTAT;                //Power Up Status Register
 461     volatile uint32 CMDTSTAT;               //Command Timing Status Register
 462     volatile uint32 CMDTSTATEN;             //Command Timing Status Enable Register
 463     uint32 reserved1[(0x60-0x54)/4];
 464     volatile uint32 MRRCFG0;                //MRR Configuration 0 Register
 465     volatile uint32 MRRSTAT0;               //MRR Status 0 Register
 466     volatile uint32 MRRSTAT1;               //MRR Status 1 Register
 467     uint32 reserved2[(0x7c-0x6c)/4];
 468     //Memory Control and Status Registers
 469     volatile uint32 MCFG1;                  //Memory Configuration 1 Register
 470     volatile uint32 MCFG;                   //Memory Configuration Register
 471     volatile uint32 PPCFG;                  //Partially Populated Memories Configuration Register
 472     volatile uint32 MSTAT;                  //Memory Status Register
 473     volatile uint32 LPDDR2ZQCFG;            //LPDDR2 ZQ Configuration Register
 474     uint32 reserved3;
 475     //DTU Control and Status Registers
 476     volatile uint32 DTUPDES;                //DTU Status Register
 477     volatile uint32 DTUNA;                  //DTU Number of Random Addresses Created Register
 478     volatile uint32 DTUNE;                  //DTU Number of Errors Register
 479     volatile uint32 DTUPRD0;                //DTU Parallel Read 0
 480     volatile uint32 DTUPRD1;                //DTU Parallel Read 1
 481     volatile uint32 DTUPRD2;                //DTU Parallel Read 2
 482     volatile uint32 DTUPRD3;                //DTU Parallel Read 3
 483     volatile uint32 DTUAWDT;                //DTU Address Width
 484     uint32 reserved4[(0xc0-0xb4)/4];
 485     //Memory Timing Registers
 486     volatile uint32 TOGCNT1U;               //Toggle Counter 1U Register
 487     volatile uint32 TINIT;                  //t_init Timing Register
 488     volatile uint32 TRSTH;                  //Reset High Time Register
 489     volatile uint32 TOGCNT100N;             //Toggle Counter 100N Register
 490     volatile uint32 TREFI;                  //t_refi Timing Register
 491     volatile uint32 TMRD;                   //t_mrd Timing Register
 492     volatile uint32 TRFC;                   //t_rfc Timing Register
 493     volatile uint32 TRP;                    //t_rp Timing Register
 494     volatile uint32 TRTW;                   //t_rtw Timing Register
 495     volatile uint32 TAL;                    //AL Latency Register
 496     volatile uint32 TCL;                    //CL Timing Register
 497     volatile uint32 TCWL;                   //CWL Register
 498     volatile uint32 TRAS;                   //t_ras Timing Register
 499     volatile uint32 TRC;                    //t_rc Timing Register
 500     volatile uint32 TRCD;                   //t_rcd Timing Register
 501     volatile uint32 TRRD;                   //t_rrd Timing Register
 502     volatile uint32 TRTP;                   //t_rtp Timing Register
 503     volatile uint32 TWR;                    //t_wr Timing Register
 504     volatile uint32 TWTR;                   //t_wtr Timing Register
 505     volatile uint32 TEXSR;                  //t_exsr Timing Register
 506     volatile uint32 TXP;                    //t_xp Timing Register
 507     volatile uint32 TXPDLL;                 //t_xpdll Timing Register
 508     volatile uint32 TZQCS;                  //t_zqcs Timing Register
 509     volatile uint32 TZQCSI;                 //t_zqcsi Timing Register
 510     volatile uint32 TDQS;                   //t_dqs Timing Register
 511     volatile uint32 TCKSRE;                 //t_cksre Timing Register
 512     volatile uint32 TCKSRX;                 //t_cksrx Timing Register
 513     volatile uint32 TCKE;                   //t_cke Timing Register
 514     volatile uint32 TMOD;                   //t_mod Timing Register
 515     volatile uint32 TRSTL;                  //Reset Low Timing Register
 516     volatile uint32 TZQCL;                  //t_zqcl Timing Register
 517     volatile uint32 TMRR;                   //t_mrr Timing Register
 518     volatile uint32 TCKESR;                 //t_ckesr Timing Register
 519     volatile uint32 TDPD;                   //t_dpd Timing Register
 520     uint32 reserved5[(0x180-0x148)/4];
 521     //ECC Configuration, Control, and Status Registers
 522     volatile uint32 ECCCFG;                   //ECC Configuration Register
 523     volatile uint32 ECCTST;                   //ECC Test Register
 524     volatile uint32 ECCCLR;                   //ECC Clear Register
 525     volatile uint32 ECCLOG;                   //ECC Log Register
 526     uint32 reserved6[(0x200-0x190)/4];
 527     //DTU Control and Status Registers
 528     volatile uint32 DTUWACTL;                 //DTU Write Address Control Register
 529     volatile uint32 DTURACTL;                 //DTU Read Address Control Register
 530     volatile uint32 DTUCFG;                   //DTU Configuration Control Register
 531     volatile uint32 DTUECTL;                  //DTU Execute Control Register
 532     volatile uint32 DTUWD0;                   //DTU Write Data 0
 533     volatile uint32 DTUWD1;                   //DTU Write Data 1
 534     volatile uint32 DTUWD2;                   //DTU Write Data 2
 535     volatile uint32 DTUWD3;                   //DTU Write Data 3
 536     volatile uint32 DTUWDM;                   //DTU Write Data Mask
 537     volatile uint32 DTURD0;                   //DTU Read Data 0
 538     volatile uint32 DTURD1;                   //DTU Read Data 1
 539     volatile uint32 DTURD2;                   //DTU Read Data 2
 540     volatile uint32 DTURD3;                   //DTU Read Data 3
 541     volatile uint32 DTULFSRWD;                //DTU LFSR Seed for Write Data Generation
 542     volatile uint32 DTULFSRRD;                //DTU LFSR Seed for Read Data Generation
 543     volatile uint32 DTUEAF;                   //DTU Error Address FIFO
 544     //DFI Control Registers
 545     volatile uint32 DFITCTRLDELAY;            //DFI tctrl_delay Register
 546     volatile uint32 DFIODTCFG;                //DFI ODT Configuration Register
 547     volatile uint32 DFIODTCFG1;               //DFI ODT Configuration 1 Register
 548     volatile uint32 DFIODTRANKMAP;            //DFI ODT Rank Mapping Register
 549     //DFI Write Data Registers
 550     volatile uint32 DFITPHYWRDATA;            //DFI tphy_wrdata Register
 551     volatile uint32 DFITPHYWRLAT;             //DFI tphy_wrlat Register
 552     uint32 reserved7[(0x260-0x258)/4];
 553     volatile uint32 DFITRDDATAEN;             //DFI trddata_en Register
 554     volatile uint32 DFITPHYRDLAT;             //DFI tphy_rddata Register
 555     uint32 reserved8[(0x270-0x268)/4];
 556     //DFI Update Registers
 557     volatile uint32 DFITPHYUPDTYPE0;          //DFI tphyupd_type0 Register
 558     volatile uint32 DFITPHYUPDTYPE1;          //DFI tphyupd_type1 Register
 559     volatile uint32 DFITPHYUPDTYPE2;          //DFI tphyupd_type2 Register
 560     volatile uint32 DFITPHYUPDTYPE3;          //DFI tphyupd_type3 Register
 561     volatile uint32 DFITCTRLUPDMIN;           //DFI tctrlupd_min Register
 562     volatile uint32 DFITCTRLUPDMAX;           //DFI tctrlupd_max Register
 563     volatile uint32 DFITCTRLUPDDLY;           //DFI tctrlupd_dly Register
 564     uint32 reserved9;
 565     volatile uint32 DFIUPDCFG;                //DFI Update Configuration Register
 566     volatile uint32 DFITREFMSKI;              //DFI Masked Refresh Interval Register
 567     volatile uint32 DFITCTRLUPDI;             //DFI tctrlupd_interval Register
 568     uint32 reserved10[(0x2ac-0x29c)/4];
 569     volatile uint32 DFITRCFG0;                //DFI Training Configuration 0 Register
 570     volatile uint32 DFITRSTAT0;               //DFI Training Status 0 Register
 571     volatile uint32 DFITRWRLVLEN;             //DFI Training dfi_wrlvl_en Register
 572     volatile uint32 DFITRRDLVLEN;             //DFI Training dfi_rdlvl_en Register
 573     volatile uint32 DFITRRDLVLGATEEN;         //DFI Training dfi_rdlvl_gate_en Register
 574     //DFI Status Registers
 575     volatile uint32 DFISTSTAT0;               //DFI Status Status 0 Register
 576     volatile uint32 DFISTCFG0;                //DFI Status Configuration 0 Register
 577     volatile uint32 DFISTCFG1;                //DFI Status configuration 1 Register
 578     uint32 reserved11;
 579     volatile uint32 DFITDRAMCLKEN;            //DFI tdram_clk_enalbe Register
 580     volatile uint32 DFITDRAMCLKDIS;           //DFI tdram_clk_disalbe Register
 581     volatile uint32 DFISTCFG2;                //DFI Status configuration 2 Register
 582     volatile uint32 DFISTPARCLR;              //DFI Status Parity Clear Register
 583     volatile uint32 DFISTPARLOG;              //DFI Status Parity Log Register
 584     uint32 reserved12[(0x2f0-0x2e4)/4];
 585     //DFI Low Power Registers
 586     volatile uint32 DFILPCFG0;                //DFI Low Power Configuration 0 Register
 587     uint32 reserved13[(0x300-0x2f4)/4];
 588     //DFI Training 2 Registers
 589     volatile uint32 DFITRWRLVLRESP0;          //DFI Training dif_wrlvl_resp Status 0 Register
 590     volatile uint32 DFITRWRLVLRESP1;          //DFI Training dif_wrlvl_resp Status 1 Register
 591     volatile uint32 DFITRWRLVLRESP2;          //DFI Training dif_wrlvl_resp Status 2 Register
 592     volatile uint32 DFITRRDLVLRESP0;          //DFI Training dif_rdlvl_resp Status 0 Register
 593     volatile uint32 DFITRRDLVLRESP1;          //DFI Training dif_rdlvl_resp Status 1 Register
 594     volatile uint32 DFITRRDLVLRESP2;          //DFI Training dif_rdlvl_resp Status 2 Register
 595     volatile uint32 DFITRWRLVLDELAY0;         //DFI Training dif_wrlvl_delay Configuration 0 Register
 596     volatile uint32 DFITRWRLVLDELAY1;         //DFI Training dif_wrlvl_delay Configuration 1 Register
 597     volatile uint32 DFITRWRLVLDELAY2;         //DFI Training dif_wrlvl_delay Configuration 2 Register
 598     volatile uint32 DFITRRDLVLDELAY0;         //DFI Training dif_rdlvl_delay Configuration 0 Register
 599     volatile uint32 DFITRRDLVLDELAY1;         //DFI Training dif_rdlvl_delay Configuration 1 Register
 600     volatile uint32 DFITRRDLVLDELAY2;         //DFI Training dif_rdlvl_delay Configuration 2 Register
 601     volatile uint32 DFITRRDLVLGATEDELAY0;     //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
 602     volatile uint32 DFITRRDLVLGATEDELAY1;     //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
 603     volatile uint32 DFITRRDLVLGATEDELAY2;     //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
 604     volatile uint32 DFITRCMD;                 //DFI Training Command Register
 605     uint32 reserved14[(0x3f8-0x340)/4];
 606     //IP Status Registers
 607     volatile uint32 IPVR;                     //IP Version Register
 608     volatile uint32 IPTR;                     //IP Type Register
 609 }DDR_REG_T, *pDDR_REG_T;
 610
 611 /*
 612  * PUBL
 613  */
 614 //PIR
 615 #define INIT                 (1<<0)
 616 #define DLLSRST              (1<<1)
 617 #define DLLLOCK              (1<<2)
 618 #define ZCAL                 (1<<3)
 619 #define ITMSRST              (1<<4)
 620 #define DRAMRST              (1<<5)
 621 #define DRAMINIT             (1<<6)
 622 #define QSTRN                (1<<7)
 623 #define EYETRN               (1<<8)
 624 #define ICPC                 (1<<16)
 625 #define DLLBYP               (1<<17)
 626 #define CTLDINIT             (1<<18)
 627 #define CLRSR                (1<<28)
 628 #define LOCKBYP              (1<<29)
 629 #define ZCALBYP              (1<<30)
 630 #define INITBYP              (1u<<31)
 631
 632 //PGCR
 633 #define DFTLMT(n)            ((n)<<3)
 634 #define DFTCMP(n)            ((n)<<2)
 635 #define DQSCFG(n)            ((n)<<1)
 636 #define ITMDMD(n)            ((n)<<0)
 637 #define RANKEN(n)            ((n)<<18)
 638
 639 //PGSR
 640 #define IDONE                (1<<0)
 641 #define DLDONE               (1<<1)
 642 #define ZCDONE               (1<<2)
 643 #define DIDONE               (1<<3)
 644 #define DTDONE               (1<<4)
 645 #define DTERR                (1<<5)
 646 #define DTIERR               (1<<6)
 647 #define DFTERR               (1<<7)
 648 #define TQ                   (1u<<31)
 649
 650 //PTR0
 651 #define tITMSRST(n)          ((n)<<18)
 652 #define tDLLLOCK(n)          ((n)<<6)
 653 #define tDLLSRST(n)          ((n)<<0)
 654
 655 //PTR1
 656 #define tDINIT1(n)           ((n)<<19)
 657 #define tDINIT0(n)           ((n)<<0)
 658
 659 //PTR2
 660 #define tDINIT3(n)           ((n)<<17)
 661 #define tDINIT2(n)           ((n)<<0)
 662
 663 //DSGCR
 664 #define DQSGE(n)             ((n)<<8)
 665 #define DQSGX(n)             ((n)<<5)
 666
 667 typedef union DCR_Tag
 668 {
 669     uint32 d32;
 670     struct
 671     {
 672         unsigned DDRMD : 3;
 673         unsigned DDR8BNK : 1;
 674         unsigned PDQ : 3;
 675         unsigned MPRDQ : 1;
 676         unsigned DDRTYPE : 2;
 677         unsigned reserved10_26 : 17;
 678         unsigned NOSRA : 1;
 679         unsigned DDR2T : 1;
 680         unsigned UDIMM : 1;
 681         unsigned RDIMM : 1;
 682         unsigned TPD : 1;
 683     } b;
 684 }DCR_T;
 685
 686 typedef volatile struct DATX8_REG_Tag
 687 {
 688     volatile uint32 DXGCR;                 //DATX8 General Configuration Register
 689     volatile uint32 DXGSR[2];              //DATX8 General Status Register
 690     volatile uint32 DXDLLCR;               //DATX8 DLL Control Register
 691     volatile uint32 DXDQTR;                //DATX8 DQ Timing Register
 692     volatile uint32 DXDQSTR;               //DATX8 DQS Timing Register
 693     uint32 reserved[0x80-0x76];
 694 }DATX8_REG_T;
 695
 696 /* DDR PHY register struct */
 697 typedef volatile struct DDRPHY_REG_Tag
 698 {
 699     volatile uint32 RIDR;                   //Revision Identification Register
 700     volatile uint32 PIR;                    //PHY Initialization Register
 701     volatile uint32 PGCR;                   //PHY General Configuration Register
 702     volatile uint32 PGSR;                   //PHY General Status Register
 703     volatile uint32 DLLGCR;                 //DLL General Control Register
 704     volatile uint32 ACDLLCR;                //AC DLL Control Register
 705     volatile uint32 PTR[3];                 //PHY Timing Registers 0-2
 706     volatile uint32 ACIOCR;                 //AC I/O Configuration Register
 707     volatile uint32 DXCCR;                  //DATX8 Common Configuration Register
 708     volatile uint32 DSGCR;                  //DDR System General Configuration Register
 709     DCR_T DCR;                    //DRAM Configuration Register
 710     volatile uint32 DTPR[3];                //DRAM Timing Parameters Register 0-2
 711     volatile uint32 MR[4];                    //Mode Register 0-3
 712     volatile uint32 ODTCR;                  //ODT Configuration Register
 713     volatile uint32 DTAR;                   //Data Training Address Register
 714     volatile uint32 DTDR[2];                //Data Training Data Register 0-1
 715
 716     uint32 reserved1[0x30-0x18];
 717     uint32 DCU[0x38-0x30];
 718     uint32 reserved2[0x40-0x38];
 719     uint32 BIST[0x51-0x40];
 720     uint32 reserved3[0x60-0x51];
 721
 722     volatile uint32 ZQ0CR[2];               //ZQ 0 Impedance Control Register 0-1
 723     volatile uint32 ZQ0SR[2];               //ZQ 0 Impedance Status Register 0-1
 724     volatile uint32 ZQ1CR[2];               //ZQ 1 Impedance Control Register 0-1
 725     volatile uint32 ZQ1SR[2];               //ZQ 1 Impedance Status Register 0-1
 726     volatile uint32 ZQ2CR[2];               //ZQ 2 Impedance Control Register 0-1
 727     volatile uint32 ZQ2SR[2];               //ZQ 2 Impedance Status Register 0-1
 728     volatile uint32 ZQ3CR[2];               //ZQ 3 Impedance Control Register 0-1
 729     volatile uint32 ZQ3SR[2];               //ZQ 3 Impedance Status Register 0-1
 730
 731     DATX8_REG_T     DATX8[9];               //DATX8 Register
 732 }DDRPHY_REG_T, *pDDRPHY_REG_T;
 733
 734 typedef union NOC_TIMING_Tag
 735 {
 736     uint32 d32;
 737     struct
 738     {
 739         unsigned ActToAct : 6;
 740         unsigned RdToMiss : 6;
 741         unsigned WrToMiss : 6;
 742         unsigned BurstLen : 3;
 743         unsigned RdToWr : 5;
 744         unsigned WrToRd : 5;
 745         unsigned BwRatio : 1;
 746     } b;
 747 }NOC_TIMING_T;
 748
 749 typedef union NOC_ACTIVATE_Tag
 750 {
 751     uint32 d32;
 752     struct
 753     {
 754         unsigned Rrd : 4;  //bit[0:3]
 755         unsigned Faw : 6;  //bit[4:9]
 756         unsigned Fawbank : 1; //bit 10
 757         unsigned reserved : 21;
 758     } b;
 759 }NOC_ACTIVATE_T;
 760
 761 typedef volatile struct MSCH_REG_Tag
 762 {
 763     volatile uint32 coreid;
 764     volatile uint32 revisionid;
 765     volatile uint32 ddrconf;
 766     volatile NOC_TIMING_T ddrtiming;
 767     volatile uint32 ddrmode;
 768     volatile uint32 readlatency;
 769     uint32 reserved1[(0x38-0x18)/4];
 770     volatile NOC_ACTIVATE_T activate;
 771     volatile uint32 devtodev;
 772 }MSCH_REG, *pMSCH_REG;
 773
 774 #define CH_MAX                 (2)
 775 #define DRAM_PHYS              (0)   //DRAM Channel a physical address start
 776 #define pPMU_Reg               ((pPMU_FILE)RK_PMU_VIRT)
 777 #define pCRU_Reg               ((pCRU_REG)RK_CRU_VIRT)
 778 #define pGRF_Reg               ((pREG_FILE)RK_GRF_VIRT)
 779 #define pDDR_REG(ch)           ((ch) ? ((pDDR_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)):((pDDR_REG_T)RK_DDR_VIRT))
 780 #define pPHY_REG(ch)           ((ch) ? ((pDDRPHY_REG_T)(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)) : ((pDDRPHY_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE)))
 781 #define pMSCH_REG(ch)          ((ch)? ((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT+0x80)):((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT)))
 782 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 783 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 784 #define GET_LPDDR3_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 785 #define DDR_GET_RANK_2_ROW15() (0)
 786 #define DDR_GET_BANK_2_RANK()  (0)
 787 #define DDR_HW_WAKEUP(ch,en)   do{pGRF_Reg->GRF_SOC_CON[0] = (1<<(16+5+ch)) | (en<<(5+ch));}while(0)
 788 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[0])
 789 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS[1] & (1<<5))
 790 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<2))<<16)|(src<<2)| div;}while(0)
 791 #define GET_DDR_PLL_SRC()           ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<2)) ? GPLL : DPLL)
 792 #define DDR_GPLL_CLK_GATE(en)       do{pCRU_Reg->CRU_CLKGATE_CON[0] = 0x02000000 | (en<<9);}while(0)
 793 #define SET_DDRPHY_CLKGATE(ch,dis)  do{pCRU_Reg->CRU_CLKGATE_CON[4] = ((0x1<<(12+ch))<<16) | (dis<<(12+ch));}while(0)
 794 #define READ_DDR_STRIDE()           (readl_relaxed(RK_SGRF_VIRT+0x8) &0x1F)
 795
 796 #define READ_CH_CNT()         (1+((pPMU_Reg->PMU_PMU_SYS_REG[2]>>12)&0x1))
 797 #define READ_CH_INFO()        ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>28)&0x3)
 798 #define READ_CH_ROW_INFO(ch)  ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>(30+(ch)))&0x1)    //row_3_4:0=normal, 1=6Gb or 12Gb
 799
 800 #define SET_PLL_MODE(pll, mode) do{pCRU_Reg->CRU_MODE_CON = ((mode<<((pll)*4))|(0x3<<(16+(pll)*4)));}while(0)
 801 #define SET_PLL_PD(pll, pd)     do{pCRU_Reg->CRU_PLL_CON[pll][3] = ((0x1<<1)<<16) | (pd<<1);}while(0)
 802
 803 #define READ_DRAMTYPE_INFO()    ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>13)&0x7)
 804 #define READ_CS_INFO(ch)        ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(11+(ch)*16))&0x1)+1)
 805 #define READ_BW_INFO(ch)        (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(2+(ch)*16))&0x3))
 806 #define READ_COL_INFO(ch)       (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(9+(ch)*16))&0x3))
 807 #define READ_BK_INFO(ch)        (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(8+(ch)*16))&0x1))
 808 #define READ_ROW_INFO(ch,cs)    (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(6-(2*cs)+(ch)*16))&0x3))
 809 #define READ_DIE_BW_INFO(ch)    (2>>((pPMU_Reg->PMU_PMU_SYS_REG[2]>>((ch)*16))&0x3))
 810
 811 static const uint16_t  ddr_cfg_2_rbc[] =
 812 {
 813     /****************************/
 814     // [8:7]  bank(n:n bit bank)
 815     // [6:4]  row(12+n)
 816     // [3:2]  bank(n:n bit bank)
 817     // [1:0]  col(9+n)
 818     /****************************/
 819     //all config have (13col,3bank,16row,1cs)
 820     //bank,  row,   bank, col          col bank row(32bit)
 821     ((3<<7)|(3<<4)|(0<<2)|2),  // 0     11   8   15
 822     ((0<<7)|(1<<4)|(3<<2)|1),  // 1     10   8   13
 823     ((0<<7)|(2<<4)|(3<<2)|1),  // 2     10   8   14
 824     ((0<<7)|(3<<4)|(3<<2)|1),  // 3     10   8   15
 825     ((0<<7)|(4<<4)|(3<<2)|1),  // 4     10   8   16
 826     ((0<<7)|(1<<4)|(3<<2)|2),  // 5     11   8   13  // 32bit not use
 827     ((0<<7)|(2<<4)|(3<<2)|2),  // 6     11   8   14
 828     ((0<<7)|(3<<4)|(3<<2)|2),  // 7     11   8   15
 829     ((0<<7)|(1<<4)|(3<<2)|0),  // 8     9    8   13
 830     ((0<<7)|(2<<4)|(3<<2)|0),  // 9     9    8   14
 831     ((0<<7)|(3<<4)|(3<<2)|0),  // 10    9    8   15
 832     ((0<<7)|(2<<4)|(2<<2)|0),  // 11    9    4   14
 833     ((0<<7)|(1<<4)|(2<<2)|1),  // 12    10   4   13
 834     ((0<<7)|(0<<4)|(2<<2)|2),  // 13    11   4   12
 835     ((3<<7)|(4<<4)|(0<<2)|1),  // 14    10   8   16 / 10, 4,15 / 10, 8, 15
 836     ((0<<7)|(4<<4)|(3<<2)|2),  // 15    11   8   16
 837 };
 838
 839 /***********************************
 840  * LPDDR2 define
 841  ***********************************/
 842 //MR0 (Device Information)
 843 #define  LPDDR2_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 844 #define  LPDDR2_DI     (0x1<<1)     // 0:S2 or S4 SDRAM, 1:NVM
 845 #define  LPDDR2_DNVI   (0x1<<2)     // 0:DNV not supported, 1:DNV supported
 846 #define  LPDDR2_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 847                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 848
 849 //MR1 (Device Feature)
 850 #define LPDDR2_BL4     (0x2)
 851 #define LPDDR2_BL8     (0x3)
 852 #define LPDDR2_BL16    (0x4)
 853 #define LPDDR2_nWR(n)  (((n)-2)<<5)
 854
 855 //MR2 (Device Feature 2)
 856 #define LPDDR2_RL3_WL1  (0x1)
 857 #define LPDDR2_RL4_WL2  (0x2)
 858 #define LPDDR2_RL5_WL2  (0x3)
 859 #define LPDDR2_RL6_WL3  (0x4)
 860 #define LPDDR2_RL7_WL4  (0x5)
 861 #define LPDDR2_RL8_WL4  (0x6)
 862
 863 //MR3 (IO Configuration 1)
 864 #define LPDDR2_DS_34    (0x1)
 865 #define LPDDR2_DS_40    (0x2)
 866 #define LPDDR2_DS_48    (0x3)
 867 #define LPDDR2_DS_60    (0x4)
 868 #define LPDDR2_DS_80    (0x6)
 869 #define LPDDR2_DS_120   (0x7)   //optional
 870
 871 //MR4 (Device Temperature)
 872 #define LPDDR2_tREF_MASK (0x7)
 873 #define LPDDR2_4_tREF    (0x1)
 874 #define LPDDR2_2_tREF    (0x2)
 875 #define LPDDR2_1_tREF    (0x3)
 876 #define LPDDR2_025_tREF  (0x5)
 877 #define LPDDR2_025_tREF_DERATE    (0x6)
 878
 879 #define LPDDR2_TUF       (0x1<<7)
 880
 881 //MR8 (Basic configuration 4)
 882 #define LPDDR2_S4        (0x0)
 883 #define LPDDR2_S2        (0x1)
 884 #define LPDDR2_N         (0x2)
 885 #define LPDDR2_Density(mr8)  (8<<(((mr8)>>2)&0xf))   // Unit:MB
 886 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
 887
 888 //MR10 (Calibration)
 889 #define LPDDR2_ZQINIT   (0xFF)
 890 #define LPDDR2_ZQCL     (0xAB)
 891 #define LPDDR2_ZQCS     (0x56)
 892 #define LPDDR2_ZQRESET  (0xC3)
 893
 894 //MR16 (PASR Bank Mask)
 895 // S2 SDRAM Only
 896 #define LPDDR2_PASR_Full (0x0)
 897 #define LPDDR2_PASR_1_2  (0x1)
 898 #define LPDDR2_PASR_1_4  (0x2)
 899 #define LPDDR2_PASR_1_8  (0x3)
 900
 901 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 902
 903 //MR32 (DQ Calibration Pattern A)
 904
 905 //MR40 (DQ Calibration Pattern B)
 906
 907 /***********************************
 908  * LPDDR3 define
 909  ***********************************/
 910 //MR0 (Device Information)
 911 #define  LPDDR3_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 912 #define  LPDDR3_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 913                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 914 #define  LPDDR3_WL_SUPOT (1<<6)     // 0:DRAM does not support WL(Set B), 1:DRAM support WL(Set B)
 915 #define  LPDDR3_RL3_SUPOT (1<<7)    // 0:DRAM does not support RL=3,nWR=3,WL=1; 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
 916
 917 //MR1 (Device Feature)
 918 #define LPDDR3_BL8     (0x3)
 919 #define LPDDR3_nWR(n)  ((n)<<5)
 920
 921 //MR2 (Device Feature 2)
 922 //WL Set A,default
 923 #define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 924 #define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 925 #define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 926 #define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 927 #define LPDDR3_RL10_WL6  (0x8)       // <=667MHz,default
 928 #define LPDDR3_RL11_WL6  (0x9)       // <=733MHz
 929 #define LPDDR3_RL12_WL6  (0xa)       // <=800MHz
 930 #define LPDDR3_RL14_WL8  (0xc)       // <=933MHz
 931 #define LPDDR3_RL16_WL8  (0xe)       // <=1066MHz
 932 //WL Set B, optional
 933 //#define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 934 //#define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 935 //#define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 936 //#define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 937 #define LPDDR3_RL10_WL8  (0x8)       // <=667MHz,default
 938 #define LPDDR3_RL11_WL9  (0x9)       // <=733MHz
 939 #define LPDDR3_RL12_WL9  (0xa)       // <=800MHz
 940 #define LPDDR3_RL14_WL11 (0xc)       // <=933MHz
 941 #define LPDDR3_RL16_WL13 (0xe)       // <=1066MHz
 942
 943 #define LPDDR3_nWRE      (1<<4)      // 1:enable nWR programming > 9(defualt)
 944 #define LPDDR3_WL_S      (1<<6)      // 1:Select WL Set B
 945 #define LPDDR3_WR_LEVEL  (1<<7)      // 1:enable
 946
 947 //MR3 (IO Configuration 1)
 948 #define LPDDR3_DS_34    (0x1)
 949 #define LPDDR3_DS_40    (0x2)
 950 #define LPDDR3_DS_48    (0x3)
 951 #define LPDDR3_DS_60    (0x4)        //reserved
 952 #define LPDDR3_DS_80    (0x6)        //reserved
 953 #define LPDDR3_DS_34D_40U   (0x9)
 954 #define LPDDR3_DS_40D_48U   (0xa)
 955 #define LPDDR3_DS_34D_48U   (0xb)
 956
 957 //MR4 (Device Temperature)
 958 #define LPDDR3_tREF_MASK (0x7)
 959 #define LPDDR3_LT_EXED   (0x0)       // SDRAM Low temperature operating limit exceeded
 960 #define LPDDR3_4_tREF    (0x1)
 961 #define LPDDR3_2_tREF    (0x2)
 962 #define LPDDR3_1_tREF    (0x3)
 963 #define LPDDR3_05_tREF   (0x4)
 964 #define LPDDR3_025_tREF  (0x5)
 965 #define LPDDR3_025_tREF_DERATE    (0x6)
 966 #define LPDDR3_HT_EXED   (0x7)       // SDRAM High temperature operating limit exceeded
 967
 968 #define LPDDR3_TUF       (0x1<<7)    // 1:value has changed since last read of MR4
 969
 970 //MR8 (Basic configuration 4)
 971 #define LPDDR3_S8        (0x3)
 972 #define LPDDR3_Density(mr8)  (8<<((mr8>>2)&0xf))   // Unit:MB
 973 #define LPDDR3_IO_Width(mr8) (32>>((mr8>>6)&0x3))
 974
 975 //MR10 (Calibration)
 976 #define LPDDR3_ZQINIT   (0xFF)
 977 #define LPDDR3_ZQCL     (0xAB)
 978 #define LPDDR3_ZQCS     (0x56)
 979 #define LPDDR3_ZQRESET  (0xC3)
 980
 981 //MR11 (ODT Control)
 982 #define LPDDR3_ODT_60   (1)           //optional for 1333 and 1600
 983 #define LPDDR3_ODT_120  (2)
 984 #define LPDDR3_ODT_240  (3)
 985 #define LPDDR3_ODT_DIS  (0)
 986
 987 //MR16 (PASR Bank Mask)
 988
 989 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 990
 991 //MR32 (DQ Calibration Pattern A)
 992
 993 //MR40 (DQ Calibration Pattern B)
 994
 995 /***********************************
 996  * DDR3 define
 997  ***********************************/
 998 //mr0 for ddr3
 999 #define DDR3_BL8          (0)
1000 #define DDR3_BC4_8        (1)
1001 #define DDR3_BC4          (2)
1002 #define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
1003 #define DDR3_WR(n)        (((n)&0x7)<<9)
1004 #define DDR3_DLL_RESET    (1<<8)
1005 #define DDR3_DLL_DeRESET  (0<<8)
1006
1007 //mr1 for ddr3
1008 #define DDR3_DLL_ENABLE    (0)
1009 #define DDR3_DLL_DISABLE   (1)
1010 #define DDR3_MR1_AL(n)  (((n)&0x3)<<3)
1011
1012 #define DDR3_DS_40            (0)
1013 #define DDR3_DS_34            (1<<1)
1014 #define DDR3_Rtt_Nom_DIS      (0)
1015 #define DDR3_Rtt_Nom_60       (1<<2)
1016 #define DDR3_Rtt_Nom_120      (1<<6)
1017 #define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
1018
1019     //mr2 for ddr3
1020 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
1021 #define DDR3_Rtt_WR_DIS       (0)
1022 #define DDR3_Rtt_WR_60        (1<<9)
1023 #define DDR3_Rtt_WR_120       (2<<9)
1024
1025 /***********************************
1026  * DDR2 define
1027  ***********************************/
1028 //MR;                     //Mode Register
1029 #define DDR2_BL4           (2)
1030 #define DDR2_BL8           (3)
1031 #define DDR2_CL(n)         (((n)&0x7)<<4)
1032 #define DDR2_WR(n)        ((((n)-1)&0x7)<<9)
1033 #define DDR2_DLL_RESET    (1<<8)
1034 #define DDR2_DLL_DeRESET  (0<<8)
1035
1036 //EMR;                    //Extended Mode Register
1037 #define DDR2_DLL_ENABLE    (0)
1038 #define DDR2_DLL_DISABLE   (1)
1039
1040 #define DDR2_STR_FULL     (0)
1041 #define DDR2_STR_REDUCE   (1<<1)
1042 #define DDR2_AL(n)        (((n)&0x7)<<3)
1043 #define DDR2_Rtt_Nom_DIS      (0)
1044 #define DDR2_Rtt_Nom_150      (0x40)
1045 #define DDR2_Rtt_Nom_75       (0x4)
1046 #define DDR2_Rtt_Nom_50       (0x44)
1047
1048 /***********************************
1049  * LPDDR define
1050  ***********************************/
1051 #define mDDR_BL2           (1)
1052 #define mDDR_BL4           (2)
1053 #define mDDR_BL8           (3)
1054 #define mDDR_CL(n)         (((n)&0x7)<<4)
1055
1056 #define mDDR_DS_Full       (0)
1057 #define mDDR_DS_1_2        (1<<5)
1058 #define mDDR_DS_1_4        (2<<5)
1059 #define mDDR_DS_1_8        (3<<5)
1060 #define mDDR_DS_3_4        (4<<5)
1061
1062 static const uint8_t ddr3_cl_cwl[22][7]={
1063 /*speed   0~330         331~400       401~533        534~666       667~800        801~933      934~1066
1064  * tCK    >3            2.5~3         1.875~2.5      1.5~1.875     1.25~1.5       1.07~1.25    0.938~1.07
1065  *        cl<<4, cwl    cl<<4, cwl    cl<<4, cwl              */
1066          {((5<<4)|5),   ((5<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800D (5-5-5)
1067          {((5<<4)|5),   ((6<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800E (6-6-6)
1068
1069          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    0,            0,             0,            0}, //DDR3_1066E (6-6-6)
1070          {((5<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    0,            0,             0,            0}, //DDR3_1066F (7-7-7)
1071          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    0,            0,             0,            0}, //DDR3_1066G (8-8-8)
1072
1073          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   0,             0,            0}, //DDR3_1333F (7-7-7)
1074          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   0,             0,            0}, //DDR3_1333G (8-8-8)
1075          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((9<<4)|7),   0,             0,            0}, //DDR3_1333H (9-9-9)
1076          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  0,             0,            0}, //DDR3_1333J (10-10-10)
1077
1078          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((8<<4)|8),    0,            0}, //DDR3_1600G (8-8-8)
1079          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    0,            0}, //DDR3_1600H (9-9-9)
1080          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   0,            0}, //DDR3_1600J (10-10-10)
1081          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   0,            0}, //DDR3_1600K (11-11-11)
1082
1083          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  0}, //DDR3_1866J (10-10-10)
1084          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   ((10<<4)|8),   ((11<<4)|9),  0}, //DDR3_1866K (11-11-11)
1085          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((12<<4)|9),  0}, //DDR3_1866L (12-12-12)
1086          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  0}, //DDR3_1866M (13-13-13)
1087
1088          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((9<<4)|8),    ((10<<4)|9),  ((11<<4)|10)}, //DDR3_2133K (11-11-11)
1089          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  ((12<<4)|10)}, //DDR3_2133L (12-12-12)
1090          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   ((12<<4)|9),  ((13<<4)|10)}, //DDR3_2133M (13-13-13)
1091          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)},  //DDR3_2133N (14-14-14)
1092
1093          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)} //DDR3_DEFAULT
1094 };
1095
1096 static const uint16_t ddr3_tRC_tFAW[22]={
1097 /**    tRC    tFAW   */
1098     ((50<<8)|50), //DDR3_800D (5-5-5)
1099     ((53<<8)|50), //DDR3_800E (6-6-6)
1100
1101     ((49<<8)|50), //DDR3_1066E (6-6-6)
1102     ((51<<8)|50), //DDR3_1066F (7-7-7)
1103     ((53<<8)|50), //DDR3_1066G (8-8-8)
1104
1105     ((47<<8)|45), //DDR3_1333F (7-7-7)
1106     ((48<<8)|45), //DDR3_1333G (8-8-8)
1107     ((50<<8)|45), //DDR3_1333H (9-9-9)
1108     ((51<<8)|45), //DDR3_1333J (10-10-10)
1109
1110     ((45<<8)|40), //DDR3_1600G (8-8-8)
1111     ((47<<8)|40), //DDR3_1600H (9-9-9)
1112     ((48<<8)|40), //DDR3_1600J (10-10-10)
1113     ((49<<8)|40), //DDR3_1600K (11-11-11)
1114
1115     ((45<<8)|35), //DDR3_1866J (10-10-10)
1116     ((46<<8)|35), //DDR3_1866K (11-11-11)
1117     ((47<<8)|35), //DDR3_1866L (12-12-12)
1118     ((48<<8)|35), //DDR3_1866M (13-13-13)
1119
1120     ((44<<8)|35), //DDR3_2133K (11-11-11)
1121     ((45<<8)|35), //DDR3_2133L (12-12-12)
1122     ((46<<8)|35), //DDR3_2133M (13-13-13)
1123     ((47<<8)|35), //DDR3_2133N (14-14-14)
1124
1125     ((53<<8)|50)  //DDR3_DEFAULT
1126 };
1127
1128 typedef enum DRAM_TYPE_Tag
1129 {
1130     LPDDR = 0,
1131     DDR,
1132     DDR2,
1133     DDR3,
1134     LPDDR2,
1135     LPDDR3,
1136
1137     DRAM_MAX
1138 }DRAM_TYPE;
1139
1140 typedef struct PCTRL_TIMING_Tag
1141 {
1142     uint32 ddrFreq;
1143     //Memory Timing Registers
1144     uint32 togcnt1u;               //Toggle Counter 1U Register
1145     uint32 tinit;                  //t_init Timing Register
1146     uint32 trsth;                  //Reset High Time Register
1147     uint32 togcnt100n;             //Toggle Counter 100N Register
1148     uint32 trefi;                  //t_refi Timing Register
1149     uint32 tmrd;                   //t_mrd Timing Register
1150     uint32 trfc;                   //t_rfc Timing Register
1151     uint32 trp;                    //t_rp Timing Register
1152     uint32 trtw;                   //t_rtw Timing Register
1153     uint32 tal;                    //AL Latency Register
1154     uint32 tcl;                    //CL Timing Register
1155     uint32 tcwl;                   //CWL Register
1156     uint32 tras;                   //t_ras Timing Register
1157     uint32 trc;                    //t_rc Timing Register
1158     uint32 trcd;                   //t_rcd Timing Register
1159     uint32 trrd;                   //t_rrd Timing Register
1160     uint32 trtp;                   //t_rtp Timing Register
1161     uint32 twr;                    //t_wr Timing Register
1162     uint32 twtr;                   //t_wtr Timing Register
1163     uint32 texsr;                  //t_exsr Timing Register
1164     uint32 txp;                    //t_xp Timing Register
1165     uint32 txpdll;                 //t_xpdll Timing Register
1166     uint32 tzqcs;                  //t_zqcs Timing Register
1167     uint32 tzqcsi;                 //t_zqcsi Timing Register
1168     uint32 tdqs;                   //t_dqs Timing Register
1169     uint32 tcksre;                 //t_cksre Timing Register
1170     uint32 tcksrx;                 //t_cksrx Timing Register
1171     uint32 tcke;                   //t_cke Timing Register
1172     uint32 tmod;                   //t_mod Timing Register
1173     uint32 trstl;                  //Reset Low Timing Register
1174     uint32 tzqcl;                  //t_zqcl Timing Register
1175     uint32 tmrr;                   //t_mrr Timing Register
1176     uint32 tckesr;                 //t_ckesr Timing Register
1177     uint32 tdpd;                   //t_dpd Timing Register
1178 }PCTL_TIMING_T;
1179
1180 typedef union DTPR_0_Tag
1181 {
1182     uint32 d32;
1183     struct
1184     {
1185         unsigned tMRD : 2;
1186         unsigned tRTP : 3;
1187         unsigned tWTR : 3;
1188         unsigned tRP : 4;
1189         unsigned tRCD : 4;
1190         unsigned tRAS : 5;
1191         unsigned tRRD : 4;
1192         unsigned tRC : 6;
1193         unsigned tCCD : 1;
1194     } b;
1195 }DTPR_0_T;
1196
1197 typedef union DTPR_1_Tag
1198 {
1199     uint32 d32;
1200     struct
1201     {
1202         unsigned tAOND : 2;
1203         unsigned tRTW : 1;
1204         unsigned tFAW : 6;
1205         unsigned tMOD : 2;
1206         unsigned tRTODT : 1;
1207         unsigned reserved12_15 : 4;
1208         unsigned tRFC : 8;
1209         unsigned tDQSCK : 3;
1210         unsigned tDQSCKmax : 3;
1211         unsigned reserved30_31 : 2;
1212     } b;
1213 }DTPR_1_T;
1214
1215 typedef union DTPR_2_Tag
1216 {
1217     uint32 d32;
1218     struct
1219     {
1220         unsigned tXS : 10;
1221         unsigned tXP : 5;
1222         unsigned tCKE : 4;
1223         unsigned tDLLK : 10;
1224         unsigned reserved29_31 : 3;
1225     } b;
1226 }DTPR_2_T;
1227
1228 typedef struct PHY_TIMING_Tag
1229 {
1230     DTPR_0_T  dtpr0;
1231     DTPR_1_T  dtpr1;
1232     DTPR_2_T  dtpr2;
1233     uint32    mr[4];   //LPDDR2 no MR0, mr[2] is mDDR MR1
1234     uint32    mr11;    //for LPDDR3 only
1235 }PHY_TIMING_T;
1236
1237 typedef struct PCTL_REG_Tag
1238 {
1239     uint32 SCFG;
1240     uint32 CMDTSTATEN;
1241     uint32 MCFG1;
1242     uint32 MCFG;
1243     PCTL_TIMING_T pctl_timing;
1244     //DFI Control Registers
1245     uint32 DFITCTRLDELAY;
1246     uint32 DFIODTCFG;
1247     uint32 DFIODTCFG1;
1248     uint32 DFIODTRANKMAP;
1249     //DFI Write Data Registers
1250     uint32 DFITPHYWRDATA;
1251     uint32 DFITPHYWRLAT;
1252     //DFI Read Data Registers
1253     uint32 DFITRDDATAEN;
1254     uint32 DFITPHYRDLAT;
1255     //DFI Update Registers
1256     uint32 DFITPHYUPDTYPE0;
1257     uint32 DFITPHYUPDTYPE1;
1258     uint32 DFITPHYUPDTYPE2;
1259     uint32 DFITPHYUPDTYPE3;
1260     uint32 DFITCTRLUPDMIN;
1261     uint32 DFITCTRLUPDMAX;
1262     uint32 DFITCTRLUPDDLY;
1263     uint32 DFIUPDCFG;
1264     uint32 DFITREFMSKI;
1265     uint32 DFITCTRLUPDI;
1266     //DFI Status Registers
1267     uint32 DFISTCFG0;
1268     uint32 DFISTCFG1;
1269     uint32 DFITDRAMCLKEN;
1270     uint32 DFITDRAMCLKDIS;
1271     uint32 DFISTCFG2;
1272     //DFI Low Power Register
1273     uint32 DFILPCFG0;
1274 }PCTL_REG_T;
1275
1276 typedef struct PUBL_DQS_REG_Tag
1277 {
1278     uint32 DX0GCR;
1279     uint32 DX0DLLCR;
1280     uint32 DX0DQTR;
1281     uint32 DX0DQSTR;
1282
1283     uint32 DX1GCR;
1284     uint32 DX1DLLCR;
1285     uint32 DX1DQTR;
1286     uint32 DX1DQSTR;
1287
1288     uint32 DX2GCR;
1289     uint32 DX2DLLCR;
1290     uint32 DX2DQTR;
1291     uint32 DX2DQSTR;
1292
1293     uint32 DX3GCR;
1294     uint32 DX3DLLCR;
1295     uint32 DX3DQTR;
1296     uint32 DX3DQSTR;
1297 }PUBL_DQS_REG;
1298
1299 typedef struct PUBL_REG_Tag
1300 {
1301     uint32 PIR;
1302     uint32 PGCR;
1303     uint32 DLLGCR;
1304     uint32 ACDLLCR;
1305     uint32 PTR[3];
1306     uint32 ACIOCR;
1307     uint32 DXCCR;
1308     uint32 DSGCR;
1309     uint32 DCR;
1310     PHY_TIMING_T phy_timing;
1311     uint32 ODTCR;
1312     uint32 DTAR;
1313     uint32 ZQ0CR0;
1314     uint32 ZQ1CR0;
1315 }PUBL_REG_T;
1316
1317 typedef struct SET_REG_Tag
1318 {
1319     uint32 addr;
1320     uint32 val;
1321 }SET_REG_T;
1322
1323 typedef struct BACKUP_REG_Tag
1324 {
1325     uint32 tag;
1326     /* any addr = 0xFFFFFFFF, indicate invalid */
1327     uint32 pctlAddr[CH_MAX];
1328     PCTL_REG_T pctl;
1329     uint32 publAddr[CH_MAX];
1330     PUBL_REG_T publ;
1331     PUBL_DQS_REG dqs[CH_MAX];
1332     uint32 nocAddr[CH_MAX];
1333     MSCH_REG   noc[CH_MAX];
1334
1335     uint32 pllpdAddr;
1336     uint32 pllpdMask;
1337     uint32 pllpdVal;
1338
1339     uint32 dpllmodeAddr;
1340     uint32 dpllSlowMode;
1341     uint32 dpllNormalMode;
1342     uint32 dpllResetAddr;
1343     uint32 dpllReset;
1344     uint32 dpllDeReset;
1345     uint32 dpllConAddr;
1346     uint32 dpllCon[4];
1347     uint32 dpllLockAddr;
1348     uint32 dpllLockMask;
1349     uint32 dpllLockVal;
1350
1351     uint32 ddrPllSrcDivAddr;
1352     uint32 ddrPllSrcDiv;
1353
1354     uint32 retenDisAddr;
1355     uint32 retenDisVal;
1356     uint32 retenStAddr;
1357     uint32 retenStMask;
1358     uint32 retenStVal;
1359
1360     /* ddr relative grf register */
1361     uint32 grfRegCnt;     //if no grf, set 0
1362     SET_REG_T grf[3];        //SET_REG_T grf[grfRegCnt];
1363
1364     /* other ddr relative register */
1365     //uint32 otherRegCnt; // if = 0xFFFFFFFF, indicate invalid
1366     //SET_REG_T other[grfRegCnt];
1367     uint32 endTag;         //must = 0xFFFFFFFF
1368 }BACKUP_REG_T;
1369
1370 typedef struct CHANNEL_INFO_Tag
1371 {
1372     //inited data
1373     uint32        chNum;  //channel number,0:channel a; 1:channel b;
1374     pDDR_REG_T    pDDR_Reg;
1375     pDDRPHY_REG_T pPHY_Reg;
1376     pMSCH_REG     pMSCH_Reg;
1377     //need init data
1378     DRAM_TYPE     mem_type; // =DRAM_MAX, channel invalid
1379     uint32        ddr_speed_bin;    // used for ddr3 only
1380     uint32        ddr_capability_per_die;  // one chip cs capability
1381 }CH_INFO,*pCH_INFO;
1382
1383 struct ddr_freq_t {
1384     unsigned long screen_ft_us;
1385     unsigned long long t0;
1386     unsigned long long t1;
1387     unsigned long t2;
1388 };
1389
1390 typedef struct STRIDE_INFO_Tag
1391 {
1392     uint32  size;
1393     uint32  halfCap;
1394 }STRIDE_INFO;
1395
1396 static const STRIDE_INFO   gStrideInfo[]={
1397     {0x10000000,0x10000000},  // 256
1398     {0x20000000,0x20000000},  // 512
1399     {0x40000000,0x40000000},  // 1G
1400     {0x80000000,0x80000000},  // 2G
1401
1402     {128,0x20000000},
1403     {256,0x20000000},
1404     {512,0x20000000},
1405     {4096,0x20000000},
1406
1407     {128,0x40000000},
1408     {256,0x40000000},
1409     {512,0x40000000},
1410     {4096,0x40000000},
1411
1412     {128,0x80000000},
1413     {256,0x80000000},
1414     {512,0x80000000},
1415     {4096,0x80000000},
1416
1417     {128,0x60000000},
1418     {256,0x60000000},
1419     {512,0x60000000},
1420     {4096,0x60000000},
1421
1422     {0,0x20000000},
1423     {0,0x40000000},
1424     {0,0x80000000},
1425     {0,0x80000000},  // 4GB
1426
1427     {0,0},  //reserved
1428     {0,0},  //reserved
1429
1430     {0,0},
1431     {128,0},
1432 };
1433
1434 CH_INFO DEFINE_PIE_DATA(ddr_ch[2]);
1435 static pCH_INFO p_ddr_ch[2];    //only used in kern, not pie
1436 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
1437 static BACKUP_REG_T *p_ddr_reg;
1438 static __attribute__((aligned(4096))) uint32 ddr_data_training_buf[32+8192/4];  //data in two channel even use max stride
1439 uint32 DEFINE_PIE_DATA(ddr_freq);
1440 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
1441
1442 /***********************************
1443  * ARCH Relative Data and Function
1444  ***********************************/
1445 static __sramdata uint32 clkr;
1446 static __sramdata uint32 clkf;
1447 static __sramdata uint32 clkod;
1448 uint32 DEFINE_PIE_DATA(ddr_select_gpll_div); // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1449 static uint32 *p_ddr_select_gpll_div;
1450
1451 static void __sramfunc ddr_delayus(uint32 us);
1452
1453 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
1454 {
1455     uint32 ret = 0;
1456
1457      // freq = (Fin/NR)*NF/OD
1458     if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1)             // DPLL Normal mode
1459         ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x1fff)+1)    // NF = 2*(CLKF+1)
1460                 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1)           // NR = CLKR+1
1461                 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xF)+1));             // OD = 2^CLKOD
1462     else
1463         ret = 24;
1464
1465     return ret;
1466 }
1467
1468 /*****************************************
1469 NR   NO     NF               Fout                       freq Step     finally use
1470 1    8      12.5 - 62.5      37.5MHz  - 187.5MHz        3MHz          50MHz   <= 150MHz
1471 1    6      12.5 - 62.5      50MHz    - 250MHz          4MHz          150MHz  <= 200MHz
1472 1    4      12.5 - 62.5      75MHz    - 375MHz          6MHz          200MHz  <= 300MHz
1473 1    2      12.5 - 62.5      150MHz   - 750MHz          12MHz         300MHz  <= 600MHz
1474 1    1      12.5 - 62.5      300MHz   - 1500MHz         24MHz         600MHz  <= 1200MHz
1475 ******************************************/
1476 static uint32 __sramfunc ddr_set_pll_rk3188_plus(uint32 nMHz, uint32 set)
1477 {
1478     uint32 ret = 0;
1479     int delay;
1480
1481     if(nMHz == 24)
1482     {
1483         ret = 24;
1484         goto out;
1485     }
1486
1487     if(set==0)
1488     {
1489         if(nMHz <= 150)
1490         {
1491             clkod = 8;
1492         }
1493         else if(nMHz <= 200)
1494         {
1495             clkod = 6;
1496         }
1497         else if(nMHz <= 300)
1498         {
1499             clkod = 4;
1500         }
1501         else if(nMHz <= 600)
1502         {
1503             clkod = 2;
1504         }
1505         else
1506         {
1507             clkod = 1;
1508         }
1509         clkr = 1;
1510         clkf=(nMHz*clkr*clkod)/24;
1511         ret = (24*clkf)/(clkr*clkod);
1512     }
1513     else if(set == 1)
1514     {
1515         SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)-1));  //clk_ddr_src = GPLL
1516
1517         SET_PLL_MODE(DPLL,0);            //PLL slow-mode
1518         dsb();
1519
1520         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
1521         ddr_delayus(1);
1522         pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
1523         pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
1524         pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
1525         ddr_delayus(1);
1526         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
1527         dsb();
1528     }
1529     else
1530     {
1531         delay = 1000;
1532         while (delay > 0)
1533         {
1534             if (GET_DPLL_LOCK_STATUS())
1535                 break;
1536             ddr_delayus(1);
1537             delay--;
1538         }
1539
1540         SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1541         SET_PLL_MODE(DPLL,1);            //PLL normal
1542         dsb();
1543     }
1544
1545 out:
1546     return ret;
1547 }
1548
1549 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1550 {
1551     return ddr_set_pll_rk3188_plus(nMHz,set);
1552 }
1553 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1554 static uint32 (*p_ddr_set_pll)(uint32 nMHz, uint32 set);
1555
1556 static void __sramfunc idle_port(void)
1557 {
1558     register int i,j;
1559     uint32 clk_gate[19];
1560
1561     pPMU_Reg->PMU_IDLE_REQ |= idle_req_core_cfg;
1562     dsb();
1563     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) == 0 );
1564
1565     //save clock gate status
1566     for(i=0;i<19;i++)
1567         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1568
1569     //enable all clock gate for request idle
1570     for(i=0;i<19;i++)
1571         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1572
1573     i = pPMU_Reg->PMU_PWRDN_ST;
1574     j = idle_req_dma_cfg;
1575
1576     if ( (i & pd_peri_pwr_st) == 0 )
1577     {
1578         j |= idle_req_peri_cfg;
1579     }
1580
1581     if ( (i & pd_video_pwr_st) == 0 )
1582     {
1583         j |= idle_req_video_cfg;
1584     }
1585
1586     if ( (i & pd_gpu_pwr_st) == 0 )
1587     {
1588         j |= idle_req_gpu_cfg;
1589     }
1590
1591     if ( (i & pd_hevc_pwr_st) == 0 )
1592     {
1593         j |= idle_req_hevc_cfg;
1594     }
1595
1596     if ( (i & pd_vio_pwr_st) == 0 )
1597     {
1598         j |= idle_req_vio_cfg;
1599     }
1600
1601     pPMU_Reg->PMU_IDLE_REQ |= j;
1602     dsb();
1603     while( (pPMU_Reg->PMU_IDLE_ST & j) != j );
1604
1605     //resume clock gate status
1606     for(i=0;i<19;i++)
1607         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1608 }
1609
1610 static void __sramfunc deidle_port(void)
1611 {
1612     register int i,j;
1613     uint32 clk_gate[19];
1614
1615     //save clock gate status
1616     for(i=0;i<19;i++)
1617         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1618
1619     //enable all clock gate for request idle
1620     for(i=0;i<19;i++)
1621         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1622
1623     i = pPMU_Reg->PMU_PWRDN_ST;
1624     j = idle_req_dma_cfg;
1625
1626     if ( (i & pd_peri_pwr_st) == 0 )
1627     {
1628         j |= idle_req_peri_cfg;
1629     }
1630
1631     if ( (i & pd_video_pwr_st) == 0 )
1632     {
1633         j |= idle_req_video_cfg;
1634     }
1635
1636     if ( (i & pd_gpu_pwr_st) == 0 )
1637     {
1638         j |= idle_req_gpu_cfg;
1639     }
1640
1641     if ( (i & pd_hevc_pwr_st) == 0 )
1642     {
1643         j |= idle_req_hevc_cfg;
1644     }
1645
1646     if ( (i & pd_vio_pwr_st) == 0 )
1647     {
1648         j |= idle_req_vio_cfg;
1649     }
1650
1651     pPMU_Reg->PMU_IDLE_REQ &= ~j;
1652     dsb();
1653     while( (pPMU_Reg->PMU_IDLE_ST & j) != 0 );
1654
1655     pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_core_cfg;
1656     dsb();
1657     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) != 0 );
1658
1659     //resume clock gate status
1660     for(i=0;i<19;i++)
1661         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1662
1663 }
1664
1665 /***********************************
1666  * Only DDR Relative Function
1667  ***********************************/
1668
1669 /****************************************************************************
1670 Internal sram us delay function
1671 Cpu highest frequency is 1.6 GHz
1672 1 cycle = 1/1.6 ns
1673 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1674 *****************************************************************************/
1675 __sramdata volatile uint32 loops_per_us;
1676
1677 #define LPJ_100MHZ  999456UL
1678
1679 static void __sramfunc ddr_delayus(uint32 us)
1680 {
1681     do
1682     {
1683         volatile unsigned int i = (loops_per_us*us);
1684         if (i < 7) i = 7;
1685         barrier();
1686         asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1687     } while (0);
1688 }
1689
1690 void PIE_FUNC(ddr_copy)(uint64_t *pDest, uint64_t *pSrc, uint32 wword)
1691 {
1692     uint32 i;
1693
1694     for(i=0; i<wword; i++)
1695     {
1696         pDest[i] = pSrc[i];
1697     }
1698 }
1699 EXPORT_PIE_SYMBOL(FUNC(ddr_copy));
1700
1701 static void ddr_get_datatraing_addr(uint32 *pdtar)
1702 {
1703     uint32          addr;
1704     uint32          stride;
1705     uint32          strideSize;
1706     uint32          halfCap;
1707     uint32          ch,chCnt;
1708     uint32          socAddr[2];
1709     uint32          chAddr[2];
1710     uint32          col;
1711     uint32          row;
1712     uint32          bank;
1713     uint32          bw;
1714     uint32          conf;
1715
1716     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1717     {
1718         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1719         {
1720             chCnt++;
1721         }
1722     }
1723
1724     // caculate aglined physical address
1725     addr =  __pa((unsigned long)ddr_data_training_buf);
1726     ddr_print("addr=0x%x\n",addr);
1727     if(addr&0x3F)
1728     {
1729         addr += (64-(addr&0x3F));  // 64byte align
1730     }
1731     addr -= DRAM_PHYS;
1732     if(chCnt > 1)
1733     {
1734         //find stride info
1735         stride = READ_DDR_STRIDE();
1736         strideSize = gStrideInfo[stride].size;
1737         halfCap = gStrideInfo[stride].halfCap;
1738         ddr_print("stride=%d, size=%d, halfcap=%x\n", stride,strideSize,halfCap);
1739         //get soc addr
1740         if(addr & strideSize)  // odd stride size
1741         {
1742             socAddr[0] = addr + strideSize;
1743             socAddr[1] = addr;
1744         }
1745         else
1746         {
1747             socAddr[0] = addr;
1748             socAddr[1] = addr + strideSize;
1749         }
1750         ddr_print("socAddr[0]=0x%x, socAddr[1]=0x%x\n", socAddr[0], socAddr[1]);
1751         if((stride >= 0x10) && (stride <= 0x13))  // 3GB stride
1752         {
1753             //conver to ch addr
1754             if(addr < 0x40000000)
1755             {
1756                 chAddr[0] = socAddr[0];
1757                 chAddr[1] = socAddr[1] - strideSize;
1758             }
1759             else if(addr < 0x80000000)
1760             {
1761                 chAddr[0] = socAddr[0] - 0x40000000 + strideSize;
1762                 chAddr[1] = socAddr[1] - 0x40000000;
1763             }
1764             else if(addr < 0xA0000000)
1765             {
1766                 chAddr[0] = socAddr[0] - 0x40000000;
1767                 chAddr[1] = socAddr[1] - 0x40000000 - strideSize;
1768             }
1769             else
1770             {
1771                 chAddr[0] = socAddr[0] - 0x60000000 + strideSize;
1772                 chAddr[1] = socAddr[1] - 0x60000000;
1773             }
1774         }
1775         else
1776         {
1777             //conver to ch addr
1778             if(addr <  halfCap)
1779             {
1780                 chAddr[0] = socAddr[0];
1781                 chAddr[1] = socAddr[1] - strideSize;
1782             }
1783             else
1784             {
1785                 chAddr[0] = socAddr[0] - halfCap + strideSize;
1786                 chAddr[1] = socAddr[1] - halfCap;
1787             }
1788         }
1789         ddr_print("chAddr[0]=0x%x, chAddr[1]=0x%x\n", chAddr[0], chAddr[1]);
1790     }
1791     else
1792     {
1793         chAddr[0] = addr;
1794         chAddr[1] = addr;
1795     }
1796
1797     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1798     {
1799         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1800         {
1801             // find out col£¬row£¬bank,config
1802             row = READ_ROW_INFO(ch,0);
1803             bank = READ_BK_INFO(ch);
1804             col = READ_COL_INFO(ch);
1805             bw = READ_BW_INFO(ch);
1806             conf = p_ddr_ch[ch]->pMSCH_Reg->ddrconf;
1807             // according different address mapping, caculate DTAR register value
1808             pdtar[ch] = 0;
1809             pdtar[ch] |= ((chAddr[ch])>>bw) & ((0x1<<col)-1);  // col
1810             pdtar[ch] |= (((chAddr[ch])>>(bw+col+((ddr_cfg_2_rbc[conf]>>2)&0x3))) & ((0x1<<row)-1)) << 12;  // row
1811             if(((ddr_cfg_2_rbc[conf]>>7)&0x3)==3)
1812             {
1813                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col+row)) & ((0x1<<bank)-1))  << 28);  // bank
1814             }
1815             else
1816             {
1817                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col)) & 0x7) << 28);  // bank
1818             }
1819         }
1820     }
1821     ddr_print("dtar[0]=0x%x, dtar[1]=0x%x\n", pdtar[0], pdtar[1]);
1822 }
1823
1824 static __sramfunc void ddr_reset_dll(uint32 ch)
1825 {
1826     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1827     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1828
1829     pPHY_Reg->ACDLLCR &= ~0x40000000;
1830     pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1831     pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1832     if(!(pDDR_Reg->PPCFG & 1))
1833     {
1834         pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1835         pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1836     }
1837     ddr_delayus(1);
1838     pPHY_Reg->ACDLLCR |= 0x40000000;
1839     pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1840     pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1841     if(!(pDDR_Reg->PPCFG & 1))
1842     {
1843         pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1844         pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1845     }
1846     ddr_delayus(1);
1847 }
1848
1849 static __sramfunc void ddr_move_to_Lowpower_state(uint32 ch)
1850 {
1851     register uint32 value;
1852     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1853
1854     while(1)
1855     {
1856         value = pDDR_Reg->STAT.b.ctl_stat;
1857         if(value == Low_power)
1858         {
1859             break;
1860         }
1861         switch(value)
1862         {
1863             case Init_mem:
1864                 pDDR_Reg->SCTL = CFG_STATE;
1865                 dsb();
1866                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1867             case Config:
1868                 pDDR_Reg->SCTL = GO_STATE;
1869                 dsb();
1870                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1871             case Access:
1872                 pDDR_Reg->SCTL = SLEEP_STATE;
1873                 dsb();
1874                 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1875                 break;
1876             default:  //Transitional state
1877                 break;
1878         }
1879     }
1880 }
1881
1882 static __sramfunc void ddr_move_to_Access_state(uint32 ch)
1883 {
1884     register uint32 value;
1885     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1886     register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1887
1888     //set auto self-refresh idle
1889     pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00) | DATA(ddr_sr_idle) | (1<<31);
1890     dsb();
1891
1892     while(1)
1893     {
1894         value = pDDR_Reg->STAT.b.ctl_stat;
1895         if((value == Access)
1896            || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1897         {
1898             break;
1899         }
1900         switch(value)
1901         {
1902             case Low_power:
1903                 pDDR_Reg->SCTL = WAKEUP_STATE;
1904                 dsb();
1905                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1906                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1907                 break;
1908             case Init_mem:
1909                 pDDR_Reg->SCTL = CFG_STATE;
1910                 dsb();
1911                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1912             case Config:
1913                 pDDR_Reg->SCTL = GO_STATE;
1914                 dsb();
1915                 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1916                       || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1917                 break;
1918             default:  //Transitional state
1919                 break;
1920         }
1921     }
1922     /* de_hw_wakeup :enable auto sr if sr_idle != 0 */
1923     DDR_HW_WAKEUP(ch,0);
1924 }
1925
1926 static __sramfunc void ddr_move_to_Config_state(uint32 ch)
1927 {
1928     register uint32 value;
1929     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1930     register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1931
1932     /* hw_wakeup :disable auto sr */
1933     DDR_HW_WAKEUP(ch,1);
1934         dsb();
1935
1936     while(1)
1937     {
1938         value = pDDR_Reg->STAT.b.ctl_stat;
1939         if(value == Config)
1940         {
1941             break;
1942         }
1943         switch(value)
1944         {
1945             case Low_power:
1946                 pDDR_Reg->SCTL = WAKEUP_STATE;
1947                 dsb();
1948                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1949                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1950             case Access:
1951             case Init_mem:
1952                 pDDR_Reg->SCTL = CFG_STATE;
1953                 dsb();
1954                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1955                 break;
1956             default:  //Transitional state
1957                 break;
1958         }
1959     }
1960 }
1961
1962 //arg°üÀ¨bank_addrºÍcmd_addr
1963 static void __sramfunc ddr_send_command(uint32 ch, uint32 rank, uint32 cmd, uint32 arg)
1964 {
1965     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1966
1967     pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1968     dsb();
1969     while(pDDR_Reg->MCMD & start_cmd);
1970 }
1971
1972 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
1973 //0  DTT³É¹¦
1974 //!0 DTTÊ§°Ü
1975 static uint32 __sramfunc ddr_data_training_trigger(uint32 ch)
1976 {
1977     uint32        cs;
1978     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1979     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1980
1981     // disable auto refresh
1982     pDDR_Reg->TREFI = 0;
1983     dsb();
1984     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
1985        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
1986     {
1987         // passive window
1988         pPHY_Reg->PGCR |= (1<<1);
1989     }
1990     // clear DTDONE status
1991     pPHY_Reg->PIR |= CLRSR;
1992     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
1993     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18);  //use cs0 dtt
1994     // trigger DTT
1995     pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
1996     return cs;
1997 }
1998 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
1999 //0  DTT³É¹¦
2000 //!0 DTTÊ§°Ü
2001 static uint32 __sramfunc ddr_data_training(uint32 ch, uint32 cs)
2002 {
2003     uint32        i,byte;
2004     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2005     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2006
2007     // wait echo byte DTDONE
2008     while((pPHY_Reg->DATX8[0].DXGSR[0] & 1) != 1);
2009     while((pPHY_Reg->DATX8[1].DXGSR[0] & 1) != 1);
2010     if(!(pDDR_Reg->PPCFG & 1))
2011     {
2012         while((pPHY_Reg->DATX8[2].DXGSR[0] & 1) != 1);
2013         while((pPHY_Reg->DATX8[3].DXGSR[0] & 1) != 1);
2014         byte=4;
2015     }
2016     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18);  //restore cs
2017     for(i=0;i<byte;i++)
2018     {
2019         pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))
2020                                       | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)
2021                                       | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
2022     }
2023     // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×î³¤Ê±¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
2024     if(cs > 1)
2025     {
2026         ddr_send_command(ch,cs, REF_cmd, 0);
2027         ddr_send_command(ch,cs, REF_cmd, 0);
2028         ddr_send_command(ch,cs, REF_cmd, 0);
2029         ddr_send_command(ch,cs, REF_cmd, 0);
2030     }
2031     else
2032     {
2033         ddr_send_command(ch,cs, REF_cmd, 0);
2034         ddr_send_command(ch,cs, REF_cmd, 0);
2035     }
2036     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
2037        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
2038     {
2039         // active window
2040         pPHY_Reg->PGCR &= ~(1<<1);
2041     }
2042     // resume auto refresh
2043     pDDR_Reg->TREFI = DATA(ddr_reg).pctl.pctl_timing.trefi;
2044
2045     if(pPHY_Reg->PGSR & DTERR)
2046     {
2047         return (-1);
2048     }
2049     else
2050     {
2051         return 0;
2052     }
2053 }
2054
2055 static void __sramfunc ddr_set_dll_bypass(uint32 ch, uint32 freq)
2056 {
2057     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2058     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2059
2060     if(freq<=150)
2061     {
2062         pPHY_Reg->DLLGCR &= ~(1<<23);
2063         pPHY_Reg->ACDLLCR |= 0x80000000;
2064         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2065         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2066         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2067         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2068         pPHY_Reg->PIR |= DLLBYP;
2069     }
2070     else if(freq<=250)
2071     {
2072         pPHY_Reg->DLLGCR |= (1<<23);
2073         pPHY_Reg->ACDLLCR |= 0x80000000;
2074         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2075         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2076         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2077         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2078         pPHY_Reg->PIR |= DLLBYP;
2079     }
2080     else
2081     {
2082         pPHY_Reg->DLLGCR &= ~(1<<23);
2083         pPHY_Reg->ACDLLCR &= ~0x80000000;
2084         pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
2085         pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
2086         if(!(pDDR_Reg->PPCFG & 1))
2087         {
2088             pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
2089             pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
2090         }
2091         pPHY_Reg->PIR &= ~DLLBYP;
2092     }
2093 }
2094
2095 static noinline uint32 ddr_get_parameter(uint32 nMHz)
2096 {
2097     uint32 tmp;
2098     uint32 ret = 0;
2099     uint32 al;
2100     uint32 bl,bl_tmp;
2101     uint32 cl;
2102     uint32 cwl;
2103     PCTL_TIMING_T *p_pctl_timing=&(p_ddr_reg->pctl.pctl_timing);
2104     PHY_TIMING_T  *p_publ_timing=&(p_ddr_reg->publ.phy_timing);
2105     NOC_TIMING_T  *p_noc_timing=&(p_ddr_reg->noc[0].ddrtiming);
2106     NOC_ACTIVATE_T  *p_noc_activate=&(p_ddr_reg->noc[0].activate);
2107     uint32 ch;
2108     uint32 mem_type;
2109     uint32 ddr_speed_bin=DDR3_DEFAULT;
2110     uint32 ddr_capability_per_die=0;
2111
2112     for(ch=0;ch<CH_MAX;ch++)
2113     {
2114         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
2115         {
2116             mem_type = p_ddr_ch[ch]->mem_type;
2117             if(ddr_speed_bin == DDR3_DEFAULT)
2118             {
2119                 ddr_speed_bin = p_ddr_ch[ch]->ddr_speed_bin;
2120             }
2121             else
2122             {
2123                 ddr_speed_bin = (ddr_speed_bin > p_ddr_ch[ch]->ddr_speed_bin) ? ddr_speed_bin : p_ddr_ch[ch]->ddr_speed_bin;
2124             }
2125             if(ddr_capability_per_die == 0)
2126             {
2127                 ddr_capability_per_die = p_ddr_ch[ch]->ddr_capability_per_die;
2128             }
2129             else
2130             {
2131                 ddr_capability_per_die = (ddr_capability_per_die > p_ddr_ch[ch]->ddr_capability_per_die) ? ddr_capability_per_die : p_ddr_ch[ch]->ddr_capability_per_die;
2132             }
2133             break;
2134         }
2135     }
2136
2137     p_pctl_timing->togcnt1u = nMHz;
2138     p_pctl_timing->togcnt100n = nMHz/10;
2139     p_pctl_timing->tinit = 200;
2140     p_pctl_timing->trsth = 500;
2141
2142     if(mem_type == DDR3)
2143     {
2144         if(ddr_speed_bin > DDR3_DEFAULT){
2145             ret = -1;
2146             goto out;
2147         }
2148
2149         #define DDR3_tREFI_7_8_us    (78)  //unit 100ns
2150         #define DDR3_tMRD            (4)   //tCK
2151         #define DDR3_tRFC_512Mb      (90)  //ns
2152         #define DDR3_tRFC_1Gb        (110) //ns
2153         #define DDR3_tRFC_2Gb        (160) //ns
2154         #define DDR3_tRFC_4Gb        (300) //ns
2155         #define DDR3_tRFC_8Gb        (350) //ns
2156         #define DDR3_tRTW            (2)   //register min valid value
2157         #define DDR3_tRAS            (37)  //ns
2158         #define DDR3_tRRD            (10)  //ns
2159         #define DDR3_tRTP            (7)   //ns
2160         #define DDR3_tWR             (15)  //ns
2161         #define DDR3_tWTR            (7)   //ns
2162         #define DDR3_tXP             (7)   //ns
2163         #define DDR3_tXPDLL          (24)  //ns
2164         #define DDR3_tZQCS           (80)  //ns
2165         #define DDR3_tZQCSI          (0)   //ns
2166         #define DDR3_tDQS            (1)   //tCK
2167         #define DDR3_tCKSRE          (10)  //ns
2168         #define DDR3_tCKE_400MHz     (7)   //ns
2169         #define DDR3_tCKE_533MHz     (6)   //ns
2170         #define DDR3_tMOD            (15)  //ns
2171         #define DDR3_tRSTL           (100) //ns
2172         #define DDR3_tZQCL           (320) //ns
2173         #define DDR3_tDLLK           (512) //tCK
2174
2175         al = 0;
2176         bl = 8;
2177         if(nMHz <= 330)
2178         {
2179             tmp = 0;
2180         }
2181         else if(nMHz<=400)
2182         {
2183             tmp = 1;
2184         }
2185         else if(nMHz<=533)
2186         {
2187             tmp = 2;
2188         }
2189         else if(nMHz<=666)
2190         {
2191             tmp = 3;
2192         }
2193         else if(nMHz<=800)
2194         {
2195             tmp = 4;
2196         }
2197         else if(nMHz<=933)
2198         {
2199             tmp = 5;
2200         }
2201         else
2202         {
2203             tmp = 6;
2204         }
2205
2206         if(nMHz < 300)       //when dll bypss cl = cwl = 6;
2207         {
2208             cl = 6;
2209             cwl = 6;
2210         }
2211         else
2212         {
2213             cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
2214             cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
2215         }
2216         if(cl == 0)
2217             ret = -4;
2218         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2219         {
2220             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
2221         }
2222         else
2223         {
2224             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
2225         }
2226         p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
2227         p_publ_timing->mr[3] = 0;
2228         /**************************************************
2229          * PCTL Timing
2230          **************************************************/
2231         /*
2232          * tREFI, average periodic refresh interval, 7.8us
2233          */
2234         p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
2235         /*
2236          * tMRD, 4 tCK
2237          */
2238         p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
2239         p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
2240         /*
2241          * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
2242          */
2243         if(ddr_capability_per_die <= 0x4000000)         // 512Mb 90ns
2244         {
2245             tmp = DDR3_tRFC_512Mb;
2246         }
2247         else if(ddr_capability_per_die <= 0x8000000)    // 1Gb 110ns
2248         {
2249             tmp = DDR3_tRFC_1Gb;
2250         }
2251         else if(ddr_capability_per_die <= 0x10000000)   // 2Gb 160ns
2252         {
2253             tmp = DDR3_tRFC_2Gb;
2254         }
2255         else if(ddr_capability_per_die <= 0x20000000)   // 4Gb 300ns
2256         {
2257             tmp = DDR3_tRFC_4Gb;
2258         }
2259         else    // 8Gb  350ns
2260         {
2261             tmp = DDR3_tRFC_8Gb;
2262         }
2263         p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2264         p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000);
2265         /*
2266          * tXSR, =tDLLK=512 tCK
2267          */
2268         p_pctl_timing->texsr = DDR3_tDLLK;
2269         p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
2270         /*
2271          * tRP=CL
2272          */
2273         p_pctl_timing->trp = cl;
2274         p_publ_timing->dtpr0.b.tRP = cl;
2275         /*
2276          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2277          */
2278         p_noc_timing->b.WrToMiss = (cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl);
2279         /*
2280          * tRC=tRAS+tRP
2281          */
2282         p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2283         p_noc_timing->b.ActToAct = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2284         p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2285
2286         p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
2287         p_publ_timing->dtpr1.b.tRTW = 0;
2288         p_noc_timing->b.RdToWr = (cl+2-cwl);
2289         p_pctl_timing->tal = al;
2290         p_pctl_timing->tcl = cl;
2291         p_pctl_timing->tcwl = cwl;
2292         /*
2293          * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
2294          */
2295         p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
2296         p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000);
2297         /*
2298          * tRCD=CL
2299          */
2300         p_pctl_timing->trcd = cl;
2301         p_publ_timing->dtpr0.b.tRCD = cl;
2302         /*
2303          * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2304          *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2305          *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2306          *
2307          */
2308         tmp = ((DDR3_tRRD*nMHz+999)/1000);
2309         if(tmp < 4)
2310         {
2311             tmp = 4;
2312         }
2313         p_pctl_timing->trrd = (tmp&0xF);
2314         p_publ_timing->dtpr0.b.tRRD = tmp;
2315         p_noc_activate->b.Rrd = tmp;
2316         /*
2317          * tRTP, max(4 tCK,7.5ns)
2318          */
2319         tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2320         if(tmp < 4)
2321         {
2322             tmp = 4;
2323         }
2324         p_pctl_timing->trtp = tmp&0xF;
2325         p_publ_timing->dtpr0.b.tRTP = tmp;
2326         /*
2327          * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2328          */
2329         p_noc_timing->b.RdToMiss = (tmp+cl+cl-(bl>>1));
2330         /*
2331          * tWR, 15ns
2332          */
2333         tmp = ((DDR3_tWR*nMHz+999)/1000);
2334         p_pctl_timing->twr = tmp&0x1F;
2335         if(tmp<9)
2336         {
2337             tmp = tmp - 4;
2338         }
2339         else
2340         {
2341             tmp += (tmp&0x1) ? 1:0;
2342             tmp = tmp>>1;
2343         }
2344         bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2345         p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2346
2347         /*
2348          * tWTR, max(4 tCK,7.5ns)
2349          */
2350         tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2351         if(tmp < 4)
2352         {
2353             tmp = 4;
2354         }
2355         p_pctl_timing->twtr = tmp&0xF;
2356         p_publ_timing->dtpr0.b.tWTR = tmp;
2357         /*
2358          * WrToRd=WL+tWTR
2359          */
2360         p_noc_timing->b.WrToRd = (tmp+cwl);
2361         /*
2362          * tXP, max(3 tCK, 7.5ns)(<933MHz)
2363          */
2364         tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2365         if(tmp < 3)
2366         {
2367             tmp = 3;
2368         }
2369         p_pctl_timing->txp = tmp&0x7;
2370         /*
2371          * tXPDLL, max(10 tCK,24ns)
2372          */
2373         tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2374         if(tmp < 10)
2375         {
2376             tmp = 10;
2377         }
2378         p_pctl_timing->txpdll = tmp & 0x3F;
2379         p_publ_timing->dtpr2.b.tXP = tmp;
2380         /*
2381          * tZQCS, max(64 tCK, 80ns)
2382          */
2383         tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2384         if(tmp < 64)
2385         {
2386             tmp = 64;
2387         }
2388         p_pctl_timing->tzqcs = tmp&0x7F;
2389         /*
2390          * tZQCSI,
2391          */
2392         p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2393         /*
2394          * tDQS,
2395          */
2396         p_pctl_timing->tdqs = DDR3_tDQS;
2397         /*
2398          * tCKSRE, max(5 tCK, 10ns)
2399          */
2400         tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2401         if(tmp < 5)
2402         {
2403             tmp = 5;
2404         }
2405         p_pctl_timing->tcksre = tmp & 0x1F;
2406         /*
2407          * tCKSRX, max(5 tCK, 10ns)
2408          */
2409         p_pctl_timing->tcksrx = tmp & 0x1F;
2410         /*
2411          * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2412          */
2413         if(nMHz>=533)
2414         {
2415             tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2416         }
2417         else
2418         {
2419             tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2420         }
2421         if(tmp < 3)
2422         {
2423             tmp = 3;
2424         }
2425         p_pctl_timing->tcke = tmp & 0x7;
2426         /*
2427          * tCKESR, =tCKE + 1tCK
2428          */
2429         p_pctl_timing->tckesr = (tmp+1)&0xF;
2430         p_publ_timing->dtpr2.b.tCKE = tmp+1;
2431         /*
2432          * tMOD, max(12 tCK,15ns)
2433          */
2434         tmp = ((DDR3_tMOD*nMHz+999)/1000);
2435         if(tmp < 12)
2436         {
2437             tmp = 12;
2438         }
2439         p_pctl_timing->tmod = tmp&0x1F;
2440         p_publ_timing->dtpr1.b.tMOD = (tmp-12);
2441         /*
2442          * tRSTL, 100ns
2443          */
2444         p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2445         /*
2446          * tZQCL, max(256 tCK, 320ns)
2447          */
2448         tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2449         if(tmp < 256)
2450         {
2451             tmp = 256;
2452         }
2453         p_pctl_timing->tzqcl = tmp&0x3FF;
2454         /*
2455          * tMRR, 0 tCK
2456          */
2457         p_pctl_timing->tmrr = 0;
2458         /*
2459          * tDPD, 0
2460          */
2461         p_pctl_timing->tdpd = 0;
2462
2463         /**************************************************
2464          * PHY Timing
2465          **************************************************/
2466         /*
2467          * tCCD, BL/2 for DDR2 and 4 for DDR3
2468          */
2469         p_publ_timing->dtpr0.b.tCCD = 0;
2470         /*
2471          * tDQSCKmax,5.5ns
2472          */
2473         p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2474         /*
2475          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2476          *         1:ODT may not be turned on until one clock after the read post-amble
2477          */
2478         p_publ_timing->dtpr1.b.tRTODT = 1;
2479         /*
2480          * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page)   50ns(533MHz 2KB page)
2481          */
2482         tmp = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000);
2483         p_publ_timing->dtpr1.b.tFAW = tmp;
2484         p_noc_activate->b.Fawbank = 1;
2485         p_noc_activate->b.Faw = tmp;
2486         /*
2487          * tAOND_tAOFD
2488          */
2489         p_publ_timing->dtpr1.b.tAOND = 0;
2490         /*
2491          * tDLLK,512 tCK
2492          */
2493         p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2494         /**************************************************
2495          * NOC Timing
2496          **************************************************/
2497         p_noc_timing->b.BurstLen = (bl>>1);
2498     }
2499     else if(mem_type == LPDDR2)
2500     {
2501         #define LPDDR2_tREFI_3_9_us    (39)  //unit 100ns
2502         #define LPDDR2_tREFI_7_8_us    (78)  //unit 100ns
2503         #define LPDDR2_tMRD            (5)   //tCK
2504         #define LPDDR2_tRFC_8Gb        (210)  //ns
2505         #define LPDDR2_tRFC_4Gb        (130)  //ns
2506         #define LPDDR2_tRPpb_4_BANK             (24)  //ns
2507         #define LPDDR2_tRPab_SUB_tRPpb_4_BANK   (0)   //ns
2508         #define LPDDR2_tRPpb_8_BANK             (24)  //ns
2509         #define LPDDR2_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2510         #define LPDDR2_tRTW          (1)   //tCK register min valid value
2511         #define LPDDR2_tRAS          (42)  //ns
2512         #define LPDDR2_tRCD          (24)  //ns
2513         #define LPDDR2_tRRD          (10)  //ns
2514         #define LPDDR2_tRTP          (7)   //ns
2515         #define LPDDR2_tWR           (15)  //ns
2516         #define LPDDR2_tWTR_GREAT_200MHz         (7)  //ns
2517         #define LPDDR2_tWTR_LITTLE_200MHz        (10) //ns
2518         #define LPDDR2_tXP           (7)  //ns
2519         #define LPDDR2_tXPDLL        (0)
2520         #define LPDDR2_tZQCS         (90) //ns
2521         #define LPDDR2_tZQCSI        (0)
2522         #define LPDDR2_tDQS          (1)
2523         #define LPDDR2_tCKSRE        (1)  //tCK
2524         #define LPDDR2_tCKSRX        (2)  //tCK
2525         #define LPDDR2_tCKE          (3)  //tCK
2526         #define LPDDR2_tMOD          (0)
2527         #define LPDDR2_tRSTL         (0)
2528         #define LPDDR2_tZQCL         (360)  //ns
2529         #define LPDDR2_tMRR          (2)    //tCK
2530         #define LPDDR2_tCKESR        (15)   //ns
2531         #define LPDDR2_tDPD_US       (500)  //us
2532         #define LPDDR2_tFAW_GREAT_200MHz    (50)  //ns
2533         #define LPDDR2_tFAW_LITTLE_200MHz   (60)  //ns
2534         #define LPDDR2_tDLLK         (2)  //tCK
2535         #define LPDDR2_tDQSCK_MAX    (3)  //tCK
2536         #define LPDDR2_tDQSCK_MIN    (0)  //tCK
2537         #define LPDDR2_tDQSS         (1)  //tCK
2538
2539         uint32 trp_tmp;
2540         uint32 trcd_tmp;
2541         uint32 tras_tmp;
2542         uint32 trtp_tmp;
2543         uint32 twr_tmp;
2544
2545         al = 0;
2546         bl = 8;
2547         /*     1066 933 800 667 533 400 333
2548          * RL,   8   7   6   5   4   3   3
2549          * WL,   4   4   3   2   2   1   1
2550          */
2551         if(nMHz<=200)
2552         {
2553             cl = 3;
2554             cwl = 1;
2555             p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2556         }
2557         else if(nMHz<=266)
2558         {
2559             cl = 4;
2560             cwl = 2;
2561             p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2562         }
2563         else if(nMHz<=333)
2564         {
2565             cl = 5;
2566             cwl = 2;
2567             p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2568         }
2569         else if(nMHz<=400)
2570         {
2571             cl = 6;
2572             cwl = 3;
2573             p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2574         }
2575         else if(nMHz<=466)
2576         {
2577             cl = 7;
2578             cwl = 4;
2579             p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2580         }
2581         else //(nMHz<=1066)
2582         {
2583             cl = 8;
2584             cwl = 4;
2585             p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2586         }
2587         p_publ_timing->mr[3] = LPDDR2_DS_34;
2588         p_publ_timing->mr[0] = 0;
2589         /**************************************************
2590          * PCTL Timing
2591          **************************************************/
2592         /*
2593          * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2594          */
2595         if(ddr_capability_per_die >= 0x10000000)   // 2Gb
2596         {
2597             p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2598         }
2599         else
2600         {
2601             p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2602         }
2603
2604         /*
2605          * tMRD, (=tMRW), 5 tCK
2606          */
2607         p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2608         p_publ_timing->dtpr0.b.tMRD = 3;
2609         /*
2610          * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2611          */
2612         if(ddr_capability_per_die >= 0x40000000)   // 8Gb
2613         {
2614             p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2615             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000);
2616             /*
2617              * tXSR, max(2tCK,tRFC+10ns)
2618              */
2619             tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
2620         }
2621         else
2622         {
2623             p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2624             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000);
2625             tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
2626         }
2627         if(tmp<2)
2628         {
2629             tmp=2;
2630         }
2631         p_pctl_timing->texsr = tmp&0x3FF;
2632         p_publ_timing->dtpr2.b.tXS = tmp;
2633
2634         /*
2635          * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
2636          */
2637         //if(pPHY_Reg->DCR.b.DDR8BNK)
2638         if(1)
2639         {
2640             trp_tmp = ((LPDDR2_tRPpb_8_BANK*nMHz+999)/1000);
2641             if(trp_tmp<3)
2642             {
2643                 trp_tmp=3;
2644             }
2645             p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
2646         }
2647         else
2648         {
2649             trp_tmp = ((LPDDR2_tRPpb_4_BANK*nMHz+999)/1000);
2650             if(trp_tmp<3)
2651             {
2652                 trp_tmp=3;
2653             }
2654             p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
2655         }
2656         p_publ_timing->dtpr0.b.tRP = trp_tmp;
2657         /*
2658          * tRAS, max(3tCK,42ns)
2659          */
2660         tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
2661         if(tras_tmp<3)
2662         {
2663             tras_tmp=3;
2664         }
2665         p_pctl_timing->tras = (tras_tmp&0x3F);
2666         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
2667
2668         /*
2669          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
2670          */
2671         trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
2672         if(trcd_tmp<3)
2673         {
2674             trcd_tmp=3;
2675         }
2676         p_pctl_timing->trcd = (trcd_tmp&0xF);
2677         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
2678
2679         /*
2680          * tRTP, max(2tCK, 7.5ns)
2681          */
2682         trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2683         if(trtp_tmp<2)
2684         {
2685             trtp_tmp = 2;
2686         }
2687         p_pctl_timing->trtp = trtp_tmp&0xF;
2688         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
2689
2690         /*
2691          * tWR, max(3tCK,15ns)
2692          */
2693         twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
2694         if(twr_tmp<3)
2695         {
2696             twr_tmp=3;
2697         }
2698         p_pctl_timing->twr = twr_tmp&0x1F;
2699         bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2700         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
2701
2702         /*
2703          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2704          */
2705         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
2706         /*
2707          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2708          */
2709         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
2710         /*
2711          * tRC=tRAS+tRP
2712          */
2713         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
2714         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
2715         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
2716
2717         /*
2718          * RdToWr=(cl+2-cwl)
2719          */
2720         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
2721         p_publ_timing->dtpr1.b.tRTW = 0;
2722         p_noc_timing->b.RdToWr = (cl+2-cwl);
2723         p_pctl_timing->tal = al;
2724         p_pctl_timing->tcl = cl;
2725         p_pctl_timing->tcwl = cwl;
2726         /*
2727          * tRRD, max(2tCK,10ns)
2728          */
2729         tmp=((LPDDR2_tRRD*nMHz+999)/1000);
2730         if(tmp<2)
2731         {
2732             tmp=2;
2733         }
2734         p_pctl_timing->trrd = (tmp&0xF);
2735         p_publ_timing->dtpr0.b.tRRD = tmp;
2736         p_noc_activate->b.Rrd = tmp;
2737         /*
2738          * tWTR, max(2tCK, 7.5ns(533-266MHz)  10ns(200-166MHz))
2739          */
2740         if(nMHz > 200)
2741         {
2742             tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2743         }
2744         else
2745         {
2746             tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2747         }
2748         if(tmp<2)
2749         {
2750             tmp=2;
2751         }
2752         p_pctl_timing->twtr = tmp&0xF;
2753         p_publ_timing->dtpr0.b.tWTR = tmp;
2754         /*
2755          * WrToRd=WL+tWTR
2756          */
2757         p_noc_timing->b.WrToRd = (cwl+tmp);
2758         /*
2759          * tXP, max(2tCK,7.5ns)
2760          */
2761         tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
2762         if(tmp<2)
2763         {
2764             tmp=2;
2765         }
2766         p_pctl_timing->txp = tmp&0x7;
2767         p_publ_timing->dtpr2.b.tXP = tmp;
2768         /*
2769          * tXPDLL, 0ns
2770          */
2771         p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2772         /*
2773          * tZQCS, 90ns
2774          */
2775         p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2776         /*
2777          * tZQCSI,
2778          */
2779         //if(pDDR_Reg->MCFG &= lpddr2_s4)
2780         if(1)
2781         {
2782             p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2783         }
2784         else
2785         {
2786             p_pctl_timing->tzqcsi = 0;
2787         }
2788         /*
2789          * tDQS,
2790          */
2791         p_pctl_timing->tdqs = LPDDR2_tDQS;
2792         /*
2793          * tCKSRE, 1 tCK
2794          */
2795         p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2796         /*
2797          * tCKSRX, 2 tCK
2798          */
2799         p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2800         /*
2801          * tCKE, 3 tCK
2802          */
2803         p_pctl_timing->tcke = LPDDR2_tCKE;
2804         p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2805         /*
2806          * tMOD, 0 tCK
2807          */
2808         p_pctl_timing->tmod = LPDDR2_tMOD;
2809         p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2810         /*
2811          * tRSTL, 0 tCK
2812          */
2813         p_pctl_timing->trstl = LPDDR2_tRSTL;
2814         /*
2815          * tZQCL, 360ns
2816          */
2817         p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2818         /*
2819          * tMRR, 2 tCK
2820          */
2821         p_pctl_timing->tmrr = LPDDR2_tMRR;
2822         /*
2823          * tCKESR, max(3tCK,15ns)
2824          */
2825         tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
2826         if(tmp < 3)
2827         {
2828             tmp = 3;
2829         }
2830         p_pctl_timing->tckesr = tmp&0xF;
2831         /*
2832          * tDPD, 500us
2833          */
2834         p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2835
2836         /**************************************************
2837          * PHY Timing
2838          **************************************************/
2839         /*
2840          * tCCD, BL/2 for DDR2 and 4 for DDR3
2841          */
2842         p_publ_timing->dtpr0.b.tCCD = 0;
2843         /*
2844          * tDQSCKmax,5.5ns
2845          */
2846         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2847         /*
2848          * tDQSCKmin,2.5ns
2849          */
2850         p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2851         /*
2852          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2853          *         1:ODT may not be turned on until one clock after the read post-amble
2854          */
2855         p_publ_timing->dtpr1.b.tRTODT = 1;
2856         /*
2857          * tFAW,max(8tCK, 50ns(200-533MHz)  60ns(166MHz))
2858          */
2859         if(nMHz>=200)
2860         {
2861             tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
2862         }
2863         else
2864         {
2865             tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
2866         }
2867         if(tmp<8)
2868         {
2869             tmp=8;
2870         }
2871         p_publ_timing->dtpr1.b.tFAW = tmp;
2872         p_noc_activate->b.Fawbank = 1;
2873         p_noc_activate->b.Faw = tmp;
2874         /*
2875          * tAOND_tAOFD
2876          */
2877         p_publ_timing->dtpr1.b.tAOND = 0;
2878         /*
2879          * tDLLK,0
2880          */
2881         p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2882         /**************************************************
2883          * NOC Timing
2884          **************************************************/
2885         p_noc_timing->b.BurstLen = (bl>>1);
2886     }
2887     else if(mem_type == LPDDR3)
2888     {
2889         #define LPDDR3_tREFI_3_9_us    (39)  //unit 100ns
2890         #define LPDDR3_tMRD            (10)   //tCK
2891         #define LPDDR3_tRFC_8Gb        (210)  //ns
2892         #define LPDDR3_tRFC_4Gb        (130)  //ns
2893         #define LPDDR3_tRPpb_8_BANK             (24)  //ns
2894         #define LPDDR3_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2895         #define LPDDR3_tRTW          (1)   //tCK register min valid value
2896         #define LPDDR3_tRAS          (42)  //ns
2897         #define LPDDR3_tRCD          (24)  //ns
2898         #define LPDDR3_tRRD          (10)  //ns
2899         #define LPDDR3_tRTP          (7)   //ns
2900         #define LPDDR3_tWR           (15)  //ns
2901         #define LPDDR3_tWTR          (7)  //ns
2902         #define LPDDR3_tXP           (7)  //ns
2903         #define LPDDR3_tXPDLL        (0)
2904         #define LPDDR3_tZQCS         (90) //ns
2905         #define LPDDR3_tZQCSI        (0)
2906         #define LPDDR3_tDQS          (1)
2907         #define LPDDR3_tCKSRE        (2)  //tCK
2908         #define LPDDR3_tCKSRX        (2)  //tCK
2909         #define LPDDR3_tCKE          (3)  //tCK
2910         #define LPDDR3_tMOD          (0)
2911         #define LPDDR3_tRSTL         (0)
2912         #define LPDDR3_tZQCL         (360)  //ns
2913         #define LPDDR3_tMRR          (4)    //tCK
2914         #define LPDDR3_tCKESR        (15)   //ns
2915         #define LPDDR3_tDPD_US       (500)   //us
2916         #define LPDDR3_tFAW          (50)  //ns
2917         #define LPDDR3_tDLLK         (2)  //tCK
2918         #define LPDDR3_tDQSCK_MAX    (3)  //tCK
2919         #define LPDDR3_tDQSCK_MIN    (0)  //tCK
2920         #define LPDDR3_tDQSS         (1)  //tCK
2921
2922         uint32 trp_tmp;
2923         uint32 trcd_tmp;
2924         uint32 tras_tmp;
2925         uint32 trtp_tmp;
2926         uint32 twr_tmp;
2927
2928         al = 0;
2929         bl = 8;
2930         /* Only support Write Latency Set A here
2931          *     1066 933 800 733 667 600 533 400 166
2932          * RL,   16  14  12  11  10  9   8   6   3
2933          * WL,   8   8   6   6   6   5   4   3   1
2934          */
2935         if(nMHz<=166)
2936         {
2937             cl = 3;
2938             cwl = 1;
2939             p_publ_timing->mr[2] = LPDDR3_RL3_WL1;
2940         }
2941         else if(nMHz<=400)
2942         {
2943             cl = 6;
2944             cwl = 3;
2945             p_publ_timing->mr[2] = LPDDR3_RL6_WL3;
2946         }
2947         else if(nMHz<=533)
2948         {
2949             cl = 8;
2950             cwl = 4;
2951             p_publ_timing->mr[2] = LPDDR3_RL8_WL4;
2952         }
2953         else if(nMHz<=600)
2954         {
2955             cl = 9;
2956             cwl = 5;
2957             p_publ_timing->mr[2] = LPDDR3_RL9_WL5;
2958         }
2959         else if(nMHz<=667)
2960         {
2961             cl = 10;
2962             cwl = 6;
2963             p_publ_timing->mr[2] = LPDDR3_RL10_WL6;
2964         }
2965         else if(nMHz<=733)
2966         {
2967             cl = 11;
2968             cwl = 6;
2969             p_publ_timing->mr[2] = LPDDR3_RL11_WL6;
2970         }
2971         else if(nMHz<=800)
2972         {
2973             cl = 12;
2974             cwl = 6;
2975             p_publ_timing->mr[2] = LPDDR3_RL12_WL6;
2976         }
2977         else if(nMHz<=933)
2978         {
2979             cl = 14;
2980             cwl = 8;
2981             p_publ_timing->mr[2] = LPDDR3_RL14_WL8;
2982         }
2983         else //(nMHz<=1066)
2984         {
2985             cl = 16;
2986             cwl = 8;
2987             p_publ_timing->mr[2] = LPDDR3_RL16_WL8;
2988         }
2989         p_publ_timing->mr[3] = LPDDR3_DS_34;
2990         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2991         {
2992             p_publ_timing->mr11 = LPDDR3_ODT_DIS;
2993         }
2994         else
2995         {
2996             p_publ_timing->mr11 = LPDDR3_ODT_240;
2997         }
2998         p_publ_timing->mr[0] = 0;
2999         /**************************************************
3000          * PCTL Timing
3001          **************************************************/
3002         /*
3003          * tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb)
3004          */
3005         p_pctl_timing->trefi = LPDDR3_tREFI_3_9_us;
3006
3007         /*
3008          * tMRD, (=tMRW), 10 tCK
3009          */
3010         p_pctl_timing->tmrd = LPDDR3_tMRD & 0x7;
3011         p_publ_timing->dtpr0.b.tMRD = 3;  //max value
3012         /*
3013          * tRFC, 130ns(4Gb) 210ns(>4Gb)
3014          */
3015         if(ddr_capability_per_die > 0x20000000)   // >4Gb
3016         {
3017             p_pctl_timing->trfc = (LPDDR3_tRFC_8Gb*nMHz+999)/1000;
3018             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_8Gb*nMHz+999)/1000);
3019             /*
3020              * tXSR, max(2tCK,tRFC+10ns)
3021              */
3022             tmp=(((LPDDR3_tRFC_8Gb+10)*nMHz+999)/1000);
3023         }
3024         else
3025         {
3026             p_pctl_timing->trfc = (LPDDR3_tRFC_4Gb*nMHz+999)/1000;
3027             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_4Gb*nMHz+999)/1000);
3028             tmp=(((LPDDR3_tRFC_4Gb+10)*nMHz+999)/1000);
3029         }
3030         if(tmp<2)
3031         {
3032             tmp=2;
3033         }
3034         p_pctl_timing->texsr = tmp&0x3FF;
3035         p_publ_timing->dtpr2.b.tXS = tmp;
3036
3037         /*
3038          * tRP, max(3tCK, 18ns(Fast) 21ns(Typ) 27ns(Slow))
3039          */
3040         //if(pPHY_Reg->DCR.b.DDR8BNK)
3041         if(1)
3042         {
3043             trp_tmp = ((LPDDR3_tRPpb_8_BANK*nMHz+999)/1000);
3044             if(trp_tmp<3)
3045             {
3046                 trp_tmp=3;
3047             }
3048             p_pctl_timing->trp = ((((LPDDR3_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
3049         }
3050         p_publ_timing->dtpr0.b.tRP = trp_tmp;
3051         /*
3052          * tRAS, max(3tCK,42ns)
3053          */
3054         tras_tmp=((LPDDR3_tRAS*nMHz+999)/1000);
3055         if(tras_tmp<3)
3056         {
3057             tras_tmp=3;
3058         }
3059         p_pctl_timing->tras = (tras_tmp&0x3F);
3060         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
3061
3062         /*
3063          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
3064          */
3065         trcd_tmp = ((LPDDR3_tRCD*nMHz+999)/1000);
3066         if(trcd_tmp<3)
3067         {
3068             trcd_tmp=3;
3069         }
3070         p_pctl_timing->trcd = (trcd_tmp&0xF);
3071         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
3072
3073         /*
3074          * tRTP, max(4tCK, 7.5ns)
3075          */
3076         trtp_tmp = ((LPDDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
3077         if(trtp_tmp<4)
3078         {
3079             trtp_tmp = 4;
3080         }
3081         p_pctl_timing->trtp = trtp_tmp&0xF;
3082         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
3083
3084         /*
3085          * tWR, max(4tCK,15ns)
3086          */
3087         twr_tmp=((LPDDR3_tWR*nMHz+999)/1000);
3088         if(twr_tmp<4)
3089         {
3090             twr_tmp=4;
3091         }
3092         p_pctl_timing->twr = twr_tmp&0x1F;
3093         bl_tmp = LPDDR3_BL8;
3094         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
3095
3096         /*
3097          * WrToMiss=WL*tCK + tWR + tRP + tRCD
3098          */
3099         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
3100         /*
3101          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
3102          */
3103         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
3104         /*
3105          * tRC=tRAS+tRP
3106          */
3107         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
3108         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
3109         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
3110
3111         /*
3112          * RdToWr=(cl+2-cwl)
3113          */
3114         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
3115         p_publ_timing->dtpr1.b.tRTW = 0;
3116         p_noc_timing->b.RdToWr = (cl+2-cwl);
3117         p_pctl_timing->tal = al;
3118         p_pctl_timing->tcl = cl;
3119         p_pctl_timing->tcwl = cwl;
3120         /*
3121          * tRRD, max(2tCK,10ns)
3122          */
3123         tmp=((LPDDR3_tRRD*nMHz+999)/1000);
3124         if(tmp<2)
3125         {
3126             tmp=2;
3127         }
3128         p_pctl_timing->trrd = (tmp&0xF);
3129         p_publ_timing->dtpr0.b.tRRD = tmp;
3130         p_noc_activate->b.Rrd = tmp;
3131         /*
3132          * tWTR, max(4tCK, 7.5ns)
3133          */
3134         tmp=((LPDDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
3135         if(tmp<4)
3136         {
3137             tmp=4;
3138         }
3139         p_pctl_timing->twtr = tmp&0xF;
3140         p_publ_timing->dtpr0.b.tWTR = tmp;
3141         /*
3142          * WrToRd=WL+tWTR
3143          */
3144         p_noc_timing->b.WrToRd = (cwl+tmp);
3145         /*
3146          * tXP, max(3tCK,7.5ns)
3147          */
3148         tmp=((LPDDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
3149         if(tmp<3)
3150         {
3151             tmp=3;
3152         }
3153         p_pctl_timing->txp = tmp&0x7;
3154         p_publ_timing->dtpr2.b.tXP = tmp;
3155         /*
3156          * tXPDLL, 0ns
3157          */
3158         p_pctl_timing->txpdll = LPDDR3_tXPDLL;
3159         /*
3160          * tZQCS, 90ns
3161          */
3162         p_pctl_timing->tzqcs = ((LPDDR3_tZQCS*nMHz+999)/1000)&0x7F;
3163         /*
3164          * tZQCSI,
3165          */
3166         p_pctl_timing->tzqcsi = LPDDR3_tZQCSI;
3167         /*
3168          * tDQS,
3169          */
3170         p_pctl_timing->tdqs = LPDDR3_tDQS;
3171         /*
3172          * tCKSRE=tCPDED, 2 tCK
3173          */
3174         p_pctl_timing->tcksre = LPDDR3_tCKSRE;
3175         /*
3176          * tCKSRX, 2 tCK
3177          */
3178         p_pctl_timing->tcksrx = LPDDR3_tCKSRX;
3179         /*
3180          * tCKE, (max 7.5ns,3 tCK)
3181          */
3182         tmp=((7*nMHz+(nMHz>>1)+999)/1000);
3183         if(tmp<LPDDR3_tCKE)
3184         {
3185             tmp=LPDDR3_tCKE;
3186         }
3187         p_pctl_timing->tcke = tmp;
3188         p_publ_timing->dtpr2.b.tCKE = tmp;
3189         /*
3190          * tMOD, 0 tCK
3191          */
3192         p_pctl_timing->tmod = LPDDR3_tMOD;
3193         p_publ_timing->dtpr1.b.tMOD = LPDDR3_tMOD;
3194         /*
3195          * tRSTL, 0 tCK
3196          */
3197         p_pctl_timing->trstl = LPDDR3_tRSTL;
3198         /*
3199          * tZQCL, 360ns
3200          */
3201         p_pctl_timing->tzqcl = ((LPDDR3_tZQCL*nMHz+999)/1000)&0x3FF;
3202         /*
3203          * tMRR, 4 tCK
3204          */
3205         p_pctl_timing->tmrr = LPDDR3_tMRR;
3206         /*
3207          * tCKESR, max(3tCK,15ns)
3208          */
3209         tmp = ((LPDDR3_tCKESR*nMHz+999)/1000);
3210         if(tmp < 3)
3211         {
3212             tmp = 3;
3213         }
3214         p_pctl_timing->tckesr = tmp&0xF;
3215         /*
3216          * tDPD, 500us
3217          */
3218         p_pctl_timing->tdpd = LPDDR3_tDPD_US;
3219
3220         /**************************************************
3221          * PHY Timing
3222          **************************************************/
3223         /*
3224          * tCCD, BL/2 for DDR2 and 4 for DDR3
3225          */
3226         p_publ_timing->dtpr0.b.tCCD = 0;
3227         /*
3228          * tDQSCKmax,5.5ns
3229          */
3230         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR3_tDQSCK_MAX;
3231         /*
3232          * tDQSCKmin,2.5ns
3233          */
3234         p_publ_timing->dtpr1.b.tDQSCK = LPDDR3_tDQSCK_MIN;
3235         /*
3236          * tRTODT, 0:ODT may be turned on immediately after read post-amble
3237          *         1:ODT may not be turned on until one clock after the read post-amble
3238          */
3239         p_publ_timing->dtpr1.b.tRTODT = 1;
3240         /*
3241          * tFAW,max(8tCK, 50ns)
3242          */
3243         tmp=((LPDDR3_tFAW*nMHz+999)/1000);
3244         if(tmp<8)
3245         {
3246             tmp=8;
3247         }
3248         p_publ_timing->dtpr1.b.tFAW = tmp;
3249         p_noc_activate->b.Fawbank = 1;
3250         p_noc_activate->b.Faw = tmp;
3251         /*
3252          * tAOND_tAOFD
3253          */
3254         p_publ_timing->dtpr1.b.tAOND = 0;
3255         /*
3256          * tDLLK,0
3257          */
3258         p_publ_timing->dtpr2.b.tDLLK = LPDDR3_tDLLK;
3259         /**************************************************
3260          * NOC Timing
3261          **************************************************/
3262         p_noc_timing->b.BurstLen = (bl>>1);
3263     }
3264
3265 out:
3266     return ret;
3267 }
3268
3269 static uint32 __sramfunc ddr_update_timing(uint32 ch)
3270 {
3271     uint32 i,bl_tmp=0;
3272     PCTL_TIMING_T *p_pctl_timing=&(DATA(ddr_reg).pctl.pctl_timing);
3273     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3274     NOC_TIMING_T  *p_noc_timing=&(DATA(ddr_reg).noc[0].ddrtiming);
3275     NOC_ACTIVATE_T  *p_noc_activate=&(DATA(ddr_reg).noc[0].activate);
3276     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3277     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3278     pMSCH_REG     pMSCH_Reg= DATA(ddr_ch[ch]).pMSCH_Reg;
3279
3280     FUNC(ddr_copy)((uint64_t *)&(pDDR_Reg->TOGCNT1U), (uint64_t*)&(p_pctl_timing->togcnt1u), 17);
3281     pPHY_Reg->DTPR[0] = p_publ_timing->dtpr0.d32;
3282     pPHY_Reg->DTPR[1] = p_publ_timing->dtpr1.d32;
3283     pPHY_Reg->DTPR[2] = p_publ_timing->dtpr2.d32;
3284     pMSCH_Reg->ddrtiming.d32 = (pMSCH_Reg->ddrtiming.b.BwRatio) | p_noc_timing->d32;
3285     pMSCH_Reg->activate.d32 = p_noc_activate->d32;
3286     // Update PCTL BL
3287     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3288     {
3289         bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3290         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
3291         if(DATA(ddr_freq) <= DDR3_DDR2_DLL_DISABLE_FREQ)
3292         {
3293             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-3;
3294         }
3295         else
3296         {
3297             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-2;
3298         }
3299         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL-1;
3300     }
3301     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3302     {
3303         if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
3304         {
3305             bl_tmp = mddr_lpddr2_bl_8;
3306         }
3307         else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3308         {
3309             bl_tmp = mddr_lpddr2_bl_4;
3310         }
3311         else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
3312         {
3313             bl_tmp = mddr_lpddr2_bl_16;
3314         }
3315         if((DATA(ddr_freq)>=200)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3316         {
3317             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3318         }
3319         else
3320         {
3321             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
3322         }
3323         i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
3324         pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8);  //tDQSCKmax-tDQSCK
3325         pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-1;
3326         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL;
3327     }
3328
3329     return 0;
3330 }
3331
3332 static uint32 __sramfunc ddr_update_mr(uint32 ch)
3333 {
3334     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3335     uint32         cs,dll_off;
3336     pDDRPHY_REG_T  pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3337
3338     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3339     dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
3340     FUNC(ddr_copy)((uint64_t *)&(pPHY_Reg->MR[0]), (uint64_t*)&(p_publ_timing->mr[0]), 2);
3341     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3342     {
3343         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
3344         if(DATA(ddr_freq)>DDR3_DDR2_DLL_DISABLE_FREQ)
3345         {
3346             if(dll_off)  // off -> on
3347             {
3348                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));  //DLL enable
3349                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET));  //DLL reset
3350                 ddr_delayus(1);  //at least 200 DDR cycle
3351                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3352             }
3353             else // on -> on
3354             {
3355                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
3356                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3357             }
3358         }
3359         else
3360         {
3361             pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3362             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));  //DLL disable
3363             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3364         }
3365     }
3366     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3367     {
3368         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
3369         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
3370         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
3371         if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3372         {
3373             ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(11) | lpddr2_op((p_publ_timing->mr11)));
3374         }
3375     }
3376     else //mDDR
3377     {
3378         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3379         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
3380     }
3381     return 0;
3382 }
3383
3384 static void __sramfunc ddr_update_odt(uint32 ch)
3385 {
3386     uint32        cs,tmp;
3387     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3388     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3389
3390     //adjust DRV and ODT
3391     if((DATA(ddr_ch[ch]).mem_type == DDR3) || (DATA(ddr_ch[ch]).mem_type == LPDDR3))
3392     {
3393         if(DATA(ddr_freq) <= DDR3_DDR2_ODT_DISABLE_FREQ)
3394         {
3395             pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3396             pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3397             if(!(pDDR_Reg->PPCFG & 1))
3398             {
3399                 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3400                 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3401             }
3402         }
3403         else
3404         {
3405             pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9);  //dynamic RTT enable
3406             pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
3407             if(!(pDDR_Reg->PPCFG & 1))
3408             {
3409                 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
3410                 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
3411             }
3412         }
3413     }
3414     else
3415     {
3416         pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3417         pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3418         if(!(pDDR_Reg->PPCFG & 1))
3419         {
3420             pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3421             pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3422         }
3423     }
3424     if(DATA(ddr_ch[ch]).mem_type == LPDDR2)
3425     {
3426         tmp = GET_LPDDR2_DS_ODT();  //DS=34ohm,ODT=171ohm
3427     }
3428     else if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3429     {
3430         tmp = GET_LPDDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3431     }
3432     else
3433     {
3434         tmp = GET_DDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3435     }
3436     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3437     if(cs > 1)
3438     {
3439         pPHY_Reg->ZQ1CR[0] = tmp;
3440         dsb();
3441     }
3442     pPHY_Reg->ZQ0CR[0] = tmp;
3443     dsb();
3444 }
3445
3446 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
3447 {
3448     uint32 ch;
3449     pDDR_REG_T    pDDR_Reg;
3450     pDDRPHY_REG_T pPHY_Reg;
3451
3452     for(ch=0;ch<CH_MAX;ch++)
3453     {
3454         pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3455         pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3456
3457         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3458         {
3459             ddr_move_to_Lowpower_state(ch);
3460             pDDR_Reg->TZQCSI = 0;
3461         }
3462     }
3463 }
3464
3465 #if defined(CONFIG_ARCH_RK3066B)
3466 static __sramdata uint32 data8_dqstr[25][4];
3467 static __sramdata uint32 min_ddr_freq,dqstr_flag=false;
3468
3469 int ddr_get_datatraing_value_3168(bool end_flag,uint32 dqstr_value,uint32 min_freq)
3470 {
3471     if(end_flag == true)
3472     {
3473         dqstr_flag = true;    //complete learn data training value flag
3474         min_ddr_freq = min_freq;
3475         return 0;
3476     }
3477
3478     data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3479     data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3480     data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3481     data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3482
3483     ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3484         clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3485         data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3486     return 0;
3487 }
3488
3489 static void __sramfunc ddr_set_pll_enter_3168(uint32 freq_slew)
3490 {
3491     uint32 value_1u,value_100n;
3492     ddr_move_to_Config_state();
3493
3494     if(freq_slew == 1)
3495     {
3496         value_100n = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3497         value_1u = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3498         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3499         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3500         ddr_update_timing();
3501         ddr_update_mr();
3502         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = value_100n;
3503         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = value_1u;
3504     }
3505     else
3506     {
3507         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3508         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3509     }
3510
3511     pDDR_Reg->TZQCSI = 0;
3512     ddr_move_to_Lowpower_state();
3513
3514     ddr_set_dll_bypass(0);  //dll bypass
3515     SET_DDRPHY_CLKGATE(ch,1);  //disable DDR PHY clock
3516     dsb();
3517 }
3518
3519 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32 dqstr_value)
3520 {
3521     SET_DDRPHY_CLKGATE(ch,0);  //enable DDR PHY clock
3522     dsb();
3523     ddr_set_dll_bypass(DATA(ddr_freq));
3524     ddr_reset_dll();
3525
3526     if(dqstr_flag==true)
3527     {
3528         pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3529         pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3530         pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3531         pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3532     }
3533
3534     ddr_update_odt();
3535     ddr_move_to_Config_state();
3536     if(freq_slew == 1)
3537     {
3538         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3539         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3540         pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl.pctl_timing.tzqcsi;
3541     }
3542     else
3543     {
3544         ddr_update_timing();
3545         ddr_update_mr();
3546     }
3547     ddr_data_training();
3548     ddr_move_to_Access_state();
3549 }
3550 #endif
3551
3552 static void __sramfunc ddr_chb_update_timing_odt(void)
3553 {
3554     ddr_set_dll_bypass(1,0); //always use dll bypass
3555     ddr_update_timing(1);
3556     ddr_update_odt(1);
3557 }
3558
3559 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3560 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew,uint32 dqstr_value)
3561 {
3562     uint32 n,ch;
3563     uint32 cs[CH_MAX];
3564
3565     /** 2. ddr enter self-refresh mode or precharge power-down mode */
3566     idle_port();
3567 #if defined(CONFIG_ARCH_RK3066B)
3568     ddr_set_pll_enter_3168(freq_slew);
3569 #else
3570     ddr_selfrefresh_enter(freq);
3571 #endif
3572
3573     /** 3. change frequence  */
3574     FUNC(ddr_set_pll)(freq,1);
3575     DATA(ddr_freq) = freq;
3576
3577     /** 5. Issues a Mode Exit command   */
3578 #if defined(CONFIG_ARCH_RK3066B)
3579     ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3580 #else
3581     //ddr_selfrefresh_exit();
3582     if(DATA(ddr_ch[1]).mem_type != DRAM_MAX)
3583     {
3584         ddr_chb_update_timing_odt();
3585     }
3586     ddr_set_dll_bypass(0,0); //always use dll bypass
3587     ddr_update_timing(0);
3588     ddr_update_odt(0);
3589     FUNC(ddr_set_pll)(freq,2);
3590     for(ch=0;ch<CH_MAX;ch++)
3591     {
3592         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3593         {
3594             ddr_set_dll_bypass(ch,DATA(ddr_freq));
3595             ddr_reset_dll(ch);
3596             //ddr_delayus(10);   //wait DLL lock
3597
3598             ddr_move_to_Config_state(ch);
3599             ddr_update_mr(ch);
3600             cs[ch] = ddr_data_training_trigger(ch);
3601         }
3602     }
3603     for(ch=0;ch<CH_MAX;ch++)
3604     {
3605         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3606         {
3607             n = ddr_data_training(ch,cs[ch]);
3608             ddr_move_to_Access_state(ch);
3609             if(n!=0)
3610             {
3611                 sram_printascii("DTT failed!\n");
3612             }
3613         }
3614     }
3615 #endif
3616     deidle_port();
3617     dsb();
3618 }
3619
3620 struct ddr_change_freq_sram_param {
3621     uint32 arm_freq;
3622     uint32 freq;
3623     uint32 freq_slew;
3624     uint32 dqstr_value;
3625 };
3626
3627 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
3628 {
3629     struct ddr_change_freq_sram_param *param = arg;
3630     loops_per_us = LPJ_100MHZ * param->arm_freq / 1000000;
3631     /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3632     ddr_SRE_2_SRX(param->freq, param->freq_slew, param->dqstr_value);
3633 }
3634 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
3635
3636 static int dclk_div;
3637 static noinline uint32 ddr_change_freq_sram(void *arg)
3638 {
3639     uint32 freq;
3640     uint32 freq_slew=0;
3641     uint32 dqstr_value=0;
3642     unsigned long flags;
3643     struct ddr_change_freq_sram_param param;
3644     volatile uint32 n;
3645     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3646     uint32 i;
3647     uint32 gpllvaluel;
3648     uint32 nMHz=*(uint32 *)arg;
3649     struct ddr_freq_t *p_ddr_freq_t=(struct ddr_freq_t *)((uint32)arg + 4);
3650
3651
3652 #if defined(CONFIG_ARCH_RK3066B)
3653     if(dqstr_flag==true)
3654     {
3655         dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
3656         freq_slew = (nMHz>ddr_freq)? 1 : 0;
3657     }
3658 #endif
3659
3660     dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(29)) >> 8) & 0xff;
3661
3662     param.arm_freq = ddr_get_pll_freq(APLL);
3663     gpllvaluel = ddr_get_pll_freq(GPLL);
3664     if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3665     {
3666         if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3667         {
3668             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 4;
3669         }
3670         else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3671         {
3672             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 2;
3673         }
3674         else        //200-400MHz  /1:200MHz-400MHz
3675         {
3676             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 1;
3677         }
3678     }
3679     else
3680     {
3681         ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3682     }
3683     freq=p_ddr_set_pll(nMHz,0);
3684
3685     ddr_get_parameter(freq);
3686
3687     /** 1. Make sure there is no host access */
3688     local_irq_save(flags);
3689     local_fiq_disable();
3690     flush_tlb_all();
3691     isb();
3692
3693 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3694     if(p_ddr_freq_t->screen_ft_us > 0)
3695     {
3696         p_ddr_freq_t->t1 = cpu_clock(0);
3697         p_ddr_freq_t->t2 = (uint32)(p_ddr_freq_t->t1 - p_ddr_freq_t->t0);   //ns
3698
3699         //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
3700         if( (p_ddr_freq_t->t2 > p_ddr_freq_t->screen_ft_us*1000) && (p_ddr_freq_t->screen_ft_us != 0xfefefefe))
3701         {
3702             freq = 0;
3703             goto end;
3704         }
3705         else
3706         {
3707             rk_fb_poll_wait_frame_complete();
3708         }
3709     }
3710 #endif
3711     for(i=0;i<SRAM_SIZE/4096;i++)
3712     {
3713         n=temp[1024*i];
3714         barrier();
3715     }
3716
3717     for(i=0;i<CH_MAX;i++)
3718     {
3719         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3720         {
3721             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3722             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3723             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3724         }
3725     }
3726     n= pCRU_Reg->CRU_PLL_CON[0][0];
3727     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3728     n= READ_GRF_REG();
3729     dsb();
3730
3731     param.freq = freq;
3732     param.freq_slew = freq_slew;
3733     param.dqstr_value = dqstr_value;
3734     cru_writel(0 |CRU_W_MSK_SETBITS(0xff,8,0xff), RK3288_CRU_CLKSELS_CON(29));
3735     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
3736                     &param,
3737                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
3738     cru_writel(0 |CRU_W_MSK_SETBITS(dclk_div,8,0xff), RK3288_CRU_CLKSELS_CON(29));
3739 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3740 end:
3741 #endif
3742     local_fiq_enable();
3743     local_irq_restore(flags);
3744     return freq;
3745 }
3746
3747 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
3748 static uint32 ddr_change_freq_gpll_dpll(uint32 nMHz)
3749 {
3750     uint32 gpll_freq,gpll_div;
3751     struct ddr_freq_t ddr_freq_t;
3752     ddr_freq_t.screen_ft_us = 0;
3753
3754     if(true == ddr_rk3188_dpll_is_good)
3755     {
3756         gpllvaluel = ddr_get_pll_freq(GPLL);
3757
3758         if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3759         {
3760             gpll_div = (gpllvaluel+nMHz-1)/nMHz;
3761             if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3762             {
3763                 gpll_freq = gpllvaluel/4;
3764                 gpll_div = 4;
3765             }
3766             else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3767             {
3768                 gpll_freq = gpllvaluel/2;
3769                 gpll_div = 2;
3770             }
3771             else        //200-400MHz  /1:200MHz-400MHz
3772             {
3773                 gpll_freq = gpllvaluel;
3774                 gpll_div = 1;
3775             }
3776
3777             *p_ddr_select_gpll_div=gpll_div;    //select GPLL
3778             ddr_change_freq_sram(gpll_freq,ddr_freq_t);
3779             *p_ddr_select_gpll_div=0;
3780
3781             p_ddr_set_pll(nMHz,0); //count DPLL
3782             p_ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3783         }
3784         else
3785         {
3786             ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3787         }
3788     }
3789
3790     return ddr_change_freq_sram(nMHz,ddr_freq_t);
3791
3792 }
3793 #endif
3794
3795 bool DEFINE_PIE_DATA(cpu_pause[NR_CPUS]);
3796 volatile bool *DATA(p_cpu_pause);
3797 static inline bool is_cpu0_paused(unsigned int cpu) { smp_rmb(); return DATA(cpu_pause)[0]; }
3798 static inline void set_cpuX_paused(unsigned int cpu, bool pause) { DATA(cpu_pause)[cpu] = pause; smp_wmb(); }
3799 static inline bool is_cpuX_paused(unsigned int cpu) { smp_rmb(); return DATA(p_cpu_pause)[cpu]; }
3800 static inline void set_cpu0_paused(bool pause) { DATA(p_cpu_pause)[0] = pause; smp_wmb();}
3801
3802 #define MAX_TIMEOUT (16000000UL << 6) //>0.64s
3803
3804 /* Do not use stack, safe on SMP */
3805 void PIE_FUNC(_pause_cpu)(void *arg)
3806 {
3807     unsigned int cpu = (unsigned int)arg;
3808
3809     set_cpuX_paused(cpu, true);
3810     while (is_cpu0_paused(cpu));
3811     set_cpuX_paused(cpu, false);
3812 }
3813
3814 static void pause_cpu(void *info)
3815 {
3816     unsigned int cpu = raw_smp_processor_id();
3817
3818     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(_pause_cpu)),
3819             (void *)cpu,
3820             rockchip_sram_stack-(cpu-1)*PAUSE_CPU_STACK_SIZE);
3821 }
3822
3823 static void wait_cpu(void *info)
3824 {
3825 }
3826
3827 static int call_with_single_cpu(u32 (*fn)(void *arg), void *arg)
3828 {
3829     u32 timeout = MAX_TIMEOUT;
3830     unsigned int cpu;
3831     unsigned int this_cpu = smp_processor_id();
3832     int ret = 0;
3833
3834     cpu_maps_update_begin();
3835     local_bh_disable();
3836     set_cpu0_paused(true);
3837     smp_call_function((smp_call_func_t)pause_cpu, NULL, 0);
3838
3839     for_each_online_cpu(cpu) {
3840         if (cpu == this_cpu)
3841             continue;
3842         while (!is_cpuX_paused(cpu) && --timeout);
3843         if (timeout == 0) {
3844             pr_err("pause cpu %d timeout\n", cpu);
3845             goto out;
3846         }
3847     }
3848
3849     ret = fn(arg);
3850
3851 out:
3852     set_cpu0_paused(false);
3853     local_bh_enable();
3854     smp_call_function(wait_cpu, NULL, true);
3855     cpu_maps_update_done();
3856
3857     return ret;
3858 }
3859
3860 void PIE_FUNC(ddr_adjust_config)(void *arg)
3861 {
3862     uint32 value[CH_MAX];
3863     uint32 ch;
3864     pDDR_REG_T    pDDR_Reg;
3865     pDDRPHY_REG_T pPHY_Reg;
3866
3867     for(ch=0;ch<CH_MAX;ch++)
3868     {
3869         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3870         {
3871             value[ch] = ((uint32 *)arg)[ch];
3872             pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3873             pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3874
3875             //enter config state
3876             ddr_move_to_Config_state(ch);
3877
3878             //set data training address
3879             pPHY_Reg->DTAR = value[ch];
3880
3881             //set auto power down idle
3882             pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
3883
3884             //CKDV=00
3885             pPHY_Reg->PGCR &= ~(0x3<<12);
3886
3887             //enable the hardware low-power interface
3888             pDDR_Reg->SCFG.b.hw_low_power_en = 1;
3889
3890             if(pDDR_Reg->PPCFG & 1)
3891             {
3892                 pPHY_Reg->DATX8[2].DXGCR &= ~(1);          //disable byte
3893                 pPHY_Reg->DATX8[3].DXGCR &= ~(1);
3894                 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;  //disable DLL
3895                 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
3896             }
3897
3898             ddr_update_odt(ch);
3899
3900             //enter access state
3901             ddr_move_to_Access_state(ch);
3902         }
3903     }
3904 }
3905 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
3906
3907 static uint32 _ddr_adjust_config(void *dtar)
3908 {
3909     uint32 i;
3910     unsigned long flags;
3911     volatile uint32 n;
3912     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3913
3914      /** 1. Make sure there is no host access */
3915     local_irq_save(flags);
3916     local_fiq_disable();
3917     flush_tlb_all();
3918     isb();
3919
3920     for(i=0;i<SRAM_SIZE/4096;i++)
3921     {
3922         n=temp[1024*i];
3923         barrier();
3924     }
3925     for(i=0;i<CH_MAX;i++)
3926     {
3927         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3928         {
3929             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3930             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3931             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3932         }
3933     }
3934     n= pCRU_Reg->CRU_PLL_CON[0][0];
3935     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3936     n= READ_GRF_REG();
3937     dsb();
3938
3939     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
3940                     (void *)dtar,
3941                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
3942     local_fiq_enable();
3943     local_irq_restore(flags);
3944     return 0;
3945 }
3946
3947 static void ddr_adjust_config(void)
3948 {
3949     uint32 dtar[CH_MAX];
3950     uint32 i;
3951
3952     //get data training address before idle port
3953     ddr_get_datatraing_addr(dtar);
3954
3955     call_with_single_cpu(&_ddr_adjust_config, (void*)dtar);
3956     //_ddr_adjust_config(dtar);
3957     //disable unused channel
3958     for(i=0;i<CH_MAX;i++)
3959     {
3960         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3961         {
3962             //FIXME
3963         }
3964     }
3965 }
3966
3967 static int __ddr_change_freq(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
3968 {
3969     struct {
3970         uint32_t nMHz;
3971         struct ddr_freq_t *p_ddr_freq_t;
3972     }freq;
3973     int ret = 0;
3974
3975     freq.nMHz = nMHz;
3976     freq.p_ddr_freq_t = &ddr_freq_t;
3977     ret = call_with_single_cpu(&ddr_change_freq_sram,
3978                                (void*)&freq);
3979
3980     return ret;
3981 }
3982
3983 static int _ddr_change_freq(uint32 nMHz)
3984 {
3985         struct ddr_freq_t ddr_freq_t;
3986         int test_count=0;
3987
3988         ddr_freq_t.screen_ft_us = 0;
3989         ddr_freq_t.t0 = 0;
3990         ddr_freq_t.t1 = 0;
3991 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3992         do
3993         {
3994                 if(rk_fb_poll_wait_frame_complete() == true)
3995                 {
3996                         ddr_freq_t.t0 = cpu_clock(0);
3997                         ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
3998
3999                         test_count++;
4000                         if(test_count > 10) //test 10 times
4001                         {
4002                                 ddr_freq_t.screen_ft_us = 0xfefefefe;
4003                         }
4004                         usleep_range(ddr_freq_t.screen_ft_us-test_count*1000,ddr_freq_t.screen_ft_us-test_count*1000);
4005
4006                         flush_tlb_all();
4007                 }
4008         }while(__ddr_change_freq(nMHz, ddr_freq_t)==0);
4009 #else
4010         return __ddr_change_freq(nMHz, ddr_freq_t);
4011 #endif
4012 }
4013
4014 static long _ddr_round_rate(uint32 nMHz)
4015 {
4016         return p_ddr_set_pll(nMHz, 0);
4017 }
4018
4019 static void _ddr_set_auto_self_refresh(bool en)
4020 {
4021     //set auto self-refresh idle
4022     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
4023 }
4024
4025 #define PERI_ACLK_DIV_MASK 0x1f
4026 #define PERI_ACLK_DIV_OFF 0
4027
4028 #define PERI_HCLK_DIV_MASK 0x3
4029 #define PERI_HCLK_DIV_OFF 8
4030
4031 #define PERI_PCLK_DIV_MASK 0x3
4032 #define PERI_PCLK_DIV_OFF 12
4033 static __sramdata u32 cru_sel32_sram;
4034 static void __sramfunc ddr_suspend(void)
4035 {
4036 #if 0
4037     u32 i;
4038     volatile u32 n;
4039     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
4040     int pll_id;
4041
4042         pll_id=GET_DDR_PLL_SRC();
4043     /** 1. Make sure there is no host access */
4044     flush_cache_all();
4045     outer_flush_all();
4046     //flush_tlb_all();
4047
4048     for(i=0;i<SRAM_SIZE/4096;i++)
4049     {
4050         n=temp[1024*i];
4051         barrier();
4052     }
4053
4054     n= pDDR_Reg->SCFG.d32;
4055     n= pPHY_Reg->RIDR;
4056     n= pCRU_Reg->CRU_PLL_CON[0][0];
4057     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
4058     n= *(volatile uint32_t *)SysSrv_DdrConf;
4059     n= READ_GRF_REG();
4060     dsb();
4061
4062     ddr_selfrefresh_enter(0);
4063
4064     SET_PLL_MODE(pll_id, 0);   //PLL slow-mode
4065     dsb();
4066     ddr_delayus(1);
4067     SET_PLL_PD(pll_id, 1);         //PLL power-down
4068     dsb();
4069     ddr_delayus(1);
4070     if(pll_id==GPLL)
4071     {
4072         cru_sel32_sram=   pCRU_Reg->CRU_CLKSEL_CON[10];
4073
4074         pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
4075                                    | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
4076                                    |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
4077     }
4078     pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29)));  //CKOE
4079 #endif
4080 }
4081
4082 static void __sramfunc ddr_resume(void)
4083 {
4084 #if 0
4085     int delay=1000;
4086     int pll_id;
4087
4088     pll_id=GET_DDR_PLL_SRC();
4089         pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29));  //CKOE
4090         dsb();
4091
4092         if(pll_id==GPLL)
4093         pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
4094
4095     SET_PLL_PD(pll_id, 0);         //PLL no power-down
4096     dsb();
4097     while (delay > 0)
4098     {
4099         if (GET_DPLL_LOCK_STATUS())
4100             break;
4101         ddr_delayus(1);
4102         delay--;
4103     }
4104
4105     SET_PLL_MODE(pll_id, 1);   //PLL normal
4106     dsb();
4107
4108     ddr_selfrefresh_exit();
4109 #endif
4110 }
4111
4112 //pArg:Ö¸ÕëÄÚÈÝ±íÊ¾pll pd or not¡£
4113 void ddr_reg_save(uint32 *pArg)
4114 {
4115     uint32        ch;
4116     pDDR_REG_T    pDDR_Reg=NULL;
4117     pDDRPHY_REG_T pPHY_Reg=NULL;
4118     pMSCH_REG     pMSCH_Reg;
4119
4120     p_ddr_reg->tag = 0x56313031;
4121     if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4122     {
4123         p_ddr_reg->pctlAddr[0] = RK3288_DDR_PCTL0_PHYS;
4124         p_ddr_reg->publAddr[0] = RK3288_DDR_PUBL0_PHYS;
4125         p_ddr_reg->nocAddr[0] = RK3288_SERVICE_BUS_PHYS;
4126         pDDR_Reg = p_ddr_ch[0]->pDDR_Reg;
4127         pPHY_Reg = p_ddr_ch[0]->pPHY_Reg;
4128     }
4129     else
4130     {
4131         p_ddr_reg->pctlAddr[0] = 0xFFFFFFFF;
4132         p_ddr_reg->publAddr[0] = 0xFFFFFFFF;
4133         p_ddr_reg->nocAddr[0] = 0xFFFFFFFF;
4134     }
4135     if(p_ddr_ch[1]->mem_type != DRAM_MAX)
4136     {
4137         p_ddr_reg->pctlAddr[1] = RK3288_DDR_PCTL1_PHYS;
4138         p_ddr_reg->publAddr[1] = RK3288_DDR_PUBL1_PHYS;
4139         p_ddr_reg->nocAddr[1] = RK3288_SERVICE_BUS_PHYS+0x80;
4140         if((pDDR_Reg == NULL) || (pPHY_Reg == NULL))
4141         {
4142             pDDR_Reg = p_ddr_ch[1]->pDDR_Reg;
4143             pPHY_Reg = p_ddr_ch[1]->pPHY_Reg;
4144         }
4145     }
4146     else
4147     {
4148         p_ddr_reg->pctlAddr[1] = 0xFFFFFFFF;
4149         p_ddr_reg->publAddr[1] = 0xFFFFFFFF;
4150         p_ddr_reg->nocAddr[1] = 0xFFFFFFFF;
4151     }
4152
4153     //PCTLR
4154     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->pctl.pctl_timing.togcnt1u), (uint64_t *)&(pDDR_Reg->TOGCNT1U), 17);
4155     p_ddr_reg->pctl.SCFG = pDDR_Reg->SCFG.d32;
4156     p_ddr_reg->pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
4157     p_ddr_reg->pctl.MCFG1 = pDDR_Reg->MCFG1;
4158     p_ddr_reg->pctl.MCFG = pDDR_Reg->MCFG;
4159     p_ddr_reg->pctl.pctl_timing.ddrFreq = *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
4160     p_ddr_reg->pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
4161     p_ddr_reg->pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
4162     p_ddr_reg->pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
4163     p_ddr_reg->pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
4164     p_ddr_reg->pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
4165     p_ddr_reg->pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
4166     p_ddr_reg->pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
4167     p_ddr_reg->pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
4168     p_ddr_reg->pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
4169     p_ddr_reg->pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
4170     p_ddr_reg->pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
4171     p_ddr_reg->pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
4172     p_ddr_reg->pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
4173     p_ddr_reg->pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
4174     p_ddr_reg->pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
4175
4176     p_ddr_reg->pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
4177     p_ddr_reg->pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
4178     p_ddr_reg->pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
4179     p_ddr_reg->pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
4180     p_ddr_reg->pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
4181     p_ddr_reg->pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
4182     p_ddr_reg->pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
4183     p_ddr_reg->pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
4184     p_ddr_reg->pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
4185
4186     //PUBL
4187     p_ddr_reg->publ.phy_timing.dtpr0.d32 = pPHY_Reg->DTPR[0];
4188     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->publ.phy_timing.dtpr1), (uint64_t *)&(pPHY_Reg->DTPR[1]), 3);
4189     p_ddr_reg->publ.PIR = pPHY_Reg->PIR;
4190     p_ddr_reg->publ.PGCR = pPHY_Reg->PGCR;
4191     p_ddr_reg->publ.DLLGCR = pPHY_Reg->DLLGCR;
4192     p_ddr_reg->publ.ACDLLCR = pPHY_Reg->ACDLLCR;
4193     p_ddr_reg->publ.PTR[0] = pPHY_Reg->PTR[0];
4194     p_ddr_reg->publ.PTR[1] = pPHY_Reg->PTR[1];
4195     p_ddr_reg->publ.PTR[2] = pPHY_Reg->PTR[2];
4196     p_ddr_reg->publ.ACIOCR = pPHY_Reg->ACIOCR;
4197     p_ddr_reg->publ.DXCCR = pPHY_Reg->DXCCR;
4198     p_ddr_reg->publ.DSGCR = pPHY_Reg->DSGCR;
4199     p_ddr_reg->publ.DCR = pPHY_Reg->DCR.d32;
4200     p_ddr_reg->publ.ODTCR = pPHY_Reg->ODTCR;
4201     p_ddr_reg->publ.DTAR = pPHY_Reg->DTAR;
4202     p_ddr_reg->publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
4203     p_ddr_reg->publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
4204
4205     for(ch=0;ch<CH_MAX;ch++)
4206     {
4207         if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4208         {
4209             pPHY_Reg = p_ddr_ch[ch]->pPHY_Reg;
4210             p_ddr_reg->dqs[ch].DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
4211             p_ddr_reg->dqs[ch].DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
4212             p_ddr_reg->dqs[ch].DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
4213             p_ddr_reg->dqs[ch].DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
4214
4215             p_ddr_reg->dqs[ch].DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
4216             p_ddr_reg->dqs[ch].DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
4217             p_ddr_reg->dqs[ch].DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
4218             p_ddr_reg->dqs[ch].DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
4219
4220             p_ddr_reg->dqs[ch].DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
4221             p_ddr_reg->dqs[ch].DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
4222             p_ddr_reg->dqs[ch].DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
4223             p_ddr_reg->dqs[ch].DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
4224
4225             p_ddr_reg->dqs[ch].DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
4226             p_ddr_reg->dqs[ch].DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
4227             p_ddr_reg->dqs[ch].DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
4228             p_ddr_reg->dqs[ch].DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
4229
4230             //NOC
4231             pMSCH_Reg= p_ddr_ch[ch]->pMSCH_Reg;
4232             p_ddr_reg->noc[ch].ddrconf = pMSCH_Reg->ddrconf;
4233             p_ddr_reg->noc[ch].ddrtiming.d32 = pMSCH_Reg->ddrtiming.d32;
4234             p_ddr_reg->noc[ch].ddrmode = pMSCH_Reg->ddrmode;
4235             p_ddr_reg->noc[ch].readlatency = pMSCH_Reg->readlatency;
4236             p_ddr_reg->noc[ch].activate.d32 = pMSCH_Reg->activate.d32;
4237             p_ddr_reg->noc[ch].devtodev = pMSCH_Reg->devtodev;
4238         }
4239     }
4240
4241     //PLLPD
4242     p_ddr_reg->pllpdAddr = (uint32_t)pArg;  //pll power-down tag addr
4243     p_ddr_reg->pllpdMask = 1;
4244     p_ddr_reg->pllpdVal = 1;
4245
4246     //DPLL
4247     p_ddr_reg->dpllmodeAddr = RK3288_CRU_PHYS + 0x50;  //APCRU_MODE_CON
4248     p_ddr_reg->dpllSlowMode = ((3<<4)<<16) | (0<<4);
4249     p_ddr_reg->dpllNormalMode = ((3<<4)<<16) | (1<<4);
4250     p_ddr_reg->dpllResetAddr = RK3288_CRU_PHYS + 0x1c; //APCRU_DPLL_CON3
4251     p_ddr_reg->dpllReset = (((0x1<<5)<<16) | (0x1<<5));
4252     p_ddr_reg->dpllDeReset = (((0x1<<5)<<16) | (0x0<<5));
4253     p_ddr_reg->dpllConAddr = RK3288_CRU_PHYS + 0x10;   //APCRU_DPLL_CON0
4254     p_ddr_reg->dpllCon[0] = pCRU_Reg->CRU_PLL_CON[DPLL][0] | (0xFFFF<<16);
4255     p_ddr_reg->dpllCon[1] = pCRU_Reg->CRU_PLL_CON[DPLL][1] | (0xFFFF<<16);
4256     p_ddr_reg->dpllCon[2] = pCRU_Reg->CRU_PLL_CON[DPLL][2] | (0xFFFF<<16);
4257     p_ddr_reg->dpllCon[3] = pCRU_Reg->CRU_PLL_CON[DPLL][3] | (0xFFFF<<16);
4258     p_ddr_reg->dpllLockAddr = RK3288_GRF_PHYS + 0x284;  //GRF_SOC_STATUS1
4259     p_ddr_reg->dpllLockMask = (1<<5);
4260     p_ddr_reg->dpllLockVal = (1<<5);
4261
4262     //SET_DDR_PLL_SRC
4263     p_ddr_reg->ddrPllSrcDivAddr = RK3288_CRU_PHYS + 0xc8;
4264     p_ddr_reg->ddrPllSrcDiv = (pCRU_Reg->CRU_CLKSEL_CON[26] & 0x7) | (0x7<<16);
4265
4266     p_ddr_reg->retenDisAddr = RK3288_PMU_PHYS+0x18;  //pmu_pwrmode_con
4267     p_ddr_reg->retenDisVal = (3<<21);  //OR operation
4268     p_ddr_reg->retenStAddr = RK3288_PMU_PHYS+0x1c;  //pmu_pwrmode_con
4269     p_ddr_reg->retenStMask = (1<<6);
4270     p_ddr_reg->retenStVal = (0<<6);
4271
4272     p_ddr_reg->grfRegCnt = 3;
4273     //DDR_16BIT,DDR_HW_WAKEUP,DDR_TYPE
4274     p_ddr_reg->grf[0].addr = RK3288_GRF_PHYS + 0x244;
4275     p_ddr_reg->grf[0].val = (pGRF_Reg->GRF_SOC_CON[0] & ((0x3<<8)|(0x3<<5)|(0x3<<3))) | (((0x3<<8)|(0x3<<5)|(0x3<<3))<<16);
4276
4277     //LPDDR_TYPE
4278     p_ddr_reg->grf[1].addr = RK3288_GRF_PHYS + 0x24c;
4279     p_ddr_reg->grf[1].val = (pGRF_Reg->GRF_SOC_CON[2] & (0x3f<<8)) | ((0x3f<<8)<<16);
4280
4281     //STRIDE
4282     p_ddr_reg->grf[2].addr = RK3288_SGRF_PHYS + 0x8;
4283     p_ddr_reg->grf[2].val = READ_DDR_STRIDE() | (0x1F<<16);
4284
4285     p_ddr_reg->endTag = 0xFFFFFFFF;
4286 }
4287
4288 __attribute__((aligned(4)))   uint32 ddr_reg_resume[]=
4289 {
4290 #include "ddr_reg_resume.inc"
4291 };
4292
4293 char * ddr_get_resume_code_info(u32 *size)
4294 {
4295     *size=sizeof(ddr_reg_resume);
4296
4297     return (char *)ddr_reg_resume;
4298
4299 }
4300 EXPORT_SYMBOL(ddr_get_resume_code_info);
4301
4302 char * ddr_get_resume_data_info(u32 *size)
4303 {
4304     *size=sizeof(DATA(ddr_reg));
4305     return (char *) kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4306 }
4307 EXPORT_SYMBOL(ddr_get_resume_data_info);
4308
4309
4310 static int ddr_init(uint32 dram_speed_bin, uint32 freq)
4311 {
4312     uint32 tmp;
4313     uint32 die=1;
4314     uint32 gsr,dqstr;
4315     struct clk *clk;
4316     uint32 ch,cap=0,cs_cap;
4317
4318     ddr_print("version 1.00 20140603 \n");
4319
4320     p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4321     p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
4322     DATA(p_cpu_pause) = kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
4323
4324     tmp = clk_get_rate(clk_get(NULL, "clk_ddr"))/1000000;
4325     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)) = tmp;
4326     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
4327
4328     for(ch=0;ch<CH_MAX;ch++)
4329     {
4330         p_ddr_ch[ch] = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_ch[ch]));
4331
4332         p_ddr_ch[ch]->chNum = ch;
4333         p_ddr_ch[ch]->pDDR_Reg = pDDR_REG(ch);
4334         p_ddr_ch[ch]->pPHY_Reg = pPHY_REG(ch);
4335         p_ddr_ch[ch]->pMSCH_Reg = pMSCH_REG(ch);
4336
4337         if(!(READ_CH_INFO()&(1<<ch)))
4338         {
4339             p_ddr_ch[ch]->mem_type = DRAM_MAX;
4340             continue;
4341         }
4342         else
4343         {
4344             if(ch)
4345             {
4346                 ddr_print("Channel b: \n");
4347             }
4348             else
4349             {
4350                 ddr_print("Channel a: \n");
4351             }
4352             tmp = p_ddr_ch[ch]->pPHY_Reg->DCR.b.DDRMD;
4353             if((tmp ==  LPDDR2) && (READ_DRAMTYPE_INFO() == 6))
4354             {
4355                 tmp = LPDDR3;
4356             }
4357             switch(tmp)
4358             {
4359                 case DDR3:
4360                     ddr_print("DDR3 Device\n");
4361                     break;
4362                 case LPDDR3:
4363                     ddr_print("LPDDR3 Device\n");
4364                     break;
4365                 case LPDDR2:
4366                     ddr_print("LPDDR2 Device\n");
4367                     break;
4368                 default:
4369                     ddr_print("Unkown Device\n");
4370                     tmp = DRAM_MAX;
4371                     break;
4372             }
4373             p_ddr_ch[ch]->mem_type = tmp;
4374             if(tmp == DRAM_MAX)
4375             {
4376                 p_ddr_ch[ch]->mem_type = DRAM_MAX;
4377                 continue;
4378             }
4379         }
4380
4381         p_ddr_ch[ch]->ddr_speed_bin = dram_speed_bin;
4382         //get capability per chip, not total size, used for calculate tRFC
4383         die = (8<<READ_BW_INFO(ch))/(8<<READ_DIE_BW_INFO(ch));
4384         cap = (1 << (READ_ROW_INFO(ch,0)+READ_COL_INFO(ch)+READ_BK_INFO(ch)+READ_BW_INFO(ch)));
4385         cs_cap = cap;
4386         if(READ_CS_INFO(ch) > 1)
4387         {
4388             cap += cap >> (READ_ROW_INFO(ch,0)-READ_ROW_INFO(ch,1));
4389         }
4390         if(READ_CH_ROW_INFO(ch))
4391         {
4392             cap = cap*3/4;
4393         }
4394         p_ddr_ch[ch]->ddr_capability_per_die = cs_cap/die;
4395         ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
4396                                                                         READ_BW_INFO(ch)*16,\
4397                                                                         READ_COL_INFO(ch), \
4398                                                                         (0x1<<(READ_BK_INFO(ch))), \
4399                                                                         READ_ROW_INFO(ch,0), \
4400                                                                         READ_CS_INFO(ch), \
4401                                                                         (cap>>20));
4402     }
4403
4404     ddr_adjust_config();
4405
4406     clk = clk_get(NULL, "clk_ddr");
4407     if (IS_ERR(clk)) {
4408         ddr_print("failed to get ddr clk\n");
4409         clk = NULL;
4410     }
4411     if(freq != 0)
4412         tmp = clk_set_rate(clk, 1000*1000*freq);
4413     else
4414         tmp = clk_set_rate(clk, clk_get_rate(clk));
4415     ddr_print("init success!!! freq=%luMHz\n", clk ? clk_get_rate(clk)/1000000 : freq);
4416
4417     for(ch=0;ch<CH_MAX;ch++)
4418     {
4419         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
4420         {
4421             if(ch)
4422             {
4423                 ddr_print("Channel b: \n");
4424             }
4425             else
4426             {
4427                 ddr_print("Channel a: \n");
4428             }
4429             for(tmp=0;tmp<4;tmp++)
4430             {
4431                 gsr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXGSR[0];
4432                 dqstr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXDQSTR;
4433                 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=%d,%d, DGSL=%d,%d extra clock, DGPS=%d,%d\n", \
4434                                                                     (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), \
4435                                                                     ((gsr>>13)&0x7), ((gsr>>16)&0x7),\
4436                                                                     (dqstr&0x7), ((dqstr>>3)&0x7),\
4437                                                                     ((((dqstr>>12)&0x3)+1)*90), ((((dqstr>>14)&0x3)+1)*90));
4438             }
4439             ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
4440                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
4441                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
4442                                                         p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]&0x3,\
4443                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
4444                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
4445                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>6)&0x3);
4446             ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
4447             ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
4448         }
4449     }
4450
4451     return 0;
4452 }
4453