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[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-rockchip / ddr_rk3126.c
1 /*
2  * arch/arm/mach-rk2928/ddr.c-- for ddr3&ddr2
3  *
4  * Function Driver for DDR controller
5  *
6  * Copyright (C) 2012 Fuzhou Rockchip Electronics Co.,Ltd
7  * Author:
8  * hcy@rock-chips.com
9  * yk@rock-chips.com
10  * typ@rock-chips.com
11  *
12  * v1.00
13  */
14
15 #include <linux/kernel.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/clk.h>
19
20 #include <asm/cacheflush.h>
21 #include <asm/tlbflush.h>
22 #include <linux/cpu.h>
23 #include <dt-bindings/clock/ddr.h>
24 #include <linux/rockchip/cru.h>
25 #include <linux/rk_fb.h>
26 #include "cpu_axi.h"
27
28 typedef uint32_t uint32;
29
30 #define DDR3_DDR2_DLL_DISABLE_FREQ    (300)     /* ¿ÅÁ£dll disableµÄƵÂÊ*/
31 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)     /*¿ÅÁ£odt disableµÄƵÂÊ*/
32 #define SR_IDLE                       (0x1)     /*unit:32*DDR clk cycle, and 0 for disable auto self-refresh*/
33 #define PD_IDLE                       (0x40)    /*unit:DDR clk cycle, and 0 for disable auto power-down*/
34 #define PHY_ODT_DISABLE_FREQ          (333)     /*¶¨ÒåÖ÷¿Ø¶Ëodt disableµÄƵÂÊ*/
35 #define PHY_DLL_DISABLE_FREQ          (266)     /*¶¨ÒåÖ÷¿Ø¶Ëdll bypassµÄƵÂÊ*/
36
37 #define ddr_print(x...) printk("DDR DEBUG: " x)
38
39 #define SRAM_CODE_OFFSET        rockchip_sram_virt
40 #define SRAM_SIZE               rockchip_sram_size
41
42 #ifdef CONFIG_FB_ROCKCHIP
43 #define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
44 #endif
45
46 /*#define PHY_RX_PHASE_CAL*/
47 #define PHY_DE_SKEW_STEP  (20)
48 /***********************************
49  * DDR3 define
50  ***********************************/
51 /*mr0 for ddr3*/
52 #define DDR3_BL8          (0)
53 #define DDR3_BC4_8        (1)
54 #define DDR3_BC4          (2)
55 #define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
56 #define DDR3_WR(n)        (((n)&0x7)<<9)
57 #define DDR3_DLL_RESET    (1<<8)
58 #define DDR3_DLL_DeRESET  (0<<8)
59
60 /*mr1 for ddr3*/
61 #define DDR3_DLL_ENABLE    (0)
62 #define DDR3_DLL_DISABLE   (1)
63 #define DDR3_MR1_AL(n)  (((n)&0x7)<<3)
64
65 #define DDR3_DS_40            (0)
66 #define DDR3_DS_34            (1<<1)
67 #define DDR3_Rtt_Nom_DIS      (0)
68 #define DDR3_Rtt_Nom_60       (1<<2)
69 #define DDR3_Rtt_Nom_120      (1<<6)
70 #define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
71
72 /*mr2 for ddr3*/
73 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
74 #define DDR3_Rtt_WR_DIS       (0)
75 #define DDR3_Rtt_WR_60        (1<<9)
76 #define DDR3_Rtt_WR_120       (2<<9)
77
78 #define DDR_PLL_REFDIV  (1)
79 #define FBDIV(n)        ((0xFFF<<16) | (n&0xfff))
80 #define REFDIV(n)       ((0x3F<<16) | (n&0x3f))
81 #define POSTDIV1(n)     ((0x7<<(12+16)) | ((n&0x7)<<12))
82 #define POSTDIV2(n)     ((0x7<<(6+16)) | ((n&0x7)<<6))
83
84 #define PLL_LOCK_STATUS  (0x1<<10)
85  /*CRU Registers updated*/
86 typedef volatile struct tagCRU_STRUCT {
87         uint32 CRU_PLL_CON[4][4];
88         uint32 CRU_MODE_CON;
89         uint32 CRU_CLKSEL_CON[35];
90         uint32 CRU_CLKGATE_CON[11];     /*0xd0*/
91         uint32 reserved1;       /*0xfc*/
92         uint32 CRU_GLB_SRST_FST_VALUE;  /*0x100*/
93         uint32 CRU_GLB_SRST_SND_VALUE;
94         uint32 reserved2[2];
95         uint32 CRU_SOFTRST_CON[9];      /*0x110*/
96         uint32 CRU_MISC_CON;    /*0x134*/
97         uint32 reserved3[2];
98         uint32 CRU_GLB_CNT_TH;  /*0x140*/
99         uint32 reserved4[3];
100         uint32 CRU_GLB_RST_ST;  /*0x150*/
101         uint32 reserved5[(0x1c0 - 0x154) / 4];
102         uint32 CRU_SDMMC_CON[2];        /*0x1c0*/
103         uint32 CRU_SDIO_CON[2];
104         uint32 reserved6[2];
105         uint32 CRU_EMMC_CON[2]; /*0x1d8*/
106         uint32 reserved7[(0x1f0 - 0x1e0) / 4];
107         uint32 CRU_PLL_PRG_EN;
108 } CRU_REG, *pCRU_REG;
109
110 typedef struct tagGPIO_LH {
111         uint32 GPIOL;
112         uint32 GPIOH;
113 } GPIO_LH_T;
114
115 typedef struct tagGPIO_IOMUX {
116         uint32 GPIOA_IOMUX;
117         uint32 GPIOB_IOMUX;
118         uint32 GPIOC_IOMUX;
119         uint32 GPIOD_IOMUX;
120 } GPIO_IOMUX_T;
121
122 /********************************
123 *GRF ¼Ä´æÆ÷ÖÐGRF_OS_REG1 ´æddr rank£¬typeµÈÐÅÏ¢
124 *GRF_SOC_CON2¼Ä´æÆ÷ÖпØÖÆc_sysreqÐźÅÏòpctl·¢ËͽøÈëlow power ÇëÇó
125 *GRF_DDRC_STAT ¿É²éѯpctlÊÇ·ñ½ÓÊÜÇëÇó ½øÈëlow power
126 ********************************/
127 /*REG FILE registers*/
128 /*GRF_SOC_STATUS0*/
129 #define sys_pwr_idle     (1<<27)
130 #define gpu_pwr_idle     (1<<26)
131 #define vpu_pwr_idle     (1<<25)
132 #define vio_pwr_idle     (1<<24)
133 #define peri_pwr_idle    (1<<23)
134 #define core_pwr_idle     (1<<22)
135 /*GRF_SOC_CON2*/
136 #define core_pwr_idlereq    (13)
137 #define peri_pwr_idlereq    (12)
138 #define vio_pwr_idlereq     (11)
139 #define vpu_pwr_idlereq     (10)
140 #define gpu_pwr_idlereq     (9)
141 #define sys_pwr_idlereq     (8)
142 #define GRF_DDR_LP_EN     (0x1<<(2+16))
143 #define GRF_DDR_LP_DISB     ((0x1<<(2+16))|(0x1<<2))
144
145 /*grf updated*/
146 typedef volatile struct tagREG_FILE {
147         uint32 reserved0[(0xa8 - 0x0) / 4];
148         GPIO_IOMUX_T GRF_GPIO_IOMUX[4]; /*0x00a8*/
149         uint32 GRF_GPIO2C_IOMUX2;       /*0xe8*/
150         uint32 GRF_CIF_IOMUX[2];
151         uint32 reserved1[(0x100 - 0xf4) / 4];
152         uint32 GRF_GPIO_DS;     /*0x100*/
153         uint32 reserved2[(0x118 - 0x104) / 4];
154         GPIO_LH_T GRF_GPIO_PULL[4];     /*0x118*/
155         uint32 reserved3[1];
156         uint32 GRF_ACODEC_CON;  /*0x13c*/
157         uint32 GRF_SOC_CON[3];  /*0x140*/
158         uint32 GRF_SOC_STATUS0;
159         uint32 GRF_LVDS_CON0;   /*0x150*/
160         uint32 reserved4[(0x15c - 0x154) / 4];
161         uint32 GRF_DMAC_CON[3]; /*0x15c*/
162         uint32 GRF_MAC_CON[2];
163         uint32 GRF_TVE_CON;     /*0x170*/
164         uint32 reserved5[(0x17c - 0x174) / 4];
165         uint32 GRF_UOC0_CON0;   /*0x17c*/
166         uint32 reserved6;
167         uint32 GRF_UOC1_CON[5]; /*0x184*/
168         uint32 reserved7;
169         uint32 GRF_DDRC_STAT;   /*0x19c*/
170         uint32 reserved8;
171         uint32 GRF_SOC_STATUS1; /*0x1a4*/
172         uint32 GRF_CPU_CON[4];
173         uint32 reserved9[(0x1c0 - 0x1b8) / 4];
174         uint32 GRF_CPU_STATUS[2];       /*0x1c0*/
175         uint32 GRF_OS_REG[8];
176         uint32 reserved10[(0x200 - 0x1e8) / 4];
177         uint32 GRF_PVTM_CON[4]; /*0x200*/
178         uint32 GRF_PVTM_STATUS[4];
179         /*uint32 reserved10[(0x220-0x214)/4];*/
180         uint32 GRF_DFI_WRNUM;   /*0X220*/
181         uint32 GRF_DFI_RDNUM;
182         uint32 GRF_DFI_ACTNUM;
183         uint32 GRF_DFI_TIMERVAL;
184         uint32 GRF_NIF_FIFO[4];
185         uint32 reserved11[(0x280 - 0x240) / 4];
186         uint32 GRF_USBPHY0_CON[8];      /*0x280*/
187         uint32 GRF_USBPHY1_CON[8];
188         uint32 GRF_UOC_STATUS0; /*0x2c0*/
189         uint32 reserved12[(0x300 - 0x2c4) / 4];
190         uint32 GRF_CHIP_TAG;
191         uint32 GRF_SDMMC_DET_CNT;
192         uint32 reserved13[(0x37c - 0x308) / 4];
193         uint32 GRF_EFUSE_PRG_EN;
194 } REG_FILE, *pREG_FILE;
195
196 /*SCTL*/
197 #define INIT_STATE                     (0)
198 #define CFG_STATE                      (1)
199 #define GO_STATE                       (2)
200 #define SLEEP_STATE                    (3)
201 #define WAKEUP_STATE                   (4)
202
203 /*STAT*/
204 #define Init_mem                       (0)
205 #define Config                         (1)
206 #define Config_req                     (2)
207 #define Access                         (3)
208 #define Access_req                     (4)
209 #define Low_power                      (5)
210 #define Low_power_entry_req            (6)
211 #define Low_power_exit_req             (7)
212
213 /*MCFG*/
214 #define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
215 #define pd_idle(n)                     ((n)<<8)
216 #define mddr_en                        (2<<22)
217 #define lpddr2_en                      (3<<22)
218 #define ddr2_en                        (0<<5)
219 #define ddr3_en                        (1<<5)
220 #define lpddr2_s2                      (0<<6)
221 #define lpddr2_s4                      (1<<6)
222 #define mddr_lpddr2_bl_2               (0<<20)
223 #define mddr_lpddr2_bl_4               (1<<20)
224 #define mddr_lpddr2_bl_8               (2<<20)
225 #define mddr_lpddr2_bl_16              (3<<20)
226 #define ddr2_ddr3_bl_4                 (0)
227 #define ddr2_ddr3_bl_8                 (1)
228 #define tfaw_cfg(n)                    (((n)-4)<<18)
229 #define pd_exit_slow                   (0<<17)
230 #define pd_exit_fast                   (1<<17)
231 #define pd_type(n)                     ((n)<<16)
232 #define two_t_en(n)                    ((n)<<3)
233 #define bl8int_en(n)                   ((n)<<2)
234 #define cke_or_en(n)                   ((n)<<1)
235
236 /*POWCTL*/
237 #define power_up_start                 (1<<0)
238
239 /*POWSTAT*/
240 #define power_up_done                  (1<<0)
241
242 /*DFISTSTAT0*/
243 #define dfi_init_complete              (1<<0)
244
245 /*CMDTSTAT*/
246 #define cmd_tstat                      (1<<0)
247
248 /*CMDTSTATEN*/
249 #define cmd_tstat_en                   (1<<1)
250
251 /*MCMD*/
252 #define Deselect_cmd                   (0)
253 #define PREA_cmd                       (1)
254 #define REF_cmd                        (2)
255 #define MRS_cmd                        (3)
256 #define ZQCS_cmd                       (4)
257 #define ZQCL_cmd                       (5)
258 #define RSTL_cmd                       (6)
259 #define MRR_cmd                        (8)
260 #define DPDE_cmd                       (9)
261
262 #define lpddr2_op(n)                   ((n)<<12)
263 #define lpddr2_ma(n)                   ((n)<<4)
264
265 #define bank_addr(n)                   ((n)<<17)
266 #define cmd_addr(n)                    ((n)<<4)
267
268 #define start_cmd                      (1u<<31)
269
270 typedef union STAT_Tag {
271         uint32 d32;
272         struct {
273                 unsigned ctl_stat:3;
274                 unsigned reserved3:1;
275                 unsigned lp_trig:3;
276                 unsigned reserved7_31:25;
277         } b;
278 } STAT_T;
279
280 typedef union SCFG_Tag {
281         uint32 d32;
282         struct {
283                 unsigned hw_low_power_en:1;
284                 unsigned reserved1_5:5;
285                 unsigned nfifo_nif1_dis:1;
286                 unsigned reserved7:1;
287                 unsigned bbflags_timing:4;
288                 unsigned reserved12_31:20;
289         } b;
290 } SCFG_T;
291
292 /* DDR Controller register struct */
293 typedef volatile struct DDR_REG_Tag {
294         /*Operational State, Control, and Status Registers*/
295         SCFG_T SCFG;            /*State Configuration Register*/
296         volatile uint32 SCTL;   /*State Control Register*/
297         STAT_T STAT;            /*State Status Register*/
298         volatile uint32 INTRSTAT;       /*Interrupt Status Register*/
299         uint32 reserved0[(0x40 - 0x10) / 4];
300         /*Initailization Control and Status Registers*/
301         volatile uint32 MCMD;   /*Memory Command Register*/
302         volatile uint32 POWCTL; /*Power Up Control Registers*/
303         volatile uint32 POWSTAT;        /*Power Up Status Register*/
304         volatile uint32 CMDTSTAT;       /*Command Timing Status Register*/
305         volatile uint32 CMDTSTATEN;     /*Command Timing Status Enable Register*/
306         uint32 reserved1[(0x60 - 0x54) / 4];
307         volatile uint32 MRRCFG0;        /*MRR Configuration 0 Register*/
308         volatile uint32 MRRSTAT0;       /*MRR Status 0 Register*/
309         volatile uint32 MRRSTAT1;       /*MRR Status 1 Register*/
310         uint32 reserved2[(0x7c - 0x6c) / 4];
311         /*Memory Control and Status Registers*/
312         volatile uint32 MCFG1;  /*Memory Configuration 1 Register*/
313         volatile uint32 MCFG;   /*Memory Configuration Register*/
314         volatile uint32 PPCFG;  /*Partially Populated Memories Configuration Register*/
315         volatile uint32 MSTAT;  /*Memory Status Register*/
316         volatile uint32 LPDDR2ZQCFG;    /*LPDDR2 ZQ Configuration Register*/
317         uint32 reserved3;
318         /*DTU Control and Status Registers*/
319         volatile uint32 DTUPDES;        /*DTU Status Register*/
320         volatile uint32 DTUNA;  /*DTU Number of Random Addresses Created Register*/
321         volatile uint32 DTUNE;  /*DTU Number of Errors Register*/
322         volatile uint32 DTUPRD0;        /*DTU Parallel Read 0*/
323         volatile uint32 DTUPRD1;        /*DTU Parallel Read 1*/
324         volatile uint32 DTUPRD2;        /*DTU Parallel Read 2*/
325         volatile uint32 DTUPRD3;        /*DTU Parallel Read 3*/
326         volatile uint32 DTUAWDT;        /*DTU Address Width*/
327         uint32 reserved4[(0xc0 - 0xb4) / 4];
328         /*Memory Timing Registers*/
329         volatile uint32 TOGCNT1U;       /*Toggle Counter 1U Register*/
330         volatile uint32 TINIT;  /*t_init Timing Register*/
331         volatile uint32 TRSTH;  /*Reset High Time Register*/
332         volatile uint32 TOGCNT100N;     /*Toggle Counter 100N Register*/
333         volatile uint32 TREFI;  /*t_refi Timing Register*/
334         volatile uint32 TMRD;   /*t_mrd Timing Register*/
335         volatile uint32 TRFC;   /*t_rfc Timing Register*/
336         volatile uint32 TRP;    /*t_rp Timing Register*/
337         volatile uint32 TRTW;   /*t_rtw Timing Register*/
338         volatile uint32 TAL;    /*AL Latency Register*/
339         volatile uint32 TCL;    /*CL Timing Register*/
340         volatile uint32 TCWL;   /*CWL Register*/
341         volatile uint32 TRAS;   /*t_ras Timing Register*/
342         volatile uint32 TRC;    /*t_rc Timing Register*/
343         volatile uint32 TRCD;   /*t_rcd Timing Register*/
344         volatile uint32 TRRD;   /*t_rrd Timing Register*/
345         volatile uint32 TRTP;   /*t_rtp Timing Register*/
346         volatile uint32 TWR;    /*t_wr Timing Register*/
347         volatile uint32 TWTR;   /*t_wtr Timing Register*/
348         volatile uint32 TEXSR;  /*t_exsr Timing Register*/
349         volatile uint32 TXP;    /*t_xp Timing Register*/
350         volatile uint32 TXPDLL; /*t_xpdll Timing Register*/
351         volatile uint32 TZQCS;  /*t_zqcs Timing Register*/
352         volatile uint32 TZQCSI; /*t_zqcsi Timing Register*/
353         volatile uint32 TDQS;   /*t_dqs Timing Register*/
354         volatile uint32 TCKSRE; /*t_cksre Timing Register*/
355         volatile uint32 TCKSRX; /*t_cksrx Timing Register*/
356         volatile uint32 TCKE;   /*t_cke Timing Register*/
357         volatile uint32 TMOD;   /*t_mod Timing Register*/
358         volatile uint32 TRSTL;  /*Reset Low Timing Register*/
359         volatile uint32 TZQCL;  /*t_zqcl Timing Register*/
360         volatile uint32 TMRR;   /*t_mrr Timing Register*/
361         volatile uint32 TCKESR; /*t_ckesr Timing Register*/
362         volatile uint32 TDPD;   /*t_dpd Timing Register*/
363         uint32 reserved5[(0x180 - 0x148) / 4];
364         /*ECC Configuration, Control, and Status Registers*/
365         volatile uint32 ECCCFG; /*ECC Configuration Register*/
366         volatile uint32 ECCTST; /*ECC Test Register*/
367         volatile uint32 ECCCLR; /*ECC Clear Register*/
368         volatile uint32 ECCLOG; /*ECC Log Register*/
369         uint32 reserved6[(0x200 - 0x190) / 4];
370         /*DTU Control and Status Registers*/
371         volatile uint32 DTUWACTL;       /*DTU Write Address Control Register*/
372         volatile uint32 DTURACTL;       /*DTU Read Address Control Register*/
373         volatile uint32 DTUCFG; /*DTU Configuration Control Register*/
374         volatile uint32 DTUECTL;        /*DTU Execute Control Register*/
375         volatile uint32 DTUWD0; /*DTU Write Data 0*/
376         volatile uint32 DTUWD1; /*DTU Write Data 1*/
377         volatile uint32 DTUWD2; /*DTU Write Data 2*/
378         volatile uint32 DTUWD3; /*DTU Write Data 3*/
379         volatile uint32 DTUWDM; /*DTU Write Data Mask*/
380         volatile uint32 DTURD0; /*DTU Read Data 0*/
381         volatile uint32 DTURD1; /*DTU Read Data 1*/
382         volatile uint32 DTURD2; /*DTU Read Data 2*/
383         volatile uint32 DTURD3; /*DTU Read Data 3*/
384         volatile uint32 DTULFSRWD;      /*DTU LFSR Seed for Write Data Generation*/
385         volatile uint32 DTULFSRRD;      /*DTU LFSR Seed for Read Data Generation*/
386         volatile uint32 DTUEAF; /*DTU Error Address FIFO*/
387         /*DFI Control Registers*/
388         volatile uint32 DFITCTRLDELAY;  /*DFI tctrl_delay Register*/
389         volatile uint32 DFIODTCFG;      /*DFI ODT Configuration Register*/
390         volatile uint32 DFIODTCFG1;     /*DFI ODT Configuration 1 Register*/
391         volatile uint32 DFIODTRANKMAP;  /*DFI ODT Rank Mapping Register*/
392         /*DFI Write Data Registers*/
393         volatile uint32 DFITPHYWRDATA;  /*DFI tphy_wrdata Register*/
394         volatile uint32 DFITPHYWRLAT;   /*DFI tphy_wrlat Register*/
395         uint32 reserved7[(0x260 - 0x258) / 4];
396         volatile uint32 DFITRDDATAEN;   /*DFI trddata_en Register*/
397         volatile uint32 DFITPHYRDLAT;   /*DFI tphy_rddata Register*/
398         uint32 reserved8[(0x270 - 0x268) / 4];
399         /*DFI Update Registers*/
400         volatile uint32 DFITPHYUPDTYPE0;        /*DFI tphyupd_type0 Register*/
401         volatile uint32 DFITPHYUPDTYPE1;        /*DFI tphyupd_type1 Register*/
402         volatile uint32 DFITPHYUPDTYPE2;        /*DFI tphyupd_type2 Register*/
403         volatile uint32 DFITPHYUPDTYPE3;        /*DFI tphyupd_type3 Register*/
404         volatile uint32 DFITCTRLUPDMIN; /*DFI tctrlupd_min Register*/
405         volatile uint32 DFITCTRLUPDMAX; /*DFI tctrlupd_max Register*/
406         volatile uint32 DFITCTRLUPDDLY; /*DFI tctrlupd_dly Register*/
407         uint32 reserved9;
408         volatile uint32 DFIUPDCFG;      /*DFI Update Configuration Register*/
409         volatile uint32 DFITREFMSKI;    /*DFI Masked Refresh Interval Register*/
410         volatile uint32 DFITCTRLUPDI;   /*DFI tctrlupd_interval Register*/
411         uint32 reserved10[(0x2ac - 0x29c) / 4];
412         volatile uint32 DFITRCFG0;      /*DFI Training Configuration 0 Register*/
413         volatile uint32 DFITRSTAT0;     /*DFI Training Status 0 Register*/
414         volatile uint32 DFITRWRLVLEN;   /*DFI Training dfi_wrlvl_en Register*/
415         volatile uint32 DFITRRDLVLEN;   /*DFI Training dfi_rdlvl_en Register*/
416         volatile uint32 DFITRRDLVLGATEEN;       /*DFI Training dfi_rdlvl_gate_en Register*/
417         /*DFI Status Registers*/
418         volatile uint32 DFISTSTAT0;     /*DFI Status Status 0 Register*/
419         volatile uint32 DFISTCFG0;      /*DFI Status Configuration 0 Register*/
420         volatile uint32 DFISTCFG1;      /*DFI Status configuration 1 Register*/
421         uint32 reserved11;
422         volatile uint32 DFITDRAMCLKEN;  /*DFI tdram_clk_enalbe Register*/
423         volatile uint32 DFITDRAMCLKDIS; /*DFI tdram_clk_disalbe Register*/
424         volatile uint32 DFISTCFG2;      /*DFI Status configuration 2 Register*/
425         volatile uint32 DFISTPARCLR;    /*DFI Status Parity Clear Register*/
426         volatile uint32 DFISTPARLOG;    /*DFI Status Parity Log Register*/
427         uint32 reserved12[(0x2f0 - 0x2e4) / 4];
428         /*DFI Low Power Registers*/
429         volatile uint32 DFILPCFG0;      /*DFI Low Power Configuration 0 Register*/
430         uint32 reserved13[(0x300 - 0x2f4) / 4];
431         /*DFI Training 2 Registers*/
432         volatile uint32 DFITRWRLVLRESP0;        /*DFI Training dif_wrlvl_resp Status 0 Register*/
433         volatile uint32 DFITRWRLVLRESP1;        /*DFI Training dif_wrlvl_resp Status 1 Register*/
434         volatile uint32 DFITRWRLVLRESP2;        /*DFI Training dif_wrlvl_resp Status 2 Register*/
435         volatile uint32 DFITRRDLVLRESP0;        /*DFI Training dif_rdlvl_resp Status 0 Register*/
436         volatile uint32 DFITRRDLVLRESP1;        /*DFI Training dif_rdlvl_resp Status 1 Register*/
437         volatile uint32 DFITRRDLVLRESP2;        /*DFI Training dif_rdlvl_resp Status 2 Register*/
438         volatile uint32 DFITRWRLVLDELAY0;       /*DFI Training dif_wrlvl_delay Configuration 0 Register*/
439         volatile uint32 DFITRWRLVLDELAY1;       /*DFI Training dif_wrlvl_delay Configuration 1 Register*/
440         volatile uint32 DFITRWRLVLDELAY2;       /*DFI Training dif_wrlvl_delay Configuration 2 Register*/
441         volatile uint32 DFITRRDLVLDELAY0;       /*DFI Training dif_rdlvl_delay Configuration 0 Register*/
442         volatile uint32 DFITRRDLVLDELAY1;       /*DFI Training dif_rdlvl_delay Configuration 1 Register*/
443         volatile uint32 DFITRRDLVLDELAY2;       /*DFI Training dif_rdlvl_delay Configuration 2 Register*/
444         volatile uint32 DFITRRDLVLGATEDELAY0;   /*DFI Training dif_rdlvl_gate_delay Configuration 0 Register*/
445         volatile uint32 DFITRRDLVLGATEDELAY1;   /*DFI Training dif_rdlvl_gate_delay Configuration 1 Register*/
446         volatile uint32 DFITRRDLVLGATEDELAY2;   /*DFI Training dif_rdlvl_gate_delay Configuration 2 Register*/
447         volatile uint32 DFITRCMD;       /*DFI Training Command Register*/
448         uint32 reserved14[(0x3f8 - 0x340) / 4];
449         /*IP Status Registers*/
450         volatile uint32 IPVR;   /*IP Version Register*/
451         volatile uint32 IPTR;   /*IP Type Register*/
452 } DDR_REG_T, *pDDR_REG_T;
453
454 /*PHY_REG2*/
455 #define PHY_AUTO_CALIBRATION (1<<0)
456 #define PHY_SW_CALIBRATION   (1<<1)
457 /*PHY_REG1*/
458 #define PHY_DDR2             (1)
459 #define PHY_DDR3             (0)
460 #define PHY_LPDDR2           (2)
461 #define PHY_Burst8           (1<<2)
462
463 #define PHY_RON_DISABLE     (0)
464 #define PHY_RON_309ohm      (1)
465 #define PHY_RON_155ohm      (2)
466 #define PHY_RON_103ohm      (3)
467 #define PHY_RON_77ohm       (4)
468 #define PHY_RON_63ohm       (5)
469 #define PHY_RON_52ohm       (6)
470 #define PHY_RON_45ohm       (7)
471 /*#define PHY_RON_77ohm       (8)*/
472 #define PHY_RON_62ohm       (9)
473 /*#define PHY_RON_52ohm       (10)*/
474 #define PHY_RON_44ohm       (11)
475 #define PHY_RON_39ohm       (12)
476 #define PHY_RON_34ohm       (13)
477 #define PHY_RON_31ohm       (14)
478 #define PHY_RON_28ohm       (15)
479
480 #define PHY_RTT_DISABLE     (0)
481 #define PHY_RTT_816ohm      (1)
482 #define PHY_RTT_431ohm      (2)
483 #define PHY_RTT_287ohm      (3)
484 #define PHY_RTT_216ohm      (4)
485 #define PHY_RTT_172ohm      (5)
486 #define PHY_RTT_145ohm      (6)
487 #define PHY_RTT_124ohm      (7)
488 #define PHY_RTT_215ohm      (8)
489 /*#define PHY_RTT_172ohm      (9)*/
490 #define PHY_RTT_144ohm      (10)
491 #define PHY_RTT_123ohm      (11)
492 #define PHY_RTT_108ohm      (12)
493 #define PHY_RTT_96ohm       (13)
494 #define PHY_RTT_86ohm       (14)
495 #define PHY_RTT_78ohm       (15)
496
497 #define PHY_DRV_ODT_SET(n) ((n<<4)|n)
498
499 /* DDR PHY register struct  updated */
500 typedef volatile struct DDRPHY_REG_Tag {
501         volatile uint32 PHY_REG0;       /*PHY soft reset Register*/
502         volatile uint32 PHY_REG1;       /*phy working mode, burst length*/
503         volatile uint32 PHY_REG2;       /*PHY DQS squelch calibration Register*/
504         volatile uint32 PHY_REG3;       /*channel A read odt delay*/
505         volatile uint32 PHY_REG4;       /*channel B read odt dleay*/
506         uint32 reserved0[(0x2c - 0x14) / 4];
507         volatile uint32 PHY_REGb;       /*cl,al*/
508         volatile uint32 PHY_REGc;       /*CWL set register*/
509         uint32 reserved1[(0x44 - 0x34) / 4];
510         volatile uint32 PHY_REG11;      /*cmd drv*/
511         volatile uint32 PHY_REG12;      /*cmd weak pull up*/
512         volatile uint32 PHY_REG13;      /*cmd dll delay*/
513         volatile uint32 PHY_REG14;      /*CK dll delay*/
514         uint32 reserved2;       /*0x54*/
515         volatile uint32 PHY_REG16;      /*/CK drv*/
516         uint32 reserved3[(0x80 - 0x5c) / 4];
517         volatile uint32 PHY_REG20;      /*left channel a drv*/
518         volatile uint32 PHY_REG21;      /*left channel a odt*/
519         uint32 reserved4[(0x98 - 0x88) / 4];
520         volatile uint32 PHY_REG26;      /*left channel a dq write dll*/
521         volatile uint32 PHY_REG27;      /*left channel a dqs write dll*/
522         volatile uint32 PHY_REG28;      /*left channel a dqs read dll*/
523         uint32 reserved5[(0xc0 - 0xa4) / 4];
524         volatile uint32 PHY_REG30;      /*right channel a drv*/
525         volatile uint32 PHY_REG31;      /*right channel a odt*/
526         uint32 reserved6[(0xd8 - 0xc8) / 4];
527         volatile uint32 PHY_REG36;      /*right channel a dq write dll*/
528         volatile uint32 PHY_REG37;      /*right channel a dqs write dll*/
529         volatile uint32 PHY_REG38;      /*right channel a dqs read dll*/
530         uint32 reserved7[(0x100 - 0xe4) / 4];
531         volatile uint32 PHY_REG40;      /*left channel b drv*/
532         volatile uint32 PHY_REG41;      /*left channel b odt*/
533         uint32 reserved8[(0x118 - 0x108) / 4];
534         volatile uint32 PHY_REG46;      /*left channel b dq write dll*/
535         volatile uint32 PHY_REG47;      /*left channel b dqs write dll*/
536         volatile uint32 PHY_REG48;      /*left channel b dqs read dll*/
537         uint32 reserved9[(0x140 - 0x124) / 4];
538         volatile uint32 PHY_REG50;      /*right channel b drv*/
539         volatile uint32 PHY_REG51;      /*right channel b odt*/
540         uint32 reserved10[(0x158 - 0x148) / 4];
541         volatile uint32 PHY_REG56;      /*right channel b dq write dll*/
542         volatile uint32 PHY_REG57;      /*right channel b dqs write dll*/
543         volatile uint32 PHY_REG58;      /*right channel b dqs read dll*/
544         uint32 reserved11[(0x290 - 0x164) / 4];
545         volatile uint32 PHY_REGDLL;     /*dll bypass switch reg*/
546         uint32 reserved12[(0x2c0 - 0x294) / 4];
547         volatile uint32 PHY_REG_skew[(0x3b0 - 0x2c0) / 4];      /*de-skew*/
548         uint32 reserved13[(0x3e8 - 0x3b0) / 4];
549         volatile uint32 PHY_REGfa;      /*idqs*/
550         volatile uint32 PHY_REGfb;      /* left channel a calibration result*/
551         volatile uint32 PHY_REGfc;      /* right channel a calibration result*/
552         volatile uint32 PHY_REGfd;      /*left channel b calibration result*/
553         volatile uint32 PHY_REGfe;      /* right channel b calibration result*/
554         volatile uint32 PHY_REGff;      /*calibrationg done*/
555 } DDRPHY_REG_T, *pDDRPHY_REG_T;
556
557 #define pCRU_Reg               ((pCRU_REG)RK_CRU_VIRT)
558 #define pGRF_Reg               ((pREG_FILE)RK_GRF_VIRT)
559 #define pDDR_Reg               ((pDDR_REG_T)RK_DDR_VIRT)
560 #define pPHY_Reg               ((pDDRPHY_REG_T)(RK_DDR_VIRT+RK3036_DDR_PCTL_SIZE))
561 #define SysSrv_DdrTiming       (RK_CPU_AXI_BUS_VIRT+0xc)
562 #define READ_CS_INFO()   ((((pGRF_Reg->GRF_OS_REG[1])>>11)&0x1)+1)
563 #define READ_COL_INFO()  (9+(((pGRF_Reg->GRF_OS_REG[1])>>9)&0x3))
564 #define READ_BK_INFO()   (3-(((pGRF_Reg->GRF_OS_REG[1])>>8)&0x1))
565 #define READ_CS0_ROW_INFO()  (13+(((pGRF_Reg->GRF_OS_REG[1])>>6)&0x3))
566 #define READ_CS1_ROW_INFO()  (13+(((pGRF_Reg->GRF_OS_REG[1])>>4)&0x3))
567 #define READ_BW_INFO()   (2>>(((pGRF_Reg->GRF_OS_REG[1])&0xc)>>2))      /*´úÂëÖР0->8bit 1->16bit 2->32bit  ÓëgrfÖж¨ÒåÏà·´*/
568 #define READ_DIE_BW_INFO()   (2>>((pGRF_Reg->GRF_OS_REG[1])&0x3))
569
570 /***********************************
571  * LPDDR2 define
572  ***********************************/
573 /*MR0 (Device Information)*/
574 #define  LPDDR2_DAI    (0x1)    /* 0:DAI complete, 1:DAI still in progress*/
575 #define  LPDDR2_DI     (0x1<<1) /* 0:S2 or S4 SDRAM, 1:NVM*/
576 #define  LPDDR2_DNVI   (0x1<<2) /* 0:DNV not supported, 1:DNV supported*/
577 #define  LPDDR2_RZQI   (0x3<<3) /*00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float*/
578                                     /*10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.*/
579
580 /*MR1 (Device Feature)*/
581 #define LPDDR2_BL4     (0x2)
582 #define LPDDR2_BL8     (0x3)
583 #define LPDDR2_BL16    (0x4)
584 #define LPDDR2_nWR(n)  (((n)-2)<<5)
585
586 /*MR2 (Device Feature 2)*/
587 #define LPDDR2_RL3_WL1  (0x1)
588 #define LPDDR2_RL4_WL2  (0x2)
589 #define LPDDR2_RL5_WL2  (0x3)
590 #define LPDDR2_RL6_WL3  (0x4)
591 #define LPDDR2_RL7_WL4  (0x5)
592 #define LPDDR2_RL8_WL4  (0x6)
593
594 /*MR3 (IO Configuration 1)*/
595 #define LPDDR2_DS_34    (0x1)
596 #define LPDDR2_DS_40    (0x2)
597 #define LPDDR2_DS_48    (0x3)
598 #define LPDDR2_DS_60    (0x4)
599 #define LPDDR2_DS_80    (0x6)
600 #define LPDDR2_DS_120   (0x7)   /*optional*/
601
602 /*MR4 (Device Temperature)*/
603 #define LPDDR2_tREF_MASK (0x7)
604 #define LPDDR2_4_tREF    (0x1)
605 #define LPDDR2_2_tREF    (0x2)
606 #define LPDDR2_1_tREF    (0x3)
607 #define LPDDR2_025_tREF  (0x5)
608 #define LPDDR2_025_tREF_DERATE    (0x6)
609
610 #define LPDDR2_TUF       (0x1<<7)
611
612 /*MR8 (Basic configuration 4)*/
613 #define LPDDR2_S4        (0x0)
614 #define LPDDR2_S2        (0x1)
615 #define LPDDR2_N         (0x2)
616 #define LPDDR2_Density(mr8)  (8<<(((mr8)>>2)&0xf))      /*Unit:MB*/
617 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
618
619 /*MR10 (Calibration)*/
620 #define LPDDR2_ZQINIT   (0xFF)
621 #define LPDDR2_ZQCL     (0xAB)
622 #define LPDDR2_ZQCS     (0x56)
623 #define LPDDR2_ZQRESET  (0xC3)
624
625 /*MR16 (PASR Bank Mask)*/
626 /*S2 SDRAM Only*/
627 #define LPDDR2_PASR_Full (0x0)
628 #define LPDDR2_PASR_1_2  (0x1)
629 #define LPDDR2_PASR_1_4  (0x2)
630 #define LPDDR2_PASR_1_8  (0x3)
631
632 typedef enum PLL_ID_Tag {
633         APLL = 0,
634         DPLL,
635         CPLL,
636         GPLL,
637         PLL_MAX
638 } PLL_ID;
639
640 typedef enum DRAM_TYPE_Tag {
641         LPDDR = 0,
642         DDR,
643         DDR2,
644         DDR3,
645         LPDDR2,
646
647         DRAM_MAX
648 } DRAM_TYPE;
649
650 struct ddr_freq_t {
651         unsigned long screen_ft_us;
652         unsigned long long t0;
653         unsigned long long t1;
654         unsigned long t2;
655 };
656
657 typedef struct PCTRL_TIMING_Tag {
658         uint32 ddrFreq;
659         /*Memory Timing Registers*/
660         uint32 togcnt1u;        /*Toggle Counter 1U Register*/
661         uint32 tinit;           /*t_init Timing Register*/
662         uint32 trsth;           /*Reset High Time Register*/
663         uint32 togcnt100n;      /*Toggle Counter 100N Register*/
664         uint32 trefi;           /*t_refi Timing Register*/
665         uint32 tmrd;            /*t_mrd Timing Register*/
666         uint32 trfc;            /*t_rfc Timing Register*/
667         uint32 trp;                 /*t_rp Timing Register*/
668         uint32 trtw;            /*t_rtw Timing Register*/
669         uint32 tal;                 /*AL Latency Register*/
670         uint32 tcl;                 /*CL Timing Register*/
671         uint32 tcwl;            /*CWL Register*/
672         uint32 tras;            /*t_ras Timing Register*/
673         uint32 trc;                 /*t_rc Timing Register*/
674         uint32 trcd;            /*t_rcd Timing Register*/
675         uint32 trrd;            /*t_rrd Timing Register*/
676         uint32 trtp;            /*t_rtp Timing Register*/
677         uint32 twr;                 /*t_wr Timing Register*/
678         uint32 twtr;            /*t_wtr Timing Register*/
679         uint32 texsr;           /*t_exsr Timing Register*/
680         uint32 txp;                 /*t_xp Timing Register*/
681         uint32 txpdll;          /*t_xpdll Timing Register*/
682         uint32 tzqcs;           /*t_zqcs Timing Register*/
683         uint32 tzqcsi;          /*t_zqcsi Timing Register*/
684         uint32 tdqs;            /*t_dqs Timing Register*/
685         uint32 tcksre;          /*t_cksre Timing Register*/
686         uint32 tcksrx;          /*t_cksrx Timing Register*/
687         uint32 tcke;            /*t_cke Timing Register*/
688         uint32 tmod;            /*t_mod Timing Register*/
689         uint32 trstl;           /*Reset Low Timing Register*/
690         uint32 tzqcl;           /*t_zqcl Timing Register*/
691         uint32 tmrr;            /*t_mrr Timing Register*/
692         uint32 tckesr;          /*t_ckesr Timing Register*/
693         uint32 tdpd;            /*t_dpd Timing Register*/
694 } PCTL_TIMING_T;
695
696 struct ddr_change_freq_sram_param {
697         uint32 freq;
698         uint32 freq_slew;
699 };
700
701 typedef union NOC_TIMING_Tag {
702         uint32 d32;
703         struct {
704                 unsigned ActToAct:6;
705                 unsigned RdToMiss:6;
706                 unsigned WrToMiss:6;
707                 unsigned BurstLen:3;
708                 unsigned RdToWr:5;
709                 unsigned WrToRd:5;
710                 unsigned BwRatio:1;
711         } b;
712 } NOC_TIMING_T;
713
714 typedef struct BACKUP_REG_Tag {
715         PCTL_TIMING_T pctl_timing;
716         NOC_TIMING_T noc_timing;
717         uint32 ddrMR[4];
718         uint32 mem_type;
719         uint32 ddr_speed_bin;
720         uint32 ddr_capability_per_die;
721 } BACKUP_REG_T;
722
723 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
724 static BACKUP_REG_T *p_ddr_reg;
725
726 uint32 DEFINE_PIE_DATA(ddr_freq);
727 static uint32 *p_ddr_freq;
728 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
729 uint32 DEFINE_PIE_DATA(ddr_dll_status); /* ¼Ç¼ddr dllµÄ״̬£¬ÔÚselfrefresh exitʱѡÔñÊÇ·ñ½øÐÐdll reset*/
730
731 uint32_t ddr3_cl_cwl[22][4] = {
732 /*   0~330           330~400         400~533        speed
733 * tCK  >3             2.5~3          1.875~2.5     1.875~1.5
734 *    cl<<16, cwl    cl<<16, cwl     cl<<16, cwl              */
735         {((5 << 16) | 5), ((5 << 16) | 5), 0, 0},       /*DDR3_800D*/
736         {((5 << 16) | 5), ((6 << 16) | 5), 0, 0},       /*DDR3_800E*/
737
738         {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), 0}, /*DDR3_1066E*/
739         {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), 0}, /*DDR3_1066F*/
740         {((5 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), 0}, /*DDR3_1066G*/
741
742         {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)},   /*DDR3_1333F*/
743         {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((8 << 16) | 7)},   /*DDR3_1333G*/
744         {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)},   /*DDR3_1333H*/
745         {((5 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)},  /*DDR3_1333J*/
746
747         {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)},   /*DDR3_1600G*/
748         {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)},   /*DDR3_1600H*/
749         {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)},   /*DDR3_1600J*/
750         {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((10 << 16) | 7)},  /*DDR3_1600K*/
751
752         {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)},   /*DDR3_1866J*/
753         {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((8 << 16) | 7)},   /*DDR3_1866K*/
754         {((6 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)},   /*DDR3_1866L*/
755         {((6 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)},  /*DDR3_1866M*/
756
757         {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)},   /*DDR3_2133K*/
758         {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)},   /*DDR3_2133L*/
759         {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)},   /*DDR3_2133M*/
760         {((6 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)},   /*DDR3_2133N*/
761
762         {((6 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)}   /*DDR3_DEFAULT*/
763 };
764
765 uint32_t ddr3_tRC_tFAW[22] = {
766 /**    tRC    tFAW   */
767         ((50 << 16) | 50),      /*DDR3_800D*/
768         ((53 << 16) | 50),      /*DDR3_800E*/
769
770         ((49 << 16) | 50),      /*DDR3_1066E*/
771         ((51 << 16) | 50),      /*DDR3_1066F*/
772         ((53 << 16) | 50),      /*DDR3_1066G*/
773
774         ((47 << 16) | 45),      /*DDR3_1333F*/
775         ((48 << 16) | 45),      /*DDR3_1333G*/
776         ((50 << 16) | 45),      /*DDR3_1333H*/
777         ((51 << 16) | 45),      /*DDR3_1333J*/
778
779         ((45 << 16) | 40),      /*DDR3_1600G*/
780         ((47 << 16) | 40),      /*DDR3_1600H*/
781         ((48 << 16) | 40),      /*DDR3_1600J*/
782         ((49 << 16) | 40),      /*DDR3_1600K*/
783
784         ((45 << 16) | 35),      /*DDR3_1866J*/
785         ((46 << 16) | 35),      /*DDR3_1866K*/
786         ((47 << 16) | 35),      /*DDR3_1866L*/
787         ((48 << 16) | 35),      /*DDR3_1866M*/
788
789         ((44 << 16) | 35),      /*DDR3_2133K*/
790         ((45 << 16) | 35),      /*DDR3_2133L*/
791         ((46 << 16) | 35),      /*DDR3_2133M*/
792         ((47 << 16) | 35),      /*DDR3_2133N*/
793
794         ((53 << 16) | 50)       /*DDR3_DEFAULT*/
795 };
796
797 /****************************************************************************
798 *Internal sram us delay function
799 *Cpu highest frequency is 1.6 GHz
800 *1 cycle = 1/1.6 ns
801 *1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
802 ******************************************************************************/
803 volatile uint32 DEFINE_PIE_DATA(loops_per_us);
804 #define LPJ_100MHZ  999456UL
805
806 /*----------------------------------------------------------------------
807 *Name   : void __sramlocalfunc ddr_delayus(uint32_t us)
808 *Desc   : ddr ÑÓʱº¯Êý
809 *Params  : uint32_t us  --ÑÓʱʱ¼ä
810 *Return  : void
811 *Notes   : loops_per_us ÎªÈ«¾Ö±äÁ¿ ÐèÒª¸ù¾Ýarm freq¶ø¶¨
812 *----------------------------------------------------------------------*/
813 static void __sramfunc ddr_delayus(uint32 us)
814 {
815         do {
816                 volatile unsigned int i = (DATA(loops_per_us) * us);
817                 if (i < 7)
818                         i = 7;
819                 barrier();
820                 asm volatile (".align 4; 1: subs %0, %0, #1; bne 1b;":"+r" (i));
821         } while (0);
822 }
823
824 /*----------------------------------------------------------------------
825 *Name   : __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
826 *Desc   : ddr ¿½±´¼Ä´æÆ÷º¯Êý
827 *Params  : pDest ->Ä¿±ê¼Ä´æÆ÷Ê×µØÖ·
828 *          pSrc  ->Ô´±ê¼Ä´æÆ÷Ê×µØÖ·
829 *          words ->¿½±´³¤¶È
830 *Return  : void
831 *Notes   :
832 *----------------------------------------------------------------------*/
833
834 static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
835 {
836         uint32 i;
837
838         for (i = 0; i < words; i++) {
839                 pDest[i] = pSrc[i];
840         }
841 }
842
843 /*----------------------------------------------------------------------
844 *Name   : __sramfunc void ddr_move_to_Lowpower_state(void)
845 *Desc   : pctl ½øÈë lowpower state
846 *Params  : void
847 *Return  : void
848 *Notes   :
849 *----------------------------------------------------------------------*/
850 static __sramfunc void ddr_move_to_Lowpower_state(void)
851 {
852         volatile uint32 value;
853
854         while (1) {
855                 value = pDDR_Reg->STAT.b.ctl_stat;
856                 if (value == Low_power) {
857                         break;
858                 }
859                 switch (value) {
860                 case Init_mem:
861                         pDDR_Reg->SCTL = CFG_STATE;
862                         dsb();
863                         while ((pDDR_Reg->STAT.b.ctl_stat) != Config)
864                         ;
865                 case Config:
866                         pDDR_Reg->SCTL = GO_STATE;
867                         dsb();
868                         while ((pDDR_Reg->STAT.b.ctl_stat) != Access)
869                         ;
870                 case Access:
871                         pDDR_Reg->SCTL = SLEEP_STATE;
872                         dsb();
873                         while ((pDDR_Reg->STAT.b.ctl_stat) != Low_power)
874                         ;
875                         break;
876                 default:        /*Transitional state*/
877                         break;
878                 }
879         }
880 }
881
882 /*----------------------------------------------------------------------
883 *Name   : __sramfunc void ddr_move_to_Access_state(void)
884 *Desc   : pctl ½øÈë Access state
885 *Params  : void
886 *Return  : void
887 *Notes   :
888 *----------------------------------------------------------------------*/
889 static __sramfunc void ddr_move_to_Access_state(void)
890 {
891         volatile uint32 value;
892
893         /*set auto self-refresh idle*/
894         pDDR_Reg->MCFG1 =
895             (pDDR_Reg->MCFG1 & 0xffffff00) | DATA(ddr_sr_idle) | (1 << 31);
896         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & 0xffff00ff) | (PD_IDLE << 8);
897         while (1) {
898                 value = pDDR_Reg->STAT.b.ctl_stat;
899                 if ((value == Access)
900                     || ((pDDR_Reg->STAT.b.lp_trig == 1)
901                         && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))) {
902                         break;
903                 }
904                 switch (value) {
905                 case Low_power:
906                         pDDR_Reg->SCTL = WAKEUP_STATE;
907                         dsb();
908                         while ((pDDR_Reg->STAT.b.ctl_stat) != Access)
909                         ;
910                         break;
911                 case Init_mem:
912                         pDDR_Reg->SCTL = CFG_STATE;
913                         dsb();
914                         while ((pDDR_Reg->STAT.b.ctl_stat) != Config)
915                         ;
916                 case Config:
917                         pDDR_Reg->SCTL = GO_STATE;
918                         dsb();
919                         while (!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
920                                  || ((pDDR_Reg->STAT.b.lp_trig == 1)
921                                      && ((pDDR_Reg->STAT.b.ctl_stat) ==
922                                          Low_power))))
923                     ;
924                         break;
925                 default:        /*Transitional state*/
926                         break;
927                 }
928         }
929         pGRF_Reg->GRF_SOC_CON[2] = (1 << 16 | 0);       /*de_hw_wakeup :enable auto sr if sr_idle != 0*/
930 }
931
932 /*----------------------------------------------------------------------
933 *Name   : __sramfunc void ddr_move_to_Config_state(void)
934 *Desc   : pctl ½øÈë config state
935 *Params  : void
936 *Return  : void
937 *Notes   :
938 *----------------------------------------------------------------------*/
939 static __sramfunc void ddr_move_to_Config_state(void)
940 {
941         volatile uint32 value;
942         pGRF_Reg->GRF_SOC_CON[2] = (1 << 16 | 1);       /*hw_wakeup :disable auto sr*/
943         while (1) {
944                 value = pDDR_Reg->STAT.b.ctl_stat;
945                 if (value == Config) {
946                         break;
947                 }
948                 switch (value) {
949                 case Low_power:
950                         pDDR_Reg->SCTL = WAKEUP_STATE;
951                         dsb();
952                 case Access:
953                 case Init_mem:
954                         pDDR_Reg->SCTL = CFG_STATE;
955                         dsb();
956                         break;
957                 default:        /*Transitional state*/
958                         break;
959                 }
960         }
961 }
962
963 /*----------------------------------------------------------------------
964 *Name   : void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
965 *Desc   : Í¨¹ýд pctl MCMD¼Ä´æÆ÷Ïòddr·¢ËÍÃüÁî
966 *Params  : rank ->ddr rank Êý
967 *          cmd  ->·¢ËÍÃüÁîÀàÐÍ
968 *          arg  ->·¢Ë͵ÄÊý¾Ý
969 *Return  : void
970 *Notes   : arg°üÀ¨bank_addrºÍcmd_addr
971 *----------------------------------------------------------------------*/
972 static void __sramfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
973 {
974         pDDR_Reg->MCMD = (start_cmd | (rank << 20) | arg | cmd);
975         dsb();
976         while (pDDR_Reg->MCMD & start_cmd)
977         ;
978 }
979
980 __sramdata uint32 copy_data[8] = {
981      0xffffffff, 0x00000000, 0x55555555, 0xAAAAAAAA,
982         0xEEEEEEEE, 0x11111111, 0x22222222, 0xDDDDDDDD
983 };
984
985  EXPORT_PIE_SYMBOL(copy_data[8]);
986 uint32 *p_copy_data;
987
988 /*----------------------------------------------------------------------
989 Name    : uint32_t __sramlocalfunc ddr_data_training(void)
990 Desc    : ¶Ôddr×ödata training
991 Params  : void
992 Return  : void
993 Notes   : Ã»ÓÐ×ödata trainingУÑé
994 ----------------------------------------------------------------------*/
995 static uint32_t __sramfunc ddr_data_training(void)
996 {
997         uint32 value, dram_bw;
998         value = pDDR_Reg->TREFI;
999         pDDR_Reg->TREFI = 0;
1000         dram_bw = (pPHY_Reg->PHY_REG0 >> 4) & 0xf;
1001         pPHY_Reg->PHY_REG2 |= PHY_AUTO_CALIBRATION;
1002         /*wait echo byte DTDONE*/
1003         ddr_delayus(5);
1004         /*stop DTT*/
1005         while ((pPHY_Reg->PHY_REGff & 0xf) != dram_bw)
1006         ;
1007         pPHY_Reg->PHY_REG2 = (pPHY_Reg->PHY_REG2 & (~0x1));
1008         /*send some auto refresh to complement the lost while DTT*/
1009         ddr_send_command(3, REF_cmd, 0);
1010         ddr_send_command(3, REF_cmd, 0);
1011         ddr_send_command(3, REF_cmd, 0);
1012         ddr_send_command(3, REF_cmd, 0);
1013
1014         /*resume auto refresh*/
1015         pDDR_Reg->TREFI = value;
1016         return 0;
1017 }
1018
1019 /*----------------------------------------------------------------------
1020 Name    : void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
1021 Desc    : ÉèÖÃPHY dll ¹¤×÷ģʽ
1022 Params  : freq -> ddr¹¤×÷ƵÂÊ
1023 Return  : void
1024 Notes   :
1025 ----------------------------------------------------------------------*/
1026 static void __sramfunc ddr_set_dll_bypass(uint32 freq)
1027 {
1028 #if defined (PHY_RX_PHASE_CAL)
1029         uint32 phase_90, dll_set, de_skew;
1030
1031         phase_90 = 1000000 / freq / 4;
1032         dll_set = (phase_90 - 300 + (0x7*PHY_DE_SKEW_STEP)) / (phase_90 / 4);
1033         de_skew = (phase_90 - 300 + (0x7*PHY_DE_SKEW_STEP) - ((phase_90 / 4) * dll_set));
1034         if (de_skew > PHY_DE_SKEW_STEP * 15) {
1035                 if (dll_set == 3) {
1036                         de_skew = 15;
1037                 } else {
1038                         dll_set += 1;
1039                         de_skew = 0;
1040                 }
1041         } else {
1042                 de_skew = de_skew / PHY_DE_SKEW_STEP;
1043         }
1044
1045         pPHY_Reg->PHY_REG28 = dll_set;/*rx dll 45¡ãdelay*/
1046         pPHY_Reg->PHY_REG38 = dll_set;/*rx dll 45¡ãdelay*/
1047         pPHY_Reg->PHY_REG48 = dll_set;/*rx dll 45¡ãdelay*/
1048         pPHY_Reg->PHY_REG58 = dll_set;/*rx dll 45¡ãdelay*/
1049         pPHY_Reg->PHY_REG_skew[(0x324-0x2c0)/4] = 0x7 | (de_skew << 4);
1050         pPHY_Reg->PHY_REG_skew[(0x350-0x2c0)/4] = 0x7 | (de_skew << 4);
1051         pPHY_Reg->PHY_REG_skew[(0x37c-0x2c0)/4] = 0x7 | (de_skew << 4);
1052         pPHY_Reg->PHY_REG_skew[(0x3a8-0x2c0)/4] = 0x7 | (de_skew << 4);
1053 #else
1054         uint32 phase;
1055         if (freq < 350) {
1056                 phase = 3;
1057         } else if (freq < 600) {
1058                 phase = 2;
1059         } else
1060                 phase = 1;
1061         pPHY_Reg->PHY_REG28 = phase;    /*rx dll 45¡ãdelay*/
1062         pPHY_Reg->PHY_REG38 = phase;    /*rx dll 45¡ãdelay*/
1063         pPHY_Reg->PHY_REG48 = phase;    /*rx dll 45¡ãdelay*/
1064         pPHY_Reg->PHY_REG58 = phase;    /*rx dll 45¡ãdelay*/
1065 #endif
1066         if (freq <= PHY_DLL_DISABLE_FREQ) {
1067                 pPHY_Reg->PHY_REGDLL |= 0x1F;   /*TX DLL bypass */
1068         } else {
1069                 pPHY_Reg->PHY_REGDLL &= ~0x1F;  /* TX DLL bypass*/
1070         }
1071
1072         dsb();
1073 }
1074
1075 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id)  /*APLL-1;CPLL-2;DPLL-3;GPLL-4*/
1076 {
1077         uint32 ret = 0;
1078
1079         if (((pCRU_Reg->CRU_MODE_CON >> (pll_id * 4)) & 1) == 1)        /* DPLL Normal mode*/
1080                 ret = 24 * ((pCRU_Reg->CRU_PLL_CON[pll_id][0] & 0xfff)) /* NF = 2*(CLKF+1)*/
1081                     / ((pCRU_Reg->CRU_PLL_CON[pll_id][1] & 0x3f)
1082                        * ((pCRU_Reg->CRU_PLL_CON[pll_id][0] >> 12) & 0x7) * ((pCRU_Reg->CRU_PLL_CON[pll_id][1] >> 6) & 0x7));   /* OD = 2^CLKOD*/
1083         else
1084                 ret = 24;
1085
1086         return ret;
1087 }
1088
1089 static __sramdata uint32 clkFbDiv;
1090 static __sramdata uint32 clkPostDiv1;
1091 static __sramdata uint32 clkPostDiv2;
1092
1093 /*****************************************
1094 *REFDIV   FBDIV     POSTDIV1/POSTDIV2      FOUTPOSTDIV           freq Step        FOUTPOSRDIV            finally use
1095 *==================================================================================================================
1096 *1        17 - 66   4                      100MHz - 400MHz          6MHz          200MHz  <= 300MHz             <= 150MHz
1097 *1        17 - 66   3                      133MHz - 533MHz          8MHz
1098 *1        17 - 66   2                      200MHz - 800MHz          12MHz         300MHz  <= 600MHz      150MHz <= 300MHz
1099 *1        17 - 66   1                      400MHz - 1600MHz         24MHz         600MHz  <= 1200MHz     300MHz <= 600MHz
1100 *******************************************/
1101 /*for minimum jitter operation, the highest VCO and FREF frequencies should be used.*/
1102 /*----------------------------------------------------------------------
1103 *Name    : uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
1104 *Desc    : ÉèÖÃddr pll
1105 *Params  : nMHZ -> ddr¹¤×÷ƵÂÊ
1106 *          set  ->0»ñÈ¡ÉèÖõÄƵÂÊÐÅÏ¢
1107 *                 1ÉèÖÃddr pll
1108 *Return  : ÉèÖõÄƵÂÊÖµ
1109 *Notes   : ÔÚ±äƵʱÐèÒªÏÈset=0µ÷ÓÃÒ»´Îddr_set_pll£¬ÔÙset=1 µ÷ÓÃddr_set_pll
1110 -*---------------------------------------------------------------------*/
1111 static uint32 __sramfunc ddr_set_pll(uint32 nMHz, uint32 set)
1112 {
1113         uint32 ret = 0;
1114         int delay = 1000;
1115         uint32 pll_id = 1;      /*DPLL*/
1116
1117         if (nMHz == 24) {
1118                 ret = 24;
1119                 goto out;
1120         }
1121         if (!set) {
1122                 if (nMHz <= 150) {      /*ʵ¼ÊÊä³öƵÂÊ<300*/
1123                         clkPostDiv1 = 6;
1124                 } else if (nMHz <= 200) {
1125                         clkPostDiv1 = 4;
1126                 } else if (nMHz <= 300) {
1127                         clkPostDiv1 = 3;
1128                 } else if (nMHz <= 450) {
1129                         clkPostDiv1 = 2;
1130                 } else {
1131                         clkPostDiv1 = 1;
1132                 }
1133                 clkPostDiv2 = 1;
1134                 clkFbDiv = (nMHz * 2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2) / 24;        /*×îºóËÍÈëddrµÄÊÇÔÙ¾­¹ý2·ÖƵ*/
1135                 ret =
1136                     (24 * clkFbDiv) / (2 * DDR_PLL_REFDIV * clkPostDiv1 *
1137                                        clkPostDiv2);
1138         } else {
1139                 pCRU_Reg->CRU_MODE_CON = (0x1 << ((pll_id * 4) + 16)) | (0x0 << (pll_id * 4));  /*PLL slow-mode*/
1140
1141                 pCRU_Reg->CRU_PLL_CON[pll_id][0] =
1142                     FBDIV(clkFbDiv) | POSTDIV1(clkPostDiv1);
1143                 pCRU_Reg->CRU_PLL_CON[pll_id][1] = REFDIV(DDR_PLL_REFDIV) | POSTDIV2(clkPostDiv2) | (0x10001 << 12);    /*interger mode*/
1144
1145                 ddr_delayus(1);
1146
1147                 while (delay > 0) {
1148                         ddr_delayus(1);
1149                         if (pCRU_Reg->CRU_PLL_CON[pll_id][1] & (PLL_LOCK_STATUS))       /*wait for pll locked*/
1150                                 break;
1151                         delay--;
1152                 }
1153
1154                 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 << 16) | 0x0);     /*clk_ddr_src:clk_ddrphy = 1:1*/
1155                 pCRU_Reg->CRU_MODE_CON = (0x1 << ((pll_id * 4) + 16)) | (0x1 << (pll_id * 4));  /*PLL normal*/
1156         }
1157 out:
1158         return ret;
1159 }
1160
1161 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1162 {
1163         return ddr_set_pll(nMHz, set);
1164 }
1165
1166 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1167 static uint32(*p_ddr_set_pll) (uint32 nMHz, uint32 set);
1168
1169 /*----------------------------------------------------------------------
1170 *Name    : uint32_t ddr_get_parameter(uint32_t nMHz)
1171 *Desc    : »ñÈ¡ÅäÖòÎÊý
1172 *Params  : nMHZ -> ddr¹¤×÷ƵÂÊ
1173 *Return  : 0 ³É¹¦
1174 *          -1 Ê§°Ü
1175 *          -4 ÆµÂÊÖµ³¬¹ý¿ÅÁ£×î´óƵÂÊ
1176 *Notes   :
1177 *----------------------------------------------------------------------*/
1178 static uint32 ddr_get_parameter(uint32 nMHz)
1179 {
1180         uint32_t tmp;
1181         uint32_t ret = 0;
1182         uint32_t al;
1183         uint32_t bl;
1184         uint32_t cl;
1185         uint32_t cwl;
1186         uint32_t bl_tmp;
1187         PCTL_TIMING_T *p_pctl_timing = &(p_ddr_reg->pctl_timing);
1188         NOC_TIMING_T *p_noc_timing = &(p_ddr_reg->noc_timing);
1189
1190         p_pctl_timing->togcnt1u = nMHz;
1191         p_pctl_timing->togcnt100n = nMHz / 10;
1192         p_pctl_timing->tinit = 200;
1193         p_pctl_timing->trsth = 500;
1194
1195         if (p_ddr_reg->mem_type == DDR3) {
1196                 if (p_ddr_reg->ddr_speed_bin > DDR3_DEFAULT) {
1197                         ret = -1;
1198                         goto out;
1199                 }
1200 #define DDR3_tREFI_7_8_us    (78)
1201 #define DDR3_tMRD            (4)
1202 #define DDR3_tRFC_512Mb      (90)
1203 #define DDR3_tRFC_1Gb        (110)
1204 #define DDR3_tRFC_2Gb        (160)
1205 #define DDR3_tRFC_4Gb        (300)
1206 #define DDR3_tRFC_8Gb        (350)
1207 #define DDR3_tRTW            (2)        /*register min valid value*/
1208 #define DDR3_tRAS            (37)
1209 #define DDR3_tRRD            (10)
1210 #define DDR3_tRTP            (7)
1211 #define DDR3_tWR             (15)
1212 #define DDR3_tWTR            (7)
1213 #define DDR3_tXP             (7)
1214 #define DDR3_tXPDLL          (24)
1215 #define DDR3_tZQCS           (80)
1216 #define DDR3_tZQCSI          (10000)
1217 #define DDR3_tDQS            (1)
1218 #define DDR3_tCKSRE          (10)
1219 #define DDR3_tCKE_400MHz     (7)
1220 #define DDR3_tCKE_533MHz     (6)
1221 #define DDR3_tMOD            (15)
1222 #define DDR3_tRSTL           (100)
1223 #define DDR3_tZQCL           (320)
1224 #define DDR3_tDLLK           (512)
1225
1226                 al = 0;
1227                 bl = 8;
1228                 if (nMHz <= 330) {
1229                         tmp = 0;
1230                 } else if (nMHz <= 400) {
1231                         tmp = 1;
1232                 } else if (nMHz <= 533) {
1233                         tmp = 2;
1234                 } else {        /*666MHz*/
1235                         tmp = 3;
1236                 }
1237                 if (nMHz <= DDR3_DDR2_DLL_DISABLE_FREQ) {       /*when dll bypss cl = cwl = 6*/
1238                         cl = 6;
1239                         cwl = 6;
1240                 } else {
1241                         cl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] >> 16;
1242                         cwl =
1243                             ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] & 0x0ff;
1244                 }
1245                 if (cl == 0) {
1246                         ret = -4;       /*³¬¹ý¿ÅÁ£µÄ×î´óƵÂÊ*/
1247                 }
1248                 if (nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ) {
1249                         p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
1250                 } else {
1251                         p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
1252                 }
1253                 p_ddr_reg->ddrMR[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */ ;
1254                 p_ddr_reg->ddrMR[3] = 0;
1255                 /**************************************************
1256                 * PCTL Timing
1257                 **************************************************/
1258                 /*
1259                  * tREFI, average periodic refresh interval, 7.8us
1260                  */
1261                 p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
1262                 /*
1263                  * tMRD, 4 tCK
1264                  */
1265                 p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
1266                 /*
1267                  * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
1268                  */
1269                 if (p_ddr_reg->ddr_capability_per_die <= 0x4000000) {   /*512Mb 90ns*/
1270                         tmp = DDR3_tRFC_512Mb;
1271                 } else if (p_ddr_reg->ddr_capability_per_die <= 0x8000000) {    /*1Gb 110ns*/
1272                         tmp = DDR3_tRFC_1Gb;
1273                 } else if (p_ddr_reg->ddr_capability_per_die <= 0x10000000) {   /*2Gb 160ns*/
1274                         tmp = DDR3_tRFC_2Gb;
1275                 } else if (p_ddr_reg->ddr_capability_per_die <= 0x20000000) {/*4Gb 300ns*/
1276                         tmp = DDR3_tRFC_4Gb;
1277                 } else{         /*8Gb  350ns*/
1278                         tmp = DDR3_tRFC_8Gb;
1279                 }
1280                 p_pctl_timing->trfc = (tmp * nMHz + 999) / 1000;
1281                 /*
1282                  * tXSR, =tDLLK=512 tCK
1283                  */
1284                 p_pctl_timing->texsr = DDR3_tDLLK;
1285                 /*
1286                  * tRP=CL
1287                  */
1288                 p_pctl_timing->trp = cl;
1289                 /*
1290                  * WrToMiss=WL*tCK + tWR + tRP + tRCD
1291                  */
1292                 p_noc_timing->b.WrToMiss =
1293                     ((cwl + ((DDR3_tWR * nMHz + 999) / 1000) + cl + cl) & 0x3F);
1294                 /*
1295                  * tRC=tRAS+tRP
1296                  */
1297                 p_pctl_timing->trc =
1298                     ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin] >> 16) * nMHz +
1299                        999) / 1000) & 0x3F);
1300                 p_noc_timing->b.ActToAct =
1301                     ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin] >> 16) * nMHz +
1302                        999) / 1000) & 0x3F);
1303
1304                 p_pctl_timing->trtw = (cl + 2 - cwl);   /*DDR3_tRTW*/
1305                 p_noc_timing->b.RdToWr = ((cl + 2 - cwl) & 0x1F);
1306                 p_pctl_timing->tal = al;
1307                 p_pctl_timing->tcl = cl;
1308                 p_pctl_timing->tcwl = cwl;
1309                 /*
1310                  * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
1311                  */
1312                 p_pctl_timing->tras =
1313                     (((DDR3_tRAS * nMHz + (nMHz >> 1) + 999) / 1000) & 0x3F);
1314                 /*
1315                  * tRCD=CL
1316                  */
1317                 p_pctl_timing->trcd = cl;
1318                 /*
1319                  * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
1320                  *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
1321                  *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
1322                  *
1323                  */
1324                 tmp = ((DDR3_tRRD * nMHz + 999) / 1000);
1325                 if (tmp < 4) {
1326                         tmp = 4;
1327                 }
1328                 p_pctl_timing->trrd = (tmp & 0xF);
1329                 /*
1330                  * tRTP, max(4 tCK,7.5ns)
1331                  */
1332                 tmp = ((DDR3_tRTP * nMHz + (nMHz >> 1) + 999) / 1000);
1333                 if (tmp < 4) {
1334                         tmp = 4;
1335                 }
1336                 p_pctl_timing->trtp = tmp & 0xF;
1337                 /*
1338                  * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
1339                  */
1340                 p_noc_timing->b.RdToMiss = ((tmp + cl + cl - (bl >> 1)) & 0x3F);
1341                 /*
1342                  * tWR, 15ns
1343                  */
1344                 tmp = ((DDR3_tWR * nMHz + 999) / 1000);
1345                 p_pctl_timing->twr = tmp & 0x1F;
1346                 if (tmp < 9)
1347                         tmp = tmp - 4;
1348                 else
1349                         tmp = tmp >> 1;
1350                 p_ddr_reg->ddrMR[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
1351
1352                 /*
1353                  * tWTR, max(4 tCK,7.5ns)
1354                  */
1355                 tmp = ((DDR3_tWTR * nMHz + (nMHz >> 1) + 999) / 1000);
1356                 if (tmp < 4) {
1357                         tmp = 4;
1358                 }
1359                 p_pctl_timing->twtr = tmp & 0xF;
1360                 p_noc_timing->b.WrToRd = ((tmp + cwl) & 0x1F);
1361                 /*
1362                  * tXP, max(3 tCK, 7.5ns)(<933MHz)
1363                  */
1364                 tmp = ((DDR3_tXP * nMHz + (nMHz >> 1) + 999) / 1000);
1365                 if (tmp < 3) {
1366                         tmp = 3;
1367                 }
1368                 p_pctl_timing->txp = tmp & 0x7;
1369                 /*
1370                  * tXPDLL, max(10 tCK,24ns)
1371                  */
1372                 tmp = ((DDR3_tXPDLL * nMHz + 999) / 1000);
1373                 if (tmp < 10) {
1374                         tmp = 10;
1375                 }
1376                 p_pctl_timing->txpdll = tmp & 0x3F;
1377                 /*
1378                  * tZQCS, max(64 tCK, 80ns)
1379                  */
1380                 tmp = ((DDR3_tZQCS * nMHz + 999) / 1000);
1381                 if (tmp < 64) {
1382                         tmp = 64;
1383                 }
1384                 p_pctl_timing->tzqcs = tmp & 0x7F;
1385                 /*
1386                  * tZQCSI,
1387                  */
1388                 p_pctl_timing->tzqcsi = DDR3_tZQCSI;
1389                 /*
1390                  * tDQS,
1391                  */
1392                 p_pctl_timing->tdqs = DDR3_tDQS;
1393                 /*
1394                  * tCKSRE, max(5 tCK, 10ns)
1395                  */
1396                 tmp = ((DDR3_tCKSRE * nMHz + 999) / 1000);
1397                 if (tmp < 5) {
1398                         tmp = 5;
1399                 }
1400                 p_pctl_timing->tcksre = tmp & 0x1F;
1401                 /*
1402                  * tCKSRX, max(5 tCK, 10ns)
1403                  */
1404                 p_pctl_timing->tcksrx = tmp & 0x1F;
1405                 /*
1406                  * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
1407                  */
1408                 if (nMHz >= 533) {
1409                         tmp = ((DDR3_tCKE_533MHz * nMHz + 999) / 1000);
1410                 } else {
1411                         tmp =
1412                             ((DDR3_tCKE_400MHz * nMHz + (nMHz >> 1) +
1413                               999) / 1000);
1414                 }
1415                 if (tmp < 3) {
1416                         tmp = 3;
1417                 }
1418                 p_pctl_timing->tcke = tmp & 0x7;
1419                 /*
1420                  * tCKESR, =tCKE + 1tCK
1421                  */
1422                 p_pctl_timing->tckesr = (tmp + 1) & 0xF;
1423                 /*
1424                  * tMOD, max(12 tCK,15ns)
1425                  */
1426                 tmp = ((DDR3_tMOD * nMHz + 999) / 1000);
1427                 if (tmp < 12) {
1428                         tmp = 12;
1429                 }
1430                 p_pctl_timing->tmod = tmp & 0x1F;
1431                 /*
1432                  * tRSTL, 100ns
1433                  */
1434                 p_pctl_timing->trstl =
1435                     ((DDR3_tRSTL * nMHz + 999) / 1000) & 0x7F;
1436                 /*
1437                  * tZQCL, max(256 tCK, 320ns)
1438                  */
1439                 tmp = ((DDR3_tZQCL * nMHz + 999) / 1000);
1440                 if (tmp < 256) {
1441                         tmp = 256;
1442                 }
1443                 p_pctl_timing->tzqcl = tmp & 0x3FF;
1444                 /*
1445                  * tMRR, 0 tCK
1446                  */
1447                 p_pctl_timing->tmrr = 0;
1448                 /*
1449                  * tDPD, 0
1450                  */
1451                 p_pctl_timing->tdpd = 0;
1452
1453                 /**************************************************
1454                 *NOC Timing
1455                 **************************************************/
1456                 p_noc_timing->b.BurstLen = ((bl >> 1) & 0x7);
1457         } else if (p_ddr_reg->mem_type == LPDDR2) {
1458 #define LPDDR2_tREFI_3_9_us    (38)     /*unit 100ns*/
1459 #define LPDDR2_tREFI_7_8_us    (78)     /*unit 100ns*/
1460 #define LPDDR2_tMRD            (5)      /*tCK*/
1461 #define LPDDR2_tRFC_8Gb        (210)    /*ns*/
1462 #define LPDDR2_tRFC_4Gb        (130)    /*ns*/
1463 #define LPDDR2_tRP_4_BANK               (24)    /*ns*/
1464 #define LPDDR2_tRPab_SUB_tRPpb_4_BANK   (0)
1465 #define LPDDR2_tRP_8_BANK               (27)    /*ns*/
1466 #define LPDDR2_tRPab_SUB_tRPpb_8_BANK   (3)
1467 #define LPDDR2_tRTW          (1)        /*tCK register min valid value*/
1468 #define LPDDR2_tRAS          (42)       /*ns*/
1469 #define LPDDR2_tRCD          (24)       /*ns*/
1470 #define LPDDR2_tRRD          (10)       /*ns*/
1471 #define LPDDR2_tRTP          (7)        /*ns*/
1472 #define LPDDR2_tWR           (15)       /*ns*/
1473 #define LPDDR2_tWTR_GREAT_200MHz         (7)    /*ns*/
1474 #define LPDDR2_tWTR_LITTLE_200MHz        (10)   /*ns*/
1475 #define LPDDR2_tXP           (7)        /*ns*/
1476 #define LPDDR2_tXPDLL        (0)
1477 #define LPDDR2_tZQCS         (90)       /*ns*/
1478 #define LPDDR2_tZQCSI        (0)
1479 #define LPDDR2_tDQS          (1)
1480 #define LPDDR2_tCKSRE        (1)        /*tCK*/
1481 #define LPDDR2_tCKSRX        (2)        /*tCK*/
1482 #define LPDDR2_tCKE          (3)        /*tCK*/
1483 #define LPDDR2_tMOD          (0)
1484 #define LPDDR2_tRSTL         (0)
1485 #define LPDDR2_tZQCL         (360)      /*ns*/
1486 #define LPDDR2_tMRR          (2)        /*tCK*/
1487 #define LPDDR2_tCKESR        (15)       /*ns*/
1488 #define LPDDR2_tDPD_US       (500)
1489 #define LPDDR2_tFAW_GREAT_200MHz    (50)        /*ns*/
1490 #define LPDDR2_tFAW_LITTLE_200MHz   (60)        /*ns*/
1491 #define LPDDR2_tDLLK         (2)        /*tCK*/
1492 #define LPDDR2_tDQSCK_MAX    (3)        /*tCK*/
1493 #define LPDDR2_tDQSCK_MIN    (0)        /*tCK*/
1494 #define LPDDR2_tDQSS         (1)        /*tCK*/
1495
1496                 uint32 trp_tmp;
1497                 uint32 trcd_tmp;
1498                 uint32 tras_tmp;
1499                 uint32 trtp_tmp;
1500                 uint32 twr_tmp;
1501
1502                 al = 0;
1503                 if (nMHz >= 200) {
1504                         bl = 4; /*you can change burst here*/
1505                 } else {
1506                         bl = 8; /* freq < 200MHz, BL fixed 8*/
1507                 }
1508                 /*     1066 933 800 667 533 400 333
1509                  * RL,   8   7   6   5   4   3   3
1510                  * WL,   4   4   3   2   2   1   1
1511                  */
1512                 if (nMHz <= 200) {
1513                         cl = 3;
1514                         cwl = 1;
1515                         p_ddr_reg->ddrMR[2] = LPDDR2_RL3_WL1;
1516                 } else if (nMHz <= 266) {
1517                         cl = 4;
1518                         cwl = 2;
1519                         p_ddr_reg->ddrMR[2] = LPDDR2_RL4_WL2;
1520                 } else if (nMHz <= 333) {
1521                         cl = 5;
1522                         cwl = 2;
1523                         p_ddr_reg->ddrMR[2] = LPDDR2_RL5_WL2;
1524                 } else if (nMHz <= 400) {
1525                         cl = 6;
1526                         cwl = 3;
1527                         p_ddr_reg->ddrMR[2] = LPDDR2_RL6_WL3;
1528                 } else if (nMHz <= 466) {
1529                         cl = 7;
1530                         cwl = 4;
1531                         p_ddr_reg->ddrMR[2] = LPDDR2_RL7_WL4;
1532                 } else {                /*(nMHz<=1066)*/
1533                         cl = 8;
1534                         cwl = 4;
1535                         p_ddr_reg->ddrMR[2] = LPDDR2_RL8_WL4;
1536                 }
1537                 p_ddr_reg->ddrMR[3] = LPDDR2_DS_34;
1538                 p_ddr_reg->ddrMR[0] = 0;
1539                 /**************************************************
1540                 * PCTL Timing
1541                 **************************************************/
1542                 /*
1543                  * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
1544                  */
1545                 if (p_ddr_reg->ddr_capability_per_die >= 0x10000000) {  /*2Gb*/
1546                         p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
1547                 } else {
1548                         p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
1549                 }
1550
1551                 /*
1552                  * tMRD, (=tMRW), 5 tCK
1553                  */
1554                 p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
1555                 /*
1556                  * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
1557                  */
1558                 if (p_ddr_reg->ddr_capability_per_die >= 0x40000000) {  /*8Gb*/
1559                         p_pctl_timing->trfc =
1560                             (LPDDR2_tRFC_8Gb * nMHz + 999) / 1000;
1561                         /*
1562                          * tXSR, max(2tCK,tRFC+10ns)
1563                          */
1564                         tmp = (((LPDDR2_tRFC_8Gb + 10) * nMHz + 999) / 1000);
1565                 } else {
1566                         p_pctl_timing->trfc =
1567                             (LPDDR2_tRFC_4Gb * nMHz + 999) / 1000;
1568                         tmp = (((LPDDR2_tRFC_4Gb + 10) * nMHz + 999) / 1000);
1569                 }
1570                 if (tmp < 2) {
1571                         tmp = 2;
1572                 }
1573                 p_pctl_timing->texsr = tmp & 0x3FF;
1574                 /*
1575                  * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
1576                  */
1577                 trp_tmp = ((LPDDR2_tRP_8_BANK * nMHz + 999) / 1000);
1578                 if (trp_tmp < 3) {
1579                         trp_tmp = 3;
1580                 }
1581                 p_pctl_timing->trp =
1582                     ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK * nMHz +
1583                         999) / 1000) & 0x3) << 16) | (trp_tmp & 0xF);
1584
1585                 /*
1586                  * tRAS, max(3tCK,42ns)
1587                  */
1588                 tras_tmp = ((LPDDR2_tRAS * nMHz + 999) / 1000);
1589                 if (tras_tmp < 3) {
1590                         tras_tmp = 3;
1591                 }
1592                 p_pctl_timing->tras = (tras_tmp & 0x3F);
1593
1594                 /*
1595                  * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
1596                  */
1597                 trcd_tmp = ((LPDDR2_tRCD * nMHz + 999) / 1000);
1598                 if (trcd_tmp < 3) {
1599                         trcd_tmp = 3;
1600                 }
1601                 p_pctl_timing->trcd = (trcd_tmp & 0xF);
1602                 /*
1603                  * tRTP, max(2tCK, 7.5ns)
1604                  */
1605                 trtp_tmp = ((LPDDR2_tRTP * nMHz + (nMHz >> 1) + 999) / 1000);
1606                 if (trtp_tmp < 2) {
1607                         trtp_tmp = 2;
1608                 }
1609                 p_pctl_timing->trtp = trtp_tmp & 0xF;
1610                 /*
1611                  * tWR, max(3tCK,15ns)
1612                  */
1613                 twr_tmp = ((LPDDR2_tWR * nMHz + 999) / 1000);
1614                 if (twr_tmp < 3) {
1615                         twr_tmp = 3;
1616                 }
1617                 p_pctl_timing->twr = twr_tmp & 0x1F;
1618                 bl_tmp =
1619                     (bl ==
1620                      16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
1621                 p_ddr_reg->ddrMR[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
1622
1623                 /*
1624                  * WrToMiss=WL*tCK + tDQSS + tWR + tRP + tRCD
1625                  */
1626                 p_noc_timing->b.WrToMiss =
1627                     ((cwl + LPDDR2_tDQSS + twr_tmp + trp_tmp +
1628                       trcd_tmp) & 0x3F);
1629                 /*
1630                  * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
1631                  */
1632                 p_noc_timing->b.RdToMiss =
1633                     ((trtp_tmp + trp_tmp + trcd_tmp - (bl >> 1)) & 0x3F);
1634                 /*
1635                  * tRC=tRAS+tRP
1636                  */
1637                 p_pctl_timing->trc = ((tras_tmp + trp_tmp) & 0x3F);
1638                 p_noc_timing->b.ActToAct = ((tras_tmp + trp_tmp) & 0x3F);
1639                 /*
1640                  * RdToWr=RL+tDQSCK-WL
1641                  */
1642                 p_pctl_timing->trtw = (cl + LPDDR2_tDQSCK_MAX + (bl / 2) + 1 - cwl);    /*LPDDR2_tRTW*/
1643                 p_noc_timing->b.RdToWr =
1644                     ((cl + LPDDR2_tDQSCK_MAX + 1 - cwl) & 0x1F);
1645                 p_pctl_timing->tal = al;
1646                 p_pctl_timing->tcl = cl;
1647                 p_pctl_timing->tcwl = cwl;
1648                 /*
1649                  * tRRD, max(2tCK,10ns)
1650                  */
1651                 tmp = ((LPDDR2_tRRD * nMHz + 999) / 1000);
1652                 if (tmp < 2) {
1653                         tmp = 2;
1654                 }
1655                 p_pctl_timing->trrd = (tmp & 0xF);
1656                 /*
1657                  * tWTR, max(2tCK, 7.5ns(533-266MHz)  10ns(200-166MHz))
1658                  */
1659                 if (nMHz > 200) {
1660                         tmp =
1661                             ((LPDDR2_tWTR_GREAT_200MHz * nMHz + (nMHz >> 1) +
1662                               999) / 1000);
1663                 } else {
1664                         tmp = ((LPDDR2_tWTR_LITTLE_200MHz * nMHz + 999) / 1000);
1665                 }
1666                 if (tmp < 2) {
1667                         tmp = 2;
1668                 }
1669                 p_pctl_timing->twtr = tmp & 0xF;
1670                 /*
1671                  * WrToRd=WL+tDQSS+tWTR
1672                  */
1673                 p_noc_timing->b.WrToRd = ((cwl + LPDDR2_tDQSS + tmp) & 0x1F);
1674                 /*
1675                  * tXP, max(2tCK,7.5ns)
1676                  */
1677                 tmp = ((LPDDR2_tXP * nMHz + (nMHz >> 1) + 999) / 1000);
1678                 if (tmp < 2) {
1679                         tmp = 2;
1680                 }
1681                 p_pctl_timing->txp = tmp & 0x7;
1682                 /*
1683                  * tXPDLL, 0ns
1684                  */
1685                 p_pctl_timing->txpdll = LPDDR2_tXPDLL;
1686                 /*
1687                  * tZQCS, 90ns
1688                  */
1689                 p_pctl_timing->tzqcs =
1690                     ((LPDDR2_tZQCS * nMHz + 999) / 1000) & 0x7F;
1691                 /*
1692                  * tZQCSI,
1693                  */
1694                 /*if (pDDR_Reg->MCFG &= lpddr2_s4) {*/
1695                 if (1) {
1696                         p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
1697                 } else {
1698                         p_pctl_timing->tzqcsi = 0;
1699                 }
1700                 /*
1701                  * tDQS,
1702                  */
1703                 p_pctl_timing->tdqs = LPDDR2_tDQS;
1704                 /*
1705                  * tCKSRE, 1 tCK
1706                  */
1707                 p_pctl_timing->tcksre = LPDDR2_tCKSRE;
1708                 /*
1709                  * tCKSRX, 2 tCK
1710                  */
1711                 p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
1712                 /*
1713                  * tCKE, 3 tCK
1714                  */
1715                 p_pctl_timing->tcke = LPDDR2_tCKE;
1716                 /*
1717                  * tMOD, 0 tCK
1718                  */
1719                 p_pctl_timing->tmod = LPDDR2_tMOD;
1720                 /*
1721                  * tRSTL, 0 tCK
1722                  */
1723                 p_pctl_timing->trstl = LPDDR2_tRSTL;
1724                 /*
1725                  * tZQCL, 360ns
1726                  */
1727                 p_pctl_timing->tzqcl =
1728                     ((LPDDR2_tZQCL * nMHz + 999) / 1000) & 0x3FF;
1729                 /*
1730                  * tMRR, 2 tCK
1731                  */
1732                 p_pctl_timing->tmrr = LPDDR2_tMRR;
1733                 /*
1734                  * tCKESR, max(3tCK,15ns)
1735                  */
1736                 tmp = ((LPDDR2_tCKESR * nMHz + 999) / 1000);
1737                 if (tmp < 3) {
1738                         tmp = 3;
1739                 }
1740                 p_pctl_timing->tckesr = tmp & 0xF;
1741                 /*
1742                  * tDPD, 500us
1743                  */
1744                 p_pctl_timing->tdpd = LPDDR2_tDPD_US;
1745
1746                 /*************************************************
1747                 * NOC Timing
1748                 **************************************************/
1749                 p_noc_timing->b.BurstLen = ((bl >> 1) & 0x7);
1750         }
1751
1752 out:
1753         return ret;
1754 }
1755
1756 /*----------------------------------------------------------------------
1757 *Name    : uint32_t __sramlocalfunc ddr_update_timing(void)
1758 *Desc    : ¸üÐÂpctl phy Ïà¹Øtiming¼Ä´æÆ÷
1759 *Params  : void
1760 *Return  : 0 ³É¹¦
1761 *Notes   :
1762 *----------------------------------------------------------------------*/
1763 static uint32 __sramfunc ddr_update_timing(void)
1764 {
1765         uint32_t bl_tmp;
1766         uint32_t ret = 0;
1767
1768         PCTL_TIMING_T *p_pctl_timing = &(DATA(ddr_reg).pctl_timing);
1769         NOC_TIMING_T *p_noc_timing = &(DATA(ddr_reg).noc_timing);
1770
1771         ddr_copy((uint32 *)&(pDDR_Reg->TOGCNT1U),
1772                  (uint32 *)&(p_pctl_timing->togcnt1u), 34);
1773 /*    pPHY_Reg->PHY_REG1 |= PHY_Burst8;*/    /*ddr3 burst length¹Ì¶¨Îª8*/
1774         pPHY_Reg->PHY_REGb = ((p_pctl_timing->tcl << 4) | (p_pctl_timing->tal));
1775         pPHY_Reg->PHY_REGc = p_pctl_timing->tcwl;
1776         *(volatile uint32 *)SysSrv_DdrTiming = p_noc_timing->d32;
1777         /*Update PCTL BL*/
1778         if (DATA(ddr_reg).mem_type == DDR3) {
1779                 pDDR_Reg->MCFG =
1780                     (pDDR_Reg->MCFG &
1781                      (~(0x1 | (0x3 << 18) | (0x1 << 17) | (0x1 << 16))))
1782                     | ddr2_ddr3_bl_8 | tfaw_cfg(5) | pd_exit_slow | pd_type(1);
1783                 pDDR_Reg->DFITRDDATAEN = (pDDR_Reg->TAL + pDDR_Reg->TCL) - 3;   /*trdata_en = rl-3*/
1784                 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL - 1;
1785         } else if (DATA(ddr_reg).mem_type == LPDDR2) {
1786                 if ((DATA(ddr_reg).ddrMR[1] & 0x7) == LPDDR2_BL8) {
1787                         bl_tmp = mddr_lpddr2_bl_8;
1788                         pPHY_Reg->PHY_REG1 |= PHY_Burst8;
1789                 } else if ((DATA(ddr_reg).ddrMR[1] & 0x7) == LPDDR2_BL4) {
1790                         bl_tmp = mddr_lpddr2_bl_4;
1791                         pPHY_Reg->PHY_REG1 &= (~PHY_Burst8);
1792                 } else{         /*if((DATA(ddr_reg).ddrMR[1] & 0x7) == LPDDR2_BL16)*/
1793                         bl_tmp = mddr_lpddr2_bl_16;
1794                         ret = -1;
1795                 }
1796                 if (DATA(ddr_freq) >= 200) {
1797                         pDDR_Reg->MCFG =
1798                             (pDDR_Reg->MCFG &
1799                              (~
1800                               ((0x3 << 20) | (0x3 << 18) | (0x1 << 17) |
1801                                (0x1 << 16)))) | bl_tmp | tfaw_cfg(5) |
1802                             pd_exit_fast | pd_type(1);
1803                 } else {
1804                         pDDR_Reg->MCFG =
1805                             (pDDR_Reg->MCFG &
1806                              (~
1807                               ((0x3 << 20) | (0x3 << 18) | (0x1 << 17) |
1808                                (0x1 << 16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(6) |
1809                             pd_exit_fast | pd_type(1);
1810                 }
1811                 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL - 1;
1812                 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL;
1813
1814         }
1815         return ret;
1816 }
1817
1818 /*----------------------------------------------------------------------
1819 *Name    : uint32_t __sramlocalfunc ddr_update_mr(void)
1820 *Desc    : ¸üпÅÁ£MR¼Ä´æÆ÷
1821 *Params  : void
1822 *Return  : void
1823 *Notes   :
1824 *----------------------------------------------------------------------*/
1825 static uint32 __sramfunc ddr_update_mr(void)
1826 {
1827         uint32 cs;
1828
1829         cs = READ_CS_INFO();
1830         cs = (2 << cs) - 1;     /*case 0:1rank cs=1; case 1:2rank cs =3*/
1831         if (DATA(ddr_reg).mem_type == DDR3) {
1832                 if (DATA(ddr_freq) > DDR3_DDR2_DLL_DISABLE_FREQ) {
1833                         if (DATA(ddr_dll_status) == DDR3_DLL_DISABLE) { /*off -> on*/
1834                                 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1])));     /*DLL enable*/
1835                                 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((DATA(ddr_reg).ddrMR[0])) | DDR3_DLL_RESET));  /*DLL reset*/
1836                                 ddr_delayus(2); /*at least 200 DDR cycle*/
1837                                 ddr_send_command(cs, MRS_cmd,
1838                                                  bank_addr(0x0) |
1839                                                  cmd_addr((DATA(ddr_reg).ddrMR
1840                                                            [0])));
1841                                 DATA(ddr_dll_status) = DDR3_DLL_ENABLE;
1842                         } else{         /*on -> on*/
1843                                 ddr_send_command(cs, MRS_cmd,
1844                                                  bank_addr(0x1) |
1845                                                  cmd_addr((DATA(ddr_reg).ddrMR
1846                                                            [1])));
1847                                 ddr_send_command(cs, MRS_cmd,
1848                                                  bank_addr(0x0) |
1849                                                  cmd_addr((DATA(ddr_reg).ddrMR
1850                                                            [0])));
1851                         }
1852                 } else {
1853                         ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((DATA(ddr_reg).ddrMR[1])) | DDR3_DLL_DISABLE));        /*DLL disable*/
1854                         ddr_send_command(cs, MRS_cmd,
1855                                          bank_addr(0x0) |
1856                                          cmd_addr((DATA(ddr_reg).ddrMR[0])));
1857                         DATA(ddr_dll_status) = DDR3_DLL_DISABLE;
1858                 }
1859                 ddr_send_command(cs, MRS_cmd,
1860                                  bank_addr(0x2) |
1861                                  cmd_addr((DATA(ddr_reg).ddrMR[2])));
1862         } else if (DATA(ddr_reg).mem_type == LPDDR2) {
1863                 ddr_send_command(cs, MRS_cmd,
1864                                  lpddr2_ma(0x1) |
1865                                  lpddr2_op(DATA(ddr_reg).ddrMR[1]));
1866                 ddr_send_command(cs, MRS_cmd,
1867                                  lpddr2_ma(0x2) |
1868                                  lpddr2_op(DATA(ddr_reg).ddrMR[2]));
1869                 ddr_send_command(cs, MRS_cmd,
1870                                  lpddr2_ma(0x3) |
1871                                  lpddr2_op(DATA(ddr_reg).ddrMR[3]));
1872         }
1873         return 0;
1874 }
1875
1876 /*----------------------------------------------------------------------
1877 *Name    : void __sramlocalfunc ddr_update_odt(void)
1878 *Desc    : update PHY odt & PHY driver impedance
1879 *Params  : void
1880 *Return  : void
1881 *Notes   :-------------------------------------------------*/
1882 static void __sramfunc ddr_update_odt(void)
1883 {
1884         /*adjust DRV and ODT*/
1885         if (DATA(ddr_freq) <= PHY_ODT_DISABLE_FREQ) {
1886                 pPHY_Reg->PHY_REG21 = PHY_DRV_ODT_SET(PHY_RTT_DISABLE); /*DQS0 odt*/
1887                 pPHY_Reg->PHY_REG31 = PHY_DRV_ODT_SET(PHY_RTT_DISABLE); /*DQS1 odt*/
1888                 pPHY_Reg->PHY_REG41 = PHY_DRV_ODT_SET(PHY_RTT_DISABLE); /*DQS2 odt*/
1889                 pPHY_Reg->PHY_REG51 = PHY_DRV_ODT_SET(PHY_RTT_DISABLE); /*DQS3 odt*/
1890         } else {
1891                 pPHY_Reg->PHY_REG21 = PHY_DRV_ODT_SET(PHY_RTT_216ohm);  /*DQS0 odt*/
1892                 pPHY_Reg->PHY_REG31 = PHY_DRV_ODT_SET(PHY_RTT_216ohm);  /*DQS1 odt*/
1893                 pPHY_Reg->PHY_REG41 = PHY_DRV_ODT_SET(PHY_RTT_216ohm);  /*DQS2 odt*/
1894                 pPHY_Reg->PHY_REG51 = PHY_DRV_ODT_SET(PHY_RTT_216ohm);  /*DQS3 odt*/
1895         }
1896
1897         pPHY_Reg->PHY_REG11 = PHY_DRV_ODT_SET(PHY_RON_44ohm);   /*cmd drv*/
1898         pPHY_Reg->PHY_REG16 = PHY_DRV_ODT_SET(PHY_RON_44ohm);   /*clk drv*/
1899
1900         pPHY_Reg->PHY_REG20 = PHY_DRV_ODT_SET(PHY_RON_44ohm);   /*DQS0 drv*/
1901         pPHY_Reg->PHY_REG30 = PHY_DRV_ODT_SET(PHY_RON_44ohm);   /*DQS1 drv*/
1902         pPHY_Reg->PHY_REG40 = PHY_DRV_ODT_SET(PHY_RON_44ohm);   /*DQS2 drv*/
1903         pPHY_Reg->PHY_REG50 = PHY_DRV_ODT_SET(PHY_RON_44ohm);   /*DQS3 drv*/
1904
1905         dsb();
1906 }
1907
1908 #if 0
1909 void PIE_FUNC(ddr_adjust_config)(void)
1910 {
1911         /*enter config state*/
1912         ddr_move_to_Config_state();
1913
1914         /*set auto power down idle*/
1915         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & 0xffff00ff) | (PD_IDLE << 8);
1916         /*enable the hardware low-power interface*/
1917         pDDR_Reg->SCFG.b.hw_low_power_en = 1;
1918         ddr_update_odt();
1919         /*enter access state*/
1920         ddr_move_to_Access_state();
1921 }
1922
1923 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
1924
1925 /*----------------------------------------------------------------------
1926 Name    : __sramfunc void ddr_adjust_config(uint32_t dram_type)
1927 Desc    :
1928 Params  : dram_type ->¿ÅÁ£ÀàÐÍ
1929 Return  : void
1930 Notes   :
1931 ----------------------------------------------------------------------*/
1932
1933 static void ddr_adjust_config(uint32_t dram_type)
1934 {
1935         unsigned long save_sp;
1936         uint32 i;
1937         volatile uint32 n;
1938         volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
1939
1940     /** 1. Make sure there is no host access */
1941         flush_cache_all();
1942         outer_flush_all();
1943         flush_tlb_all();
1944         for (i = 0; i < 2; i++) {
1945                 n = temp[1024 * i];
1946                 barrier();
1947         }
1948         n = pDDR_Reg->SCFG.d32;
1949         n = pPHY_Reg->PHY_REG1;
1950         n = pCRU_Reg->CRU_PLL_CON[0][0];
1951         n = *(volatile uint32_t *)SysSrv_DdrTiming;
1952         dsb();
1953
1954         call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
1955                         (void *)0, rockchip_sram_stack);
1956
1957 }
1958 #endif
1959
1960 static void __sramfunc idle_port(void)
1961 {
1962         int i;
1963         uint32 clk_gate[11];
1964
1965         /*save clock gate status*/
1966         for (i = 0; i < 11; i++) {
1967                 clk_gate[i] = pCRU_Reg->CRU_CLKGATE_CON[i];
1968         }
1969         /*enable all clock gate for request idle*/
1970         for (i = 0; i < 11; i++) {
1971                 pCRU_Reg->CRU_CLKGATE_CON[i] = 0xffff0000;
1972         }
1973
1974         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + peri_pwr_idlereq)) + (1 << peri_pwr_idlereq);    /*peri   bit 12*/
1975         dsb();
1976         while ((pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) == 0)   /*bit 23*/
1977         ;
1978         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + vio_pwr_idlereq)) + (1 << vio_pwr_idlereq);      /*vio*/
1979         dsb();
1980         while ((pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) == 0)
1981         ;
1982
1983         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + vpu_pwr_idlereq)) + (1 << vpu_pwr_idlereq);      /*vpu*/
1984         dsb();
1985         while ((pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) == 0)
1986         ;
1987
1988         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + gpu_pwr_idlereq)) + (1 << gpu_pwr_idlereq);      /*gpu*/
1989         dsb();
1990         while ((pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) == 0)
1991         ;
1992
1993         /*resume clock gate status*/
1994         for (i = 0; i < 10; i++)
1995                 pCRU_Reg->CRU_CLKGATE_CON[i] = (clk_gate[i] | 0xffff0000);
1996 }
1997
1998 static void __sramfunc deidle_port(void)
1999 {
2000         int i;
2001         uint32 clk_gate[11];
2002
2003         /*save clock gate status*/
2004         for (i = 0; i < 11; i++) {
2005                 clk_gate[i] = pCRU_Reg->CRU_CLKGATE_CON[i];
2006         }
2007         /*enable all clock gate for request idle*/
2008         for (i = 0; i < 11; i++) {
2009                 pCRU_Reg->CRU_CLKGATE_CON[i] = 0xffff0000;
2010         }
2011
2012         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + peri_pwr_idlereq)) + (0 << peri_pwr_idlereq);    /*peri   bit 12*/
2013         dsb();
2014         while ((pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) != 0)
2015         ;
2016
2017         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + vio_pwr_idlereq)) + (0 << vio_pwr_idlereq);      /*vio*/
2018         dsb();
2019         while ((pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) != 0)
2020         ;
2021
2022         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + vpu_pwr_idlereq)) + (0 << vpu_pwr_idlereq);      /*vpu*/
2023         dsb();
2024         while ((pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) != 0)
2025         ;
2026
2027         pGRF_Reg->GRF_SOC_CON[2] = (1 << (16 + gpu_pwr_idlereq)) + (0 << gpu_pwr_idlereq);      /*gpu*/
2028         dsb();
2029         while ((pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) != 0)
2030         ;
2031
2032         /*resume clock gate status*/
2033         for (i = 0; i < 10; i++)
2034                 pCRU_Reg->CRU_CLKGATE_CON[i] = (clk_gate[i] | 0xffff0000);
2035
2036 }
2037
2038 /*----------------------------------------------------------------------
2039 *Name    : void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
2040 *Desc    : ½øÈë×ÔË¢ÐÂ
2041 *Params  : nMHz ->ddrƵÂÊ
2042 *Return  : void
2043 *Notes   :
2044 *----------------------------------------------------------------------*/
2045 #if 1
2046 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
2047 {
2048         ddr_move_to_Config_state();
2049         ddr_move_to_Lowpower_state();
2050         pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_EN;
2051         pPHY_Reg->PHY_REG0 = (pPHY_Reg->PHY_REG0 & (~(0x3 << 2)));      /*phy soft reset*/
2052         dsb();
2053         pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1 << 2) << 16) | (1 << 2);   /*disable DDR PHY clock*/
2054         ddr_delayus(1);
2055 }
2056
2057 /*EXPORT_SYMBOL(ddr_selfrefresh_enter);*/
2058 #endif
2059
2060 uint32 dtt_buffer[8];
2061
2062 /*----------------------------------------------------------------------
2063 *Name    : void ddr_dtt_check(void)
2064 *Desc    : data training check
2065 *Params  : void
2066 *Return  : void
2067 *Notes   :
2068 *----------------------------------------------------------------------*/
2069 void ddr_dtt_check(void)
2070 {
2071 #if 1
2072         uint32 i;
2073         for (i = 0; i < 8; i++) {
2074                 dtt_buffer[i] = p_copy_data[i];
2075         }
2076         dsb();
2077         flush_cache_all();
2078         outer_flush_all();
2079         for (i = 0; i < 8; i++) {
2080                 if (dtt_buffer[i] != p_copy_data[i]) {
2081 /*            sram_printascii("DTT failed!\n");*/
2082                         break;
2083                 }
2084                 dtt_buffer[i] = 0;
2085         }
2086 #endif
2087 }
2088
2089 /*----------------------------------------------------------------------
2090 Name    : void __sramlocalfunc ddr_selfrefresh_exit(void)
2091 Desc    : Í˳ö×ÔË¢ÐÂ
2092 Params  : void
2093 Return  : void
2094 Notes   :
2095 ----------------------------------------------------------------------*/
2096 #if 1
2097 static void __sramfunc ddr_selfrefresh_exit(void)
2098 {
2099         pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1 << 2) << 16) | (0 << 2);   /*enable DDR PHY clock*/
2100         dsb();
2101         ddr_delayus(1);
2102         pPHY_Reg->PHY_REG0 = (pPHY_Reg->PHY_REG0 | (0x3 << 2)); /*phy soft de-reset*/
2103         pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_DISB;
2104         /*pPHY_Reg->PHY_REG264 |= (1<<1);*/
2105         dsb();
2106         ddr_move_to_Config_state();
2107         ddr_data_training();
2108         ddr_move_to_Access_state();
2109 /*    ddr_dtt_check();*/
2110 }
2111
2112 #endif
2113 /*----------------------------------------------------------------------
2114 *Name    : void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
2115 *Desc    : ÉèÖÃddr pllÇ°µÄtiming¼°mr²ÎÊýµ÷Õû
2116 *Params  : freq_slew :±äƵбÂÊ 1Éýƽ  0½µÆµ
2117 *Return  : void
2118 *Notes   :
2119 *----------------------------------------------------------------------*/
2120 void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
2121 {
2122         uint32 value_100n, value_1u;
2123
2124         if (freq_slew == 1) {
2125                 value_100n = DATA(ddr_reg).pctl_timing.togcnt100n;
2126                 value_1u = DATA(ddr_reg).pctl_timing.togcnt1u;
2127                 DATA(ddr_reg).pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
2128                 DATA(ddr_reg).pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
2129                 ddr_update_timing();
2130                 ddr_update_mr();
2131                 DATA(ddr_reg).pctl_timing.togcnt100n = value_100n;
2132                 DATA(ddr_reg).pctl_timing.togcnt1u = value_1u;
2133         } else {
2134                 pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
2135                 pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
2136         }
2137
2138         pDDR_Reg->TZQCSI = 0;
2139
2140 }
2141
2142 /*----------------------------------------------------------------------
2143 *Name    : void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
2144 *Desc    : ÉèÖÃddr pllºóµÄtiming¼°mr²ÎÊýµ÷Õû
2145 *Params  : freq_slew :±äƵбÂÊ 1Éýƽ  0½µÆµ
2146 *Return  : void
2147 *Notes   :
2148 *----------------------------------------------------------------------*/
2149 void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
2150 {
2151         if (freq_slew == 1) {
2152                 pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
2153                 pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
2154                 pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl_timing.tzqcsi;
2155         } else {
2156                 ddr_update_timing();
2157                 ddr_update_mr();
2158         }
2159 }
2160
2161 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew)
2162 {
2163         idle_port();
2164
2165         ddr_move_to_Config_state();
2166         DATA(ddr_freq) = freq;
2167         ddr_change_freq_in(freq_slew);
2168         ddr_move_to_Lowpower_state();
2169         pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_EN;
2170         pPHY_Reg->PHY_REG0 = (pPHY_Reg->PHY_REG0 & (~(0x3 << 2)));      /*phy soft reset*/
2171         dsb();
2172     /* 3. change frequence  */
2173         FUNC(ddr_set_pll) (freq, 1);
2174         ddr_set_dll_bypass(freq);       /*set phy dll mode;*/
2175         /*pPHY_Reg->PHY_REG0 = (pPHY_Reg->PHY_REG0 | (0x3 << 2)); */      /*phy soft de-reset */
2176         pPHY_Reg->PHY_REG0 |= (1 << 2); /*soft de-reset analogue(dll)*/
2177         ddr_delayus(5);
2178         pPHY_Reg->PHY_REG0 |= (1 << 3);/*soft de-reset digital*/
2179         pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_DISB;
2180         dsb();
2181         ddr_update_odt();
2182         ddr_move_to_Config_state();
2183         ddr_change_freq_out(freq_slew);
2184         ddr_move_to_Access_state();
2185
2186         deidle_port();
2187 }
2188
2189 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
2190 {
2191         struct ddr_change_freq_sram_param *param = arg;
2192         /* Make sure ddr_SRE_2_SRX paramter less than 4 */
2193         ddr_SRE_2_SRX(param->freq, param->freq_slew);
2194 }
2195
2196 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
2197
2198 typedef struct freq_tag {
2199         uint32_t nMHz;
2200         struct ddr_freq_t *p_ddr_freq_t;
2201 } freq_t;
2202
2203 /*----------------------------------------------------------------------
2204 *Name    : uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
2205 *Desc    : ddr±äƵ
2206 *Params  : nMHz -> ±äƵµÄƵÂÊÖµ
2207 *Return  : ÆµÂÊÖµ
2208 *Notes   :
2209 *----------------------------------------------------------------------*/
2210 static uint32 ddr_change_freq_sram(void *arg)
2211 {
2212         uint32 ret;
2213         uint32 i;
2214         volatile uint32 n;
2215         unsigned long flags;
2216         volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
2217         freq_t *p_freq_t = (freq_t *) arg;
2218         uint32 nMHz = p_freq_t->nMHz;
2219 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
2220         struct ddr_freq_t *p_ddr_freq_t = p_freq_t->p_ddr_freq_t;
2221 #endif
2222
2223         struct ddr_change_freq_sram_param param;
2224         /*uint32 freq;*/
2225         uint32 freq_slew;
2226         uint32 arm_freq;
2227         arm_freq = ddr_get_pll_freq(APLL);
2228         *kern_to_pie(rockchip_pie_chunk, &DATA(loops_per_us)) =
2229             LPJ_100MHZ * arm_freq / 1000000;
2230         ret = p_ddr_set_pll(nMHz, 0);
2231         if (ret == *p_ddr_freq) {
2232                 goto out;
2233         } else {
2234                 freq_slew = (ret > *p_ddr_freq) ? 1 : -1;
2235         }
2236         ddr_get_parameter(ret);
2237         /*kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq))= ret;*/
2238     /** 1. Make sure there is no host access */
2239         local_irq_save(flags);
2240         local_fiq_disable();
2241         flush_cache_all();
2242         outer_flush_all();
2243         flush_tlb_all();
2244
2245 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
2246         if (p_ddr_freq_t->screen_ft_us > 0) {
2247                 p_ddr_freq_t->t1 = cpu_clock(0);
2248                 p_ddr_freq_t->t2 = (uint32)(p_ddr_freq_t->t1 - p_ddr_freq_t->t0);   /*ns*/
2249
2250                 if ((p_ddr_freq_t->t2 > p_ddr_freq_t->screen_ft_us*1000) && (p_ddr_freq_t->screen_ft_us != 0xfefefefe)) {
2251                         ret = 0;
2252                         goto end;
2253                 } else {
2254                         rk_fb_poll_wait_frame_complete();
2255                 }
2256         }
2257 #endif
2258     /*8KB SRAM*/
2259         for (i = 0; i < 2; i++) {
2260                 n = temp[1024 * i];
2261                 barrier();
2262         }
2263         n = pDDR_Reg->SCFG.d32;
2264         n = pPHY_Reg->PHY_REG1;
2265         n = pCRU_Reg->CRU_PLL_CON[0][0];
2266         n = *(volatile uint32_t *)SysSrv_DdrTiming;
2267         n = pGRF_Reg->GRF_SOC_STATUS0;
2268         dsb();
2269         param.freq = ret;
2270         param.freq_slew = freq_slew;
2271         call_with_stack(fn_to_pie
2272                         (rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
2273                         &param,
2274                         rockchip_sram_stack - (NR_CPUS -
2275                                                1) * PAUSE_CPU_STACK_SIZE);
2276     /** 5. Issues a Mode Exit command   */
2277         ddr_dtt_check();
2278 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
2279 end:
2280 #endif
2281         local_fiq_enable();
2282         local_irq_restore(flags);
2283 /*    clk_set_rate(clk_get(NULL, "ddr_pll"), 0);    */
2284 out:
2285         return ret;
2286 }
2287
2288 bool DEFINE_PIE_DATA(cpu_pause[NR_CPUS]);
2289 volatile bool *DATA(p_cpu_pause);
2290 static inline bool is_cpu0_paused(unsigned int cpu)
2291 {
2292         smp_rmb();
2293         return DATA(cpu_pause)[0];
2294 }
2295
2296 static inline void set_cpuX_paused(unsigned int cpu, bool pause)
2297 {
2298         DATA(cpu_pause)[cpu] = pause;
2299         smp_wmb();
2300 }
2301
2302 static inline bool is_cpuX_paused(unsigned int cpu)
2303 {
2304         smp_rmb();
2305         return DATA(p_cpu_pause)[cpu];
2306 }
2307
2308 static inline void set_cpu0_paused(bool pause)
2309 {
2310         DATA(p_cpu_pause)[0] = pause;
2311         smp_wmb();
2312 }
2313
2314 #define MAX_TIMEOUT (16000000UL << 6)   /*>0.64s*/
2315
2316 /* Do not use stack, safe on SMP */
2317 void PIE_FUNC(_pause_cpu)(void *arg)
2318 {
2319         unsigned int cpu = (unsigned int)arg;
2320
2321         set_cpuX_paused(cpu, true);
2322         while (is_cpu0_paused(cpu))
2323     ;
2324         set_cpuX_paused(cpu, false);
2325 }
2326
2327 static void pause_cpu(void *info)
2328 {
2329         unsigned int cpu = raw_smp_processor_id();
2330
2331         call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(_pause_cpu)),
2332                         (void *)cpu,
2333                         rockchip_sram_stack - (cpu - 1) * PAUSE_CPU_STACK_SIZE);
2334 }
2335
2336 static void wait_cpu(void *info)
2337 {
2338 }
2339
2340 static int call_with_single_cpu(u32(*fn) (void *arg), void *arg)
2341 {
2342         u32 timeout = MAX_TIMEOUT;
2343         unsigned int cpu;
2344         unsigned int this_cpu = smp_processor_id();     /*»ñÈ¡µ±Ç°cpu*/
2345         int ret = 0;
2346         cpu_maps_update_begin();
2347         local_bh_disable();     /*disable swi*/
2348         set_cpu0_paused(true);
2349         smp_call_function((smp_call_func_t) pause_cpu, NULL, 0);
2350
2351         for_each_online_cpu(cpu) {
2352                 if (cpu == this_cpu)
2353                         continue;
2354                 while (!is_cpuX_paused(cpu) && --timeout)
2355                     ;
2356                 if (timeout == 0) {
2357                         pr_err("pause cpu %d timeout\n", cpu);
2358                         goto out;
2359                 }
2360         }
2361
2362         ret = fn(arg);
2363
2364 out:
2365         set_cpu0_paused(false);
2366         local_bh_enable();
2367         smp_call_function(wait_cpu, NULL, true);
2368         cpu_maps_update_done();
2369
2370         return ret;
2371 }
2372
2373 static int __ddr_change_freq(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
2374 {
2375         freq_t freq;
2376         int ret = 0;
2377
2378         freq.nMHz = nMHz;
2379         freq.p_ddr_freq_t = &ddr_freq_t;
2380         ret = call_with_single_cpu(&ddr_change_freq_sram, (void *)&freq);
2381         /*ret = ddr_change_freq_sram((void*)&freq);*/
2382         return ret;
2383 }
2384
2385 static int _ddr_change_freq(uint32 nMHz)
2386 {
2387         struct ddr_freq_t ddr_freq_t;
2388 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
2389         unsigned long remain_t, vblank_t, pass_t;
2390         static unsigned long reserve_t = 800;   /*us*/
2391         unsigned long long tmp;
2392         int test_count = 0;
2393 #endif
2394         int ret;
2395
2396         memset(&ddr_freq_t, 0x00, sizeof(ddr_freq_t));
2397
2398 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
2399         do {
2400                 ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
2401                 ddr_freq_t.t0 = rk_fb_get_prmry_screen_framedone_t();
2402                 if (!ddr_freq_t.screen_ft_us)
2403                         return __ddr_change_freq(nMHz, ddr_freq_t);
2404
2405                 tmp = cpu_clock(0) - ddr_freq_t.t0;
2406                 do_div(tmp, 1000);
2407                 pass_t = tmp;
2408                 /*lost frame interrupt*/
2409                 while (pass_t > ddr_freq_t.screen_ft_us) {
2410                         int n = pass_t / ddr_freq_t.screen_ft_us;
2411
2412                         /*printk("lost frame int, pass_t:%lu\n", pass_t);*/
2413                         pass_t -= n * ddr_freq_t.screen_ft_us;
2414                         ddr_freq_t.t0 += n * ddr_freq_t.screen_ft_us * 1000;
2415                 }
2416
2417                 remain_t = ddr_freq_t.screen_ft_us - pass_t;
2418                 if (remain_t < reserve_t) {
2419                         /*printk("remain_t(%lu) < reserve_t(%lu)\n", remain_t, reserve_t);*/
2420                         vblank_t = rk_fb_get_prmry_screen_vbt();
2421                         usleep_range(remain_t + vblank_t, remain_t + vblank_t);
2422                         continue;
2423                 }
2424                 /*test 10 times*/
2425                 test_count++;
2426                 if (test_count > 10) {
2427                         ddr_freq_t.screen_ft_us = 0xfefefefe;
2428                 }
2429                 /*printk("ft:%lu, pass_t:%lu, remaint_t:%lu, reservet_t:%lu\n",
2430                  *     ddr_freq_t.screen_ft_us, (unsigned long)pass_t, remain_t, reserve_t);*/
2431                 usleep_range(remain_t - reserve_t, remain_t - reserve_t);
2432                 flush_tlb_all();
2433
2434                 ret = __ddr_change_freq(nMHz, ddr_freq_t);
2435                 if (ret) {
2436                         reserve_t = 800;
2437                         return ret;
2438                 } else {
2439                         if (reserve_t < 3000)
2440                                 reserve_t += 200;
2441                 }
2442         } while (1);
2443 #else
2444         ret = __ddr_change_freq(nMHz, ddr_freq_t);
2445 #endif
2446
2447         return ret;
2448 }
2449
2450 EXPORT_SYMBOL(_ddr_change_freq);
2451
2452 /*----------------------------------------------------------------------
2453 *Name    : void ddr_set_auto_self_refresh(bool en)
2454 *Desc    : ÉèÖýøÈë selfrefesh µÄÖÜÆÚÊý
2455 *Params  : en -> Ê¹ÄÜauto selfrefresh
2456 *Return  : ÆµÂÊÖµ
2457 *Notes   : ÖÜÆÚÊýΪ1*32 cycle
2458 *----------------------------------------------------------------------*/
2459 void _ddr_set_auto_self_refresh(bool en)
2460 {
2461         /*set auto self-refresh idle    */
2462         *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
2463 }
2464
2465 EXPORT_SYMBOL(_ddr_set_auto_self_refresh);
2466
2467 /*----------------------------------------------------------------------
2468 *Name    : void __sramfunc ddr_suspend(void)
2469 *Desc    : ½øÈëddr suspend
2470 *Params  : void
2471 *Return  : void
2472 *Notes   :
2473 *----------------------------------------------------------------------*/
2474 #if 1
2475 void PIE_FUNC(ddr_suspend)(void)
2476 {
2477         ddr_selfrefresh_enter(0);
2478         pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x0 << (1 * 4));    /*PLL slow-mode*/
2479         dsb();
2480         ddr_delayus(1);
2481         pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x1 << 13);        /*PLL power-down*/
2482         dsb();
2483         ddr_delayus(1);
2484
2485 }
2486
2487 EXPORT_PIE_SYMBOL(FUNC(ddr_suspend));
2488
2489 void ddr_suspend(void)
2490 {
2491         uint32 i;
2492         volatile uint32 n;
2493         volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
2494     /** 1. Make sure there is no host access */
2495         flush_cache_all();
2496         outer_flush_all();
2497     /*flush_tlb_all();*/
2498
2499     /*sram size = 8KB*/
2500         for (i = 0; i < 2; i++) {
2501                 n = temp[1024 * i];
2502                 barrier();
2503         }
2504         n = pDDR_Reg->SCFG.d32;
2505         n = pPHY_Reg->PHY_REG1;
2506         n = pCRU_Reg->CRU_PLL_CON[0][0];
2507         n = *(volatile uint32_t *)SysSrv_DdrTiming;
2508         n = pGRF_Reg->GRF_SOC_STATUS0;
2509         dsb();
2510
2511         fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_suspend)) ();
2512 }
2513
2514 EXPORT_SYMBOL(ddr_suspend);
2515 #endif
2516
2517 #if 1
2518 /*----------------------------------------------------------------------
2519 *Name    : void __sramfunc ddr_resume(void)
2520 *Desc    : ddr resume
2521 *Params  : void
2522 *Return  : void
2523 *Notes   :
2524 *----------------------------------------------------------------------*/
2525 void PIE_FUNC(ddr_resume)(void)
2526 {
2527         uint32 delay = 1000;
2528
2529         pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x0 << 13);        /*PLL no power-down*/
2530         dsb();
2531         while (delay > 0) {
2532                 ddr_delayus(1);
2533                 if (pCRU_Reg->CRU_PLL_CON[1][1] & (0x1 << 10))
2534                         break;
2535                 delay--;
2536         }
2537
2538         pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x1 << (1 * 4));    /*PLL normal*/
2539         dsb();
2540
2541         ddr_selfrefresh_exit();
2542 }
2543
2544 EXPORT_PIE_SYMBOL(FUNC(ddr_resume));
2545
2546 void ddr_resume(void)
2547 {
2548         fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)) ();
2549 }
2550
2551 EXPORT_SYMBOL(ddr_resume);
2552 #endif
2553
2554 /*----------------------------------------------------------------------
2555 *Name    : uint32 ddr_get_cap(void)
2556 *Desc    : »ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
2557 *Params  : void
2558 *Return  : ¿ÅÁ£ÈÝÁ¿
2559 *Notes   :
2560 *----------------------------------------------------------------------*/
2561 uint32 ddr_get_cap(void)
2562 {
2563         uint32 cs, bank, row, col, row1, bw;
2564
2565         bank = READ_BK_INFO();
2566         row = READ_CS0_ROW_INFO();
2567         col = READ_COL_INFO();
2568         cs = READ_CS_INFO();
2569         bw = READ_BW_INFO();
2570         if (cs > 1) {
2571                 row1 = READ_CS1_ROW_INFO();
2572                 return ((1 << (row + col + bank + bw)) +
2573                         (1 << (row1 + col + bank + bw)));
2574         } else {
2575                 return (1 << (row + col + bank + bw));
2576         }
2577 }
2578
2579 EXPORT_SYMBOL(ddr_get_cap);
2580
2581 static long _ddr_round_rate(uint32 nMHz)
2582 {
2583         return p_ddr_set_pll(nMHz, 0);
2584 }
2585
2586 /*----------------------------------------------------------------------
2587 *Name    : int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
2588 *Desc    : ddr  ³õʼ»¯º¯Êý
2589 *Params  : dram_speed_bin ->ddr¿ÅÁ£ÀàÐÍ
2590 *          freq ->ƵÂÊÖµ
2591 *Return  : 0 ³É¹¦
2592 *Notes   :
2593 *----------------------------------------------------------------------*/
2594 int ddr_init(uint32_t dram_speed_bin, uint32 freq)
2595 {
2596         uint32_t value = 0;
2597         uint32_t cs, die = 1;
2598         /*uint32_t calStatusLeft, calStatusRight*/
2599         struct clk *clk;
2600         ddr_print("version 1.01 20140815\n");
2601         cs = READ_CS_INFO();    /*case 0:1rank ; case 1:2rank*/
2602
2603         p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
2604         p_ddr_freq = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
2605         p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
2606         DATA(p_cpu_pause) =
2607             kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
2608         p_ddr_reg->mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) & 0x7);
2609         p_ddr_reg->ddr_speed_bin = dram_speed_bin;
2610         *p_ddr_freq = 0;
2611         *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
2612         *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_dll_status)) =
2613             DDR3_DLL_DISABLE;
2614         p_copy_data = kern_to_pie(rockchip_pie_chunk, &copy_data[0]);
2615         if (p_ddr_reg->mem_type != DDR3) {
2616                 ddr_print("ddr type error type=%d\n", (p_ddr_reg->mem_type));
2617                 return -1;
2618         }
2619
2620         switch (READ_DIE_BW_INFO()) {
2621         case 0:         /*8bit*/
2622                 die = 2;
2623                 break;
2624         case 1:         /*16bit*/
2625                 die = 1;
2626                 break;
2627         default:
2628                 ddr_print("ddr die BW error=%d\n", READ_DIE_BW_INFO());
2629                 break;
2630         }
2631
2632         /*get capability per chip, not total size, used for calculate tRFC*/
2633         p_ddr_reg->ddr_capability_per_die = ddr_get_cap() / (cs * die);
2634         ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n",
2635                                                 cs, READ_CS0_ROW_INFO(),
2636                                                 (0x1 << (READ_BK_INFO())),
2637                                                 READ_COL_INFO(),
2638                                                 (ddr_get_cap() >> 20));
2639 #if 0
2640         while (stop)
2641         ;
2642         _ddr_change_freq(freq);
2643         ddr_print("init success!!! freq=%dMHz\n", freq);
2644 #endif
2645         clk = clk_get(NULL, "clk_ddr");
2646         if (IS_ERR(clk)) {
2647                 ddr_print("failed to get ddr clk\n");
2648                 clk = NULL;
2649         }
2650         if (freq != 0)
2651                 value = clk_set_rate(clk, 1000 * 1000 * freq);
2652         else
2653                 value = clk_set_rate(clk, clk_get_rate(clk));
2654         ddr_print("init success!!! freq=%luMHz\n",
2655                   clk ? clk_get_rate(clk) / 2000000 : freq);
2656
2657         return 0;
2658 }
2659
2660 EXPORT_SYMBOL(ddr_init);
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