arch/arm/mach-rockchip/ddr_freq.c

   1 #define pr_fmt(fmt) "ddrfreq: " fmt
   2 #define DEBUG
   3 #include <linux/clk.h>
   4 #include <linux/fb.h>
   5 #include <linux/cpu.h>
   6 #include <linux/cpufreq.h>
   7 #include <linux/delay.h>
   8 #include <linux/freezer.h>
   9 #include <linux/fs.h>
  10 #include <linux/kthread.h>
  11 #include <linux/miscdevice.h>
  12 #include <linux/module.h>
  13 #include <linux/reboot.h>
  14 #include <linux/slab.h>
  15 #include <linux/uaccess.h>
  16 #include <linux/sched/rt.h>
  17 #include <linux/of.h>
  18 #include <linux/fb.h>
  19 #include <linux/input.h>
  20 #include <asm/cacheflush.h>
  21 #include <asm/tlbflush.h>
  22 #include <linux/vmalloc.h>
  23 #include <linux/rockchip/common.h>
  24 #include <linux/rockchip/dvfs.h>
  25 #include <dt-bindings/clock/ddr.h>
  26 #include <dt-bindings/clock/rk_system_status.h>
  27 #include <asm/io.h>
  28 #include <linux/rockchip/grf.h>
  29 #include <linux/rockchip/iomap.h>
  30 #include <linux/clk-private.h>
  31 #include <linux/rockchip/cpu.h>
  32 #include "../../../drivers/clk/rockchip/clk-pd.h"
  33 #include "cpu_axi.h"
  34
  35 #ifdef CONFIG_CPU_FREQ
  36 extern int rockchip_cpufreq_reboot_limit_freq(void);
  37 #else
  38 static inline int rockchip_cpufreq_reboot_limit_freq(void) { return 0; }
  39 #endif
  40
  41 static DECLARE_COMPLETION(ddrfreq_completion);
  42 static DEFINE_MUTEX(ddrfreq_mutex);
  43
  44 #define VOP_REQ_BLOCK
  45 #ifdef VOP_REQ_BLOCK
  46 static DECLARE_COMPLETION(vop_req_completion);
  47 #endif
  48
  49 static struct dvfs_node *clk_cpu_dvfs_node = NULL;
  50 static int ddr_boost = 0;
  51 static int print=0;
  52 static int watch=0;
  53 static int high_load = 70;
  54 static int low_load = 60;
  55 static int auto_freq_interval_ms = 20;
  56 static long down_rate_delay_ms = 500;
  57 static unsigned long *auto_freq_table = NULL;
  58 static int cur_freq_index;
  59 static int auto_freq_table_size;
  60 static unsigned long vop_bandwidth_update_jiffies = 0, vop_bandwidth = 0;
  61 static int vop_bandwidth_update_flag = 0;
  62 static struct ddr_bw_info ddr_bw_ch0 = {0}, ddr_bw_ch1 = {0};
  63
  64 enum {
  65         DEBUG_DDR = 1U << 0,
  66         DEBUG_VIDEO_STATE = 1U << 1,
  67         DEBUG_SUSPEND = 1U << 2,
  68         DEBUG_VERBOSE = 1U << 3,
  69 };
  70 static int debug_mask = DEBUG_DDR;
  71
  72 module_param(debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  73 #define dprintk(mask, fmt, ...) do { if (mask & debug_mask) pr_debug(fmt, ##__VA_ARGS__); } while (0)
  74
  75 #define MHZ     (1000*1000)
  76 #define KHZ     1000
  77
  78 struct video_info {
  79         int width;
  80         int height;
  81         int ishevc;
  82         int videoFramerate;
  83         int streamBitrate;
  84
  85         struct list_head node;
  86 };
  87
  88 struct ddr {
  89         struct dvfs_node *clk_dvfs_node;
  90         struct list_head video_info_list;
  91         unsigned long normal_rate;
  92         unsigned long video_1080p_rate;
  93         unsigned long video_4k_rate;
  94         unsigned long performance_rate;
  95         unsigned long dualview_rate;
  96         unsigned long hdmi_rate;
  97         unsigned long idle_rate;
  98         unsigned long suspend_rate;
  99         unsigned long reboot_rate;
 100         unsigned long boost_rate;
 101         unsigned long isp_rate;
 102         bool auto_freq;
 103         bool auto_self_refresh;
 104         char *mode;
 105         unsigned long sys_status;
 106         struct task_struct *task;
 107         wait_queue_head_t wait;
 108 };
 109 static struct ddr ddr;
 110
 111 module_param_named(sys_status, ddr.sys_status, ulong, S_IRUGO);
 112 module_param_named(auto_self_refresh, ddr.auto_self_refresh, bool, S_IRUGO);
 113 module_param_named(mode, ddr.mode, charp, S_IRUGO);
 114
 115 static unsigned long auto_freq_round(unsigned long freq)
 116 {
 117         int i;
 118
 119         if (!auto_freq_table)
 120                 return -EINVAL;
 121
 122         for (i = 0; auto_freq_table[i] != 0; i++) {
 123                 if (auto_freq_table[i] >= freq) {
 124                         return auto_freq_table[i];
 125                 }
 126         }
 127
 128         return auto_freq_table[i-1];
 129 }
 130
 131 static unsigned long auto_freq_get_index(unsigned long freq)
 132 {
 133         int i;
 134
 135         if (!auto_freq_table)
 136                 return 0;
 137
 138         for (i = 0; auto_freq_table[i] != 0; i++) {
 139                 if (auto_freq_table[i] >= freq) {
 140                         return i;
 141                 }
 142         }
 143         return i-1;
 144 }
 145
 146 static unsigned int auto_freq_update_index(unsigned long freq)
 147 {
 148         cur_freq_index = auto_freq_get_index(freq);
 149
 150         return cur_freq_index;
 151 }
 152
 153
 154 static unsigned long auto_freq_get_next_step(void)
 155 {
 156         if (cur_freq_index < auto_freq_table_size-1) {
 157                         return auto_freq_table[cur_freq_index+1];
 158         }
 159
 160         return auto_freq_table[cur_freq_index];
 161 }
 162
 163 static void ddrfreq_mode(bool auto_self_refresh, unsigned long target_rate, char *name)
 164 {
 165         unsigned int min_rate, max_rate;
 166         int freq_limit_en;
 167
 168         ddr.mode = name;
 169         if (auto_self_refresh != ddr.auto_self_refresh) {
 170                 ddr_set_auto_self_refresh(auto_self_refresh);
 171                 ddr.auto_self_refresh = auto_self_refresh;
 172                 dprintk(DEBUG_DDR, "change auto self refresh to %d when %s\n", auto_self_refresh, name);
 173         }
 174
 175         if (target_rate != dvfs_clk_get_last_set_rate(ddr.clk_dvfs_node)) {
 176                 freq_limit_en = dvfs_clk_get_limit(clk_cpu_dvfs_node, &min_rate, &max_rate);
 177
 178                 dvfs_clk_enable_limit(clk_cpu_dvfs_node, 600000000, -1);
 179                 if (dvfs_clk_set_rate(ddr.clk_dvfs_node, target_rate) == 0) {
 180                         target_rate = dvfs_clk_get_rate(ddr.clk_dvfs_node);
 181                         auto_freq_update_index(target_rate);
 182                         dprintk(DEBUG_DDR, "change freq to %lu MHz when %s\n", target_rate / MHZ, name);
 183                 }
 184
 185                 if (freq_limit_en) {
 186                         dvfs_clk_enable_limit(clk_cpu_dvfs_node, min_rate, max_rate);
 187                 } else {
 188                         dvfs_clk_disable_limit(clk_cpu_dvfs_node);
 189                 }
 190         }
 191 }
 192
 193 unsigned long req_freq_by_vop(unsigned long bandwidth)
 194 {
 195         if (time_after(jiffies, vop_bandwidth_update_jiffies+down_rate_delay_ms))
 196                 return 0;
 197
 198         if (bandwidth >= 5000){
 199                 return 800000000;
 200         }
 201
 202         if (bandwidth >= 3500) {
 203                 return 456000000;
 204         }
 205
 206         if (bandwidth >= 2600) {
 207                 return 396000000;
 208         }
 209         if (bandwidth >= 2000) {
 210                 return 324000000;
 211         }
 212
 213         return 0;
 214 }
 215
 216 static void ddr_auto_freq(void)
 217 {
 218         unsigned long freq, new_freq=0, vop_req_freq=0, total_bw_req_freq=0;
 219         u32 ddr_percent, target_load;
 220         static u32 local_jiffies=0, max_ddr_percent=0;
 221
 222         if (!local_jiffies)
 223                 local_jiffies = jiffies;
 224         freq = dvfs_clk_get_rate(ddr.clk_dvfs_node);
 225
 226         ddr_bandwidth_get(&ddr_bw_ch0, &ddr_bw_ch1);
 227         ddr_percent = ddr_bw_ch0.ddr_percent;
 228
 229         if ((watch)||(print)) {
 230                 if((watch == 2)&& (ddr_bw_ch0.ddr_percent < max_ddr_percent)) {
 231                     return;
 232                 } else if(watch == 2) {
 233                     max_ddr_percent = ddr_bw_ch0.ddr_percent;
 234                 }
 235                 printk("Unit:MB/s total  use%%    rd    wr  cpum   gpu  peri video  vio0  vio1  vio2\n");
 236                 printk("%3u(ms): %5u %5u %5u %5u %5u %5u %5u %5u %5u %5u %5u\n",
 237                         ddr_bw_ch0.ddr_time,
 238                         ddr_bw_ch0.ddr_total,
 239                         ddr_bw_ch0.ddr_percent,
 240                         ddr_bw_ch0.ddr_rd,
 241                         ddr_bw_ch0.ddr_wr,
 242                         ddr_bw_ch0.cpum,
 243                         ddr_bw_ch0.gpu,
 244                         ddr_bw_ch0.peri,
 245                         ddr_bw_ch0.video,
 246                         ddr_bw_ch0.vio0,
 247                         ddr_bw_ch0.vio1,
 248                         ddr_bw_ch0.vio2);
 249
 250                 if (watch)
 251                         return;
 252         }
 253
 254         if (ddr_boost) {
 255                 ddr_boost = 0;
 256                 new_freq = max(ddr.boost_rate, new_freq);
 257         }
 258
 259         if(ddr_percent > high_load){
 260                 total_bw_req_freq = auto_freq_get_next_step();
 261         } else if (ddr_percent < low_load){
 262                 target_load = (low_load+high_load)/2;
 263                 total_bw_req_freq = ddr_percent*(freq/target_load);
 264         }
 265         new_freq = max(total_bw_req_freq, new_freq);
 266
 267         vop_req_freq = req_freq_by_vop(vop_bandwidth);
 268         new_freq = max(vop_req_freq, new_freq);
 269
 270         new_freq = auto_freq_round(new_freq);
 271
 272         if (new_freq < freq) {
 273                 if (time_after(jiffies, local_jiffies+down_rate_delay_ms/10)) {
 274                         local_jiffies = jiffies;
 275                         ddrfreq_mode(false, new_freq, "auto down rate");
 276                 }
 277         } else if(new_freq > freq){
 278                 local_jiffies = jiffies;
 279                 ddrfreq_mode(false, new_freq, "auto up rate");
 280         }
 281 }
 282
 283 static noinline long ddrfreq_work(unsigned long sys_status)
 284 {
 285         long timeout = MAX_SCHEDULE_TIMEOUT;
 286         unsigned long target_rate = 0;
 287         unsigned long s = sys_status;
 288         bool auto_self_refresh = false;
 289         char *mode = NULL;
 290
 291         dprintk(DEBUG_VERBOSE, "sys_status %02lx\n", sys_status);
 292
 293         if (ddr.reboot_rate && (s & SYS_STATUS_REBOOT)) {
 294                 ddrfreq_mode(false, ddr.reboot_rate, "shutdown/reboot");
 295
 296                 return timeout;
 297         }
 298
 299         if (ddr.suspend_rate && (s & SYS_STATUS_SUSPEND)) {
 300                 if (ddr.suspend_rate > target_rate) {
 301                         target_rate = ddr.suspend_rate;
 302                         auto_self_refresh = true;
 303                         mode = "suspend";
 304                 }
 305         }
 306
 307         if (ddr.performance_rate && (s & SYS_STATUS_PERFORMANCE)) {
 308                 if (ddr.performance_rate > target_rate) {
 309                         target_rate = ddr.performance_rate;
 310                         auto_self_refresh = false;
 311                         mode = "performance";
 312                 }
 313         }
 314
 315          if (ddr.dualview_rate &&
 316                 (s & SYS_STATUS_LCDC0) && (s & SYS_STATUS_LCDC1)) {
 317                  if (ddr.dualview_rate > target_rate) {
 318                          target_rate = ddr.dualview_rate;
 319                          auto_self_refresh = false;
 320                          mode = "dual-view";
 321                  }
 322          }
 323
 324          if (ddr.hdmi_rate &&
 325                 (s & SYS_STATUS_HDMI)) {
 326                  if (ddr.hdmi_rate > target_rate) {
 327                          target_rate = ddr.hdmi_rate;
 328                          auto_self_refresh = false;
 329                          mode = "hdmi";
 330                  }
 331          }
 332
 333         if (ddr.video_4k_rate && (s & SYS_STATUS_VIDEO_4K)) {
 334                 if (ddr.video_4k_rate > target_rate) {
 335                         target_rate = ddr.video_4k_rate;
 336                         auto_self_refresh = false;
 337                         mode = "video_4k";
 338                 }
 339         }
 340
 341         if (ddr.video_1080p_rate && (s & SYS_STATUS_VIDEO_1080P)) {
 342                 if (ddr.video_1080p_rate > target_rate) {
 343                         target_rate = ddr.video_1080p_rate;
 344                         auto_self_refresh = false;
 345                         mode = "video_1080p";
 346                 }
 347         }
 348
 349         if (ddr.isp_rate && (s & SYS_STATUS_ISP)) {
 350                 if (ddr.isp_rate > target_rate) {
 351                         target_rate = ddr.isp_rate;
 352                         auto_self_refresh = false;
 353                         mode = "isp";
 354                 }
 355         }
 356
 357         if (target_rate > 0) {
 358                 ddrfreq_mode(auto_self_refresh, target_rate, mode);
 359         } else {
 360                 if (ddr.auto_freq) {
 361                         ddr_auto_freq();
 362                         timeout = auto_freq_interval_ms/10;
 363                 }
 364                 else {
 365                         ddrfreq_mode(false, ddr.normal_rate, "normal");
 366                 }
 367         }
 368
 369         return timeout;
 370 #if 0
 371
 372         if (ddr.reboot_rate && (s & SYS_STATUS_REBOOT)) {
 373                 ddrfreq_mode(false, &ddr.reboot_rate, "shutdown/reboot");
 374                 rockchip_cpufreq_reboot_limit_freq();
 375                 reboot_config_done = 1;
 376         } else if (ddr.suspend_rate && (s & SYS_STATUS_SUSPEND)) {
 377                 ddrfreq_mode(true, &ddr.suspend_rate, "suspend");
 378         } else if (ddr.dualview_rate &&
 379                 (s & SYS_STATUS_LCDC0) && (s & SYS_STATUS_LCDC1)) {
 380                 ddrfreq_mode(false, &ddr.dualview_rate, "dual-view");
 381         } else if (ddr.video_1080p_rate && (s & SYS_STATUS_VIDEO_1080P)) {
 382                 ddrfreq_mode(false, &ddr.video_1080p_rate, "video_1080p");
 383         } else if (ddr.video_4k_rate && (s & SYS_STATUS_VIDEO_4K)) {
 384                 ddrfreq_mode(false, &ddr.video_4k_rate, "video_4k");
 385         } else if (ddr.performance_rate && (s & SYS_STATUS_PERFORMANCE)) {
 386                 ddrfreq_mode(false, &ddr.performance_rate, "performance");
 387         }  else if (ddr.isp_rate && (s & SYS_STATUS_ISP)) {
 388                 ddrfreq_mode(false, &ddr.isp_rate, "isp");
 389         } else if (ddr.idle_rate
 390                 && !(s & SYS_STATUS_GPU)
 391                 && !(s & SYS_STATUS_RGA)
 392                 && !(s & SYS_STATUS_CIF0)
 393                 && !(s & SYS_STATUS_CIF1)
 394                 && (clk_get_rate(cpu) < 816 * MHZ)
 395                 && (clk_get_rate(gpu) <= 200 * MHZ)
 396                 ) {
 397                 ddrfreq_mode(false, &ddr.idle_rate, "idle");
 398         } else {
 399                 if (ddr.auto_freq) {
 400                         ddr_auto_freq();
 401                         timeout = auto_freq_interval_ms;
 402                 }
 403                 else {
 404                         ddrfreq_mode(false, &ddr.normal_rate, "normal");
 405                 }
 406         }
 407
 408
 409
 410         return timeout;
 411 #endif
 412 }
 413
 414 static int ddrfreq_task(void *data)
 415 {
 416         long timeout;
 417         unsigned long status=ddr.sys_status, old_status=ddr.sys_status;
 418
 419         set_freezable();
 420
 421         do {
 422                 status = ddr.sys_status;
 423                 if (vop_bandwidth_update_flag) {
 424                         vop_bandwidth_update_flag = 0;
 425 #ifdef VOP_REQ_BLOCK
 426                         complete(&vop_req_completion);
 427 #endif
 428                 }
 429
 430                 timeout = ddrfreq_work(status);
 431                 if (old_status != status) {
 432                         complete(&ddrfreq_completion);
 433                 }
 434                 wait_event_freezable_timeout(ddr.wait, vop_bandwidth_update_flag || (status != ddr.sys_status) || kthread_should_stop(), timeout);
 435                 old_status = status;
 436         } while (!kthread_should_stop());
 437
 438         return 0;
 439 }
 440
 441 void add_video_info(struct video_info *video_info)
 442 {
 443         if (video_info)
 444                 list_add(&video_info->node, &ddr.video_info_list);
 445 }
 446
 447 void del_video_info(struct video_info *video_info)
 448 {
 449         if (video_info) {
 450                 list_del(&video_info->node);
 451                 kfree(video_info);
 452         }
 453 }
 454
 455 void clear_video_info(void)
 456 {
 457         struct video_info *video_info, *next;
 458
 459         list_for_each_entry_safe(video_info, next, &ddr.video_info_list, node) {
 460                 del_video_info(video_info);
 461         }
 462 }
 463
 464 struct video_info *find_video_info(struct video_info *match_video_info)
 465 {
 466         struct video_info *video_info;
 467
 468         if (!match_video_info)
 469                 return NULL;
 470
 471         list_for_each_entry(video_info, &ddr.video_info_list, node) {
 472                 if ((video_info->width == match_video_info->width)
 473                         && (video_info->height == match_video_info->height)
 474                         && (video_info->ishevc== match_video_info->ishevc)
 475                         && (video_info->videoFramerate == match_video_info->videoFramerate)
 476                         && (video_info->streamBitrate== match_video_info->streamBitrate)) {
 477
 478                         return video_info;
 479                 }
 480
 481         }
 482
 483         return NULL;
 484 }
 485
 486 void update_video_info(void)
 487 {
 488         struct video_info *video_info, *max_res_video;
 489         int max_res=0, res=0;
 490
 491         if (list_empty(&ddr.video_info_list)) {
 492                 rockchip_clear_system_status(SYS_STATUS_VIDEO_1080P|SYS_STATUS_VIDEO_4K);
 493                 return;
 494         }
 495
 496         list_for_each_entry(video_info, &ddr.video_info_list, node) {
 497                 res = video_info->width * video_info->height;
 498                 if (res > max_res) {
 499                         max_res = res;
 500                         max_res_video = video_info;
 501                 }
 502         }
 503
 504         if (max_res <= 1920*1080)
 505                 rockchip_set_system_status(SYS_STATUS_VIDEO_1080P);
 506         else
 507                 rockchip_set_system_status(SYS_STATUS_VIDEO_4K);
 508
 509         return;
 510 }
 511
 512 /***format: width=val,height=val,ishevc=val,videoFramerate=val,streamBitrate=val***/
 513 static long get_video_param(char **str)
 514 {
 515         char *p;
 516
 517         strsep(str,"=");
 518         p=strsep(str,",");
 519         if (p)
 520                 return simple_strtol(p,NULL,10);
 521
 522         return 0;
 523 }
 524
 525 static ssize_t video_state_write(struct file *file, const char __user *buffer,
 526                                  size_t count, loff_t *ppos)
 527 {
 528         struct video_info *video_info = NULL;
 529         char state, *cookie_pot, *buf = vzalloc(count);
 530         cookie_pot = buf;
 531
 532         if(!buf)
 533                 return -ENOMEM;
 534
 535         if (count < 1){
 536                 vfree(buf);
 537                 return -EPERM;
 538         }
 539
 540         if (copy_from_user(cookie_pot, buffer, count)) {
 541                 vfree(buf);
 542                 return -EFAULT;
 543         }
 544
 545         dprintk(DEBUG_VIDEO_STATE, "%s: %s,len %d\n", __func__, cookie_pot,count);
 546
 547         state=cookie_pot[0];
 548         if( (count>=3) && (cookie_pot[2]=='w') )
 549         {
 550                 video_info = kzalloc(sizeof(struct video_info), GFP_KERNEL);
 551                 if (!video_info){
 552                         vfree(buf);
 553                         return -ENOMEM;
 554                 }
 555                 INIT_LIST_HEAD(&video_info->node);
 556
 557                 strsep(&cookie_pot,",");
 558
 559                 video_info->width = get_video_param(&cookie_pot);
 560                 video_info->height = get_video_param(&cookie_pot);
 561                 video_info->ishevc = get_video_param(&cookie_pot);
 562                 video_info->videoFramerate = get_video_param(&cookie_pot);
 563                 video_info->streamBitrate = get_video_param(&cookie_pot);
 564
 565                 dprintk(DEBUG_VIDEO_STATE, "%s: video_state=%c,width=%d,height=%d,ishevc=%d,videoFramerate=%d,streamBitrate=%d\n",
 566                         __func__, state,video_info->width,video_info->height,
 567                         video_info->ishevc, video_info->videoFramerate,
 568                         video_info->streamBitrate);
 569
 570         }
 571         switch (state) {
 572         case '0':
 573                 del_video_info(find_video_info(video_info));
 574                 kfree(video_info);
 575                 update_video_info();
 576                 break;
 577         case '1':
 578                 add_video_info(video_info);
 579                 update_video_info();
 580                 break;
 581         case 'p'://performance
 582                 rockchip_set_system_status(SYS_STATUS_PERFORMANCE);
 583                 break;
 584         case 'n'://normal
 585                 rockchip_clear_system_status(SYS_STATUS_PERFORMANCE);
 586                 break;
 587         default:
 588                 vfree(buf);
 589                 return -EINVAL;
 590
 591         }
 592
 593         vfree(buf);
 594         return count;
 595 }
 596
 597 static int video_state_release(struct inode *inode, struct file *file)
 598 {
 599         dprintk(DEBUG_VIDEO_STATE, "video_state release\n");
 600         clear_video_info();
 601         update_video_info();
 602         return 0;
 603 }
 604
 605
 606 static const struct file_operations video_state_fops = {
 607         .owner  = THIS_MODULE,
 608         .release= video_state_release,
 609         .write  = video_state_write,
 610 };
 611
 612 static struct miscdevice video_state_dev = {
 613         .fops   = &video_state_fops,
 614         .name   = "video_state",
 615         .minor  = MISC_DYNAMIC_MINOR,
 616 };
 617
 618 static long ddr_freq_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 619 {
 620         unsigned long bandwidth = *(int*)arg;
 621         unsigned long vop_req_freq;
 622         int ret = -1;
 623
 624         vop_bandwidth = bandwidth;
 625         vop_bandwidth_update_jiffies = jiffies;
 626         vop_req_freq = req_freq_by_vop(bandwidth);
 627         if (dvfs_clk_get_rate(ddr.clk_dvfs_node) >= vop_req_freq) {
 628                 ret = 0;
 629         }
 630
 631         vop_bandwidth_update_flag = 1;
 632         wake_up(&ddr.wait);
 633 #ifdef VOP_REQ_BLOCK
 634         wait_for_completion(&vop_req_completion);
 635 #endif
 636
 637         return ret;
 638 }
 639
 640
 641 static const struct file_operations ddr_freq_fops = {
 642         .owner  = THIS_MODULE,
 643         .unlocked_ioctl = ddr_freq_ioctl,
 644 };
 645
 646 static struct miscdevice ddr_freq_dev = {
 647         .fops   = &ddr_freq_fops,
 648         .name   = "ddr_freq",
 649         .mode   = S_IRUGO | S_IWUSR | S_IWUGO,
 650         .minor  = MISC_DYNAMIC_MINOR,
 651 };
 652
 653 #ifdef CONFIG_INPUT
 654 static void ddr_freq_input_event(struct input_handle *handle, unsigned int type,
 655                 unsigned int code, int value)
 656 {
 657         if (type == EV_ABS)
 658                 ddr_boost = 1;
 659 }
 660
 661 static int ddr_freq_input_connect(struct input_handler *handler,
 662                 struct input_dev *dev, const struct input_device_id *id)
 663 {
 664         struct input_handle *handle;
 665         int error;
 666
 667         handle = kzalloc(sizeof(struct input_handle), GFP_KERNEL);
 668         if (!handle)
 669                 return -ENOMEM;
 670
 671         handle->dev = dev;
 672         handle->handler = handler;
 673         handle->name = "ddr_freq";
 674
 675         error = input_register_handle(handle);
 676         if (error)
 677                 goto err2;
 678
 679         error = input_open_device(handle);
 680         if (error)
 681                 goto err1;
 682
 683         return 0;
 684 err1:
 685         input_unregister_handle(handle);
 686 err2:
 687         kfree(handle);
 688         return error;
 689 }
 690
 691 static void ddr_freq_input_disconnect(struct input_handle *handle)
 692 {
 693         input_close_device(handle);
 694         input_unregister_handle(handle);
 695         kfree(handle);
 696 }
 697
 698 static const struct input_device_id ddr_freq_ids[] = {
 699         {
 700                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
 701                         INPUT_DEVICE_ID_MATCH_ABSBIT,
 702                 .evbit = { BIT_MASK(EV_ABS) },
 703                 .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
 704                         BIT_MASK(ABS_MT_POSITION_X) |
 705                         BIT_MASK(ABS_MT_POSITION_Y) },
 706         },
 707         {
 708                 .flags = INPUT_DEVICE_ID_MATCH_KEYBIT |
 709                         INPUT_DEVICE_ID_MATCH_ABSBIT,
 710                 .keybit = { [BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH) },
 711                 .absbit = { [BIT_WORD(ABS_X)] =
 712                         BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
 713         },
 714         {
 715                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
 716                 .evbit = { BIT_MASK(EV_KEY) },
 717         },
 718         { },
 719 };
 720
 721 static struct input_handler ddr_freq_input_handler = {
 722         .event          = ddr_freq_input_event,
 723         .connect        = ddr_freq_input_connect,
 724         .disconnect     = ddr_freq_input_disconnect,
 725         .name           = "ddr_freq",
 726         .id_table       = ddr_freq_ids,
 727 };
 728 #endif
 729 #if 0
 730 static int ddrfreq_clk_event(int status, unsigned long event)
 731 {
 732         switch (event) {
 733         case RK_CLK_PD_PREPARE:
 734                 ddrfreq_set_sys_status(status);
 735                 break;
 736         case RK_CLK_PD_UNPREPARE:
 737                 ddrfreq_clear_sys_status(status);
 738                 break;
 739         }
 740         return NOTIFY_OK;
 741 }
 742
 743 #define CLK_NOTIFIER(name, status) \
 744 static int ddrfreq_clk_##name##_event(struct notifier_block *this, unsigned long event, void *ptr) \
 745 { \
 746         return ddrfreq_clk_event(SYS_STATUS_##status, event); \
 747 } \
 748 static struct notifier_block ddrfreq_clk_##name##_notifier = { .notifier_call = ddrfreq_clk_##name##_event };
 749
 750 #define REGISTER_CLK_NOTIFIER(name) \
 751 do { \
 752         struct clk *clk = clk_get(NULL, #name); \
 753         rk_clk_pd_notifier_register(clk, &ddrfreq_clk_##name##_notifier); \
 754         clk_put(clk); \
 755 } while (0)
 756
 757 #define UNREGISTER_CLK_NOTIFIER(name) \
 758 do { \
 759         struct clk *clk = clk_get(NULL, #name); \
 760         rk_clk_pd_notifier_unregister(clk, &ddrfreq_clk_##name##_notifier); \
 761         clk_put(clk); \
 762 } while (0)
 763
 764 CLK_NOTIFIER(pd_isp, ISP)
 765 CLK_NOTIFIER(pd_vop0, LCDC0)
 766 CLK_NOTIFIER(pd_vop1, LCDC1)
 767 #endif
 768
 769 static int ddrfreq_reboot_notifier_event(struct notifier_block *this, unsigned long event, void *ptr)
 770 {
 771         rockchip_set_system_status(SYS_STATUS_REBOOT);
 772         rockchip_cpufreq_reboot_limit_freq();
 773
 774         return NOTIFY_OK;
 775 }
 776
 777 static struct notifier_block ddrfreq_reboot_notifier = {
 778         .notifier_call = ddrfreq_reboot_notifier_event,
 779 };
 780
 781 static int ddr_freq_suspend_notifier_call(struct notifier_block *self,
 782                                 unsigned long action, void *data)
 783 {
 784         struct fb_event *event = data;
 785         int blank_mode = *((int *)event->data);
 786
 787         if (action == FB_EARLY_EVENT_BLANK) {
 788                 switch (blank_mode) {
 789                 case FB_BLANK_UNBLANK:
 790                         rockchip_clear_system_status(SYS_STATUS_SUSPEND);
 791                         break;
 792                 default:
 793                         break;
 794                 }
 795         }
 796         else if (action == FB_EVENT_BLANK) {
 797                 switch (blank_mode) {
 798                 case FB_BLANK_POWERDOWN:
 799                         rockchip_set_system_status(SYS_STATUS_SUSPEND);
 800                         break;
 801                 default:
 802                         break;
 803                 }
 804         }
 805
 806         return NOTIFY_OK;
 807 }
 808
 809 static struct notifier_block ddr_freq_suspend_notifier = {
 810                 .notifier_call = ddr_freq_suspend_notifier_call,
 811 };
 812
 813 static int ddrfreq_system_status_notifier_call(struct notifier_block *nb,
 814                                 unsigned long val, void *data)
 815 {
 816         mutex_lock(&ddrfreq_mutex);
 817         ddr.sys_status = val;
 818         wake_up(&ddr.wait);
 819         wait_for_completion(&ddrfreq_completion);
 820         mutex_unlock(&ddrfreq_mutex);
 821
 822         return NOTIFY_OK;
 823 }
 824
 825 static struct notifier_block ddrfreq_system_status_notifier = {
 826                 .notifier_call = ddrfreq_system_status_notifier_call,
 827 };
 828
 829
 830 int of_init_ddr_freq_table(void)
 831 {
 832         struct device_node *clk_ddr_dev_node;
 833         const struct property *prop;
 834         const __be32 *val;
 835         int nr, i=0;
 836
 837         clk_ddr_dev_node = of_find_node_by_name(NULL, "clk_ddr");
 838         if (IS_ERR_OR_NULL(clk_ddr_dev_node)) {
 839                 pr_err("%s: get clk ddr dev node err\n", __func__);
 840                 return PTR_ERR(clk_ddr_dev_node);
 841         }
 842
 843         prop = of_find_property(clk_ddr_dev_node, "auto-freq", NULL);
 844         if (prop && prop->value)
 845                 ddr.auto_freq = be32_to_cpup(prop->value);
 846
 847         prop = of_find_property(clk_ddr_dev_node, "auto-freq-table", NULL);
 848         if (prop && prop->value) {
 849                 nr = prop->length / sizeof(u32);
 850                 auto_freq_table = kzalloc((sizeof(u32) *(nr+1)), GFP_KERNEL);
 851                 val = prop->value;
 852                 while (nr) {
 853                         auto_freq_table[i++] =
 854                                 dvfs_clk_round_rate(ddr.clk_dvfs_node, 1000 * be32_to_cpup(val++));
 855                         nr--;
 856                 }
 857                 cur_freq_index = 0;
 858                 auto_freq_table_size = i;
 859         }
 860
 861         prop = of_find_property(clk_ddr_dev_node, "freq-table", NULL);
 862         if (!prop)
 863                 return -ENODEV;
 864         if (!prop->value)
 865                 return -ENODATA;
 866
 867         nr = prop->length / sizeof(u32);
 868         if (nr % 2) {
 869                 pr_err("%s: Invalid freq list\n", __func__);
 870                 return -EINVAL;
 871         }
 872
 873         val = prop->value;
 874         while (nr) {
 875                 unsigned long status = be32_to_cpup(val++);
 876                 unsigned long rate =
 877                         dvfs_clk_round_rate(ddr.clk_dvfs_node, be32_to_cpup(val++) * 1000);
 878
 879                 if (status & SYS_STATUS_NORMAL)
 880                         ddr.normal_rate = rate;
 881                 if (status & SYS_STATUS_SUSPEND)
 882                         ddr.suspend_rate = rate;
 883                 if (status & SYS_STATUS_VIDEO_1080P)
 884                         ddr.video_1080p_rate = rate;
 885                 if (status & SYS_STATUS_VIDEO_4K)
 886                         ddr.video_4k_rate = rate;
 887                 if (status & SYS_STATUS_PERFORMANCE)
 888                         ddr.performance_rate= rate;
 889                 if ((status & SYS_STATUS_LCDC0)&&(status & SYS_STATUS_LCDC1))
 890                         ddr.dualview_rate = rate;
 891                 if (status & SYS_STATUS_HDMI)
 892                         ddr.hdmi_rate = rate;
 893                 if (status & SYS_STATUS_IDLE)
 894                         ddr.idle_rate= rate;
 895                 if (status & SYS_STATUS_REBOOT)
 896                         ddr.reboot_rate= rate;
 897                 if (status & SYS_STATUS_BOOST)
 898                         ddr.boost_rate= rate;
 899                 if (status & SYS_STATUS_ISP)
 900                         ddr.isp_rate= rate;
 901
 902                 nr -= 2;
 903         }
 904
 905         return 0;
 906 }
 907
 908 static int ddrfreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate)
 909 {
 910         unsigned long real_rate;
 911
 912         real_rate = ddr_change_freq(rate/MHZ);
 913         real_rate *= MHZ;
 914         if (!real_rate)
 915                 return -EAGAIN;
 916         if (cpu_is_rk312x()) {
 917                 clk->parent->rate = 2 * real_rate;
 918                 clk->rate = real_rate;
 919         } else {
 920                 clk->rate = real_rate;
 921                 clk->parent->rate = real_rate;
 922         }
 923
 924         return 0;
 925 }
 926
 927 #if defined(CONFIG_RK_PM_TESTS)
 928 static void ddrfreq_tst_init(void);
 929 #endif
 930
 931 static int ddrfreq_init(void)
 932 {
 933         int ret, i;
 934         struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
 935
 936 #if defined(CONFIG_RK_PM_TESTS)
 937         ddrfreq_tst_init();
 938 #endif
 939
 940         clk_cpu_dvfs_node = clk_get_dvfs_node("clk_core");
 941         if (!clk_cpu_dvfs_node){
 942                 return -EINVAL;
 943         }
 944
 945         memset(&ddr, 0x00, sizeof(ddr));
 946         ddr.clk_dvfs_node = clk_get_dvfs_node("clk_ddr");
 947         if (!ddr.clk_dvfs_node){
 948                 return -EINVAL;
 949         }
 950         clk_enable_dvfs(ddr.clk_dvfs_node);
 951
 952         dvfs_clk_register_set_rate_callback(ddr.clk_dvfs_node, ddrfreq_scale_rate_for_dvfs);
 953
 954         init_waitqueue_head(&ddr.wait);
 955         INIT_LIST_HEAD(&ddr.video_info_list);
 956         ddr.mode = "normal";
 957         ddr.normal_rate = dvfs_clk_get_rate(ddr.clk_dvfs_node);
 958         ddr.sys_status = rockchip_get_system_status();
 959
 960         of_init_ddr_freq_table();
 961
 962         if (!ddr.reboot_rate)
 963                 ddr.reboot_rate = ddr.normal_rate;
 964
 965 #ifdef CONFIG_INPUT
 966         ret = input_register_handler(&ddr_freq_input_handler);
 967         if (ret)
 968                 ddr.auto_freq = false;
 969 #endif
 970
 971         //REGISTER_CLK_NOTIFIER(pd_isp);
 972         //REGISTER_CLK_NOTIFIER(pd_vop0);
 973         //REGISTER_CLK_NOTIFIER(pd_vop1);
 974
 975         ret = misc_register(&video_state_dev);
 976         ret = misc_register(&ddr_freq_dev);
 977         if (unlikely(ret)) {
 978                 pr_err("failed to register video_state misc device! error %d\n", ret);
 979                 goto err;
 980         }
 981
 982         ddr.task = kthread_create(ddrfreq_task, NULL, "ddrfreqd");
 983         if (IS_ERR(ddr.task)) {
 984                 ret = PTR_ERR(ddr.task);
 985                 pr_err("failed to create kthread! error %d\n", ret);
 986                 goto err1;
 987         }
 988
 989         sched_setscheduler_nocheck(ddr.task, SCHED_FIFO, &param);
 990         get_task_struct(ddr.task);
 991         kthread_bind(ddr.task, 0);
 992         wake_up_process(ddr.task);
 993
 994         rockchip_register_system_status_notifier(&ddrfreq_system_status_notifier);
 995         fb_register_client(&ddr_freq_suspend_notifier);
 996         register_reboot_notifier(&ddrfreq_reboot_notifier);
 997
 998         pr_info("verion 1.2 20140526\n");
 999         pr_info("normal %luMHz video_1080p %luMHz video_4k %luMHz dualview %luMHz idle %luMHz suspend %luMHz reboot %luMHz\n",
1000                 ddr.normal_rate / MHZ,
1001                 ddr.video_1080p_rate / MHZ,
1002                 ddr.video_4k_rate / MHZ,
1003                 ddr.dualview_rate / MHZ,
1004                 ddr.idle_rate / MHZ,
1005                 ddr.suspend_rate / MHZ,
1006                 ddr.reboot_rate / MHZ);
1007
1008         pr_info("auto-freq=%d\n", ddr.auto_freq);
1009         if (auto_freq_table) {
1010                 for (i = 0; i < auto_freq_table_size; i++) {
1011                         pr_info("auto-freq-table[%d] %luMHz\n", i, auto_freq_table[i] / MHZ);
1012                 }
1013         } else {
1014                 pr_info("auto-freq-table epmty!\n");
1015         }
1016         return 0;
1017
1018 err1:
1019         misc_deregister(&video_state_dev);
1020 err:
1021         return ret;
1022 }
1023 late_initcall(ddrfreq_init);
1024 /****************************ddr bandwith tst************************************/
1025 #if defined(CONFIG_RK_PM_TESTS)
1026 static ssize_t ddrbw_dyn_show(struct kobject *kobj, struct kobj_attribute *attr,
1027                 char *buf)
1028 {
1029         char *str = buf;
1030         str += sprintf(str, "print: %d\n", print);
1031         str += sprintf(str, "watch: %d\n", watch);
1032         str += sprintf(str, "high_load: %d\n", high_load);
1033         str += sprintf(str, "low_load: %d\n", low_load);
1034         str += sprintf(str, "auto_freq_interval_ms: %d\n", auto_freq_interval_ms);
1035         str += sprintf(str, "down_rate_delay_ms: %ld\n", down_rate_delay_ms);
1036 //      str += sprintf(str, "low_load_last_ms: %d\n", low_load_last_ms);
1037         if (str != buf)
1038                 *(str - 1) = '\n';
1039         return (str - buf);
1040 }
1041
1042 static ssize_t ddrbw_dyn_store(struct kobject *kobj, struct kobj_attribute *attr,
1043                 const char *buf, size_t n)
1044 {
1045         int value;
1046         char var_name[64];
1047
1048         sscanf(buf, "%s %u", var_name, &value);
1049
1050         if((strncmp(buf, "print", strlen("print")) == 0)) {
1051                 print = value;
1052         } else if((strncmp(buf, "watch", strlen("watch")) == 0)) {
1053                 watch = value;
1054         } else if((strncmp(buf, "high", strlen("high")) == 0)) {
1055                 high_load = value;
1056         } else if((strncmp(buf, "low", strlen("low")) == 0)) {
1057                 low_load = value;
1058         } else if((strncmp(buf, "interval", strlen("interval")) == 0)) {
1059                 auto_freq_interval_ms = value;
1060         } else if((strncmp(buf, "downdelay", strlen("downdelay")) == 0)) {
1061                 down_rate_delay_ms = value;
1062         }
1063         return n;
1064 }
1065
1066 struct ddrfreq_attribute {
1067         struct attribute        attr;
1068         ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
1069                         char *buf);
1070         ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
1071                         const char *buf, size_t n);
1072 };
1073
1074 static struct ddrfreq_attribute ddrfreq_attrs[] = {
1075         /*     node_name        permision               show_func       store_func */
1076         __ATTR(ddrfreq, S_IRUSR|S_IRGRP|S_IWUSR,        ddrbw_dyn_show, ddrbw_dyn_store),
1077 };
1078 int rk_pm_tests_kobj_atrradd(const struct attribute *attr);
1079
1080 static void ddrfreq_tst_init(void)
1081 {
1082         int ret;
1083
1084         ret = rk_pm_tests_kobj_atrradd(&ddrfreq_attrs[0].attr);
1085
1086         if (ret) {
1087                 printk("%s: create ddrfreq sysfs node error, ret: %d\n", __func__, ret);
1088                 return;
1089         }
1090 }
1091 #endif