2 * Copyright (C) 2013-2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk-provider.h>
16 #include <linux/genalloc.h>
17 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/of_fdt.h>
23 #include <asm/cputype.h>
24 #ifdef CONFIG_CACHE_L2X0
25 #include <asm/hardware/cache-l2x0.h>
27 #include <linux/rockchip/common.h>
28 #include <linux/rockchip/pmu.h>
29 #include <linux/memblock.h>
34 static int __init rockchip_cpu_axi_init(void)
36 struct device_node *np, *gp, *cp;
39 np = of_find_compatible_node(NULL, NULL, "rockchip,cpu_axi_bus");
43 #define MAP(base) if (!base) base = of_iomap(cp, 0); if (!base) continue;
45 gp = of_get_child_by_name(np, "qos");
47 for_each_child_of_node(gp, cp) {
48 u32 priority[2], mode, bandwidth, saturation, extcontrol;
53 of_address_to_resource(cp, 0, &r);
54 pr_debug("qos: %s [%x ~ %x]\n", cp->name, r.start, r.end);
57 if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
59 CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], base);
60 pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
62 if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
64 CPU_AXI_SET_QOS_MODE(mode, base);
65 pr_debug("qos: %s mode %x\n", cp->name, mode);
67 if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
69 CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base);
70 pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
72 if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
74 CPU_AXI_SET_QOS_SATURATION(saturation, base);
75 pr_debug("qos: %s saturation %x\n", cp->name, saturation);
77 if (!of_property_read_u32(cp, "rockchip,extcontrol", &extcontrol)) {
79 CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base);
80 pr_debug("qos: %s extcontrol %x\n", cp->name, extcontrol);
87 gp = of_get_child_by_name(np, "msch");
89 for_each_child_of_node(gp, cp) {
95 of_address_to_resource(cp, 0, &r);
96 pr_debug("msch: %s [%x ~ %x]\n", cp->name, r.start, r.end);
99 if (!of_property_read_u32(cp, "rockchip,read-latency", &val)) {
101 writel_relaxed(val, base + 0x0014); // memory scheduler read latency
102 pr_debug("msch: %s read latency %x\n", cp->name, val);
114 early_initcall(rockchip_cpu_axi_init);
116 #ifdef CONFIG_CACHE_L2X0
117 static int __init rockchip_pl330_l2_cache_init(void)
119 struct device_node *np;
121 u32 aux[2] = { 0, ~0 }, prefetch, power;
123 if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9)
126 np = of_find_compatible_node(NULL, NULL, "rockchip,pl310-cache");
130 base = of_iomap(np, 0);
134 if (!of_property_read_u32(np, "rockchip,prefetch-ctrl", &prefetch)) {
135 /* L2X0 Prefetch Control */
136 writel_relaxed(prefetch, base + L2X0_PREFETCH_CTRL);
137 pr_debug("l2c: prefetch %x\n", prefetch);
140 if (!of_property_read_u32(np, "rockchip,power-ctrl", &power)) {
141 /* L2X0 Power Control */
142 writel_relaxed(power, base + L2X0_POWER_CTRL);
143 pr_debug("l2c: power %x\n", power);
148 of_property_read_u32_array(np, "rockchip,aux-ctrl", aux, ARRAY_SIZE(aux));
149 pr_debug("l2c: aux %08x mask %08x\n", aux[0], aux[1]);
151 l2x0_of_init(aux[0], aux[1]);
155 early_initcall(rockchip_pl330_l2_cache_init);
158 struct gen_pool *rockchip_sram_pool = NULL;
159 struct pie_chunk *rockchip_pie_chunk = NULL;
160 void *rockchip_sram_virt = NULL;
161 size_t rockchip_sram_size = 0;
162 char *rockchip_sram_stack = NULL;
165 int __init rockchip_pie_init(void)
167 struct device_node *np;
169 np = of_find_node_by_path("/");
173 rockchip_sram_pool = of_get_named_gen_pool(np, "rockchip,sram", 0);
174 if (!rockchip_sram_pool) {
175 pr_err("%s: failed to get sram pool\n", __func__);
178 rockchip_sram_size = gen_pool_size(rockchip_sram_pool);
184 static bool is_panic = false;
185 extern void console_disable_suspend(void);
187 static int panic_event(struct notifier_block *this, unsigned long event, void *ptr)
189 #if CONFIG_RK_DEBUG_UART >= 0
190 console_disable_suspend();
196 static struct notifier_block panic_block = {
197 .notifier_call = panic_event,
200 static int boot_mode;
202 int rockchip_boot_mode(void)
206 EXPORT_SYMBOL(rockchip_boot_mode);
208 static inline const char *boot_flag_name(u32 flag)
210 flag -= SYS_KERNRL_REBOOT_FLAG;
212 case BOOT_NORMAL: return "NORMAL";
213 case BOOT_LOADER: return "LOADER";
214 case BOOT_MASKROM: return "MASKROM";
215 case BOOT_RECOVER: return "RECOVER";
216 case BOOT_NORECOVER: return "NORECOVER";
217 case BOOT_SECONDOS: return "SECONDOS";
218 case BOOT_WIPEDATA: return "WIPEDATA";
219 case BOOT_WIPEALL: return "WIPEALL";
220 case BOOT_CHECKIMG: return "CHECKIMG";
221 case BOOT_FASTBOOT: return "FASTBOOT";
222 case BOOT_CHARGING: return "CHARGING";
227 static inline const char *boot_mode_name(u32 mode)
230 case BOOT_MODE_NORMAL: return "NORMAL";
231 case BOOT_MODE_FACTORY2: return "FACTORY2";
232 case BOOT_MODE_RECOVERY: return "RECOVERY";
233 case BOOT_MODE_CHARGE: return "CHARGE";
234 case BOOT_MODE_POWER_TEST: return "POWER_TEST";
235 case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
236 case BOOT_MODE_REBOOT: return "REBOOT";
237 case BOOT_MODE_PANIC: return "PANIC";
238 case BOOT_MODE_WATCHDOG: return "WATCHDOG";
239 case BOOT_MODE_TSADC: return "TSADC";
244 void __init rockchip_boot_mode_init(u32 flag, u32 mode)
247 if (mode || ((flag & 0xff) && ((flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
248 printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(mode), mode, boot_flag_name(flag), flag);
249 atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
252 void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode)
254 *flag = SYS_LOADER_REBOOT_FLAG + BOOT_NORMAL;
255 *mode = BOOT_MODE_REBOOT;
258 if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
259 *flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
260 else if(!strcmp(cmd, "recovery"))
261 *flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
262 else if (!strcmp(cmd, "fastboot"))
263 *flag = SYS_LOADER_REBOOT_FLAG + BOOT_FASTBOOT;
264 else if (!strcmp(cmd, "charge")) {
265 *flag = SYS_LOADER_REBOOT_FLAG + BOOT_CHARGING;
266 *mode = BOOT_MODE_CHARGE;
270 *mode = BOOT_MODE_PANIC;
274 struct rockchip_pmu_operations rockchip_pmu_ops;
275 void (*ddr_bandwidth_get)(struct ddr_bw_info *ddr_bw_ch0,
276 struct ddr_bw_info *ddr_bw_ch1);
277 int (*ddr_change_freq)(uint32_t nMHz) = NULL;
278 long (*ddr_round_rate)(uint32_t nMHz) = NULL;
279 void (*ddr_set_auto_self_refresh)(bool en) = NULL;
281 extern struct ion_platform_data ion_pdata;
282 extern void __init ion_reserve(struct ion_platform_data *data);
283 extern int __init rockchip_ion_find_heap(unsigned long node,
284 const char *uname, int depth, void *data);
285 void __init rockchip_ion_reserve(void)
287 #ifdef CONFIG_ION_ROCKCHIP
288 printk("%s\n", __func__);
289 of_scan_flat_dt(rockchip_ion_find_heap, (void*)&ion_pdata);
290 ion_reserve(&ion_pdata);
294 bool rockchip_jtag_enabled = false;
295 static int __init rockchip_jtag_enable(char *__unused)
297 rockchip_jtag_enabled = true;
298 printk("rockchip jtag enabled\n");
301 __setup("rockchip_jtag", rockchip_jtag_enable);
303 phys_addr_t uboot_logo_base=0;
304 phys_addr_t uboot_logo_size=0;
305 phys_addr_t uboot_logo_offset=0;
307 void __init rockchip_uboot_mem_reserve(void)
309 if (uboot_logo_size==0)
312 if (!memblock_is_region_reserved(uboot_logo_base, uboot_logo_size)
313 && !memblock_reserve(uboot_logo_base, uboot_logo_size)){
314 pr_info("%s: reserve %pa@%pa for uboot logo\n", __func__,
315 &uboot_logo_size, &uboot_logo_base);
317 pr_err("%s: reserve of %pa@%pa failed\n", __func__,
318 &uboot_logo_size, &uboot_logo_base);
322 static int __init rockchip_uboot_logo_setup(char *p)
326 uboot_logo_size = memparse(p, &endp);
328 uboot_logo_base = memparse(endp + 1, &endp);
330 uboot_logo_offset = memparse(endp + 1, NULL);
334 pr_info("%s: mem: %pa@%pa, offset:%pa\n", __func__,
335 &uboot_logo_size, &uboot_logo_base, &uboot_logo_offset);
339 early_param("uboot_logo", rockchip_uboot_logo_setup);
341 static int __init rockchip_uboot_mem_late_init(void)
343 phys_addr_t addr = 0;
346 if (uboot_logo_size) {
347 addr = PAGE_ALIGN(uboot_logo_base);
348 end = (uboot_logo_base+uboot_logo_size)&PAGE_MASK;
350 pr_info("%s: Freeing uboot logo memory: %pa@%pa\n", __func__,
351 &uboot_logo_size, &uboot_logo_base);
353 memblock_free(uboot_logo_base, uboot_logo_size);
355 for (; addr < end; addr += PAGE_SIZE)
356 free_reserved_page(pfn_to_page(addr >> PAGE_SHIFT));
361 late_initcall(rockchip_uboot_mem_late_init);