arch/arm/mach-rockchip/common.c

   1 /*
   2  * Copyright (C) 2013-2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/genalloc.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/of_fdt.h>
  23 #include <asm/cputype.h>
  24 #ifdef CONFIG_CACHE_L2X0
  25 #include <asm/hardware/cache-l2x0.h>
  26 #endif
  27 #include <linux/rockchip/common.h>
  28 #include <linux/rockchip/pmu.h>
  29 #include "cpu_axi.h"
  30 #include "loader.h"
  31 #include "sram.h"
  32
  33 static int __init rockchip_cpu_axi_init(void)
  34 {
  35         struct device_node *np, *gp, *cp;
  36         void __iomem *base;
  37
  38         np = of_find_compatible_node(NULL, NULL, "rockchip,cpu_axi_bus");
  39         if (!np)
  40                 return -ENODEV;
  41
  42 #define MAP(base) if (!base) base = of_iomap(cp, 0); if (!base) continue;
  43
  44         gp = of_get_child_by_name(np, "qos");
  45         if (gp) {
  46                 for_each_child_of_node(gp, cp) {
  47                         u32 priority[2], mode, bandwidth, saturation, extcontrol;
  48                         base = NULL;
  49 #ifdef DEBUG
  50                         {
  51                                 struct resource r;
  52                                 of_address_to_resource(cp, 0, &r);
  53                                 pr_debug("qos: %s [%x ~ %x]\n", cp->name, r.start, r.end);
  54                         }
  55 #endif
  56                         if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
  57                                 MAP(base);
  58                                 CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], base);
  59                                 pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
  60                         }
  61                         if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
  62                                 MAP(base);
  63                                 CPU_AXI_SET_QOS_MODE(mode, base);
  64                                 pr_debug("qos: %s mode %x\n", cp->name, mode);
  65                         }
  66                         if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
  67                                 MAP(base);
  68                                 CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base);
  69                                 pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
  70                         }
  71                         if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
  72                                 MAP(base);
  73                                 CPU_AXI_SET_QOS_SATURATION(saturation, base);
  74                                 pr_debug("qos: %s saturation %x\n", cp->name, saturation);
  75                         }
  76                         if (!of_property_read_u32(cp, "rockchip,extcontrol", &extcontrol)) {
  77                                 MAP(base);
  78                                 CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base);
  79                                 pr_debug("qos: %s extcontrol %x\n", cp->name, extcontrol);
  80                         }
  81                         if (base)
  82                                 iounmap(base);
  83                 }
  84         };
  85
  86         gp = of_get_child_by_name(np, "msch");
  87         if (gp) {
  88                 for_each_child_of_node(gp, cp) {
  89                         u32 val;
  90                         base = NULL;
  91 #ifdef DEBUG
  92                         {
  93                                 struct resource r;
  94                                 of_address_to_resource(cp, 0, &r);
  95                                 pr_debug("msch: %s [%x ~ %x]\n", cp->name, r.start, r.end);
  96                         }
  97 #endif
  98                         if (!of_property_read_u32(cp, "rockchip,read-latency", &val)) {
  99                                 MAP(base);
 100                                 writel_relaxed(val, base + 0x0014);     // memory scheduler read latency
 101                                 pr_debug("msch: %s read latency %x\n", cp->name, val);
 102                         }
 103                         if (base)
 104                                 iounmap(base);
 105                 }
 106         }
 107         dsb(sy);
 108
 109 #undef MAP
 110
 111         return 0;
 112 }
 113 early_initcall(rockchip_cpu_axi_init);
 114
 115 #ifdef CONFIG_CACHE_L2X0
 116 static int __init rockchip_pl330_l2_cache_init(void)
 117 {
 118         struct device_node *np;
 119         void __iomem *base;
 120         u32 aux[2] = { 0, ~0 }, prefetch, power;
 121
 122         if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9)
 123                 return -ENODEV;
 124
 125         np = of_find_compatible_node(NULL, NULL, "rockchip,pl310-cache");
 126         if (!np)
 127                 return -ENODEV;
 128
 129         base = of_iomap(np, 0);
 130         if (!base)
 131                 return -EINVAL;
 132
 133         if (!of_property_read_u32(np, "rockchip,prefetch-ctrl", &prefetch)) {
 134                 /* L2X0 Prefetch Control */
 135                 writel_relaxed(prefetch, base + L2X0_PREFETCH_CTRL);
 136                 pr_debug("l2c: prefetch %x\n", prefetch);
 137         }
 138
 139         if (!of_property_read_u32(np, "rockchip,power-ctrl", &power)) {
 140                 /* L2X0 Power Control */
 141                 writel_relaxed(power, base + L2X0_POWER_CTRL);
 142                 pr_debug("l2c: power %x\n", power);
 143         }
 144
 145         iounmap(base);
 146
 147         of_property_read_u32_array(np, "rockchip,aux-ctrl", aux, ARRAY_SIZE(aux));
 148         pr_debug("l2c: aux %08x mask %08x\n", aux[0], aux[1]);
 149
 150         l2x0_of_init(aux[0], aux[1]);
 151
 152         return 0;
 153 }
 154 early_initcall(rockchip_pl330_l2_cache_init);
 155 #endif
 156
 157 struct gen_pool *rockchip_sram_pool = NULL;
 158 struct pie_chunk *rockchip_pie_chunk = NULL;
 159 void *rockchip_sram_virt = NULL;
 160 size_t rockchip_sram_size = 0;
 161 char *rockchip_sram_stack = NULL;
 162
 163 #ifdef CONFIG_PIE
 164 int __init rockchip_pie_init(void)
 165 {
 166         struct device_node *np;
 167
 168         np = of_find_node_by_path("/");
 169         if (!np)
 170                 return -ENODEV;
 171
 172         rockchip_sram_pool = of_get_named_gen_pool(np, "rockchip,sram", 0);
 173         if (!rockchip_sram_pool) {
 174                 pr_err("%s: failed to get sram pool\n", __func__);
 175                 return -ENODEV;
 176         }
 177         rockchip_sram_size = gen_pool_size(rockchip_sram_pool);
 178
 179         return 0;
 180 }
 181 #endif
 182
 183 static bool is_panic = false;
 184 extern void console_disable_suspend(void);
 185
 186 static int panic_event(struct notifier_block *this, unsigned long event, void *ptr)
 187 {
 188 #if CONFIG_RK_DEBUG_UART >= 0
 189         console_disable_suspend();
 190 #endif
 191         is_panic = true;
 192         return NOTIFY_DONE;
 193 }
 194
 195 static struct notifier_block panic_block = {
 196         .notifier_call  = panic_event,
 197 };
 198
 199 static int boot_mode;
 200
 201 int rockchip_boot_mode(void)
 202 {
 203         return boot_mode;
 204 }
 205 EXPORT_SYMBOL(rockchip_boot_mode);
 206
 207 static inline const char *boot_flag_name(u32 flag)
 208 {
 209         flag -= SYS_KERNRL_REBOOT_FLAG;
 210         switch (flag) {
 211         case BOOT_NORMAL: return "NORMAL";
 212         case BOOT_LOADER: return "LOADER";
 213         case BOOT_MASKROM: return "MASKROM";
 214         case BOOT_RECOVER: return "RECOVER";
 215         case BOOT_NORECOVER: return "NORECOVER";
 216         case BOOT_SECONDOS: return "SECONDOS";
 217         case BOOT_WIPEDATA: return "WIPEDATA";
 218         case BOOT_WIPEALL: return "WIPEALL";
 219         case BOOT_CHECKIMG: return "CHECKIMG";
 220         case BOOT_FASTBOOT: return "FASTBOOT";
 221         case BOOT_CHARGING: return "CHARGING";
 222         default: return "";
 223         }
 224 }
 225
 226 static inline const char *boot_mode_name(u32 mode)
 227 {
 228         switch (mode) {
 229         case BOOT_MODE_NORMAL: return "NORMAL";
 230         case BOOT_MODE_FACTORY2: return "FACTORY2";
 231         case BOOT_MODE_RECOVERY: return "RECOVERY";
 232         case BOOT_MODE_CHARGE: return "CHARGE";
 233         case BOOT_MODE_POWER_TEST: return "POWER_TEST";
 234         case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
 235         case BOOT_MODE_REBOOT: return "REBOOT";
 236         case BOOT_MODE_PANIC: return "PANIC";
 237         case BOOT_MODE_WATCHDOG: return "WATCHDOG";
 238         case BOOT_MODE_TSADC: return "TSADC";
 239         default: return "";
 240         }
 241 }
 242
 243 void __init rockchip_boot_mode_init(u32 flag, u32 mode)
 244 {
 245         boot_mode = mode;
 246         if (mode || ((flag & 0xff) && ((flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
 247                 printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(mode), mode, boot_flag_name(flag), flag);
 248         atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
 249 }
 250
 251 void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode)
 252 {
 253         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_NORMAL;
 254         *mode = BOOT_MODE_REBOOT;
 255
 256         if (cmd) {
 257                 if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
 258                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
 259                 else if(!strcmp(cmd, "recovery"))
 260                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
 261                 else if (!strcmp(cmd, "fastboot"))
 262                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_FASTBOOT;
 263                 else if (!strcmp(cmd, "charge")) {
 264                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_CHARGING;
 265                         *mode = BOOT_MODE_CHARGE;
 266                 }
 267         } else {
 268                 if (is_panic)
 269                         *mode = BOOT_MODE_PANIC;
 270         }
 271 }
 272
 273 struct rockchip_pmu_operations rockchip_pmu_ops;
 274 void (*ddr_bandwidth_get)(struct ddr_bw_info *ddr_bw_ch0,
 275                           struct ddr_bw_info *ddr_bw_ch1);
 276 int (*ddr_change_freq)(uint32_t nMHz) = NULL;
 277 long (*ddr_round_rate)(uint32_t nMHz) = NULL;
 278 void (*ddr_set_auto_self_refresh)(bool en) = NULL;
 279
 280 extern struct ion_platform_data ion_pdata;
 281 extern void __init ion_reserve(struct ion_platform_data *data);
 282 extern int __init rockchip_ion_find_heap(unsigned long node,
 283                                 const char *uname, int depth, void *data);
 284 void __init rockchip_ion_reserve(void)
 285 {
 286 #ifdef CONFIG_ION_ROCKCHIP
 287         printk("%s\n", __func__);
 288         of_scan_flat_dt(rockchip_ion_find_heap, (void*)&ion_pdata);
 289         ion_reserve(&ion_pdata);
 290 #endif
 291 }
 292
 293 bool rockchip_jtag_enabled = false;
 294 static int __init rockchip_jtag_enable(char *__unused)
 295 {
 296         rockchip_jtag_enabled = true;
 297         printk("rockchip jtag enabled\n");
 298         return 1;
 299 }
 300 __setup("rockchip_jtag", rockchip_jtag_enable);