2 #include <linux/delay.h>
4 #include <linux/kernel.h>
5 #include <linux/init.h>
7 #include <linux/suspend.h>
8 #include <linux/random.h>
9 #include <linux/crc32.h>
11 #include <linux/wakelock.h>
12 #include <asm/cacheflush.h>
13 #include <asm/tlbflush.h>
14 #include <asm/hardware/cache-l2x0.h>
15 #include <asm/hardware/gic.h>
18 #include <mach/board.h>
19 #include <mach/system.h>
20 #include <mach/sram.h>
21 #include <mach/gpio.h>
22 #include <mach/iomux.h>
26 #define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
27 #define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
29 #define pmu_readl(offset) readl_relaxed(RK30_PMU_BASE + offset)
30 #define pmu_writel(v,offset) do { writel_relaxed(v, RK30_PMU_BASE + offset); dsb(); } while (0)
32 #define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
33 #define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
35 #define gate_save_soc_clk(val,_save,cons,w_msk) \
36 (_save)=cru_readl(cons);\
37 cru_writel((((~(val)|(_save))&(w_msk))|((w_msk)<<16)),cons)
39 void __sramfunc sram_printch(char byte)
41 #ifdef DEBUG_UART_BASE
42 u32 clk_gate2, clk_gate4, clk_gate8;
45 | (1 << CLK_GATE_ACLK_PEIRPH % 16)
46 | (1 << CLK_GATE_HCLK_PEIRPH % 16)
47 | (1 << CLK_GATE_PCLK_PEIRPH % 16)
48 , clk_gate2, CRU_CLKGATES_CON(2), 0
49 | (1 << ((CLK_GATE_ACLK_PEIRPH % 16) + 16))
50 | (1 << ((CLK_GATE_HCLK_PEIRPH % 16) + 16))
51 | (1 << ((CLK_GATE_PCLK_PEIRPH % 16) + 16)));
52 gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
53 , clk_gate4, CRU_CLKGATES_CON(4),
54 (1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
55 gate_save_soc_clk((1 << ((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16)),
56 clk_gate8, CRU_CLKGATES_CON(8),
57 (1 << (((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16) + 16)));
60 writel_relaxed(byte, DEBUG_UART_BASE);
63 /* loop check LSR[6], Transmitter Empty bit */
64 while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
67 cru_writel(0xffff0000 | clk_gate2, CRU_CLKGATES_CON(2));
68 cru_writel(0xffff0000 | clk_gate4, CRU_CLKGATES_CON(4));
69 cru_writel(0xffff0000 | clk_gate8, CRU_CLKGATES_CON(8));
76 #ifdef CONFIG_DDR_TEST
77 static int ddr_debug=0;
78 module_param(ddr_debug, int, 0644);
80 static int inline calc_crc32(u32 addr, size_t len)
82 return crc32_le(~0, (const unsigned char *)addr, len);
85 extern __sramdata uint32_t mem_type;
86 static void __sramfunc ddr_testmode(void)
88 int32_t g_crc1, g_crc2;
92 extern char _stext[], _etext[];
115 sram_printascii("\n change freq:");
116 g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
119 nMHz = min + random32();
124 nMHz = ddr_change_freq(nMHz);
127 g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
128 if (g_crc1!=g_crc2) {
129 sram_printascii("fail\n");
131 //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
132 // sram_printascii("change freq success\n");
134 } else if(ddr_debug == 2) {
141 g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
142 nMHz = (random32()>>13);// 16.7s max
149 g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
150 if (g_crc1 != g_crc2) {
157 // ddr_print("check image crc32 fail!, count:%d\n", n++);
158 // sram_printascii("self refresh fail\n");
160 //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
161 // sram_printascii("self refresh success\n");
163 } else if (ddr_debug == 3) {
164 extern int memtester(void);
169 ddr_change_freq(ddr_debug);
174 static void __sramfunc ddr_testmode(void) {}
177 static noinline void rk30_pm_dump_irq(void)
179 u32 irq_gpio = (readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 8) >> 22) & 0x7F;
180 printk("wakeup irq: %08x %08x %08x %08x\n",
181 readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 4),
182 readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 8),
183 readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 12),
184 readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 16));
186 printk("wakeup gpio0: %08x\n", readl_relaxed(RK30_GPIO0_BASE + GPIO_INT_STATUS));
188 printk("wakeup gpio1: %08x\n", readl_relaxed(RK30_GPIO1_BASE + GPIO_INT_STATUS));
190 printk("wakeup gpio2: %08x\n", readl_relaxed(RK30_GPIO2_BASE + GPIO_INT_STATUS));
192 printk("wakeup gpio3: %08x\n", readl_relaxed(RK30_GPIO3_BASE + GPIO_INT_STATUS));
194 printk("wakeup gpio4: %08x\n", readl_relaxed(RK30_GPIO4_BASE + GPIO_INT_STATUS));
196 printk("wakeup gpio6: %08x\n", readl_relaxed(RK30_GPIO6_BASE + GPIO_INT_STATUS));
199 #define DUMP_GPIO_INTEN(ID) \
201 u32 en = readl_relaxed(RK30_GPIO##ID##_BASE + GPIO_INTEN); \
203 sram_printascii("GPIO" #ID "_INTEN: "); \
205 sram_printch('\n'); \
209 static noinline void rk30_pm_dump_inten(void)
219 static void pm_pll_wait_lock(int pll_idx)
221 u32 pll_state[4] = { 1, 0, 2, 3 };
222 u32 bit = 0x10u << pll_state[pll_idx];
223 u32 delay = pll_idx == APLL_ID ? 24000000U : 2400000000U;
225 if (grf_readl(GRF_SOC_STATUS0) & bit)
230 //CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
234 sram_printhex(pll_idx);
239 #define power_on_pll(id) \
240 cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
241 pm_pll_wait_lock((id))
243 #define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
244 #define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
246 static unsigned long save_sp;
248 static noinline void interface_ctr_reg_pread(void)
254 local_flush_tlb_all();
256 for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)SRAM_CODE_END; addr += PAGE_SIZE)
258 for (addr = (u32)SRAM_DATA_OFFSET; addr < (u32)SRAM_DATA_END; addr += PAGE_SIZE)
260 readl_relaxed(RK30_PMU_BASE);
261 readl_relaxed(RK30_GRF_BASE);
262 readl_relaxed(RK30_DDR_PCTL_BASE);
263 readl_relaxed(RK30_DDR_PUBL_BASE);
264 readl_relaxed(RK30_I2C1_BASE);
267 static inline bool pm_pmu_power_domain_is_on(enum pmu_power_domain pd, u32 pmu_pwrdn_st)
269 return !(pmu_pwrdn_st & (1 << pd));
272 static void rk30_pm_set_power_domain(u32 pmu_pwrdn_st, bool state)
274 if (pm_pmu_power_domain_is_on(PD_DBG, pmu_pwrdn_st))
275 pmu_set_power_domain(PD_DBG, state);
277 if (pm_pmu_power_domain_is_on(PD_GPU, pmu_pwrdn_st)) {
279 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
280 gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
281 cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
282 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
283 pmu_set_power_domain(PD_GPU, state);
284 cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
285 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
288 if (pm_pmu_power_domain_is_on(PD_VIDEO, pmu_pwrdn_st)) {
290 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
291 gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
292 gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
293 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
294 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
295 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
296 pmu_set_power_domain(PD_VIDEO, state);
297 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
298 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
299 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
302 if (pm_pmu_power_domain_is_on(PD_VIO, pmu_pwrdn_st)) {
304 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
305 gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
306 gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
307 gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
308 gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
309 gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
310 gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
311 gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
312 gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
313 gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
314 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
315 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
316 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
317 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
318 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
319 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
320 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
321 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
322 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
323 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
324 pmu_set_power_domain(PD_VIO, state);
325 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
326 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
327 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
328 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
329 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
330 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
331 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
332 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
333 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
334 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
338 __weak void board_gpio_suspend(void) {}
339 __weak void board_gpio_resume(void) {}
340 __weak void __sramfunc board_pmu_suspend(void) {}
341 __weak void __sramfunc board_pmu_resume(void) {}
342 __weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol){}
343 __weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol){}
345 __weak void rk30_pwm_suspend_voltage_set(void){}
346 __weak void rk30_pwm_resume_voltage_set(void){}
348 __weak void __sramfunc rk30_pwm_logic_suspend_voltage(void){}
349 __weak void __sramfunc rk30_pwm_logic_resume_voltage(void){}
351 static void __sramfunc rk30_sram_suspend(void)
354 u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
361 rk30_suspend_voltage_set(1000000);
362 rk30_pwm_logic_suspend_voltage();
366 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
367 clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
370 | (1 << CLK_GATE_CORE_PERIPH)
371 | (1 << CLK_GATE_ACLK_CPU)
372 | (1 << CLK_GATE_HCLK_CPU)
373 | (1 << CLK_GATE_PCLK_CPU)
374 , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
375 gate_save_soc_clk(0, clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
376 if(clkgt_regs[8]&((1<<12)|(1<13))){
378 | (1 << CLK_GATE_PEIRPH_SRC % 16)
379 | (1 << CLK_GATE_PCLK_PEIRPH % 16)
380 , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
383 , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
387 | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
388 | (1 << CLK_GATE_ACLK_INTMEM % 16)
389 , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
391 | (1 << CLK_GATE_PCLK_GRF % 16)
392 | (1 << CLK_GATE_PCLK_PMU % 16)
393 , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
394 gate_save_soc_clk(0 , clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
396 | (1 << CLK_GATE_CLK_L2C % 16)
397 | (1 << CLK_GATE_ACLK_INTMEM0 % 16)
398 | (1 << CLK_GATE_ACLK_INTMEM1 % 16)
399 | (1 << CLK_GATE_ACLK_INTMEM2 % 16)
400 | (1 << CLK_GATE_ACLK_INTMEM3 % 16)
401 , clkgt_regs[9], CRU_CLKGATES_CON(9), 0x07ff);
403 #ifdef CONFIG_CLK_SWITCH_TO_32K
404 cru_mode_con = cru_readl(CRU_MODE_CON);
406 PLL_MODE_DEEP(APLL_ID)|
407 PLL_MODE_DEEP(DPLL_ID)|
408 PLL_MODE_DEEP(CPLL_ID)|PLL_MODE_DEEP(GPLL_ID),CRU_MODE_CON);
412 cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
413 cru_writel((0x1f << 16) | 0x1f, CRU_CLKSELS_CON(0));
419 #ifdef CONFIG_CLK_SWITCH_TO_32K
421 cru_writel((0xffff<<16) | cru_mode_con, CRU_MODE_CON);
423 cru_writel((0x1f << 16) | cru_clksel0_con, CRU_CLKSELS_CON(0));
427 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
428 cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
432 rk30_pwm_logic_resume_voltage();
433 rk30_suspend_voltage_resume(1100000);
441 static void noinline rk30_suspend(void)
443 DDR_SAVE_SP(save_sp);
445 DDR_RESTORE_SP(save_sp);
448 static int rk30_pm_enter(suspend_state_t state)
451 u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
452 u32 clk_sel0, clk_sel1, clk_sel10;
457 // dump GPIO INTEN for debug
458 rk30_pm_dump_inten();
460 grf_writel(0xc0004000, 0x10c);
461 cru_writel(0x07000000, CRU_MISC_CON);
465 pmu_pwrdn_st = pmu_readl(PMU_PWRDN_ST);
466 rk30_pm_set_power_domain(pmu_pwrdn_st, false);
468 #ifdef CONFIG_DDR_TEST
477 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
478 clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
482 | (1 << CLK_GATE_CORE_PERIPH)
483 | (1 << CLK_GATE_DDRPHY)
484 | (1 << CLK_GATE_ACLK_CPU)
485 | (1 << CLK_GATE_HCLK_CPU)
486 | (1 << CLK_GATE_PCLK_CPU)
487 , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
489 | (1 << CLK_GATE_DDR_GPLL % 16)
490 , clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
492 | (1 << CLK_GATE_PEIRPH_SRC % 16)
493 | (1 << CLK_GATE_PCLK_PEIRPH % 16)
494 | (1 << CLK_GATE_ACLK_PEIRPH % 16)
495 , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
496 gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xff9f);
498 | (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16)
499 | (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16)
500 | (1 << CLK_GATE_ACLK_CPU_PERI % 16)
501 | (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16)
502 | (1 << CLK_GATE_ACLK_PEI_NIU % 16)
503 | (1 << CLK_GATE_HCLK_PERI_AHB_ARBI % 16)
504 | (1 << CLK_GATE_HCLK_CPUBUS % 16)
505 | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
506 | (1 << CLK_GATE_ACLK_INTMEM % 16)
507 , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
509 | (1 << CLK_GATE_PCLK_GRF % 16)
510 | (1 << CLK_GATE_PCLK_PMU % 16)
511 | (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
512 , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
513 gate_save_soc_clk(0, clkgt_regs[6], CRU_CLKGATES_CON(6), 0xffff);
515 |(1 << CLK_GATE_PCLK_PWM23%16)
516 , clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
517 gate_save_soc_clk(0 , clkgt_regs[8], CRU_CLKGATES_CON(8), 0x01ff);
519 | (1 << CLK_GATE_CLK_L2C % 16)
520 | (1 << CLK_GATE_PCLK_PUBL % 16)
521 | (1 << CLK_GATE_ACLK_INTMEM0 % 16)
522 | (1 << CLK_GATE_ACLK_INTMEM1 % 16)
523 | (1 << CLK_GATE_ACLK_INTMEM2 % 16)
524 | (1 << CLK_GATE_ACLK_INTMEM3 % 16)
525 , clkgt_regs[9], CRU_CLKGATES_CON(9), 0x07ff);
529 cru_mode_con = cru_readl(CRU_MODE_CON);
532 cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
533 cpll_con3 = cru_readl(PLL_CONS(CPLL_ID, 3));
534 cru_writel(PLL_PWR_DN_MSK | PLL_PWR_DN, PLL_CONS(CPLL_ID, 3));
537 cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
538 clk_sel10 = cru_readl(CRU_CLKSELS_CON(10));
539 cru_writel(CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
540 | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
541 | CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK)
542 , CRU_CLKSELS_CON(10));
543 cru_writel(PLL_PWR_DN_MSK | PLL_PWR_DN, PLL_CONS(GPLL_ID, 3));
546 clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
547 clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
549 cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
550 cru_writel(CORE_PERIPH_MSK | CORE_PERIPH_2
551 | CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(1)
552 , CRU_CLKSELS_CON(0));
553 cru_writel(CORE_ACLK_W_MSK | CORE_ACLK_11
554 | ACLK_HCLK_W_MSK | ACLK_HCLK_11
555 | ACLK_PCLK_W_MSK | ACLK_PCLK_11
556 | AHB2APB_W_MSK | AHB2APB_11
557 , CRU_CLKSELS_CON(1));
558 cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_DN, PLL_CONS(APLL_ID, 3));
561 rk30_pwm_suspend_voltage_set();
563 board_gpio_suspend();
565 interface_ctr_reg_pread();
572 rk30_pwm_resume_voltage_set();
576 cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
577 cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
578 power_on_pll(APLL_ID);
579 cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);
582 cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
583 cru_writel(clk_sel10, CRU_CLKSELS_CON(10));
584 power_on_pll(GPLL_ID);
585 cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
588 if (((cpll_con3 & PLL_PWR_DN_MSK) == PLL_PWR_ON) &&
589 ((PLL_MODE_NORM(CPLL_ID) & PLL_MODE_MSK(CPLL_ID)) == (cru_mode_con & PLL_MODE_MSK(CPLL_ID)))) {
590 power_on_pll(CPLL_ID);
592 cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
596 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
597 cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
603 rk30_pm_set_power_domain(pmu_pwrdn_st, true);
605 sram_printascii("0\n");
612 static int rk30_pm_prepare(void)
614 /* disable entering idle by disable_hlt() */
619 static void rk30_pm_finish(void)
624 static struct platform_suspend_ops rk30_pm_ops = {
625 .enter = rk30_pm_enter,
626 .valid = suspend_valid_only_mem,
627 .prepare = rk30_pm_prepare,
628 .finish = rk30_pm_finish,
631 static int __init rk30_pm_init(void)
633 suspend_set_ops(&rk30_pm_ops);
635 #ifdef CONFIG_EARLYSUSPEND
636 pm_set_vt_switch(0); /* disable vt switch while suspend */
641 __initcall(rk30_pm_init);