arch/arm/mach-rk30/include/mach/cru.h

   1 #ifndef __MACH_CRU_H
   2 #define __MACH_CRU_H
   3
   4 enum rk_plls_id {
   5         APLL_ID = 0,
   6         DPLL_ID,
   7         CPLL_ID,
   8         GPLL_ID,
   9         END_PLL_ID,
  10 };
  11
  12 /*****cru reg offset*****/
  13
  14 #define CRU_MODE_CON            0x40
  15 #define CRU_CLKSEL_CON          0x44
  16 #define CRU_CLKGATE_CON         0xd0
  17 #define CRU_GLB_SRST_FST        0x100
  18 #define CRU_GLB_SRST_SND        0x104
  19 #define CRU_SOFTRST_CON         0x110
  20
  21 #define PLL_CONS(id, i)         ((id) * 0x10 + ((i) * 4))
  22
  23 #define CRU_CLKSELS_CON_CNT     (35)
  24 #define CRU_CLKSELS_CON(i)      (CRU_CLKSEL_CON + ((i) * 4))
  25
  26 #define CRU_CLKGATES_CON_CNT    (10)
  27 #define CRU_CLKGATES_CON(i)     (CRU_CLKGATE_CON + ((i) * 4))
  28
  29 #define CRU_SOFTRSTS_CON_CNT    (9)
  30 #define CRU_SOFTRSTS_CON(i)     (CRU_SOFTRST_CON + ((i) * 4))
  31
  32 #define CRU_MISC_CON            (0x134)
  33 #define CRU_GLB_CNT_TH          (0x140)
  34
  35 /********************************************************************/
  36
  37 #define CRU_W_MSK(bits_shift, msk)      ((msk) << ((bits_shift) + 16))
  38 #define CRU_SET_VAL_BITS(val,bits_shift,msk) (((msk)<<((bits_shift)+16))|(val))
  39
  40 /*******************PLL CON0 BITS***************************/
  41
  42 #define PLL_CLKFACTOR_SET(val, shift, msk) \
  43         ((((val) - 1) & (msk)) << (shift))
  44
  45 #define PLL_CLKFACTOR_GET(reg, shift, msk) \
  46         ((((reg) >> (shift)) & (msk)) + 1)
  47
  48 #define PLL_OD_MSK              (0xf)
  49 #define PLL_OD_SHIFT (0x0)
  50
  51 #define PLL_CLKOD(val)          PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
  52 #define PLL_NO(reg)             PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
  53
  54 #define PLL_NO_SHIFT(reg)       PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
  55
  56 #define PLL_CLKOD_SET(val)      (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
  57
  58 #define PLL_NR_MSK              (0x3f)
  59 #define PLL_NR_SHIFT            (8)
  60 #define PLL_CLKR(val)           PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
  61 #define PLL_NR(reg)             PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
  62
  63 #define PLL_CLKR_SET(val)       (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
  64
  65 /*******************PLL CON1 BITS***************************/
  66
  67 #define PLL_NF_MSK              (0x1fff)
  68 #define PLL_NF_SHIFT            (0)
  69 #define PLL_CLKF(val)           PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
  70 #define PLL_NF(reg)             PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
  71
  72 #define PLL_CLKF_SET(val)       (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
  73
  74 /*******************PLL CON2 BITS***************************/
  75
  76 #define PLL_BWADJ_MSK           (0xfff)
  77 #define PLL_BWADJ_SHIFT         (0)
  78 #define PLL_CLK_BWADJ_SET(val)  ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
  79
  80 /*******************PLL CON3 BITS***************************/
  81
  82 #define PLL_REST_MSK            (1 << 5)
  83 #define PLL_REST_W_MSK          (PLL_REST_MSK << 16)
  84 #define PLL_REST                (1 << 5)
  85 #define PLL_REST_RESM           (0 << 5)
  86
  87 #define PLL_BYPASS_MSK          (1 << 0)
  88 #define PLL_BYPASS              (1 << 0)
  89 #define PLL_NO_BYPASS           (0 << 0)
  90
  91 #define PLL_PWR_DN_MSK          (1 << 1)
  92 #define PLL_PWR_DN_W_MSK        (PLL_PWR_DN_MSK << 16)
  93 #define PLL_PWR_DN              (1 << 1)
  94 #define PLL_PWR_ON              (0 << 1)
  95
  96 /*******************CLKSEL0 BITS***************************/
  97 //core preiph div
  98 #define CORE_PERIPH_W_MSK       (3 << 22)
  99 #define CORE_PERIPH_MSK         (3 << 6)
 100 #define CORE_PERIPH_2           (0 << 6)
 101 #define CORE_PERIPH_4           (1 << 6)
 102 #define CORE_PERIPH_8           (2 << 6)
 103 #define CORE_PERIPH_16          (3 << 6)
 104 //arm clk pll sel
 105 #define CORE_SEL_PLL_MSK        (1 << 8)
 106 #define CORE_SEL_PLL_W_MSK      (1 << 24)
 107 #define CORE_SEL_APLL           (0 << 8)
 108 #define CORE_SEL_GPLL           (1 << 8)
 109
 110 #define CORE_CLK_DIV_W_MSK      (0x1F << 16)
 111 #define CORE_CLK_DIV_MSK        (0x1F)
 112 #define CORE_CLK_DIV(i)         (((i) - 1) & 0x1F)
 113
 114 /*******************CLKSEL1 BITS***************************/
 115 //aclk div
 116 #define CORE_ACLK_W_MSK         (7 << 16)
 117 #define CORE_ACLK_MSK           (7 << 0)
 118 #define CORE_ACLK_11            (0 << 0)
 119 #define CORE_ACLK_21            (1 << 0)
 120 #define CORE_ACLK_31            (2 << 0)
 121 #define CORE_ACLK_41            (3 << 0)
 122 #define CORE_ACLK_81            (4 << 0)
 123 //hclk div
 124 #define ACLK_HCLK_W_MSK         (3 << 24)
 125 #define ACLK_HCLK_MSK           (3 << 8)
 126 #define ACLK_HCLK_11            (0 << 8)
 127 #define ACLK_HCLK_21            (1 << 8)
 128 #define ACLK_HCLK_41            (2 << 8)
 129 // pclk div
 130 #define ACLK_PCLK_W_MSK         (3 << 28)
 131 #define ACLK_PCLK_MSK           (3 << 12)
 132 #define ACLK_PCLK_11            (0 << 12)
 133 #define ACLK_PCLK_21            (1 << 12)
 134 #define ACLK_PCLK_41            (2 << 12)
 135 #define ACLK_PCLK_81            (3 << 12)
 136
 137 /*******************MODE BITS***************************/
 138
 139 #define PLL_MODE_MSK(id)        (0x3 << ((id) * 4))
 140 #define PLL_MODE_SLOW(id)       ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
 141 #define PLL_MODE_NORM(id)       ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
 142 #define PLL_MODE_DEEP(id)       ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
 143
 144 /*******************clksel10***************************/
 145
 146 #define PERI_ACLK_DIV_MASK 0x1f
 147 #define PERI_ACLK_DIV_OFF 0
 148
 149 #define PERI_HCLK_DIV_MASK 0x3
 150 #define PERI_HCLK_DIV_OFF 8
 151
 152 #define PERI_PCLK_DIV_MASK 0x3
 153 #define PERI_PCLK_DIV_OFF 12
 154
 155 /*******************gate BITS***************************/
 156
 157 #define CLK_GATE_CLKID(i)       (16 * (i))
 158 #define CLK_GATE_CLKID_CONS(i)  CRU_CLKGATES_CON((i) / 16)
 159
 160 #define CLK_GATE(i)             (1 << ((i) >> 4))
 161 #define CLK_UN_GATE(i)          (0)
 162
 163 #define CLK_GATE_W_MSK(i)       (1 << (((i) / 16) + 16))
 164
 165 enum cru_clk_gate {
 166         /* SCU CLK GATE 0 CON */
 167         CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
 168         CLK_GATE_CPU_GPLL_PATH,
 169         CLK_GATE_DDRPHY,
 170         CLK_GATE_ACLK_CPU,
 171         CLK_GATE_HCLK_CPU,
 172         CLK_GATE_PCLK_CPU,
 173         CLK_GATE_ATCLK_CPU,
 174         CLK_GATE_I2S0,
 175         CLK_GATE_I2S0_FRAC,
 176         CLK_GATE_I2S1,
 177         CLK_GATE_I2S1_FRAC,
 178         CLK_GATE_I2S2,
 179         CLK_GATE_I2S2_FRAC,
 180         CLK_GATE_SPDIF,
 181         CLK_GATE_SPDIF_FRAC,
 182         CLK_GATE_TESTCLK,
 183
 184         CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
 185         CLK_GATE_TIMER1,
 186         CLK_GATE_TIMER2,
 187         CLK_GATE_JTAG,
 188         CLK_GATE_ACLK_LCDC1_SRC,
 189         CLK_GATE_OTGPHY0,
 190         CLK_GATE_OTGPHY1,
 191         CLK_GATE_DDR_GPLL,
 192         CLK_GATE_UART0,
 193         CLK_GATE_FRAC_UART0,
 194         CLK_GATE_UART1,
 195         CLK_GATE_FRAC_UART1,
 196         CLK_GATE_UART2,
 197         CLK_GATE_FRAC_UART2,
 198         CLK_GATE_UART3,
 199         CLK_GATE_FRAC_UART3,
 200
 201         CLK_GATE_PEIRPH_SRC = CLK_GATE_CLKID(2),
 202         CLK_GATE_ACLK_PEIRPH,
 203         CLK_GATE_HCLK_PEIRPH,
 204         CLK_GATE_PCLK_PEIRPH,
 205         CLK_GATE_SMC,
 206         CLK_GATE_MAC,
 207         CLK_GATE_HSADC,
 208         CLK_GATE_HSADC_FRAC,
 209         CLK_GATE_SARADC,
 210         CLK_GATE_SPI0,
 211         CLK_GATE_SPI1,
 212         CLK_GATE_MMC0,
 213         CLK_GATE_MAC_LBTEST,
 214         CLK_GATE_SDIO,
 215         CLK_GATE_EMMC,
 216         CLK_GATE_TSADC,
 217
 218         CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
 219         CLK_GATE_DCLK_LCDC0,
 220         CLK_GATE_DCLK_LCDC1,
 221         CLK_GATE_PCLKIN_CIF0,
 222         CLK_GATE_PCLKIN_CIF1,
 223         CLK_GATE3_RES5,
 224         CLK_GATE3_RES6,
 225         CLK_GATE_CIF0_OUT,
 226         CLK_GATE_CIF1_OUT,
 227         CLK_GATE_ACLK_VEPU,
 228         CLK_GATE_HCLK_VEPU,
 229         CLK_GATE_ACLK_VDPU,
 230         CLK_GATE_HCLK_VDPU,
 231         CLK_GATE_GPU_SRC,
 232         CLK_GATE3_RES14,
 233         CLK_GATE_XIN27M,
 234
 235         CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
 236         CLK_GATE_PCLK_PERI_AXI_MATRIX,
 237         CLK_GATE_ACLK_CPU_PERI,
 238         CLK_GATE_ACLK_PERI_AXI_MATRIX,
 239         CLK_GATE_ACLK_PEI_NIU,
 240         CLK_GATE_HCLK_USB_PERI,
 241         CLK_GATE_HCLK_PERI_AHB_ARBI,
 242         CLK_GATE_HCLK_EMEM_PERI,
 243         CLK_GATE_HCLK_CPUBUS,
 244         CLK_GATE_HCLK_AHB2APB,
 245         CLK_GATE_ACLK_STRC_SYS,
 246         CLK_GATE_ACLK_L2MEM_CON,
 247         CLK_GATE_ACLK_INTMEM,
 248         CLK_GATE_PCLK_TSADC,
 249         CLK_GATE_HCLK_HDMI,
 250
 251         CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
 252         CLK_GATE_ACLK_DMAC2,
 253         CLK_GATE_PCLK_EFUSE,
 254         CLK_GATE_PCLK_TZPC,
 255         CLK_GATE_PCLK_GRF,
 256         CLK_GATE_PCLK_PMU,
 257         CLK_GATE_HCLK_ROM,
 258         CLK_GATE_PCLK_DDRUPCTL,
 259         CLK_GATE_ACLK_SMC,
 260         CLK_GATE_HCLK_NANDC,
 261         CLK_GATE_HCLK_SDMMC0,
 262         CLK_GATE_HCLK_SDIO,
 263         CLK_GATE_HCLK_EMMC,
 264         CLK_GATE_HCLK_OTG0,
 265         CLK_GATE_HCLK_OTG1,
 266         CLK_GATE_ACLK_GPU,
 267
 268         CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
 269         CLK_GATE_HCLK_LCDC0,
 270         CLK_GATE_HCLK_LCDC1,
 271         CLK_GATE_ACLK_LCDC1,
 272         CLK_GATE_HCLK_CIF0,
 273         CLK_GATE_ACLK_CIF0,
 274         CLK_GATE_HCLK_CIF1,
 275         CLK_GATE_ACLK_CIF1,
 276         CLK_GATE_ACLK_IPP,
 277         CLK_GATE_HCLK_IPP,
 278         CLK_GATE_HCLK_RGA,
 279         CLK_GATE_ACLK_RGA,
 280         CLK_GATE_HCLK_VIO_BUS,
 281         CLK_GATE_ACLK_VIO0,
 282         CLK_GATE_ACLK_VCODEC,
 283         CLK_GATE_SHCLK_VIO_H2H,
 284
 285         CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
 286         CLK_GATE_HCLK_SPDIF,
 287         CLK_GATE_HCLK_I2S0_2CH,
 288         CLK_GATE_HCLK_I2S1_2CH,
 289         CLK_GATE_HCLK_I2S_8CH,
 290         CLK_GATE_HCLK_HSADC,
 291         CLK_GATE_HCLK_PIDF,
 292         CLK_GATE_PCLK_TIMER0,
 293         CLK_GATE_PCLK_TIMER1,
 294         CLK_GATE_PCLK_TIMER2,
 295         CLK_GATE_PCLK_PWM01,
 296         CLK_GATE_PCLK_PWM23,
 297         CLK_GATE_PCLK_SPI0,
 298         CLK_GATE_PCLK_SPI1,
 299         CLK_GATE_PCLK_SARADC,
 300         CLK_GATE_PCLK_WDT,
 301
 302         CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
 303         CLK_GATE_PCLK_UART1,
 304         CLK_GATE_PCLK_UART2,
 305         CLK_GATE_PCLK_UART3,
 306         CLK_GATE_PCLK_I2C0,
 307         CLK_GATE_PCLK_I2C1,
 308         CLK_GATE_PCLK_I2C2,
 309         CLK_GATE_PCLK_I2C3,
 310         CLK_GATE_PCLK_I2C4,
 311         CLK_GATE_PCLK_GPIO0,
 312         CLK_GATE_PCLK_GPIO1,
 313         CLK_GATE_PCLK_GPIO2,
 314         CLK_GATE_PCLK_GPIO3,
 315         CLK_GATE_PCLK_GPIO4,
 316         CLK_GATE8_RES14,
 317         CLK_GATE_PCLK_GPIO6,
 318
 319         CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
 320         CLK_GATE_PCLK_DBG,
 321         CLK_GATE_CLK_TRACE,
 322         CLK_GATE_ATCLK,
 323         CLK_GATE_CLK_L2C,
 324         CLK_GATE_ACLK_VIO1,
 325         CLK_GATE_PCLK_PUBL,
 326         CLK_GATE_ACLK_INTMEM0,
 327         CLK_GATE_ACLK_INTMEM1,
 328         CLK_GATE_ACLK_INTMEM2,
 329         CLK_GATE_ACLK_INTMEM3,
 330
 331         CLK_GATE_MAX,
 332 };
 333
 334 #define SOFT_RST_ID(i)          (16 * (i))
 335
 336 enum cru_soft_reset {
 337         SOFT_RST_GLB1 = SOFT_RST_ID(0),
 338         SOFT_RST_GLB2,
 339         SOFT_RST_MCORE,
 340         SOFT_RST_CORE0,
 341         SOFT_RST_CORE1,
 342         SOFT_RST_0RES5,
 343         SOFT_RST_0RES6,
 344         SOFT_RST_MCORE_DBG,
 345         SOFT_RST_CORE0_DBG,
 346         SOFT_RST_CORE1_DBG,
 347         SOFT_RST_0RES10,
 348         SOFT_RST_0RES11,
 349         SOFT_RST_CORE0_WDT,
 350         SOFT_RST_CORE1_WDT,
 351         SOFT_RST_STRC_SYS_AXI,
 352         SOFT_RST_L2C,
 353
 354         SOFT_RST_1RES0 = SOFT_RST_ID(1),
 355         SOFT_RST_CPUSYS_AHB,
 356         SOFT_RST_L2MEM_CON_AXI,
 357         SOFT_RST_AHB2APB,
 358         SOFT_RST_DMA0,
 359         SOFT_RST_INTMEM,
 360         SOFT_RST_ROM,
 361         SOFT_RST_I2S0,
 362         SOFT_RST_I2S1,
 363         SOFT_RST_I2S2,
 364         SOFT_RST_SPDIF,
 365         SOFT_RST_TIMER0,
 366         SOFT_RST_TIMER1,
 367         SOFT_RST_TIMER2,
 368         SOFT_RST_EFUSE_APB,
 369
 370         SOFT_RST_GPIO0 = SOFT_RST_ID(2),
 371         SOFT_RST_GPIO1,
 372         SOFT_RST_GPIO2,
 373         SOFT_RST_GPIO3,
 374         SOFT_RST_GPIO4,
 375         SOFT_RST_2RES5,
 376         SOFT_RST_GPIO6,
 377         SOFT_RST_UART0,
 378         SOFT_RST_UART1,
 379         SOFT_RST_UART2,
 380         SOFT_RST_UART3,
 381         SOFT_RST_I2C0,
 382         SOFT_RST_I2C1,
 383         SOFT_RST_I2C2,
 384         SOFT_RST_I2C3,
 385         SOFT_RST_I2C4,
 386
 387         SOFT_RST_PWM0 = SOFT_RST_ID(3),
 388         SOFT_RST_PWM1,
 389         SOFT_RST_DAP_PO,
 390         SOFT_RST_DAP,
 391         SOFT_RST_DAP_SYS,
 392         SOFT_RST_TPIU_ATB,
 393         SOFT_RST_PMU_APB,
 394         SOFT_RST_GRF,
 395         SOFT_RST_PMU,
 396         SOFT_RST_PERIPHSYS_AXI,
 397         SOFT_RST_PERIPHSYS_AHB,
 398         SOFT_RST_PERIPHSYS_APB,
 399         SOFT_RST_PERIPH_NIU,
 400         SOFT_RST_CPU_PERI,
 401         SOFT_RST_EMEM_PERI,
 402         SOFT_RST_USB_PERI,
 403
 404         SOFT_RST_DMA1 = SOFT_RST_ID(4),
 405         SOFT_RST_SMC,
 406         SOFT_RST_MAC,
 407         SOFT_RST_4RES3,
 408         SOFT_RST_NANDC,
 409         SOFT_RST_USBOTG0,
 410         SOFT_RST_USBPHY0,
 411         SOFT_RST_OTGC0,
 412         SOFT_RST_USBOTG1,
 413         SOFT_RST_USBPHY1,
 414         SOFT_RST_OTGC1,
 415         SOFT_RST_4RES11,
 416         SOFT_RST_HSADC,
 417         SOFT_RST_PIDFILTER,
 418         SOFT_RST_4RES14,
 419         SOFT_RST_DDRMSCH,
 420
 421         SOFT_RST_TZPC = SOFT_RST_ID(5),
 422         SOFT_RST_MMC0,
 423         SOFT_RST_SDIO,
 424         SOFT_RST_EMMC,
 425         SOFT_RST_SPI0,
 426         SOFT_RST_SPI1,
 427         SOFT_RST_WDT,
 428         SOFT_RST_SARADC,
 429         SOFT_RST_DDRPHY,
 430         SOFT_RST_DDRPHY_APB,
 431         SOFT_RST_DDRCTRL,
 432         SOFT_RST_DDRCTRL_APB,
 433         SOFT_RST_TSADC,
 434         SOFT_RST_DDRPHY_CTL,
 435
 436         SOFT_RST_HDMI = SOFT_RST_ID(6),
 437         SOFT_RST_HDMI_AHB,
 438         SOFT_RST_VIO0_AXI,
 439         SOFT_RST_VIO_BUS_AHB,
 440         SOFT_RST_LCDC0_AXI,
 441         SOFT_RST_LCDC0_AHB,
 442         SOFT_RST_LCDC0_DCLK,
 443         SOFT_RST_LCDC1_AXI,
 444         SOFT_RST_LCDC1_AHB,
 445         SOFT_RST_LCDC1_DCLK,
 446         SOFT_RST_IPP_AXI,
 447         SOFT_RST_IPP_AHB,
 448         SOFT_RST_RGA_AXI,
 449         SOFT_RST_RGA_AHB,
 450         SOFT_RST_CIF0,
 451         SOFT_RST_CIF1,
 452
 453         SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
 454         SOFT_RST_VCODEC_AHB,
 455         SOFT_RST_VIO1_AXI,
 456         SOFT_RST_CPU_VCODEC,
 457         SOFT_RST_VCODEC_NIU_AXI,
 458         SOFT_RST_7RES5,
 459         SOFT_RST_7RES6,
 460         SOFT_RST_7RES7,
 461         SOFT_RST_GPU_AXI,
 462         SOFT_RST_7RES9,
 463         SOFT_RST_GPU_NIU_AXI,
 464         SOFT_RST_7RES11,
 465         SOFT_RST_7RES12,
 466         SOFT_RST_TFUN_ATB,
 467         SOFT_RST_TFUN_APB,
 468         SOFT_RST_CTI4_APB,
 469
 470         SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
 471         SOFT_RST_TRACE,
 472         SOFT_RST_CORE_DBG,
 473         SOFT_RST_DBG_APB,
 474         SOFT_RST_CTI0,
 475         SOFT_RST_CTI0_APB,
 476         SOFT_RST_CTI1,
 477         SOFT_RST_CTI1_APB,
 478         SOFT_RST_PTM_CORE0,
 479         SOFT_RST_PTM_CORE1,
 480         SOFT_RST_PTM0,
 481         SOFT_RST_PTM0_ATB,
 482         SOFT_RST_PTM1,
 483         SOFT_RST_PTM1_ATB,
 484         SOFT_RST_CTM,
 485         SOFT_RST_TS,
 486
 487         SOFT_RST_MAX,
 488 };
 489
 490 /*****cru reg end*****/
 491
 492 static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 493 {
 494         const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
 495         u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
 496         writel_relaxed(val, reg);
 497         dsb();
 498 }
 499
 500 #endif