arch/arm/mach-rk30/include/mach/cru-rk3066b.h

   1 enum rk_plls_id {
   2         APLL_ID = 0,
   3         DPLL_ID,
   4         CPLL_ID,
   5         GPLL_ID,
   6         END_PLL_ID,
   7 };
   8
   9 /*****cru reg offset*****/
  10
  11 #define CRU_MODE_CON            0x40
  12 #define CRU_CLKSEL_CON          0x44
  13 #define CRU_CLKGATE_CON         0xd0
  14 #define CRU_GLB_SRST_FST        0x100
  15 #define CRU_GLB_SRST_SND        0x104
  16 #define CRU_SOFTRST_CON         0x110
  17
  18 #define PLL_CONS(id, i)         ((id) * 0x10 + ((i) * 4))
  19
  20 #define CRU_CLKSELS_CON_CNT     (35)
  21 #define CRU_CLKSELS_CON(i)      (CRU_CLKSEL_CON + ((i) * 4))
  22
  23 #define CRU_CLKGATES_CON_CNT    (10)
  24 #define CRU_CLKGATES_CON(i)     (CRU_CLKGATE_CON + ((i) * 4))
  25
  26 #define CRU_SOFTRSTS_CON_CNT    (9)
  27 #define CRU_SOFTRSTS_CON(i)     (CRU_SOFTRST_CON + ((i) * 4))
  28
  29 #define CRU_MISC_CON            (0x134)
  30 #define CRU_GLB_CNT_TH          (0x140)
  31
  32 /********************************************************************/
  33 #define CRU_GET_REG_BITS_VAL(reg,bits_shift, msk)       (((reg) >> (bits_shift))&(msk))
  34 #define CRU_W_MSK(bits_shift, msk)      ((msk) << ((bits_shift) + 16))
  35 #define CRU_SET_BITS(val,bits_shift, msk)       (((val)&(msk)) << (bits_shift))
  36
  37 #define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
  38
  39 /*******************PLL CON0 BITS***************************/
  40
  41 #define PLL_CLKFACTOR_SET(val, shift, msk) \
  42         ((((val) - 1) & (msk)) << (shift))
  43
  44 #define PLL_CLKFACTOR_GET(reg, shift, msk) \
  45         ((((reg) >> (shift)) & (msk)) + 1)
  46
  47 #define PLL_OD_MSK              (0x3f)
  48 #define PLL_OD_SHIFT            (0x0)
  49
  50 #define PLL_CLKOD(val)          PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
  51 #define PLL_NO(reg)             PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
  52
  53 #define PLL_NO_SHIFT(reg)       PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
  54
  55 #define PLL_CLKOD_SET(val)      (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
  56
  57 #define PLL_NR_MSK              (0x3f)
  58 #define PLL_NR_SHIFT            (8)
  59 #define PLL_CLKR(val)           PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
  60 #define PLL_NR(reg)             PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
  61
  62 #define PLL_CLKR_SET(val)       (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
  63
  64 /*******************PLL CON1 BITS***************************/
  65
  66 #define PLL_NF_MSK              (0xffff)
  67 #define PLL_NF_SHIFT            (0)
  68 #define PLL_CLKF(val)           PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
  69 #define PLL_NF(reg)             PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
  70
  71 #define PLL_CLKF_SET(val)       (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
  72
  73 /*******************PLL CON2 BITS***************************/
  74 #if 0
  75 #define PLL_BWADJ_MSK           (0xfff)
  76 #define PLL_BWADJ_SHIFT         (0)
  77 #define PLL_CLK_BWADJ_SET(val)  ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
  78 #endif
  79 /*******************PLL CON3 BITS***************************/
  80
  81 #if 0
  82 #define PLL_REST_MSK            (1 << 5)
  83 #define PLL_REST_W_MSK          (PLL_REST_MSK << 16)
  84 #define PLL_REST                (1 << 5)
  85 #define PLL_REST_RESM           (0 << 5)
  86 #endif
  87
  88 #define PLL_BYPASS_MSK          (1 << 0)
  89 #define PLL_BYPASS              (1 << 0)
  90 #define PLL_NO_BYPASS           (0 << 0)
  91
  92 #define PLL_PWR_DN_MSK          (1 << 1)
  93 #define PLL_PWR_DN_W_MSK        (PLL_PWR_DN_MSK << 16)
  94 #define PLL_PWR_DN              (1 << 1)
  95 #define PLL_PWR_ON              (0 << 1)
  96
  97 #define PLL_STANDBY_MSK         (1 << 2)
  98 #define PLL_STANDBY             (1 << 2)
  99 #define PLL_NO_STANDBY          (0 << 2)
 100 /*******************CLKSEL0 BITS***************************/
 101 //core preiph div
 102 #define CORE_PERIPH_W_MSK       (3 << 22)
 103 #define CORE_PERIPH_MSK         (3 << 6)
 104 #define CORE_PERIPH_2           (0 << 6)
 105 #define CORE_PERIPH_4           (1 << 6)
 106 #define CORE_PERIPH_8           (2 << 6)
 107 #define CORE_PERIPH_16          (3 << 6)
 108 //arm clk pll sel
 109 #define CORE_SEL_PLL_MSK        (1 << 8)
 110 #define CORE_SEL_PLL_W_MSK      (1 << 24)
 111 #define CORE_SEL_APLL           (0 << 8)
 112 #define CORE_SEL_GPLL           (1 << 8)
 113
 114 #define CORE_CLK_DIV_W_MSK      (0x1F << 25)
 115 #define CORE_CLK_DIV_MSK        (0x1F << 9)
 116 #define CORE_CLK_DIV(i)         (((i) - 1) & 0x1F)
 117
 118 #define CPU_SEL_PLL_MSK         (1 << 5)
 119 #define CPU_SEL_PLL_W_MSK       (1 << 21)
 120 #define CPU_SEL_APLL            (0 << 5)
 121 #define CPU_SEL_GPLL            (1 << 5)
 122
 123 #define CPU_CLK_DIV_W_MSK       (0x1F << 16)
 124 #define CPU_CLK_DIV_MSK         (0x1F)
 125 #define CPU_CLK_DIV(i)          (((i) - 1) & 0x1F)
 126
 127 /*******************CLKSEL1 BITS***************************/
 128 //aclk div
 129 #define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
 130
 131 #define CPU_ACLK_W_MSK          (7 << 16)
 132 #define CPU_ACLK_MSK            (7 << 0)
 133 #define CPU_ACLK_11             (0 << 0)
 134 #define CPU_ACLK_21             (1 << 0)
 135 #define CPU_ACLK_31             (2 << 0)
 136 #define CPU_ACLK_41             (3 << 0)
 137 #define CPU_ACLK_81             (4 << 0)
 138
 139 #define CORE_ACLK_W_MSK         (7 << 19)
 140 #define CORE_ACLK_MSK           (7 << 3)
 141 #define CORE_ACLK_11            (0 << 3)
 142 #define CORE_ACLK_21            (1 << 3)
 143 #define CORE_ACLK_31            (2 << 3)
 144 #define CORE_ACLK_41            (3 << 3)
 145 #define CORE_ACLK_81            (4 << 3)
 146 //hclk div
 147 #define ACLK_HCLK_W_MSK         (3 << 24)
 148 #define ACLK_HCLK_MSK           (3 << 8)
 149 #define ACLK_HCLK_11            (0 << 8)
 150 #define ACLK_HCLK_21            (1 << 8)
 151 #define ACLK_HCLK_41            (2 << 8)
 152 // pclk div
 153 #define ACLK_PCLK_W_MSK         (3 << 28)
 154 #define ACLK_PCLK_MSK           (3 << 12)
 155 #define ACLK_PCLK_11            (0 << 12)
 156 #define ACLK_PCLK_21            (1 << 12)
 157 #define ACLK_PCLK_41            (2 << 12)
 158 #define ACLK_PCLK_81            (3 << 12)
 159 // ahb2apb div
 160 #define AHB2APB_W_MSK           (3 << 30)
 161 #define AHB2APB_MSK             (3 << 14)
 162 #define AHB2APB_11              (0 << 14)
 163 #define AHB2APB_21              (1 << 14)
 164 #define AHB2APB_41              (2 << 14)
 165
 166 /*******************MODE BITS***************************/
 167
 168 #define PLL_MODE_MSK(id)        (0x3 << ((id) * 4))
 169 #define PLL_MODE_SLOW(id)       ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
 170 #define PLL_MODE_NORM(id)       ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
 171 #define PLL_MODE_DEEP(id)       ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
 172
 173 /*******************clksel10***************************/
 174
 175 #define PERI_ACLK_DIV_MASK 0x1f
 176 #define PERI_ACLK_DIV_OFF 0
 177
 178 #define PERI_HCLK_DIV_MASK 0x3
 179 #define PERI_HCLK_DIV_OFF 8
 180
 181 #define PERI_PCLK_DIV_MASK 0x3
 182 #define PERI_PCLK_DIV_OFF 12
 183
 184 /*******************gate BITS***************************/
 185
 186 #define CLK_GATE_CLKID(i)       (16 * (i))
 187 #define CLK_GATE_CLKID_CONS(i)  CRU_CLKGATES_CON((i) / 16)
 188
 189 #define CLK_GATE(i)             (1 << ((i)%16))
 190 #define CLK_UN_GATE(i)          (0)
 191
 192 #define CLK_GATE_W_MSK(i)       (1 << (((i) % 16) + 16))
 193
 194 enum cru_clk_gate {
 195         /* SCU CLK GATE 0 CON */
 196         CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
 197         CLK_GATE_CPU_GPLL_PATH,
 198         CLK_GATE_DDRPHY,
 199         CLK_GATE_ACLK_CPU,
 200
 201         CLK_GATE_HCLK_CPU,
 202         CLK_GATE_PCLK_CPU,
 203         CLK_GATE_ATCLK_CPU,
 204         CLK_GATE_ACLK_CORE,
 205
 206         CLK_GATE_0RES8,
 207         CLK_GATE_I2S0_SRC,
 208         CLK_GATE_I2S0_FRAC,
 209         CLK_GATE_0RES11,
 210
 211         CLK_GATE_0RES12,
 212         CLK_GATE_SPDIF_SRC,
 213         CLK_GATE_SPDIF_FRAC,
 214         CLK_GATE_TESTCLK,
 215
 216         CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
 217         CLK_GATE_TIMER1,
 218         CLK_GATE_TIMER2,
 219         CLK_GATE_JTAG,
 220
 221         CLK_GATE_ACLK_LCDC1_SRC,
 222         CLK_GATE_OTGPHY0,
 223         CLK_GATE_OTGPHY1,
 224         CLK_GATE_DDR_GPLL,
 225
 226         CLK_GATE_UART0_SRC,
 227         CLK_GATE_UART0_FRAC_SRC,
 228         CLK_GATE_UART1_SRC,
 229         CLK_GATE_UART1_FRAC_SRC,
 230
 231         CLK_GATE_UART2_SRC,
 232         CLK_GATE_UART2_FRAC_SRC,
 233         CLK_GATE_UART3_SRC,
 234         CLK_GATE_UART3_FRAC_SRC,
 235
 236         CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
 237         CLK_GATE_ACLK_PERIPH,
 238         CLK_GATE_HCLK_PERIPH,
 239         CLK_GATE_PCLK_PERIPH,
 240
 241         CLK_GATE_SMC_SRC,
 242         CLK_GATE_MAC_SRC,
 243         CLK_GATE_HSADC_SRC,
 244         CLK_GATE_HSADC_FRAC_SRC,
 245
 246         CLK_GATE_SARADC_SRC,
 247         CLK_GATE_SPI0_SRC,
 248         CLK_GATE_SPI1_SRC,
 249         CLK_GATE_MMC0_SRC,
 250
 251         CLK_GATE_MAC_LBTEST,
 252         CLK_GATE_SDIO_SRC,
 253         CLK_GATE_EMMC_SRC,
 254         CLK_GATE_2RES15,
 255
 256         CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
 257         CLK_GATE_DCLK_LCDC0_SRC,
 258         CLK_GATE_DCLK_LCDC1_SRC,
 259         CLK_GATE_PCLKIN_CIF0,
 260
 261         CLK_GATE_3RES4,
 262         CLK_GATE_3RES5,
 263         CLK_GATE_HSICPHY_SRC,
 264         CLK_GATE_CIF0_OUT,
 265
 266         CLK_GATE_3RES8,
 267         CLK_GATE_ACLK_VEPU,
 268         CLK_GATE_HCLK_VEPU,
 269         CLK_GATE_ACLK_VDPU,
 270
 271         CLK_GATE_HCLK_VDPU,
 272         CLK_GATE_3RES13,
 273         CLK_GATE_3RES14,
 274         CLK_GATE_3RES15,
 275
 276         CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
 277         CLK_GATE_PCLK_PERI_AXI_MATRIX,
 278         CLK_GATE_ACLK_CPU_PERI,
 279         CLK_GATE_ACLK_PERI_AXI_MATRIX,
 280
 281         CLK_GATE_ACLK_PEI_NIU,
 282         CLK_GATE_HCLK_USB_PERI,
 283         CLK_GATE_HCLK_PERI_AHB_ARBI,
 284         CLK_GATE_HCLK_EMEM_PERI,
 285
 286         CLK_GATE_HCLK_CPUBUS,
 287         CLK_GATE_HCLK_AHB2APB,
 288         CLK_GATE_ACLK_STRC_SYS,
 289         CLK_GATE_ACLK_L2MEM_CON,
 290
 291         CLK_GATE_ACLK_INTMEM,
 292         CLK_GATE_4RES13,
 293         CLK_GATE_4RES14,
 294         CLK_GATE_HCLK_L2MEM,
 295
 296         CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
 297         CLK_GATE_ACLK_DMAC2,
 298         CLK_GATE_PCLK_EFUSE,
 299         CLK_GATE_PCLK_TZPC,
 300
 301         CLK_GATE_PCLK_GRF,
 302         CLK_GATE_PCLK_PMU,
 303         CLK_GATE_HCLK_ROM,
 304         CLK_GATE_PCLK_DDRUPCTL,
 305
 306         CLK_GATE_ACLK_SMC,
 307         CLK_GATE_HCLK_NANDC,
 308         CLK_GATE_HCLK_SDMMC0,
 309         CLK_GATE_HCLK_SDIO,
 310
 311         CLK_GATE_HCLK_EMMC,
 312         CLK_GATE_HCLK_OTG0,
 313         CLK_GATE_5RES14,
 314         CLK_GATE_5RES15,
 315
 316         CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
 317         CLK_GATE_HCLK_LCDC0,
 318         CLK_GATE_HCLK_LCDC1,
 319         CLK_GATE_ACLK_LCDC1,
 320
 321         CLK_GATE_HCLK_CIF0,
 322         CLK_GATE_ACLK_CIF0,
 323         CLK_GATE_6RES6,
 324         CLK_GATE_6RES7,
 325
 326         CLK_GATE_ACLK_IPP,
 327         CLK_GATE_HCLK_IPP,
 328         CLK_GATE_HCLK_RGA,
 329         CLK_GATE_ACLK_RGA,
 330
 331         CLK_GATE_HCLK_VIO_BUS,
 332         CLK_GATE_ACLK_VIO0,
 333         CLK_GATE_ACLK_VCODEC,
 334         CLK_GATE_HCLK_VIDEO_H2H,
 335
 336         CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
 337         CLK_GATE_HCLK_SPDIF,
 338         CLK_GATE_HCLK_I2S0_2CH,
 339         CLK_GATE_HCLK_OTG1,
 340
 341         CLK_GATE_HCLK_HSIC,
 342         CLK_GATE_HCLK_HSADC,
 343         CLK_GATE_HCLK_PIDF,
 344         CLK_GATE_PCLK_TIMER0,
 345
 346         CLK_GATE_PCLK_TIMER1,
 347         CLK_GATE_PCLK_TIMER2,
 348         CLK_GATE_PCLK_PWM01,
 349         CLK_GATE_PCLK_PWM23,
 350
 351         CLK_GATE_PCLK_SPI0,
 352         CLK_GATE_PCLK_SPI1,
 353         CLK_GATE_PCLK_SARADC,
 354         CLK_GATE_PCLK_WDT,
 355
 356         CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
 357         CLK_GATE_PCLK_UART1,
 358         CLK_GATE_PCLK_UART2,
 359         CLK_GATE_PCLK_UART3,
 360
 361         CLK_GATE_PCLK_I2C0,
 362         CLK_GATE_PCLK_I2C1,
 363         CLK_GATE_PCLK_I2C2,
 364         CLK_GATE_PCLK_I2C3,
 365
 366         CLK_GATE_PCLK_I2C4,
 367         CLK_GATE_PCLK_GPIO0,
 368         CLK_GATE_PCLK_GPIO1,
 369         CLK_GATE_PCLK_GPIO2,
 370
 371         CLK_GATE_PCLK_GPIO3,
 372         CLK_GATE_HCLK_GPS,
 373         CLK_GATE_8RES14,
 374         CLK_GATE_8RES15,
 375
 376         CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
 377         CLK_GATE_PCLK_DBG,
 378         CLK_GATE_CLK_TRACE,
 379         CLK_GATE_ATCLK,
 380
 381         CLK_GATE_CLK_L2C,
 382         CLK_GATE_ACLK_VIO1,
 383         CLK_GATE_PCLK_PUBL,
 384         CLK_GATE_ACLK_GPU_MST,
 385
 386         CLK_GATE_ACLK_GPU_SLV,
 387         CLK_GATE_CLK_GPU,
 388         CLK_GATE_9RES10,
 389         CLK_GATE_9RES11,
 390
 391         CLK_GATE_9RES12,
 392         CLK_GATE_9RES13,
 393         CLK_GATE_9RES14,
 394         CLK_GATE_9RES15,
 395
 396         CLK_GATE_MAX,
 397 };
 398
 399 /* for compatible with rk30xx */
 400 #define CLK_GATE_ACLK_CIF1      CLK_GATE_ACLK_CIF0
 401 #define CLK_GATE_ACLK_INTMEM0   CLK_GATE_CLK_L2C
 402 #define CLK_GATE_ACLK_INTMEM1   CLK_GATE_ACLK_INTMEM0
 403 #define CLK_GATE_ACLK_INTMEM2   CLK_GATE_ACLK_INTMEM0
 404 #define CLK_GATE_ACLK_INTMEM3   CLK_GATE_ACLK_INTMEM0
 405
 406 #define SOFT_RST_ID(i)          (16 * (i))
 407
 408 enum cru_soft_reset {
 409         SOFT_RST_0RES0 = SOFT_RST_ID(0),
 410         SOFT_RST_0RES1,
 411         SOFT_RST_MCORE,
 412         SOFT_RST_CORE0,
 413
 414         SOFT_RST_CORE1,
 415         SOFT_RST_0RES5,
 416         SOFT_RST_0RES6,
 417         SOFT_RST_MCORE_DBG,
 418
 419         SOFT_RST_CORE0_DBG,
 420         SOFT_RST_CORE1_DBG,
 421         SOFT_RST_0RES10,
 422         SOFT_RST_0RES11,
 423
 424         SOFT_RST_CORE0_WDT,
 425         SOFT_RST_CORE1_WDT,
 426         SOFT_RST_STRC_SYS_AXI,
 427         SOFT_RST_L2C,
 428
 429         SOFT_RST_1RES0 = SOFT_RST_ID(1),
 430         SOFT_RST_CPUSYS_AHB,
 431         SOFT_RST_L2MEM_CON_AXI,
 432         SOFT_RST_AHB2APB,
 433
 434         SOFT_RST_DMA1,
 435         SOFT_RST_INTMEM,
 436         SOFT_RST_ROM,
 437         SOFT_RST_1RES7,
 438
 439         SOFT_RST_I2S,
 440         SOFT_RST_1RES9,
 441         SOFT_RST_SPDIF,
 442         SOFT_RST_TIMER0,
 443
 444         SOFT_RST_TIMER1,
 445         SOFT_RST_TIMER2,
 446         SOFT_RST_EFUSE_APB,
 447         SOFT_RST_1RES15,
 448
 449         SOFT_RST_GPIO0 = SOFT_RST_ID(2),
 450         SOFT_RST_GPIO1,
 451         SOFT_RST_GPIO2,
 452         SOFT_RST_GPIO3,
 453
 454         SOFT_RST_2RES4,
 455         SOFT_RST_2RES5,
 456         SOFT_RST_2RES6,
 457         SOFT_RST_UART0,
 458
 459         SOFT_RST_UART1,
 460         SOFT_RST_UART2,
 461         SOFT_RST_UART3,
 462         SOFT_RST_I2C0,
 463
 464         SOFT_RST_I2C1,
 465         SOFT_RST_I2C2,
 466         SOFT_RST_I2C3,
 467         SOFT_RST_I2C4,
 468
 469         SOFT_RST_PWM0 = SOFT_RST_ID(3),
 470         SOFT_RST_PWM1,
 471         SOFT_RST_DAP_PO,
 472         SOFT_RST_DAP,
 473
 474         SOFT_RST_DAP_SYS,
 475         SOFT_RST_TPIU_ATB,
 476         SOFT_RST_PMU_APB,
 477         SOFT_RST_GRF,
 478
 479         SOFT_RST_PMU,
 480         SOFT_RST_PERIPHSYS_AXI,
 481         SOFT_RST_PERIPHSYS_AHB,
 482         SOFT_RST_PERIPHSYS_APB,
 483
 484         SOFT_RST_PERIPH_NIU,
 485         SOFT_RST_CPU_PERI,
 486         SOFT_RST_EMEM_PERI,
 487         SOFT_RST_USB_PERI,
 488
 489         SOFT_RST_DMA2 = SOFT_RST_ID(4),
 490         SOFT_RST_SMC,
 491         SOFT_RST_MAC,
 492         SOFT_RST_GPS,
 493
 494         SOFT_RST_NANDC,
 495         SOFT_RST_USBOTG0,
 496         SOFT_RST_USBPHY0,
 497         SOFT_RST_OTGC0,
 498
 499         SOFT_RST_USBOTG1,
 500         SOFT_RST_USBPHY1,
 501         SOFT_RST_OTGC1,
 502         SOFT_RST_HSICPHY,
 503
 504         SOFT_RST_HSADC,
 505         SOFT_RST_PIDFILTER,
 506         SOFT_RST_4RES14,
 507         SOFT_RST_DDRMSCH,
 508
 509         SOFT_RST_TZPC = SOFT_RST_ID(5),
 510         SOFT_RST_MMC0,
 511         SOFT_RST_SDIO,
 512         SOFT_RST_EMMC,
 513
 514         SOFT_RST_SPI0,
 515         SOFT_RST_SPI1,
 516         SOFT_RST_WDT,
 517         SOFT_RST_SARADC,
 518
 519         SOFT_RST_DDRPHY,
 520         SOFT_RST_DDRPHY_APB,
 521         SOFT_RST_DDRCTRL,
 522         SOFT_RST_DDRCTRL_APB,
 523
 524         SOFT_RST_5RES12,
 525         SOFT_RST_DDRPHY_CTL,
 526         SOFT_RST_5RES14,
 527         SOFT_RST_5RES15,
 528
 529         SOFT_RST_6RES0 = SOFT_RST_ID(6),
 530         SOFT_RST_6RES1,
 531         SOFT_RST_VIO0_AXI,
 532         SOFT_RST_VIO_BUS_AHB,
 533
 534         SOFT_RST_LCDC0_AXI,
 535         SOFT_RST_LCDC0_AHB,
 536         SOFT_RST_LCDC0_DCLK,
 537         SOFT_RST_LCDC1_AXI,
 538
 539         SOFT_RST_LCDC1_AHB,
 540         SOFT_RST_LCDC1_DCLK,
 541         SOFT_RST_IPP_AXI,
 542         SOFT_RST_IPP_AHB,
 543
 544         SOFT_RST_RGA_AXI,
 545         SOFT_RST_RGA_AHB,
 546         SOFT_RST_CIF0,
 547         SOFT_RST_CIF1,//SOFT_RST_6RES15,
 548
 549         SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
 550         SOFT_RST_VCODEC_AHB,
 551         SOFT_RST_VIO1_AXI,
 552         SOFT_RST_CPU_VCODEC,
 553
 554         SOFT_RST_VCODEC_NIU_AXI,
 555         SOFT_RST_HSIC_AHB,
 556         SOFT_RST_7RES6,
 557         SOFT_RST_7RES7,
 558
 559         SOFT_RST_GPU_CORE,
 560         SOFT_RST_7RES9,
 561         SOFT_RST_GPU_NIU_AXI,
 562         SOFT_RST_7RES11,
 563
 564         SOFT_RST_7RES12,
 565         SOFT_RST_TFUN_ATB,
 566         SOFT_RST_TFUN_APB,
 567         SOFT_RST_CTI4_APB,
 568
 569         SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
 570         SOFT_RST_TRACE,
 571         SOFT_RST_CORE_DBG,
 572         SOFT_RST_DBG_APB,
 573
 574         SOFT_RST_CTI0,
 575         SOFT_RST_CTI0_APB,
 576         SOFT_RST_CTI1,
 577         SOFT_RST_CTI1_APB,
 578
 579         SOFT_RST_PTM_CORE0,
 580         SOFT_RST_PTM_CORE1,
 581         SOFT_RST_PTM0,
 582         SOFT_RST_PTM0_ATB,
 583
 584         SOFT_RST_PTM1,
 585         SOFT_RST_PTM1_ATB,
 586         SOFT_RST_CTM,
 587         SOFT_RST_TS,
 588
 589         SOFT_RST_MAX,
 590 };
 591
 592 /*****cru reg end*****/
 593
 594 static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 595 {
 596         const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
 597         u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
 598         writel_relaxed(val, reg);
 599         dsb();
 600 }