2 * arch/arm/mach-rk30/ddr.c
4 * Function Driver for DDR controller
6 * Copyright (C) 2011 Fuzhou Rockchip Electronics Co.,Ltd
14 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/clk.h>
19 #include <asm/cacheflush.h>
20 #include <asm/tlbflush.h>
22 #include <mach/sram.h>
25 typedef uint32_t uint32;
27 #define DDR3_DDR2_DLL_DISABLE_FREQ (125)
28 #define DDR3_DDR2_ODT_DISABLE_FREQ (333)
29 #define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
30 #define PD_IDLE (0X40) //unit:DDR clk cycle, and 0 for disable auto power-down
32 #define PMU_BASE_ADDR RK30_PMU_BASE
33 #define SDRAMC_BASE_ADDR RK30_DDR_PCTL_BASE
34 #define DDR_PUBL_BASE RK30_DDR_PUBL_BASE
35 #define CRU_BASE_ADDR RK30_CRU_BASE
36 #define REG_FILE_BASE_ADDR RK30_GRF_BASE
37 #define SysSrv_DdrConf (RK30_CPU_AXI_BUS_BASE+0x08)
38 #define SysSrv_DdrTiming (RK30_CPU_AXI_BUS_BASE+0x0c)
39 #define SysSrv_DdrMode (RK30_CPU_AXI_BUS_BASE+0x10)
40 #define SysSrv_ReadLatency (RK30_CPU_AXI_BUS_BASE+0x14)
42 #define ddr_print(x...) printk( "DDR DEBUG: " x )
44 /***********************************
46 ***********************************/
47 //MR0 (Device Information)
48 #define LPDDR2_DAI (0x1) // 0:DAI complete, 1:DAI still in progress
49 #define LPDDR2_DI (0x1<<1) // 0:S2 or S4 SDRAM, 1:NVM
50 #define LPDDR2_DNVI (0x1<<2) // 0:DNV not supported, 1:DNV supported
51 #define LPDDR2_RZQI (0x3<<3) // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
52 // 10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.
54 //MR1 (Device Feature)
55 #define LPDDR2_BL4 (0x2)
56 #define LPDDR2_BL8 (0x3)
57 #define LPDDR2_BL16 (0x4)
58 #define LPDDR2_nWR(n) (((n)-2)<<5)
60 //MR2 (Device Feature 2)
61 #define LPDDR2_RL3_WL1 (0x1)
62 #define LPDDR2_RL4_WL2 (0x2)
63 #define LPDDR2_RL5_WL2 (0x3)
64 #define LPDDR2_RL6_WL3 (0x4)
65 #define LPDDR2_RL7_WL4 (0x5)
66 #define LPDDR2_RL8_WL4 (0x6)
68 //MR3 (IO Configuration 1)
69 #define LPDDR2_DS_34 (0x1)
70 #define LPDDR2_DS_40 (0x2)
71 #define LPDDR2_DS_48 (0x3)
72 #define LPDDR2_DS_60 (0x4)
73 #define LPDDR2_DS_80 (0x6)
74 #define LPDDR2_DS_120 (0x7) //optional
76 //MR4 (Device Temperature)
77 #define LPDDR2_tREF_MASK (0x7)
78 #define LPDDR2_4_tREF (0x1)
79 #define LPDDR2_2_tREF (0x2)
80 #define LPDDR2_1_tREF (0x3)
81 #define LPDDR2_025_tREF (0x5)
82 #define LPDDR2_025_tREF_DERATE (0x6)
84 #define LPDDR2_TUF (0x1<<7)
86 //MR8 (Basic configuration 4)
87 #define LPDDR2_S4 (0x0)
88 #define LPDDR2_S2 (0x1)
89 #define LPDDR2_N (0x2)
90 #define LPDDR2_Density(mr8) (8<<(((mr8)>>2)&0xf)) // Unit:MB
91 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
94 #define LPDDR2_ZQINIT (0xFF)
95 #define LPDDR2_ZQCL (0xAB)
96 #define LPDDR2_ZQCS (0x56)
97 #define LPDDR2_ZQRESET (0xC3)
99 //MR16 (PASR Bank Mask)
101 #define LPDDR2_PASR_Full (0x0)
102 #define LPDDR2_PASR_1_2 (0x1)
103 #define LPDDR2_PASR_1_4 (0x2)
104 #define LPDDR2_PASR_1_8 (0x3)
106 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
108 //MR32 (DQ Calibration Pattern A)
110 //MR40 (DQ Calibration Pattern B)
112 /***********************************
114 ***********************************/
117 #define DDR3_BC4_8 (1)
119 #define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
120 #define DDR3_WR(n) (((n)&0x7)<<9)
121 #define DDR3_DLL_RESET (1<<8)
122 #define DDR3_DLL_DeRESET (0<<8)
125 #define DDR3_DLL_ENABLE (0)
126 #define DDR3_DLL_DISABLE (1)
127 #define DDR3_MR1_AL(n) (((n)&0x3)<<3)
129 #define DDR3_DS_40 (0)
130 #define DDR3_DS_34 (1<<1)
131 #define DDR3_Rtt_Nom_DIS (0)
132 #define DDR3_Rtt_Nom_60 (1<<2)
133 #define DDR3_Rtt_Nom_120 (1<<6)
134 #define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
137 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
138 #define DDR3_Rtt_WR_DIS (0)
139 #define DDR3_Rtt_WR_60 (1<<9)
140 #define DDR3_Rtt_WR_120 (2<<9)
142 /***********************************
144 ***********************************/
145 //MR; //Mode Register
148 #define DDR2_CL(n) (((n)&0x7)<<4)
149 #define DDR2_WR(n) ((((n)-1)&0x7)<<9)
150 #define DDR2_DLL_RESET (1<<8)
151 #define DDR2_DLL_DeRESET (0<<8)
153 //EMR; //Extended Mode Register
154 #define DDR2_DLL_ENABLE (0)
155 #define DDR2_DLL_DISABLE (1)
157 #define DDR2_STR_FULL (0)
158 #define DDR2_STR_REDUCE (1<<1)
159 #define DDR2_AL(n) (((n)&0x7)<<3)
160 #define DDR2_Rtt_Nom_DIS (0)
161 #define DDR2_Rtt_Nom_150 (0x40)
162 #define DDR2_Rtt_Nom_75 (0x4)
163 #define DDR2_Rtt_Nom_50 (0x44)
165 /***********************************
167 ***********************************/
171 #define mDDR_CL(n) (((n)&0x7)<<4)
173 #define mDDR_DS_Full (0)
174 #define mDDR_DS_1_2 (1<<5)
175 #define mDDR_DS_1_4 (2<<5)
176 #define mDDR_DS_1_8 (3<<5)
177 #define mDDR_DS_3_4 (4<<5)
181 #define idle_req_cpu_cfg (1<<1)
182 #define idle_req_peri_cfg (1<<2)
183 #define idle_req_gpu_cfg (1<<3)
184 #define idle_req_video_cfg (1<<4)
185 #define idle_req_vio_cfg (1<<5)
188 #define idle_cpu (1<<26)
189 #define idle_peri (1<<25)
190 #define idle_gpu (1<<24)
191 #define idle_video (1<<23)
192 #define idle_vio (1<<22)
194 #define pd_a9_0_pwr_st (1<<0)
195 #define pd_a9_1_pwr_st (1<<1)
196 #define pd_peri_pwr_st (1<<6)
197 #define pd_vio_pwr_st (1<<7)
198 #define pd_video_pwr_st (1<<8)
199 #define pd_gpu_pwr_st (1<<9)
203 typedef volatile struct tagPMU_FILE
205 uint32 PMU_WAKEUP_CFG[2];
206 uint32 PMU_PWRDN_CON;
214 uint32 PMU_DDRIO_PWRON_CNT;
215 uint32 PMU_WAKEUP_RST_CLR_CNT;
216 uint32 PMU_SCU_PWRDWN_CNT;
217 uint32 PMU_SCU_PWRUP_CNT;
218 uint32 PMU_MISC_CON1;
219 uint32 PMU_GPIO6_CON;
220 uint32 PMU_PMU_SYS_REG[4];
221 } PMU_FILE, *pPMU_FILE;
223 #define pPMU_Reg ((pPMU_FILE)PMU_BASE_ADDR)
225 #define PLL_RESET (((0x1<<5)<<16) | (0x1<<5))
226 #define PLL_DE_RESET (((0x1<<5)<<16) | (0x0<<5))
227 #define NR(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
228 #define NO(n) ((0xF<<16) | ((n)-1))
229 #define NF(n) ((0x1FFF<<16) | ((n)-1))
230 #define NB(n) ((0xFFF<<16) | ((n)-1))
232 typedef volatile struct tagCRU_STRUCT
234 uint32 CRU_PLL_CON[4][4];
236 uint32 CRU_CLKSEL_CON[35];
237 uint32 CRU_CLKGATE_CON[10];
239 uint32 CRU_GLB_SRST_FST_VALUE;
240 uint32 CRU_GLB_SRST_SND_VALUE;
242 uint32 CRU_SOFTRST_CON[9];
245 uint32 CRU_GLB_CNT_TH;
246 } CRU_REG, *pCRU_REG;
248 #define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
250 #define bank2_to_rank_en ((1<<2) | ((1<<2)<<16))
251 #define bank2_to_rank_dis ((0<<2) | ((1<<2)<<16))
252 #define rank_to_row15_en ((1<<1) | ((1<<1)<<16))
253 #define rank_to_row15_dis ((0<<1) | ((1<<1)<<16))
255 typedef struct tagGPIO_LH
261 typedef struct tagGPIO_IOMUX
270 typedef volatile struct tagREG_FILE
272 GPIO_LH_T GRF_GPIO_DIR[7];
273 GPIO_LH_T GRF_GPIO_DO[7];
274 GPIO_LH_T GRF_GPIO_EN[7];
275 GPIO_IOMUX_T GRF_GPIO_IOMUX[7];
276 GPIO_LH_T GRF_GPIO_PULL[7];
277 uint32 GRF_SOC_CON[3];
278 uint32 GRF_SOC_STATUS0;
279 uint32 GRF_DMAC1_CON[3];
280 uint32 GRF_DMAC2_CON[4];
281 uint32 GRF_UOC0_CON[3];
282 uint32 GRF_UOC1_CON[4];
283 uint32 GRF_DDRC_CON0;
284 uint32 GRF_DDRC_STAT;
285 uint32 reserved[(0x1c8-0x1a0)/4];
286 uint32 GRF_OS_REG[4];
287 } REG_FILE, *pREG_FILE;
289 #define pGRF_Reg ((pREG_FILE)REG_FILE_BASE_ADDR)
292 #define INIT_STATE (0)
293 #define CFG_STATE (1)
295 #define SLEEP_STATE (3)
296 #define WAKEUP_STATE (4)
301 #define Config_req (2)
303 #define Access_req (4)
304 #define Low_power (5)
305 #define Low_power_entry_req (6)
306 #define Low_power_exit_req (7)
309 #define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
310 #define pd_idle(n) ((n)<<8)
311 #define mddr_en (2<<22)
312 #define lpddr2_en (3<<22)
313 #define ddr2_en (0<<5)
314 #define ddr3_en (1<<5)
315 #define lpddr2_s2 (0<<6)
316 #define lpddr2_s4 (1<<6)
317 #define mddr_lpddr2_bl_2 (0<<20)
318 #define mddr_lpddr2_bl_4 (1<<20)
319 #define mddr_lpddr2_bl_8 (2<<20)
320 #define mddr_lpddr2_bl_16 (3<<20)
321 #define ddr2_ddr3_bl_4 (0)
322 #define ddr2_ddr3_bl_8 (1)
323 #define tfaw_cfg(n) (((n)-4)<<18)
324 #define pd_exit_slow (0<<17)
325 #define pd_exit_fast (1<<17)
326 #define pd_type(n) ((n)<<16)
327 #define two_t_en(n) ((n)<<3)
328 #define bl8int_en(n) ((n)<<2)
329 #define cke_or_en(n) ((n)<<1)
332 #define power_up_start (1<<0)
335 #define power_up_done (1<<0)
338 #define dfi_init_complete (1<<0)
341 #define cmd_tstat (1<<0)
344 #define cmd_tstat_en (1<<1)
347 #define Deselect_cmd (0)
357 #define lpddr2_op(n) ((n)<<12)
358 #define lpddr2_ma(n) ((n)<<4)
360 #define bank_addr(n) ((n)<<17)
361 #define cmd_addr(n) ((n)<<4)
363 #define start_cmd (1u<<31)
365 typedef union STAT_Tag
370 unsigned ctl_stat : 3;
371 unsigned reserved3 : 1;
372 unsigned lp_trig : 3;
373 unsigned reserved7_31 : 25;
377 typedef union SCFG_Tag
382 unsigned hw_low_power_en : 1;
383 unsigned reserved1_5 : 5;
384 unsigned nfifo_nif1_dis : 1;
385 unsigned reserved7 : 1;
386 unsigned bbflags_timing : 4;
387 unsigned reserved12_31 : 20;
391 /* DDR Controller register struct */
392 typedef volatile struct DDR_REG_Tag
394 //Operational State, Control, and Status Registers
395 SCFG_T SCFG; //State Configuration Register
396 volatile uint32 SCTL; //State Control Register
397 STAT_T STAT; //State Status Register
398 volatile uint32 INTRSTAT; //Interrupt Status Register
399 uint32 reserved0[(0x40-0x10)/4];
400 //Initailization Control and Status Registers
401 volatile uint32 MCMD; //Memory Command Register
402 volatile uint32 POWCTL; //Power Up Control Registers
403 volatile uint32 POWSTAT; //Power Up Status Register
404 volatile uint32 CMDTSTAT; //Command Timing Status Register
405 volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
406 uint32 reserved1[(0x60-0x54)/4];
407 volatile uint32 MRRCFG0; //MRR Configuration 0 Register
408 volatile uint32 MRRSTAT0; //MRR Status 0 Register
409 volatile uint32 MRRSTAT1; //MRR Status 1 Register
410 uint32 reserved2[(0x7c-0x6c)/4];
411 //Memory Control and Status Registers
412 volatile uint32 MCFG1; //Memory Configuration 1 Register
413 volatile uint32 MCFG; //Memory Configuration Register
414 volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
415 volatile uint32 MSTAT; //Memory Status Register
416 volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
418 //DTU Control and Status Registers
419 volatile uint32 DTUPDES; //DTU Status Register
420 volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
421 volatile uint32 DTUNE; //DTU Number of Errors Register
422 volatile uint32 DTUPRD0; //DTU Parallel Read 0
423 volatile uint32 DTUPRD1; //DTU Parallel Read 1
424 volatile uint32 DTUPRD2; //DTU Parallel Read 2
425 volatile uint32 DTUPRD3; //DTU Parallel Read 3
426 volatile uint32 DTUAWDT; //DTU Address Width
427 uint32 reserved4[(0xc0-0xb4)/4];
428 //Memory Timing Registers
429 volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
430 volatile uint32 TINIT; //t_init Timing Register
431 volatile uint32 TRSTH; //Reset High Time Register
432 volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
433 volatile uint32 TREFI; //t_refi Timing Register
434 volatile uint32 TMRD; //t_mrd Timing Register
435 volatile uint32 TRFC; //t_rfc Timing Register
436 volatile uint32 TRP; //t_rp Timing Register
437 volatile uint32 TRTW; //t_rtw Timing Register
438 volatile uint32 TAL; //AL Latency Register
439 volatile uint32 TCL; //CL Timing Register
440 volatile uint32 TCWL; //CWL Register
441 volatile uint32 TRAS; //t_ras Timing Register
442 volatile uint32 TRC; //t_rc Timing Register
443 volatile uint32 TRCD; //t_rcd Timing Register
444 volatile uint32 TRRD; //t_rrd Timing Register
445 volatile uint32 TRTP; //t_rtp Timing Register
446 volatile uint32 TWR; //t_wr Timing Register
447 volatile uint32 TWTR; //t_wtr Timing Register
448 volatile uint32 TEXSR; //t_exsr Timing Register
449 volatile uint32 TXP; //t_xp Timing Register
450 volatile uint32 TXPDLL; //t_xpdll Timing Register
451 volatile uint32 TZQCS; //t_zqcs Timing Register
452 volatile uint32 TZQCSI; //t_zqcsi Timing Register
453 volatile uint32 TDQS; //t_dqs Timing Register
454 volatile uint32 TCKSRE; //t_cksre Timing Register
455 volatile uint32 TCKSRX; //t_cksrx Timing Register
456 volatile uint32 TCKE; //t_cke Timing Register
457 volatile uint32 TMOD; //t_mod Timing Register
458 volatile uint32 TRSTL; //Reset Low Timing Register
459 volatile uint32 TZQCL; //t_zqcl Timing Register
460 volatile uint32 TMRR; //t_mrr Timing Register
461 volatile uint32 TCKESR; //t_ckesr Timing Register
462 volatile uint32 TDPD; //t_dpd Timing Register
463 uint32 reserved5[(0x180-0x148)/4];
464 //ECC Configuration, Control, and Status Registers
465 volatile uint32 ECCCFG; //ECC Configuration Register
466 volatile uint32 ECCTST; //ECC Test Register
467 volatile uint32 ECCCLR; //ECC Clear Register
468 volatile uint32 ECCLOG; //ECC Log Register
469 uint32 reserved6[(0x200-0x190)/4];
470 //DTU Control and Status Registers
471 volatile uint32 DTUWACTL; //DTU Write Address Control Register
472 volatile uint32 DTURACTL; //DTU Read Address Control Register
473 volatile uint32 DTUCFG; //DTU Configuration Control Register
474 volatile uint32 DTUECTL; //DTU Execute Control Register
475 volatile uint32 DTUWD0; //DTU Write Data 0
476 volatile uint32 DTUWD1; //DTU Write Data 1
477 volatile uint32 DTUWD2; //DTU Write Data 2
478 volatile uint32 DTUWD3; //DTU Write Data 3
479 volatile uint32 DTUWDM; //DTU Write Data Mask
480 volatile uint32 DTURD0; //DTU Read Data 0
481 volatile uint32 DTURD1; //DTU Read Data 1
482 volatile uint32 DTURD2; //DTU Read Data 2
483 volatile uint32 DTURD3; //DTU Read Data 3
484 volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
485 volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
486 volatile uint32 DTUEAF; //DTU Error Address FIFO
487 //DFI Control Registers
488 volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
489 volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
490 volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
491 volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
492 //DFI Write Data Registers
493 volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
494 volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
495 uint32 reserved7[(0x260-0x258)/4];
496 volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
497 volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
498 uint32 reserved8[(0x270-0x268)/4];
499 //DFI Update Registers
500 volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
501 volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
502 volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
503 volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
504 volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
505 volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
506 volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
508 volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
509 volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
510 volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
511 uint32 reserved10[(0x2ac-0x29c)/4];
512 volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
513 volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
514 volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
515 volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
516 volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
517 //DFI Status Registers
518 volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
519 volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
520 volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
522 volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
523 volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
524 volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
525 volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
526 volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
527 uint32 reserved12[(0x2f0-0x2e4)/4];
528 //DFI Low Power Registers
529 volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
530 uint32 reserved13[(0x300-0x2f4)/4];
531 //DFI Training 2 Registers
532 volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
533 volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
534 volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
535 volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
536 volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
537 volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
538 volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
539 volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
540 volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
541 volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
542 volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
543 volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
544 volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
545 volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
546 volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
547 volatile uint32 DFITRCMD; //DFI Training Command Register
548 uint32 reserved14[(0x3f8-0x340)/4];
549 //IP Status Registers
550 volatile uint32 IPVR; //IP Version Register
551 volatile uint32 IPTR; //IP Type Register
552 }DDR_REG_T, *pDDR_REG_T;
554 #define pDDR_Reg ((pDDR_REG_T)SDRAMC_BASE_ADDR)
558 #define DLLSRST (1<<1)
559 #define DLLLOCK (1<<2)
561 #define ITMSRST (1<<4)
562 #define DRAMRST (1<<5)
563 #define DRAMINIT (1<<6)
565 #define EYETRN (1<<8)
567 #define DLLBYP (1<<17)
568 #define CTLDINIT (1<<18)
569 #define CLRSR (1<<28)
570 #define LOCKBYP (1<<29)
571 #define ZCALBYP (1<<30)
572 #define INITBYP (1u<<31)
575 #define DFTLMT(n) ((n)<<3)
576 #define DFTCMP(n) ((n)<<2)
577 #define DQSCFG(n) ((n)<<1)
578 #define ITMDMD(n) ((n)<<0)
579 #define RANKEN(n) ((n)<<18)
583 #define DLDONE (1<<1)
584 #define ZCDONE (1<<2)
585 #define DIDONE (1<<3)
586 #define DTDONE (1<<4)
588 #define DTIERR (1<<6)
589 #define DFTERR (1<<7)
593 #define tITMSRST(n) ((n)<<18)
594 #define tDLLLOCK(n) ((n)<<6)
595 #define tDLLSRST(n) ((n)<<0)
598 #define tDINIT1(n) ((n)<<19)
599 #define tDINIT0(n) ((n)<<0)
602 #define tDINIT3(n) ((n)<<17)
603 #define tDINIT2(n) ((n)<<0)
606 #define DQSGE(n) ((n)<<8)
607 #define DQSGX(n) ((n)<<5)
609 typedef union DCR_Tag
615 unsigned DDR8BNK : 1;
618 unsigned DDRTYPE : 2;
619 unsigned reserved10_26 : 17;
629 typedef volatile struct DATX8_REG_Tag
631 volatile uint32 DXGCR; //DATX8 General Configuration Register
632 volatile uint32 DXGSR[2]; //DATX8 General Status Register
633 volatile uint32 DXDLLCR; //DATX8 DLL Control Register
634 volatile uint32 DXDQTR; //DATX8 DQ Timing Register
635 volatile uint32 DXDQSTR; //DATX8 DQS Timing Register
636 uint32 reserved[0x80-0x76];
639 /* DDR PHY register struct */
640 typedef volatile struct DDRPHY_REG_Tag
642 volatile uint32 RIDR; //Revision Identification Register
643 volatile uint32 PIR; //PHY Initialization Register
644 volatile uint32 PGCR; //PHY General Configuration Register
645 volatile uint32 PGSR; //PHY General Status Register
646 volatile uint32 DLLGCR; //DLL General Control Register
647 volatile uint32 ACDLLCR; //AC DLL Control Register
648 volatile uint32 PTR[3]; //PHY Timing Registers 0-2
649 volatile uint32 ACIOCR; //AC I/O Configuration Register
650 volatile uint32 DXCCR; //DATX8 Common Configuration Register
651 volatile uint32 DSGCR; //DDR System General Configuration Register
652 DCR_T DCR; //DRAM Configuration Register
653 volatile uint32 DTPR[3]; //DRAM Timing Parameters Register 0-2
654 volatile uint32 MR[4]; //Mode Register 0-3
655 volatile uint32 ODTCR; //ODT Configuration Register
656 volatile uint32 DTAR; //Data Training Address Register
657 volatile uint32 DTDR[2]; //Data Training Data Register 0-1
659 uint32 reserved1[0x30-0x18];
660 uint32 DCU[0x38-0x30];
661 uint32 reserved2[0x40-0x38];
662 uint32 BIST[0x51-0x40];
663 uint32 reserved3[0x60-0x51];
665 volatile uint32 ZQ0CR[2]; //ZQ 0 Impedance Control Register 0-1
666 volatile uint32 ZQ0SR[2]; //ZQ 0 Impedance Status Register 0-1
667 volatile uint32 ZQ1CR[2]; //ZQ 1 Impedance Control Register 0-1
668 volatile uint32 ZQ1SR[2]; //ZQ 1 Impedance Status Register 0-1
669 volatile uint32 ZQ2CR[2]; //ZQ 2 Impedance Control Register 0-1
670 volatile uint32 ZQ2SR[2]; //ZQ 2 Impedance Status Register 0-1
671 volatile uint32 ZQ3CR[2]; //ZQ 3 Impedance Control Register 0-1
672 volatile uint32 ZQ3SR[2]; //ZQ 3 Impedance Status Register 0-1
674 DATX8_REG_T DATX8[9]; //DATX8 Register
675 }DDRPHY_REG_T, *pDDRPHY_REG_T;
677 #define pPHY_Reg ((pDDRPHY_REG_T)DDR_PUBL_BASE)
679 typedef enum DRAM_TYPE_Tag
690 typedef struct PCTRL_TIMING_Tag
693 //Memory Timing Registers
694 uint32 togcnt1u; //Toggle Counter 1U Register
695 uint32 tinit; //t_init Timing Register
696 uint32 trsth; //Reset High Time Register
697 uint32 togcnt100n; //Toggle Counter 100N Register
698 uint32 trefi; //t_refi Timing Register
699 uint32 tmrd; //t_mrd Timing Register
700 uint32 trfc; //t_rfc Timing Register
701 uint32 trp; //t_rp Timing Register
702 uint32 trtw; //t_rtw Timing Register
703 uint32 tal; //AL Latency Register
704 uint32 tcl; //CL Timing Register
705 uint32 tcwl; //CWL Register
706 uint32 tras; //t_ras Timing Register
707 uint32 trc; //t_rc Timing Register
708 uint32 trcd; //t_rcd Timing Register
709 uint32 trrd; //t_rrd Timing Register
710 uint32 trtp; //t_rtp Timing Register
711 uint32 twr; //t_wr Timing Register
712 uint32 twtr; //t_wtr Timing Register
713 uint32 texsr; //t_exsr Timing Register
714 uint32 txp; //t_xp Timing Register
715 uint32 txpdll; //t_xpdll Timing Register
716 uint32 tzqcs; //t_zqcs Timing Register
717 uint32 tzqcsi; //t_zqcsi Timing Register
718 uint32 tdqs; //t_dqs Timing Register
719 uint32 tcksre; //t_cksre Timing Register
720 uint32 tcksrx; //t_cksrx Timing Register
721 uint32 tcke; //t_cke Timing Register
722 uint32 tmod; //t_mod Timing Register
723 uint32 trstl; //Reset Low Timing Register
724 uint32 tzqcl; //t_zqcl Timing Register
725 uint32 tmrr; //t_mrr Timing Register
726 uint32 tckesr; //t_ckesr Timing Register
727 uint32 tdpd; //t_dpd Timing Register
730 typedef union DTPR_0_Tag
747 typedef union DTPR_1_Tag
757 unsigned reserved12_15 : 4;
760 unsigned tDQSCKmax : 3;
761 unsigned reserved30_31 : 2;
765 typedef union DTPR_2_Tag
774 unsigned reserved29_31 : 3;
778 typedef struct PHY_TIMING_Tag
783 uint32 mr[4]; //LPDDR2 no MR0, mr[2] is mDDR MR1
786 typedef union NOC_TIMING_Tag
791 unsigned ActToAct : 6;
792 unsigned RdToMiss : 6;
793 unsigned WrToMiss : 6;
794 unsigned BurstLen : 3;
797 unsigned BwRatio : 1;
801 typedef struct PCTL_REG_Tag
807 PCTL_TIMING_T pctl_timing;
808 //DFI Control Registers
809 uint32 DFITCTRLDELAY;
812 uint32 DFIODTRANKMAP;
813 //DFI Write Data Registers
814 uint32 DFITPHYWRDATA;
816 //DFI Read Data Registers
819 //DFI Update Registers
820 uint32 DFITPHYUPDTYPE0;
821 uint32 DFITPHYUPDTYPE1;
822 uint32 DFITPHYUPDTYPE2;
823 uint32 DFITPHYUPDTYPE3;
824 uint32 DFITCTRLUPDMIN;
825 uint32 DFITCTRLUPDMAX;
826 uint32 DFITCTRLUPDDLY;
830 //DFI Status Registers
833 uint32 DFITDRAMCLKEN;
834 uint32 DFITDRAMCLKDIS;
836 //DFI Low Power Register
840 typedef struct PUBL_REG_Tag
851 PHY_TIMING_T phy_timing;
878 typedef struct BACKUP_REG_Tag
883 NOC_TIMING_T noc_timing;
888 __sramdata BACKUP_REG_T ddr_reg;
890 typedef struct DDR_CONFIG_2_RBC_Tag
897 DDR_CONFIG_2_RBC_T ddr_cfg_2_rbc[16] =
899 {15,3,11}, // bank ahead
914 {15,3,10} // bank ahead
917 __attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
919 uint32_t __sramdata ddr3_cl_cwl[22][4]={
920 /* 0~330 330~400 400~533 speed
921 * tCK >3 2.5~3 1.875~2.5 1.5~1.875
922 * cl<<16, cwl cl<<16, cwl cl<<16, cwl */
923 {((5<<16)|5), ((5<<16)|5), 0 , 0}, //DDR3_800D
924 {((5<<16)|5), ((6<<16)|5), 0 , 0}, //DDR3_800E
926 {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), 0}, //DDR3_1066E
927 {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), 0}, //DDR3_1066F
928 {((5<<16)|5), ((6<<16)|5), ((8<<16)|6), 0}, //DDR3_1066G
930 {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1333F
931 {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1333G
932 {((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((9<<16)|7)}, //DDR3_1333H
933 {((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1333J
935 {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1600G
936 {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_1600H
937 {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1600J
938 {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), ((10<<16)|7)}, //DDR3_1600K
940 {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_1866J
941 {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1866K
942 {((6<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1866L
943 {((6<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1866M
945 {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_2133K
946 {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_2133L
947 {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_2133M
948 {((6<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_2133N
950 {((6<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)} //DDR3_DEFAULT
953 uint32_t __sramdata ddr3_tRC_tFAW[22]={
955 ((50<<16)|50), //DDR3_800D
956 ((53<<16)|50), //DDR3_800E
958 ((49<<16)|50), //DDR3_1066E
959 ((51<<16)|50), //DDR3_1066F
960 ((53<<16)|50), //DDR3_1066G
962 ((47<<16)|45), //DDR3_1333F
963 ((48<<16)|45), //DDR3_1333G
964 ((50<<16)|45), //DDR3_1333H
965 ((51<<16)|45), //DDR3_1333J
967 ((45<<16)|40), //DDR3_1600G
968 ((47<<16)|40), //DDR3_1600H
969 ((48<<16)|40), //DDR3_1600J
970 ((49<<16)|40), //DDR3_1600K
972 ((45<<16)|35), //DDR3_1866J
973 ((46<<16)|35), //DDR3_1866K
974 ((47<<16)|35), //DDR3_1866L
975 ((48<<16)|35), //DDR3_1866M
977 ((44<<16)|35), //DDR3_2133K
978 ((45<<16)|35), //DDR3_2133L
979 ((46<<16)|35), //DDR3_2133M
980 ((47<<16)|35), //DDR3_2133N
982 ((53<<16)|50) //DDR3_DEFAULT
984 __sramdata uint32_t mem_type; // 0:LPDDR, 1:DDR, 2:DDR2, 3:DDR3, 4:LPDDR2
985 static __sramdata uint32_t ddr_speed_bin; // used for ddr3 only
986 static __sramdata uint32_t ddr_capability_per_die; // one chip cs capability
987 static __sramdata uint32_t ddr_freq;
988 static __sramdata uint32_t ddr_sr_idle;
990 /****************************************************************************
991 Internal sram us delay function
992 Cpu highest frequency is 1.6 GHz
994 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
995 *****************************************************************************/
996 static __sramdata volatile uint32_t loops_per_us;
998 #define LPJ_100MHZ 999456UL
1000 /*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
1002 volatile uint32_t count;
1004 count = loops_per_us*us;
1005 while(count--) // 3 cycles
1009 __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
1013 for(i=0; i<words; i++)
1019 uint32 ddr_get_row(void)
1024 i = *(volatile uint32*)SysSrv_DdrConf;
1025 row = ddr_cfg_2_rbc[i].row;
1026 if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
1033 uint32 ddr_get_bank(void)
1037 i = *(volatile uint32*)SysSrv_DdrConf;
1038 return ddr_cfg_2_rbc[i].bank;
1041 uint32 ddr_get_col(void)
1045 i = *(volatile uint32*)SysSrv_DdrConf;
1046 return ddr_cfg_2_rbc[i].col;
1049 uint32_t ddr_get_datatraing_addr(void)
1057 // caculate aglined physical address
1058 addr = __pa((unsigned long)ddr_data_training_buf);
1061 addr += (64-(addr&0x3F));
1064 // find out col£¬row£¬bank
1065 row = ddr_get_row();
1066 bank = ddr_get_bank();
1067 col = ddr_get_col();
1068 // according different address mapping, caculate DTAR register value
1069 switch(*(volatile uint32*)SysSrv_DdrConf)
1073 value |= (addr>>2) & ((0x1<<col)-1); // col
1074 value |= ((addr>>(2+col)) & ((0x1<<row)-1)) << 12; // row
1075 value |= ((addr>>(2+col+row)) & ((0x1<<bank)-1)) << 28; // bank
1078 value |= (addr>>2) & ((0x1<<col)-1); // col
1079 value |= ((addr>>(2+col+bank)) & ((0x1<<row)-1)) << 12; // row
1080 value |= ((addr>>(2+col)) & ((0x1<<bank)-1)) << 28; // bank
1087 __sramlocalfunc void ddr_reset_dll(void)
1089 pPHY_Reg->ACDLLCR &= ~0x40000000;
1090 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1091 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1092 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1093 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1095 pPHY_Reg->ACDLLCR |= 0x40000000;
1096 pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1097 pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1098 pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1099 pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1103 __sramfunc void ddr_move_to_Lowpower_state(void)
1105 volatile uint32 value;
1109 value = pDDR_Reg->STAT.b.ctl_stat;
1110 if(value == Low_power)
1117 pDDR_Reg->SCTL = CFG_STATE;
1119 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1121 pDDR_Reg->SCTL = GO_STATE;
1123 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1125 pDDR_Reg->SCTL = SLEEP_STATE;
1127 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1129 default: //Transitional state
1135 __sramfunc void ddr_move_to_Access_state(void)
1137 volatile uint32 value;
1139 //set auto self-refresh idle
1140 pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|ddr_sr_idle;
1145 value = pDDR_Reg->STAT.b.ctl_stat;
1146 if((value == Access)
1147 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1154 pDDR_Reg->SCTL = WAKEUP_STATE;
1156 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1157 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1160 pDDR_Reg->SCTL = CFG_STATE;
1162 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1164 pDDR_Reg->SCTL = GO_STATE;
1166 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1167 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1169 default: //Transitional state
1175 __sramfunc void ddr_move_to_Config_state(void)
1177 volatile uint32 value;
1179 //clear auto self-refresh idle
1180 if(pDDR_Reg->MCFG1 & 0xFF)
1182 pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|0x0;
1188 value = pDDR_Reg->STAT.b.ctl_stat;
1196 pDDR_Reg->SCTL = WAKEUP_STATE;
1198 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1199 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1202 pDDR_Reg->SCTL = CFG_STATE;
1204 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1206 default: //Transitional state
1212 //arg°üÀ¨bank_addrºÍcmd_addr
1213 void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
1215 pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1217 while(pDDR_Reg->MCMD & start_cmd);
1220 //¶ÔtypeÀàÐ͵ÄDDRµÄ¼¸¸öcs½øÐÐDTT
1223 uint32_t __sramlocalfunc ddr_data_training(void)
1227 // disable auto refresh
1228 value = pDDR_Reg->TREFI;
1229 pDDR_Reg->TREFI = 0;
1231 // clear DTDONE status
1232 pPHY_Reg->PIR |= CLRSR;
1233 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
1235 pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
1237 // wait echo byte DTDONE
1238 while((pPHY_Reg->DATX8[0].DXGSR[0] & cs) != cs);
1239 while((pPHY_Reg->DATX8[1].DXGSR[0] & cs) != cs);
1240 while((pPHY_Reg->DATX8[2].DXGSR[0] & cs) != cs);
1241 while((pPHY_Reg->DATX8[3].DXGSR[0] & cs) != cs); //²âµ½1¸öCSµÄDTT×ʱ¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
1242 // send some auto refresh to complement the lost while DTT
1245 ddr_send_command(cs, REF_cmd, 0);
1246 ddr_send_command(cs, REF_cmd, 0);
1247 ddr_send_command(cs, REF_cmd, 0);
1248 ddr_send_command(cs, REF_cmd, 0);
1252 ddr_send_command(cs, REF_cmd, 0);
1253 ddr_send_command(cs, REF_cmd, 0);
1255 // resume auto refresh
1256 pDDR_Reg->TREFI = value;
1258 if(pPHY_Reg->PGSR & DTERR)
1268 void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
1272 pPHY_Reg->DLLGCR &= ~(1<<23);
1273 pPHY_Reg->ACDLLCR |= 0x80000000;
1274 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
1275 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
1276 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
1277 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
1278 pPHY_Reg->PIR |= DLLBYP;
1282 pPHY_Reg->DLLGCR |= (1<<23);
1283 pPHY_Reg->ACDLLCR |= 0x80000000;
1284 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
1285 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
1286 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
1287 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
1288 pPHY_Reg->PIR |= DLLBYP;
1292 pPHY_Reg->DLLGCR &= ~(1<<23);
1293 pPHY_Reg->ACDLLCR &= ~0x80000000;
1294 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
1295 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
1296 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
1297 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
1298 pPHY_Reg->PIR &= ~DLLBYP;
1302 static __sramdata uint32_t clkr;
1303 static __sramdata uint32_t clkf;
1304 static __sramdata uint32_t clkod;
1305 /*****************************************
1306 NR NO NF Fout freq Step finally use
1307 1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
1308 1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
1309 1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
1310 1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
1311 1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
1312 ******************************************/
1313 uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
1317 uint32_t pll_id=1; //DPLL
1318 //NOÒ»¶¨ÒªÅ¼Êý,NR¾¡Á¿Ð¡£¬jitter¾Í»áС
1332 else if(nMHz <= 200)
1336 else if(nMHz <= 300)
1340 else if(nMHz <= 600)
1349 clkf=(nMHz*clkr*clkod)/24;
1350 ret = (24*clkf)/(clkr*clkod);
1354 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
1356 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
1357 pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
1358 pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
1359 pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1361 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
1366 if (pGRF_Reg->GRF_SOC_STATUS0 & (0x1<<4))
1371 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1372 | (0x0<<8) //clk_ddr_src = DDR PLL
1373 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1375 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
1382 uint32_t ddr_get_parameter(uint32_t nMHz)
1390 PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
1391 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
1392 NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
1394 p_pctl_timing->togcnt1u = nMHz;
1395 p_pctl_timing->togcnt100n = nMHz/10;
1396 p_pctl_timing->tinit = 200;
1397 p_pctl_timing->trsth = 500;
1399 if(mem_type == DDR3)
1401 if(ddr_speed_bin > DDR3_DEFAULT){
1406 #define DDR3_tREFI_7_8_us (78)
1407 #define DDR3_tMRD (4)
1408 #define DDR3_tRFC_512Mb (90)
1409 #define DDR3_tRFC_1Gb (110)
1410 #define DDR3_tRFC_2Gb (160)
1411 #define DDR3_tRFC_4Gb (300)
1412 #define DDR3_tRFC_8Gb (350)
1413 #define DDR3_tRTW (2) //register min valid value
1414 #define DDR3_tRAS (37)
1415 #define DDR3_tRRD (10)
1416 #define DDR3_tRTP (7)
1417 #define DDR3_tWR (15)
1418 #define DDR3_tWTR (7)
1419 #define DDR3_tXP (7)
1420 #define DDR3_tXPDLL (24)
1421 #define DDR3_tZQCS (80)
1422 #define DDR3_tZQCSI (10000)
1423 #define DDR3_tDQS (1)
1424 #define DDR3_tCKSRE (10)
1425 #define DDR3_tCKE_400MHz (7)
1426 #define DDR3_tCKE_533MHz (6)
1427 #define DDR3_tMOD (15)
1428 #define DDR3_tRSTL (100)
1429 #define DDR3_tZQCL (320)
1430 #define DDR3_tDLLK (512)
1450 cl = ddr3_cl_cwl[ddr_speed_bin][tmp] >> 16;
1451 cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0x0ff;
1454 if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
1456 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
1460 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
1462 p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
1463 p_publ_timing->mr[3] = 0;
1464 /**************************************************
1466 **************************************************/
1468 * tREFI, average periodic refresh interval, 7.8us
1470 p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
1474 p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
1475 p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
1477 * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
1479 if(ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
1481 tmp = DDR3_tRFC_512Mb;
1483 else if(ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
1485 tmp = DDR3_tRFC_1Gb;
1487 else if(ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
1489 tmp = DDR3_tRFC_2Gb;
1491 else if(ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
1493 tmp = DDR3_tRFC_4Gb;
1497 tmp = DDR3_tRFC_8Gb;
1499 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
1500 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
1502 * tXSR, =tDLLK=512 tCK
1504 p_pctl_timing->texsr = DDR3_tDLLK;
1505 p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
1509 p_pctl_timing->trp = cl;
1510 p_publ_timing->dtpr0.b.tRP = cl;
1512 * WrToMiss=WL*tCK + tWR + tRP + tRCD
1514 p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
1518 p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
1519 p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
1520 p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>16)*nMHz+999)/1000)&0xF;
1522 p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
1523 p_publ_timing->dtpr1.b.tRTW = 0;
1524 p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
1525 p_pctl_timing->tal = al;
1526 p_pctl_timing->tcl = cl;
1527 p_pctl_timing->tcwl = cwl;
1529 * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
1531 p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
1532 p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x1F;
1536 p_pctl_timing->trcd = cl;
1537 p_publ_timing->dtpr0.b.tRCD = cl;
1539 * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
1540 * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
1541 * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
1544 tmp = ((DDR3_tRRD*nMHz+999)/1000);
1549 p_pctl_timing->trrd = (tmp&0xF);
1550 p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
1552 * tRTP, max(4 tCK,7.5ns)
1554 tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
1559 p_pctl_timing->trtp = tmp&0xF;
1560 p_publ_timing->dtpr0.b.tRTP = tmp;
1562 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
1564 p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
1568 tmp = ((DDR3_tWR*nMHz+999)/1000);
1569 p_pctl_timing->twr = tmp&0x1F;
1574 bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
1575 p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
1578 * tWTR, max(4 tCK,7.5ns)
1580 tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
1585 p_pctl_timing->twtr = tmp&0xF;
1586 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
1587 p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
1589 * tXP, max(3 tCK, 7.5ns)(<933MHz)
1591 tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
1596 p_pctl_timing->txp = tmp&0x7;
1597 p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
1599 * tXPDLL, max(10 tCK,24ns)
1601 tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
1606 p_pctl_timing->txpdll = tmp & 0x3F;
1608 * tZQCS, max(64 tCK, 80ns)
1610 tmp = ((DDR3_tZQCS*nMHz+999)/1000);
1615 p_pctl_timing->tzqcs = tmp&0x7F;
1619 p_pctl_timing->tzqcsi = DDR3_tZQCSI;
1623 p_pctl_timing->tdqs = DDR3_tDQS;
1625 * tCKSRE, max(5 tCK, 10ns)
1627 tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
1632 p_pctl_timing->tcksre = tmp & 0x1F;
1634 * tCKSRX, max(5 tCK, 10ns)
1636 p_pctl_timing->tcksrx = tmp & 0x1F;
1638 * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
1642 tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
1646 tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
1652 p_pctl_timing->tcke = tmp & 0x7;
1653 p_publ_timing->dtpr2.b.tCKE = tmp;
1655 * tCKESR, =tCKE + 1tCK
1657 p_pctl_timing->tckesr = (tmp+1)&0xF;
1659 * tMOD, max(12 tCK,15ns)
1661 tmp = ((DDR3_tMOD*nMHz+999)/1000);
1666 p_pctl_timing->tmod = tmp&0x1F;
1667 p_publ_timing->dtpr1.b.tMOD = tmp;
1671 p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
1673 * tZQCL, max(256 tCK, 320ns)
1675 tmp = ((DDR3_tZQCL*nMHz+999)/1000);
1680 p_pctl_timing->tzqcl = tmp&0x3FF;
1684 p_pctl_timing->tmrr = 0;
1688 p_pctl_timing->tdpd = 0;
1690 /**************************************************
1692 **************************************************/
1694 * tCCD, BL/2 for DDR2 and 4 for DDR3
1696 p_publ_timing->dtpr0.b.tCCD = 0;
1700 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
1702 * tRTODT, 0:ODT may be turned on immediately after read post-amble
1703 * 1:ODT may not be turned on until one clock after the read post-amble
1705 p_publ_timing->dtpr1.b.tRTODT = 1;
1707 * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page) 50ns(533MHz 2KB page)
1709 p_publ_timing->dtpr1.b.tFAW = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000)&0x7F;
1713 p_publ_timing->dtpr1.b.tAOND = 0;
1717 p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
1718 /**************************************************
1720 **************************************************/
1721 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
1723 else if(mem_type == LPDDR2)
1725 #define LPDDR2_tREFI_3_9_us (38)
1726 #define LPDDR2_tREFI_7_8_us (78)
1727 #define LPDDR2_tMRD (5) //tCK
1728 #define LPDDR2_tRFC_8Gb (210) //ns
1729 #define LPDDR2_tRFC_4Gb (130) //ns
1730 #define LPDDR2_tRP_4_BANK (24) //ns
1731 #define LPDDR2_tRPab_SUB_tRPpb_4_BANK (0)
1732 #define LPDDR2_tRP_8_BANK (27) //ns
1733 #define LPDDR2_tRPab_SUB_tRPpb_8_BANK (3)
1734 #define LPDDR2_tRTW (1) //tCK register min valid value
1735 #define LPDDR2_tRAS (42) //ns
1736 #define LPDDR2_tRCD (24) //ns
1737 #define LPDDR2_tRRD (10) //ns
1738 #define LPDDR2_tRTP (7) //ns
1739 #define LPDDR2_tWR (15) //ns
1740 #define LPDDR2_tWTR_GREAT_200MHz (7) //ns
1741 #define LPDDR2_tWTR_LITTLE_200MHz (10) //ns
1742 #define LPDDR2_tXP (7) //ns
1743 #define LPDDR2_tXPDLL (0)
1744 #define LPDDR2_tZQCS (90) //ns
1745 #define LPDDR2_tZQCSI (10000)
1746 #define LPDDR2_tDQS (1)
1747 #define LPDDR2_tCKSRE (1) //tCK
1748 #define LPDDR2_tCKSRX (2) //tCK
1749 #define LPDDR2_tCKE (3) //tCK
1750 #define LPDDR2_tMOD (0)
1751 #define LPDDR2_tRSTL (0)
1752 #define LPDDR2_tZQCL (360) //ns
1753 #define LPDDR2_tMRR (2) //tCK
1754 #define LPDDR2_tCKESR (15) //ns
1755 #define LPDDR2_tDPD_US (500)
1756 #define LPDDR2_tFAW_GREAT_200MHz (50) //ns
1757 #define LPDDR2_tFAW_LITTLE_200MHz (60) //ns
1758 #define LPDDR2_tDLLK (2) //tCK
1759 #define LPDDR2_tDQSCK_MAX (3) //tCK
1760 #define LPDDR2_tDQSCK_MIN (0) //tCK
1761 #define LPDDR2_tDQSS (1) //tCK
1765 /* 1066 933 800 667 533 400 333
1773 p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
1779 p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
1785 p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
1791 p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
1797 p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
1803 p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
1805 p_publ_timing->mr[3] = LPDDR2_DS_34;
1806 p_publ_timing->mr[0] = 0;
1807 /**************************************************
1809 **************************************************/
1811 * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
1813 if(ddr_capability_per_die >= 0x10000000) // 2Gb
1815 p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
1819 p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
1823 * tMRD, (=tMRW), 5 tCK
1825 p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
1826 p_publ_timing->dtpr0.b.tMRD = 3;
1828 * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
1830 if(ddr_capability_per_die >= 0x40000000) // 8Gb
1832 p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
1836 p_pctl_timing->texsr = (((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000)&0x3FF;
1837 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000)&0xFF;
1838 p_publ_timing->dtpr2.b.tXS = (((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000)&0x3FF;
1842 p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
1843 p_pctl_timing->texsr = (((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000)&0x3FF;
1844 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000)&0xFF;
1845 p_publ_timing->dtpr2.b.tXS = (((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000)&0x3FF;
1849 * tRP, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)
1851 if(pPHY_Reg->DCR.b.DDR8BNK)
1853 p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (((LPDDR2_tRP_8_BANK*nMHz+999)/1000)&0xF);
1854 p_publ_timing->dtpr0.b.tRP = ((LPDDR2_tRP_8_BANK*nMHz+999)/1000);
1856 * WrToMiss=WL*tCK + tDQSS + tWR + tRP + tRCD
1858 p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+(((LPDDR2_tWR+LPDDR2_tRP_8_BANK+LPDDR2_tRCD)*nMHz+999)/1000))&0x3F);
1860 * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
1862 p_noc_timing->b.RdToMiss = (((((LPDDR2_tRTP+LPDDR2_tRP_8_BANK+LPDDR2_tRCD)*nMHz+(nMHz>>1)+999)/1000)-(bl>>1))&0x3F);
1866 p_pctl_timing->trc = ((((LPDDR2_tRP_8_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
1867 p_noc_timing->b.ActToAct = ((((LPDDR2_tRP_8_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
1868 p_publ_timing->dtpr0.b.tRC = (((LPDDR2_tRP_8_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0xF;
1872 p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (((LPDDR2_tRP_4_BANK*nMHz+999)/1000)&0xF);
1873 p_publ_timing->dtpr0.b.tRP = ((LPDDR2_tRP_4_BANK*nMHz+999)/1000);
1874 p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+(((LPDDR2_tWR+LPDDR2_tRP_4_BANK+LPDDR2_tRCD)*nMHz+999)/1000))&0x3F);
1875 p_noc_timing->b.RdToMiss = (((((LPDDR2_tRTP+LPDDR2_tRP_4_BANK+LPDDR2_tRCD)*nMHz+(nMHz>>1)+999)/1000)-(bl>>1))&0x3F);
1876 p_pctl_timing->trc = ((((LPDDR2_tRP_4_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
1877 p_noc_timing->b.ActToAct = ((((LPDDR2_tRP_4_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
1878 p_publ_timing->dtpr0.b.tRC = (((LPDDR2_tRP_4_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0xF;
1881 p_pctl_timing->trtw = (cl+LPDDR2_tDQSCK_MAX+(bl/2)+1-cwl);//LPDDR2_tRTW;
1882 p_publ_timing->dtpr1.b.tRTW = 0;
1884 * RdToWr=RL+tDQSCK-WL
1886 p_noc_timing->b.RdToWr = ((cl+LPDDR2_tDQSCK_MAX+1-cwl)&0x1F);
1887 p_pctl_timing->tal = al;
1888 p_pctl_timing->tcl = cl;
1889 p_pctl_timing->tcwl = cwl;
1893 p_pctl_timing->tras = (((LPDDR2_tRAS*nMHz+999)/1000)&0x3F);
1894 p_publ_timing->dtpr0.b.tRAS = ((LPDDR2_tRAS*nMHz+999)/1000)&0x1F;
1896 * tRCD, 15ns(Fast) 18ns(Typ) 24ns(Slow)
1898 p_pctl_timing->trcd = (((LPDDR2_tRCD*nMHz+999)/1000)&0xF);
1899 p_publ_timing->dtpr0.b.tRCD = ((LPDDR2_tRCD*nMHz+999)/1000)&0xF;
1903 p_pctl_timing->trrd = (((LPDDR2_tRRD*nMHz+999)/1000)&0xF);
1904 p_publ_timing->dtpr0.b.tRRD = ((LPDDR2_tRRD*nMHz+999)/1000)&0xF;
1908 tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
1909 p_pctl_timing->trtp = tmp&0xF;
1910 p_publ_timing->dtpr0.b.tRTP = (tmp<2) ? 2 : tmp;
1914 p_pctl_timing->twr = ((LPDDR2_tWR*nMHz+999)/1000)&0x1F;
1915 bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
1916 p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(((LPDDR2_tWR*nMHz+999)/1000));
1918 * tWTR, 7.5ns(533-266MHz) 10ns(200-166MHz)
1922 p_pctl_timing->twtr = ((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000)&0xF;
1923 p_publ_timing->dtpr0.b.tWTR = ((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000)&0x7;
1925 * WrToRd=WL+tDQSS+tWTR
1927 p_noc_timing->b.WrToRd = ((LPDDR2_tDQSS+((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000)+cwl)&0x1F);
1931 p_pctl_timing->twtr = ((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000)&0xF;
1932 p_publ_timing->dtpr0.b.tWTR = ((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000)&0x7;
1933 p_noc_timing->b.WrToRd = ((LPDDR2_tDQSS+((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000)+cwl)&0x1F);
1938 p_pctl_timing->txp = ((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000)&0x7;
1939 p_publ_timing->dtpr2.b.tXP = ((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000)&0x1F;
1943 p_pctl_timing->txpdll = LPDDR2_tXPDLL;
1947 p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
1951 if(pDDR_Reg->MCFG &= lpddr2_s4)
1953 p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
1957 p_pctl_timing->tzqcsi = 0;
1962 p_pctl_timing->tdqs = LPDDR2_tDQS;
1966 p_pctl_timing->tcksre = LPDDR2_tCKSRE;
1970 p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
1974 p_pctl_timing->tcke = LPDDR2_tCKE;
1975 p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
1979 p_pctl_timing->tmod = LPDDR2_tMOD;
1980 p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
1984 p_pctl_timing->trstl = LPDDR2_tRSTL;
1988 p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
1992 p_pctl_timing->tmrr = LPDDR2_tMRR;
1996 p_pctl_timing->tckesr = ((LPDDR2_tCKESR*nMHz+999)/1000)&0xF;
2000 p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2002 /**************************************************
2004 **************************************************/
2006 * tCCD, BL/2 for DDR2 and 4 for DDR3
2008 p_publ_timing->dtpr0.b.tCCD = 0;
2012 p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2016 p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2018 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2019 * 1:ODT may not be turned on until one clock after the read post-amble
2021 p_publ_timing->dtpr1.b.tRTODT = 1;
2023 * tFAW,50ns(200-533MHz) 60ns(166MHz)
2027 p_publ_timing->dtpr1.b.tFAW = ((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000)&0x7F;
2031 p_publ_timing->dtpr1.b.tFAW = ((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000)&0x7F;
2036 p_publ_timing->dtpr1.b.tAOND = 0;
2040 p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2041 /**************************************************
2043 **************************************************/
2044 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2046 else if(mem_type == DDR2)
2048 #define DDR2_tREFI_7_8_us (78)
2049 #define DDR2_tMRD (2)
2050 #define DDR2_tRFC_256Mb (75)
2051 #define DDR2_tRFC_512Mb (105)
2052 #define DDR2_tRFC_1Gb (128)
2053 #define DDR2_tRFC_2Gb (195)
2054 #define DDR2_tRFC_4Gb (328)
2055 #define DDR2_tRAS (45)
2056 #define DDR2_tRTW (2) //register min valid value
2057 #define DDR2_tRRD (10)
2058 #define DDR2_tRTP (7)
2059 #define DDR2_tWR (15)
2060 #define DDR2_tWTR_LITTLE_200MHz (10)
2061 #define DDR2_tWTR_GREAT_200MHz (7)
2062 #define DDR2_tDQS (1)
2063 #define DDR2_tCKSRE (1)
2064 #define DDR2_tCKSRX (1)
2065 #define DDR2_tCKE (3)
2066 #define DDR2_tCKESR DDR2_tCKE
2067 #define DDR2_tMOD (12)
2068 #define DDR2_tFAW_333MHz (50)
2069 #define DDR2_tFAW_400MHz (45)
2070 #define DDR2_tDLLK (200)
2078 else if((nMHz > 266) && (nMHz <= 333))
2082 else if((nMHz > 333) && (nMHz <= 400))
2091 if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2093 p_publ_timing->mr[1] = DDR2_STR_REDUCE | DDR2_Rtt_Nom_DIS;
2097 p_publ_timing->mr[1] = DDR2_STR_REDUCE | DDR2_Rtt_Nom_75;
2099 p_publ_timing->mr[2] = 0;
2100 p_publ_timing->mr[3] = 0;
2101 /**************************************************
2103 **************************************************/
2105 * tREFI, average periodic refresh interval, 7.8us
2107 p_pctl_timing->trefi = DDR2_tREFI_7_8_us;
2111 p_pctl_timing->tmrd = DDR2_tMRD & 0x7;
2112 p_publ_timing->dtpr0.b.tMRD = DDR2_tMRD;
2114 * tRFC, 75ns(256Mb) 105ns(512Mb) 127.5ns(1Gb) 195ns(2Gb) 327.5ns(4Gb)
2116 if(ddr_capability_per_die <= 0x2000000) // 256Mb
2118 tmp = DDR2_tRFC_256Mb;
2120 else if(ddr_capability_per_die <= 0x4000000) // 512Mb
2122 tmp = DDR2_tRFC_512Mb;
2124 else if(ddr_capability_per_die <= 0x8000000) // 1Gb
2126 tmp = DDR2_tRFC_1Gb;
2128 else if(ddr_capability_per_die <= 0x10000000) // 2Gb
2130 tmp = DDR2_tRFC_2Gb;
2134 tmp = DDR2_tRFC_4Gb;
2136 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2137 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
2139 * tXSR, max(tRFC+10,200 tCK)
2141 tmp = (((tmp+10)*nMHz+999)/1000);
2146 p_pctl_timing->texsr = tmp&0x3FF;
2147 p_publ_timing->dtpr2.b.tXS = tmp&0x3FF;
2151 if(pPHY_Reg->DCR.b.DDR8BNK)
2153 p_pctl_timing->trp = (1<<16) | cl;
2157 p_pctl_timing->trp = cl;
2159 p_publ_timing->dtpr0.b.tRP = cl;
2161 * WrToMiss=WL*tCK + tWR + tRP + tRCD
2163 p_noc_timing->b.WrToMiss = ((cwl+((DDR2_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
2167 tmp=((DDR2_tRAS*nMHz+999)/1000);
2168 p_pctl_timing->tras = (tmp&0x3F);
2169 p_publ_timing->dtpr0.b.tRAS = tmp&0x1F;
2173 p_pctl_timing->trc = ((tmp+cl)&0x3F);
2174 p_noc_timing->b.ActToAct = ((tmp+cl)&0x3F);
2175 p_publ_timing->dtpr0.b.tRC = (tmp+cl)&0xF;
2177 p_pctl_timing->trtw = (cl+2-cwl);//DDR2_tRTW;
2178 p_publ_timing->dtpr1.b.tRTW = 0;
2179 p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
2180 p_pctl_timing->tal = al;
2181 p_pctl_timing->tcl = cl;
2182 p_pctl_timing->tcwl = cwl;
2186 p_pctl_timing->trcd = cl;
2187 p_publ_timing->dtpr0.b.tRCD = cl;
2189 * tRRD = 10ns(2KB page)
2192 p_pctl_timing->trrd = (((DDR2_tRRD*nMHz+999)/1000)&0xF);
2193 p_publ_timing->dtpr0.b.tRRD = ((DDR2_tRRD*nMHz+999)/1000)&0xF;
2197 tmp = ((DDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2198 p_pctl_timing->trtp = tmp&0xF;
2199 p_publ_timing->dtpr0.b.tRTP = tmp;
2201 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2203 p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
2207 tmp = ((DDR2_tWR*nMHz+999)/1000);
2208 p_pctl_timing->twr = tmp&0x1F;
2209 bl_tmp = (bl == 8) ? DDR2_BL8 : DDR2_BL4;
2210 p_publ_timing->mr[0] = bl_tmp | DDR2_CL(cl) | DDR2_WR(tmp);
2212 * tWTR, 10ns(200MHz) 7.5ns(>200MHz)
2216 tmp = ((DDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2220 tmp = ((DDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2222 p_pctl_timing->twtr = tmp&0xF;
2223 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2224 p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
2226 * tXP, 6-AL(200MHz) 6-AL(266MHz) 7-AL(333MHz) 8-AL(400MHz) 10-AL(533MHz)
2244 p_pctl_timing->txp = tmp&0x7;
2245 p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
2249 p_pctl_timing->txpdll = tmp & 0x3F;
2253 p_pctl_timing->tzqcs = 0;
2257 p_pctl_timing->tzqcsi = 0;
2261 p_pctl_timing->tdqs = DDR2_tDQS;
2265 p_pctl_timing->tcksre = DDR2_tCKSRE & 0x1F;
2267 * tCKSRX, no such timing
2269 p_pctl_timing->tcksrx = DDR2_tCKSRX & 0x1F;
2273 p_pctl_timing->tcke = DDR2_tCKE & 0x7;
2274 p_publ_timing->dtpr2.b.tCKE = DDR2_tCKE;
2278 p_pctl_timing->tckesr = DDR2_tCKESR&0xF;
2282 p_pctl_timing->tmod = ((DDR2_tMOD*nMHz+999)/1000)&0x1F;
2283 p_publ_timing->dtpr1.b.tMOD = ((DDR2_tMOD*nMHz+999)/1000);
2287 p_pctl_timing->trstl = 0;
2291 p_pctl_timing->tzqcl = 0;
2295 p_pctl_timing->tmrr = 0;
2299 p_pctl_timing->tdpd = 0;
2301 /**************************************************
2303 **************************************************/
2305 * tCCD, BL/2 for DDR2 and 4 for DDR3
2307 p_publ_timing->dtpr0.b.tCCD = 0;
2311 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2313 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2314 * 1:ODT may not be turned on until one clock after the read post-amble
2316 p_publ_timing->dtpr1.b.tRTODT = 1;
2318 * tFAW,50ns(<=333MHz 2KB page) 45ns(400MHz 2KB page) 45ns(533MHz 2KB page)
2322 tmp = DDR2_tFAW_333MHz;
2326 tmp = DDR2_tFAW_400MHz;
2328 p_publ_timing->dtpr1.b.tFAW = ((tmp*nMHz+999)/1000)&0x7F;
2332 p_publ_timing->dtpr1.b.tAOND = 0;
2334 * tDLLK,=tXSRD=200 tCK
2336 p_publ_timing->dtpr2.b.tDLLK = DDR2_tDLLK;
2337 /**************************************************
2339 **************************************************/
2340 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2342 else //if(mem_type == LPDDR)
2344 #define mDDR_tREFI_7_8_us (78)
2345 #define mDDR_tMRD (2)
2346 #define mDDR_tRFC_256Mb (80)
2347 #define mDDR_tRFC_512Mb (110)
2348 #define mDDR_tRFC_1Gb (140)
2349 #define mDDR_tXSR (200)
2350 #define mDDR_tRAS_100MHz (50)
2351 #define mDDR_tRAS_133MHz (45)
2352 #define mDDR_tRAS_185MHz (42)
2353 #define mDDR_tRAS_200MHz (40)
2354 #define mDDR_tRTW (3) //register min valid value
2355 #define mDDR_tRRD_133MHz (15)
2356 #define mDDR_tRRD_166MHz (12)
2357 #define mDDR_tRRD_185MHz (11)
2358 #define mDDR_tRRD_200MHz (10)
2359 #define mDDR_tRTP (0)
2360 #define mDDR_tWR (15)
2361 #define mDDR_tWTR_133MHz (1)
2362 #define mDDR_tWTR_200MHz (2)
2363 #define mDDR_tXP (25)
2364 #define mDDR_tDQS (1)
2365 #define mDDR_tCKSRE (1)
2366 #define mDDR_tCKSRX (1)
2367 #define mDDR_tCKE (2)
2372 * mobile DDR timing USE 3-3-3, CL always = 3
2376 bl_tmp = (bl == 8) ? mDDR_BL8 : ((bl == 4) ? mDDR_BL4 : mDDR_BL2);
2377 p_publ_timing->mr[0] = bl_tmp | mDDR_CL(cl);
2378 p_publ_timing->mr[2] = mDDR_DS_3_4; //mr[2] is mDDR MR1
2379 p_publ_timing->mr[1] = 0;
2380 p_publ_timing->mr[3] = 0;
2381 /**************************************************
2383 **************************************************/
2385 * tREFI, average periodic refresh interval, 7.8us
2387 p_pctl_timing->trefi = mDDR_tREFI_7_8_us;
2391 p_pctl_timing->tmrd = mDDR_tMRD & 0x7;
2392 p_publ_timing->dtpr0.b.tMRD = mDDR_tMRD;
2394 * tRFC, 80ns(128Mb,256Mb) 110ns(512Mb) 140ns(1Gb,2Gb)
2396 if(ddr_capability_per_die <= 0x2000000) // 256Mb
2398 tmp = mDDR_tRFC_256Mb;
2400 else if(ddr_capability_per_die <= 0x4000000) // 512Mb
2402 tmp = mDDR_tRFC_512Mb;
2406 tmp = mDDR_tRFC_1Gb;
2408 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2409 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
2413 p_pctl_timing->tckesr = tmp&0xF;
2417 p_pctl_timing->texsr = ((mDDR_tXSR*nMHz+999)/1000)&0x3FF;
2418 p_publ_timing->dtpr2.b.tXS = ((mDDR_tXSR*nMHz+999)/1000)&0x3FF;
2422 p_pctl_timing->trp = cl;
2423 p_publ_timing->dtpr0.b.tRP = cl;
2425 * WrToMiss=WL*tCK + tWR + tRP + tRCD
2427 p_noc_timing->b.WrToMiss = ((cwl+((mDDR_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
2429 * tRAS, 50ns(100MHz) 45ns(133MHz) 42ns(166MHz) 42ns(185MHz) 40ns(200MHz)
2433 tmp = mDDR_tRAS_100MHz;
2437 tmp = mDDR_tRAS_133MHz;
2441 tmp =mDDR_tRAS_185MHz;
2445 tmp = mDDR_tRAS_200MHz;
2447 tmp = ((tmp*nMHz+999)/1000);
2448 p_pctl_timing->tras = (tmp&0x3F);
2449 p_publ_timing->dtpr0.b.tRAS = tmp&0x1F;
2453 p_pctl_timing->trc = ((tmp+cl)&0x3F);
2454 p_noc_timing->b.ActToAct = ((tmp+cl)&0x3F);
2455 p_publ_timing->dtpr0.b.tRC = (tmp+cl)&0xF;
2456 p_pctl_timing->trtw = (cl+2-cwl);//mDDR_tRTW;
2457 p_publ_timing->dtpr1.b.tRTW = 0;
2458 p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
2459 p_pctl_timing->tal = al;
2460 p_pctl_timing->tcl = cl;
2461 p_pctl_timing->tcwl = cwl;
2465 p_pctl_timing->trcd = cl;
2466 p_publ_timing->dtpr0.b.tRCD = cl;
2468 * tRRD,15ns(100MHz) 15ns(133MHz) 12ns(166MHz) 10.8ns(185MHz) 10ns(200MHz)
2473 tmp = mDDR_tRRD_133MHz;
2477 tmp = mDDR_tRRD_166MHz;
2481 tmp = mDDR_tRRD_185MHz;
2485 tmp = mDDR_tRRD_200MHz;
2487 p_pctl_timing->trrd = (((tmp*nMHz+999)/1000)&0xF);
2488 p_publ_timing->dtpr0.b.tRRD = ((tmp*nMHz+999)/1000)&0xF;
2492 tmp = ((mDDR_tRTP*nMHz+999)/1000);
2493 p_pctl_timing->trtp = tmp&0xF;
2494 p_publ_timing->dtpr0.b.tRTP = tmp;
2496 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2498 p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
2502 p_pctl_timing->twr = ((mDDR_tWR*nMHz+999)/1000)&0x1F;
2504 * tWTR, 1 tCK(100MHz,133MHz) 2 tCK(166MHz,185MHz,200MHz)
2508 tmp = mDDR_tWTR_133MHz;
2512 tmp = mDDR_tWTR_200MHz;
2514 p_pctl_timing->twtr = tmp&0xF;
2515 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2516 p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
2521 p_pctl_timing->txp = ((mDDR_tXP*nMHz+999)/1000)&0x7;
2522 p_publ_timing->dtpr2.b.tXP = ((mDDR_tXP*nMHz+999)/1000)&0x1F;
2526 p_pctl_timing->txpdll = 0;
2530 p_pctl_timing->tzqcs = 0;
2534 p_pctl_timing->tzqcsi = 0;
2538 p_pctl_timing->tdqs = mDDR_tDQS;
2542 p_pctl_timing->tcksre = mDDR_tCKSRE & 0x1F;
2544 * tCKSRX, no such timing
2546 p_pctl_timing->tcksrx = mDDR_tCKSRX & 0x1F;
2550 p_pctl_timing->tcke = mDDR_tCKE & 0x7;
2551 p_publ_timing->dtpr2.b.tCKE = mDDR_tCKE;
2555 p_pctl_timing->tmod = 0;
2556 p_publ_timing->dtpr1.b.tMOD = 0;
2560 p_pctl_timing->trstl = 0;
2564 p_pctl_timing->tzqcl = 0;
2568 p_pctl_timing->tmrr = 0;
2572 p_pctl_timing->tdpd = 0;
2574 /**************************************************
2576 **************************************************/
2578 * tCCD, BL/2 for DDR2 and 4 for DDR3
2580 p_publ_timing->dtpr0.b.tCCD = 0;
2584 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2586 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2587 * 1:ODT may not be turned on until one clock after the read post-amble
2589 p_publ_timing->dtpr1.b.tRTODT = 1;
2593 p_publ_timing->dtpr1.b.tFAW = 0;
2597 p_publ_timing->dtpr1.b.tAOND = 0;
2601 p_publ_timing->dtpr2.b.tDLLK = 0;
2602 /**************************************************
2604 **************************************************/
2605 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2611 uint32_t __sramlocalfunc ddr_update_timing(void)
2614 PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
2615 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
2616 NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
2618 ddr_copy((uint32_t *)&(pDDR_Reg->TOGCNT1U), (uint32_t*)&(p_pctl_timing->togcnt1u), 34);
2619 ddr_copy((uint32_t *)&(pPHY_Reg->DTPR[0]), (uint32_t*)&(p_publ_timing->dtpr0), 3);
2620 *(volatile uint32_t *)SysSrv_DdrTiming = p_noc_timing->d32;
2622 if(mem_type == DDR3)
2624 bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
2625 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
2626 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
2627 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
2629 else if(mem_type == LPDDR2)
2631 switch(p_publ_timing->mr[1] & 0x7)
2634 bl_tmp = mddr_lpddr2_bl_4;
2637 bl_tmp = mddr_lpddr2_bl_8;
2640 bl_tmp = mddr_lpddr2_bl_16;
2645 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
2649 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
2651 i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
2652 pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8); //tDQSCKmax-tDQSCK
2653 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-1;
2654 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL;
2656 else if(mem_type == DDR2)
2658 bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR2_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
2659 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
2661 else// if(mem_type == LPDDR)
2663 switch(p_publ_timing->mr[0] & 0x7)
2666 bl_tmp = mddr_lpddr2_bl_2;
2669 bl_tmp = mddr_lpddr2_bl_4;
2672 bl_tmp = mddr_lpddr2_bl_8;
2675 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
2680 uint32_t __sramlocalfunc ddr_update_mr(void)
2682 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
2683 uint32_t cs,dll_off;
2685 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2686 dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
2687 ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
2688 if((mem_type == DDR3) || (mem_type == DDR2))
2690 if(ddr_freq>DDR3_DDR2_DLL_DISABLE_FREQ)
2692 if(dll_off) // off -> on
2694 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((uint8_t)(p_publ_timing->mr[1]))); //DLL enable
2695 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((uint8_t)(p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
2696 ddr_delayus(2); //at least 200 DDR cycle
2697 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((uint8_t)(p_publ_timing->mr[0])));
2701 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((uint8_t)(p_publ_timing->mr[1])));
2702 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((uint8_t)(p_publ_timing->mr[0])));
2707 pPHY_Reg->MR[1] = (((uint8_t)(p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
2708 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((uint8_t)(p_publ_timing->mr[1])) | DDR3_DLL_DISABLE)); //DLL disable
2709 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((uint8_t)(p_publ_timing->mr[0])));
2711 ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((uint8_t)(p_publ_timing->mr[2])));
2713 else if(mem_type == LPDDR2)
2715 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((uint8_t)(p_publ_timing->mr[1])));
2716 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((uint8_t)(p_publ_timing->mr[2])));
2717 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((uint8_t)(p_publ_timing->mr[3])));
2721 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((uint8_t)(p_publ_timing->mr[0])));
2722 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((uint8_t)(p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
2727 void __sramlocalfunc ddr_update_odt(void)
2731 //adjust DRV and ODT
2732 if((mem_type == DDR3) || (mem_type == DDR2))
2734 if(ddr_freq <= DDR3_DDR2_ODT_DISABLE_FREQ)
2736 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
2737 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
2738 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
2739 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
2743 pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9); //dynamic RTT enable
2744 pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
2745 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
2746 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
2751 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
2752 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
2753 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
2754 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
2756 tmp = (0x1<<28) | (0x2<<15) | (0x2<<10) | (0xb<<5) | 0xb; //DS=34ohm,ODT=171ohm
2757 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2760 pPHY_Reg->ZQ1CR[1] = tmp;
2763 pPHY_Reg->ZQ0CR[0] = tmp;
2767 __sramfunc void ddr_adjust_config(uint32_t dram_type)
2770 unsigned long save_sp;
2773 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
2775 //get data training address before idle port
2776 value = ddr_get_datatraing_addr();
2778 /** 1. Make sure there is no host access */
2783 DDR_SAVE_SP(save_sp);
2790 n= pDDR_Reg->SCFG.d32;
2792 n= pCRU_Reg->CRU_PLL_CON[0][0];
2793 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
2794 n= *(volatile uint32_t *)SysSrv_DdrConf;
2797 //enter config state
2798 ddr_move_to_Config_state();
2800 //extend capability for debug
2801 if(pGRF_Reg->GRF_SOC_CON[2] & (0x1<<1))
2803 pGRF_Reg->GRF_SOC_CON[2] = rank_to_row15_en;
2806 //set data training address
2807 pPHY_Reg->DTAR = value;
2809 //set auto power down idle
2810 pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
2813 pPHY_Reg->PGCR &= ~(0x3<<12);
2815 //enable the hardware low-power interface
2816 pDDR_Reg->SCFG.b.hw_low_power_en = 1;
2820 //enter access state
2821 ddr_move_to_Access_state();
2823 DDR_RESTORE_SP(save_sp);
2827 void __sramlocalfunc idle_port(void)
2830 uint32 clk_gate[10];
2832 //save clock gate status
2834 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
2836 //enable all clock gate for request idle
2838 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
2840 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
2842 pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
2844 while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
2847 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
2849 pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
2851 while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
2854 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
2856 pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
2858 while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
2861 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
2863 pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
2865 while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
2868 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
2870 pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
2872 while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
2875 //resume clock gate status
2877 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
2880 void __sramlocalfunc deidle_port(void)
2883 uint32 clk_gate[10];
2885 //save clock gate status
2887 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
2889 //enable all clock gate for request idle
2891 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
2893 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
2895 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
2897 while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
2899 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
2901 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
2903 while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
2906 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
2908 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
2910 while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
2913 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
2915 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
2917 while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
2920 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
2922 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
2924 while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
2927 //resume clock gate status
2929 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
2933 void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
2935 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
2938 ddr_move_to_Config_state();
2939 pDDR_Reg->TZQCSI = 0;
2940 if((nMHz<=DDR3_DDR2_DLL_DISABLE_FREQ) && ((mem_type == DDR3) || (mem_type == DDR2))) // DLL disable
2942 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2943 pPHY_Reg->MR[1] = (((uint8_t)(p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
2944 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((uint8_t)(p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));
2946 ddr_move_to_Lowpower_state();
2948 ddr_set_dll_bypass(0); //dll bypass
2949 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
2953 void __sramlocalfunc ddr_selfrefresh_exit(void)
2957 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
2959 ddr_set_dll_bypass(ddr_freq);
2961 //ddr_delayus(10); //wait DLL lock
2963 ddr_move_to_Config_state();
2964 ddr_update_timing();
2967 n = ddr_data_training();
2968 ddr_move_to_Access_state();
2971 sram_printascii("DTT failed!\n");
2975 uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
2980 unsigned long flags;
2981 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
2982 unsigned long save_sp;
2983 uint32_t regvalue = pCRU_Reg->CRU_PLL_CON[0][0];
2986 // freq = (Fin/NR)*NF/OD
2987 if((pCRU_Reg->CRU_MODE_CON&3) == 1) // CPLL Normal mode
2988 freq = 24 *((pCRU_Reg->CRU_PLL_CON[0][1]&0x1fff)+1) // NF = 2*(CLKF+1)
2989 /((((regvalue>>8)&0x3f)+1) // NR = CLKR+1
2990 *((regvalue&0xF)+1)); // OD = 2^CLKOD
2994 loops_per_us = LPJ_100MHZ*freq / 1000000;
2996 ret=ddr_set_pll(nMHz,0);
2997 ddr_get_parameter(ret);
2999 /** 1. Make sure there is no host access */
3000 local_irq_save(flags);
3001 local_fiq_disable();
3006 DDR_SAVE_SP(save_sp);
3012 n= pDDR_Reg->SCFG.d32;
3014 n= pCRU_Reg->CRU_PLL_CON[0][0];
3015 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3016 n= *(volatile uint32_t *)SysSrv_DdrConf;
3017 n= pGRF_Reg->GRF_SOC_STATUS0;
3020 /** 2. ddr enter self-refresh mode or precharge power-down mode */
3022 ddr_selfrefresh_enter(ret);
3024 /** 3. change frequence */
3028 /** 5. Issues a Mode Exit command */
3029 ddr_selfrefresh_exit();
3033 DDR_RESTORE_SP(save_sp);
3035 local_irq_restore(flags);
3039 EXPORT_SYMBOL(ddr_change_freq);
3041 void ddr_set_auto_self_refresh(bool en)
3043 //set auto self-refresh idle
3044 ddr_sr_idle = en ? SR_IDLE : 0;
3046 EXPORT_SYMBOL(ddr_set_auto_self_refresh);
3048 void __sramfunc ddr_suspend(void)
3052 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3054 /** 1. Make sure there is no host access */
3055 //flush_cache_all();
3056 //outer_flush_all();
3064 n= pDDR_Reg->SCFG.d32;
3066 n= pCRU_Reg->CRU_PLL_CON[0][0];
3067 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3068 n= *(volatile uint32_t *)SysSrv_DdrConf;
3071 ddr_selfrefresh_enter(0);
3073 pCRU_Reg->CRU_MODE_CON = (0x3<<((1*4) + 16)) | (0x0<<(1*4)); //PLL slow-mode
3076 pCRU_Reg->CRU_PLL_CON[1][3] = ((0x1<<1)<<16) | (0x1<<1); //PLL power-down
3080 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29))); //CKOE
3082 EXPORT_SYMBOL(ddr_suspend);
3084 void __sramfunc ddr_resume(void)
3087 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29)); //CKOE
3090 pCRU_Reg->CRU_PLL_CON[1][3] = ((0x1<<1)<<16) | (0x0<<1); //PLL no power-down
3095 if (pGRF_Reg->GRF_SOC_STATUS0 & (0x1<<4))
3100 pCRU_Reg->CRU_MODE_CON = (0x3<<((1*4) + 16)) | (0x1<<(1*4)); //PLL normal
3103 ddr_selfrefresh_exit();
3105 EXPORT_SYMBOL(ddr_resume);
3107 //»ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
3108 uint32 ddr_get_cap(void)
3114 i = *(volatile uint32*)SysSrv_DdrConf;
3115 switch((pPHY_Reg->PGCR>>18) & 0xF)
3129 row = ddr_cfg_2_rbc[i].row;
3130 if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
3135 return (1 << (row+(ddr_cfg_2_rbc[i].col)+(ddr_cfg_2_rbc[i].bank)+2))*cs;
3137 EXPORT_SYMBOL(ddr_get_cap);
3139 void ddr_reg_save(void)
3142 ddr_reg.pctl.SCFG = pDDR_Reg->SCFG.d32;
3143 ddr_reg.pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
3144 ddr_reg.pctl.MCFG1 = pDDR_Reg->MCFG1;
3145 ddr_reg.pctl.MCFG = pDDR_Reg->MCFG;
3146 ddr_reg.pctl.pctl_timing.ddrFreq = ddr_freq;
3147 ddr_reg.pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
3148 ddr_reg.pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
3149 ddr_reg.pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
3150 ddr_reg.pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
3151 ddr_reg.pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
3152 ddr_reg.pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
3153 ddr_reg.pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
3154 ddr_reg.pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
3155 ddr_reg.pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
3156 ddr_reg.pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
3157 ddr_reg.pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
3158 ddr_reg.pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
3159 ddr_reg.pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
3160 ddr_reg.pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
3161 ddr_reg.pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
3163 ddr_reg.pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
3164 ddr_reg.pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
3165 ddr_reg.pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
3166 ddr_reg.pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
3167 ddr_reg.pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
3168 ddr_reg.pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
3169 ddr_reg.pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
3170 ddr_reg.pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
3171 ddr_reg.pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
3174 ddr_reg.publ.PIR = pPHY_Reg->PIR;
3175 ddr_reg.publ.PGCR = pPHY_Reg->PGCR;
3176 ddr_reg.publ.DLLGCR = pPHY_Reg->DLLGCR;
3177 ddr_reg.publ.ACDLLCR = pPHY_Reg->ACDLLCR;
3178 ddr_reg.publ.PTR[0] = pPHY_Reg->PTR[0];
3179 ddr_reg.publ.PTR[1] = pPHY_Reg->PTR[1];
3180 ddr_reg.publ.PTR[2] = pPHY_Reg->PTR[2];
3181 ddr_reg.publ.ACIOCR = pPHY_Reg->ACIOCR;
3182 ddr_reg.publ.DXCCR = pPHY_Reg->DXCCR;
3183 ddr_reg.publ.DSGCR = pPHY_Reg->DSGCR;
3184 ddr_reg.publ.DCR = pPHY_Reg->DCR.d32;
3185 ddr_reg.publ.ODTCR = pPHY_Reg->ODTCR;
3186 ddr_reg.publ.DTAR = pPHY_Reg->DTAR;
3187 ddr_reg.publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
3188 ddr_reg.publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
3190 ddr_reg.publ.DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
3191 ddr_reg.publ.DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
3192 ddr_reg.publ.DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
3193 ddr_reg.publ.DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
3195 ddr_reg.publ.DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
3196 ddr_reg.publ.DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
3197 ddr_reg.publ.DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
3198 ddr_reg.publ.DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
3200 ddr_reg.publ.DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
3201 ddr_reg.publ.DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
3202 ddr_reg.publ.DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
3203 ddr_reg.publ.DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
3205 ddr_reg.publ.DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
3206 ddr_reg.publ.DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
3207 ddr_reg.publ.DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
3208 ddr_reg.publ.DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
3211 ddr_reg.DdrConf = *(volatile uint32_t *)SysSrv_DdrConf;
3212 ddr_reg.DdrMode = *(volatile uint32_t *)SysSrv_DdrMode;
3213 ddr_reg.ReadLatency = *(volatile uint32_t *)SysSrv_ReadLatency;
3215 EXPORT_SYMBOL(ddr_reg_save);
3217 __attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
3219 #include "ddr_reg_resume.inc"
3222 int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
3224 volatile uint32_t value = 0;
3228 ddr_print("version 1.00 20120820 \n");
3230 mem_type = pPHY_Reg->DCR.b.DDRMD;
3231 ddr_speed_bin = dram_speed_bin;
3237 die = 2; //there is two die DDR3 at least
3238 ddr_print("DDR3 Device\n");
3241 ddr_print("LPDDR2 Device\n");
3244 ddr_print("DDR2 Device\n");
3247 ddr_print("DDR Device\n");
3250 ddr_print("LPDDR Device\n");
3253 switch((pPHY_Reg->PGCR>>18) & 0xF)
3267 //get capability per chip, not total size, used for calculate tRFC
3268 ddr_capability_per_die = ddr_get_cap()/(cs*die);
3269 ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n",
3272 (0x1<<(ddr_get_bank())), \
3274 (ddr_get_cap()>>20));
3275 ddr_adjust_config(mem_type);
3277 value=ddr_change_freq(freq);
3278 clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
3279 ddr_print("init success!!! freq=%dMHz\n", value);
3281 for(value=0;value<4;value++)
3283 gsr = pPHY_Reg->DATX8[value].DXGSR[0];
3284 dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
3285 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
3286 (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
3288 ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
3289 (pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
3290 (pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
3291 pPHY_Reg->ZQ0SR[1]&0x3,\
3292 (pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
3293 (pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
3294 (pPHY_Reg->ZQ0SR[1]>>6)&0x3);
3295 ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", pPHY_Reg->ZQ0SR[0]&0x1F, (pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
3296 ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
3300 EXPORT_SYMBOL(ddr_init);