2 #include <linux/cpufreq.h>
3 #include <linux/kernel.h>
4 #include <linux/interrupt.h>
8 #include <asm/pgtable-hwdef.h>
9 #include <asm/hardware/gic.h>
10 #include <asm/mach/arch.h>
11 #include <asm/hardware/cache-l2x0.h>
13 #include <plat/sram.h>
14 #include <mach/board.h>
15 #include <mach/gpio.h>
16 #include <mach/iomux.h>
19 #include <mach/loader.h>
21 #include <mach/dvfs.h>
22 #include <mach/cpu_axi.h>
23 #include <mach/debug_uart.h>
25 static void __init rk30_cpu_axi_init(void)
27 CPU_AXI_SET_QOS_PRIORITY(0, 0, DMAC);
28 CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU0);
29 CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1R);
30 CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1W);
31 #ifdef CONFIG_RK29_VMAC
32 CPU_AXI_SET_QOS_PRIORITY(2, 2, PERI);
34 CPU_AXI_SET_QOS_PRIORITY(0, 0, PERI);
36 CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC0);
37 CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC1);
39 writel_relaxed(0x3f, RK30_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
43 #define L2_LY_SP_OFF (0)
44 #define L2_LY_SP_MSK (0x7)
46 #define L2_LY_RD_OFF (4)
47 #define L2_LY_RD_MSK (0x7)
49 #define L2_LY_WR_OFF (8)
50 #define L2_LY_WR_MSK (0x7)
51 #define L2_LY_SET(ly,off) (((ly)-1)<<(off))
53 #define L2_LATENCY(setup_cycles, read_cycles, write_cycles) \
54 L2_LY_SET(setup_cycles, L2_LY_SP_OFF) | \
55 L2_LY_SET(read_cycles, L2_LY_RD_OFF) | \
56 L2_LY_SET(write_cycles, L2_LY_WR_OFF)
58 static void __init rk30_l2_cache_init(void)
60 #ifdef CONFIG_CACHE_L2X0
61 u32 aux_ctrl, aux_ctrl_mask, data_latency_ctrl;
62 unsigned int max_cpu_freq = 1608000; // kHz
63 struct cpufreq_frequency_table *table = NULL;
67 clk_cpu = clk_get(NULL, "cpu");
68 if (!IS_ERR(clk_cpu)) {
69 table = dvfs_get_freq_volt_table(clk_cpu);
71 pr_err("failed to get cpu freq volt table\n");
73 pr_err("failed to get clk cpu\n");
74 for (i = 0; table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
75 if (max_cpu_freq < table[i].frequency)
76 max_cpu_freq = table[i].frequency;
79 if (max_cpu_freq <= 1608000)
80 data_latency_ctrl = L2_LATENCY(4, 6, 1);
81 else if (max_cpu_freq <= 1800000)
82 data_latency_ctrl = L2_LATENCY(5, 7, 1);
83 else if (max_cpu_freq <= 1992000)
84 data_latency_ctrl = L2_LATENCY(5, 8, 1);
86 data_latency_ctrl = L2_LATENCY(6, 8, 1);
88 writel_relaxed(L2_LATENCY(1, 1, 1), RK30_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
89 writel_relaxed(data_latency_ctrl, RK30_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
91 /* L2X0 Prefetch Control */
92 writel_relaxed(0x70000003, RK30_L2C_BASE + L2X0_PREFETCH_CTRL);
94 /* L2X0 Power Control */
95 writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK30_L2C_BASE + L2X0_POWER_CTRL);
98 (0x1 << 25) | // round-robin
99 (0x1 << 0) | // Full Line of Zero Enable
100 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
101 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
102 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
103 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
106 (0x1 << 25) | // round-robin
107 (0x1 << 0) | // Full Line of Zero Enable
108 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
109 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
110 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
111 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
113 l2x0_init(RK30_L2C_BASE, aux_ctrl, aux_ctrl_mask);
117 static int boot_mode;
119 static const char *boot_flag_name(u32 flag)
121 flag -= SYS_KERNRL_REBOOT_FLAG;
123 case BOOT_NORMAL: return "NORMAL";
124 case BOOT_LOADER: return "LOADER";
125 case BOOT_MASKROM: return "MASKROM";
126 case BOOT_RECOVER: return "RECOVER";
127 case BOOT_NORECOVER: return "NORECOVER";
128 case BOOT_SECONDOS: return "SECONDOS";
129 case BOOT_WIPEDATA: return "WIPEDATA";
130 case BOOT_WIPEALL: return "WIPEALL";
131 case BOOT_CHECKIMG: return "CHECKIMG";
132 case BOOT_FASTBOOT: return "FASTBOOT";
137 static const char *boot_mode_name(u32 mode)
140 case BOOT_MODE_NORMAL: return "NORMAL";
141 case BOOT_MODE_FACTORY2: return "FACTORY2";
142 case BOOT_MODE_RECOVERY: return "RECOVERY";
143 case BOOT_MODE_CHARGE: return "CHARGE";
144 case BOOT_MODE_POWER_TEST: return "POWER_TEST";
145 case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
146 case BOOT_MODE_REBOOT: return "REBOOT";
147 case BOOT_MODE_PANIC: return "PANIC";
148 case BOOT_MODE_WATCHDOG: return "WATCHDOG";
153 static void __init rk30_boot_mode_init(void)
155 u32 boot_flag = readl_relaxed(RK30_PMU_BASE + PMU_SYS_REG0);
156 boot_mode = readl_relaxed(RK30_PMU_BASE + PMU_SYS_REG1);
158 if (boot_flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
159 boot_mode = BOOT_MODE_RECOVERY;
161 if (boot_mode || ((boot_flag & 0xff) && ((boot_flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
162 printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(boot_mode), boot_mode, boot_flag_name(boot_flag), boot_flag);
163 #ifdef CONFIG_RK29_WATCHDOG
164 writel_relaxed(BOOT_MODE_WATCHDOG, RK30_PMU_BASE + PMU_SYS_REG1);
168 int board_boot_mode(void)
172 EXPORT_SYMBOL(board_boot_mode);
174 void __init rk30_init_irq(void)
176 gic_init(0, IRQ_LOCALTIMER, RK30_GICD_BASE, RK30_GICC_BASE);
183 static void usb_uart_init(void)
185 #if defined(CONFIG_ARCH_RK3188) && (CONFIG_RK_DEBUG_UART == 2)
186 #ifdef CONFIG_RK_USB_UART
187 if (!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1 << 13))) { //detect id
188 writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
190 if (!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1 << 10))) { //detect vbus
191 writel_relaxed(((0x01 << 2) | ((0x01 << 2) << 16)), RK30_GRF_BASE + GRF_UOC0_CON2); //software control usb phy enable
192 writel_relaxed((0x2A | (0x3F << 16)), RK30_GRF_BASE + GRF_UOC0_CON3); //usb phy enter suspend
193 writel_relaxed((0x0300 | (0x0300 << 16)), RK30_GRF_BASE + GRF_UOC0_CON0);
195 writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
199 writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
204 void __init rk30_map_io(void)
206 rk30_map_common_io();
208 rk29_setup_early_printk();
212 rk30_l2_cache_init();
213 ddr_init(DDR_TYPE, DDR_FREQ);
214 clk_disable_unused();
216 rk30_boot_mode_init();
219 static __init u32 rk30_get_ddr_size(void)
223 u32 pgtbl = PAGE_OFFSET + TEXT_OFFSET - 0x4000;
224 u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;
226 a[0] = pgtbl + (((u32)RK30_CPU_AXI_BUS_BASE >> 20) << 2);
227 a[1] = pgtbl + (((u32)RK30_DDR_PUBL_BASE >> 20) << 2);
228 a[2] = pgtbl + (((u32)RK30_GRF_BASE >> 20) << 2);
229 v[0] = readl_relaxed(a[0]);
230 v[1] = readl_relaxed(a[1]);
231 v[2] = readl_relaxed(a[2]);
232 writel_relaxed(flag | ((RK30_CPU_AXI_BUS_PHYS >> 20) << 20), a[0]);
233 writel_relaxed(flag | ((RK30_DDR_PUBL_PHYS >> 20) << 20), a[1]);
234 writel_relaxed(flag | ((RK30_GRF_PHYS >> 20) << 20), a[2]);
236 size = ddr_get_cap();
238 writel_relaxed(v[0], a[0]);
239 writel_relaxed(v[1], a[1]);
240 writel_relaxed(v[2], a[2]);
245 void __init rk30_fixup(struct machine_desc *desc, struct tag *tags,
246 char **cmdline, struct meminfo *mi)
249 mi->bank[0].start = PLAT_PHYS_OFFSET;
250 mi->bank[0].size = rk30_get_ddr_size();