arch/arm/mach-rk30/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include "clock.h"
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29
  30 #define MHZ                     (1000*1000)
  31 #define KHZ                     (1000)
  32 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  33 #define CLK_LOOPS_RATE_REF (1200) //Mhz
  34 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  35
  36 //flags bit
  37 //has extern 27mhz
  38 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  39 //max i2s rate
  40 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  41 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  42 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  43 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  44
  45
  46
  47 struct apll_clk_set {
  48         unsigned long rate;
  49         u32     pllcon0;
  50         u32     pllcon1;
  51         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  52         u32 rst_dly;//us
  53         u32     clksel0;
  54         u32     clksel1;
  55         unsigned long lpj;
  56 };
  57 struct pll_clk_set {
  58         unsigned long rate;
  59         u32     pllcon0;
  60         u32     pllcon1;
  61         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  62         u32 rst_dly;//us
  63 };
  64
  65 #define SET_PLL_DATA(_pll_id,_table) \
  66 {\
  67         .id=(_pll_id),\
  68         .table=(_table),\
  69 }
  70
  71
  72 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  73 { \
  74         .rate   = (_mhz) * KHZ, \
  75         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  76         .pllcon1 = PLL_CLKF_SET(nf),\
  77         .pllcon2 = PLL_CLK_BWADJ_SET(nf/2-1),\
  78         .rst_dly=((nr*500)/24+1),\
  79         }
  80
  81
  82 #define _APLL_SET_LPJ(_mhz) \
  83         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  84
  85
  86 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
  87         { \
  88         .rate   = _mhz * MHZ, \
  89         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no),\
  90         .pllcon1 = PLL_CLKF_SET(nf),\
  91         .pllcon2 = PLL_CLK_BWADJ_SET(nf>>1),\
  92         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
  93         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
  94         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
  95         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
  96         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
  97         _APLL_SET_LPJ(_mhz),\
  98         .rst_dly=((nr*500)/24+1),\
  99         }
 100
 101 #define CRU_DIV_SET(mask,shift,max) \
 102         .div_mask=(mask),\
 103         .div_shift=(shift),\
 104         .div_max=(max)
 105
 106
 107 #define CRU_SRC_SET(mask,shift ) \
 108         .src_mask=(mask),\
 109         .src_shift=(shift)
 110
 111 #define CRU_PARENTS_SET(parents_array) \
 112         .parents=(parents_array),\
 113         .parents_num=ARRAY_SIZE((parents_array))
 114
 115 #define CRU_GATE_MODE_SET(_func,_IDX) \
 116         .mode=_func,\
 117         .gate_idx=(_IDX)
 118
 119 struct clk_src_sel {
 120         struct clk      *parent;
 121         u8      value;//crt bit
 122         u8      flag;
 123 //selgate
 124 };
 125
 126 #define GATE_CLK(NAME,PARENT,ID) \
 127 static struct clk clk_##NAME = { \
 128         .name           = #NAME, \
 129         .parent         = &PARENT, \
 130         .mode           = gate_mode, \
 131         .gate_idx       = CLK_GATE_##ID, \
 132 }
 133 #ifdef RK30_CLK_OFFBOARD_TEST
 134 u32 TEST_GRF_REG[0x240];
 135 u32 TEST_CRU_REG[0x240];
 136 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 137
 138 u32 cru_writel_is_pr(u32 offset)
 139 {
 140         return (offset==0x4000);
 141 }
 142 void cru_writel(u32 v, u32 offset)
 143 {
 144
 145         u32 mask_v=v>>16;
 146         TEST_CRU_REG[offset/4]&=(~mask_v);
 147
 148         v&=(mask_v);
 149
 150         TEST_CRU_REG[offset/4]|=v;
 151         TEST_CRU_REG[offset/4]&=0x0000ffff;
 152
 153         if(cru_writel_is_pr(offset))
 154         {
 155                 CRU_PRINTK_DBG("cru w offset=%d,set=%x,reg=%x\n",offset,v,TEST_CRU_REG[offset/4]);
 156
 157         }
 158
 159 }
 160 void cru_writel_i2s(u32 v, u32 offset)
 161 {
 162         TEST_CRU_REG[offset/4]=v;
 163 }
 164 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 165
 166 #define regfile_readl(offset)   (0xffffffff)
 167 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 168 void rk30_clkdev_add(struct clk_lookup *cl);
 169 #else
 170 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 171 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 172 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 173 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 174
 175 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 176 #endif
 177
 178 #ifdef DEBUG
 179 #define CRU_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
 180 #define CRU_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
 181 #else
 182 #define CRU_PRINTK_DBG(fmt, args...) do {} while(0)
 183 #define CRU_PRINTK_LOG(fmt, args...) do {} while(0)
 184 #endif
 185 #define CRU_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args)
 186
 187
 188 #define get_cru_bits(con,mask,shift)\
 189         ((cru_readl((con)) >> (shift)) & (mask))
 190
 191 #define set_cru_bits_w_msk(val,mask,shift,con)\
 192         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 193
 194
 195 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 196         &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 197
 198
 199 static u32 rk30_clock_flags=0;
 200 static struct clk codec_pll_clk;
 201 static struct clk general_pll_clk;
 202 static struct clk arm_pll_clk;
 203 static unsigned long lpj_gpll;
 204 static unsigned int __initdata armclk = 504*MHZ;
 205
 206
 207 /************************clk recalc div rate*********************************/
 208
 209 //for free div
 210 static unsigned long clksel_recalc_div(struct clk *clk)
 211 {
 212         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift) + 1;
 213
 214         unsigned long rate = clk->parent->rate / div;
 215         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 216         return rate;
 217 }
 218
 219 //for div 1 2 4 2^n
 220 static unsigned long clksel_recalc_shift(struct clk *clk)
 221 {
 222         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
 223         unsigned long rate = clk->parent->rate >> shift;
 224         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 225         return rate;
 226 }
 227
 228
 229 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 230 {
 231         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
 232         unsigned long rate = clk->parent->rate >> shift;
 233         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 234         return rate;
 235 }
 236
 237 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 238 {
 239         unsigned long rate = clk->parent->rate;
 240         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 241         return rate;
 242 }
 243 /********************************set div rate***********************************/
 244
 245 //for free div
 246 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 247 {
 248         u32 div;
 249         for (div = 0; div < clk->div_max; div++) {
 250                 u32 new_rate = clk->parent->rate / (div + 1);
 251                 if (new_rate <= rate) {
 252                         set_cru_bits_w_msk(div,clk->div_mask,clk->div_shift,clk->clksel_con);
 253                         //clk->rate = new_rate;
 254                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 255                         return 0;
 256                 }
 257         }
 258         return -ENOENT;
 259 }
 260
 261 //for div 1 2 4 2^n
 262 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 263 {
 264         u32 shift;
 265         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 266                 u32 new_rate = clk->parent->rate >> shift;
 267                 if (new_rate <= rate) {
 268                         set_cru_bits_w_msk(shift,clk->div_mask,clk->div_shift,clk->clksel_con);
 269                         clk->rate = new_rate;
 270                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 271                         return 0;
 272                 }
 273         }
 274         return -ENOENT;
 275 }
 276
 277 //for div 2 4 2^n
 278 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 279 {
 280         u32 shift;
 281
 282         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 283                 u32 new_rate = clk->parent->rate >> shift;
 284                 if (new_rate <= rate) {
 285                         set_cru_bits_w_msk(shift-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 286                         clk->rate = new_rate;
 287                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 288                         return 0;
 289                 }
 290         }
 291         return -ENOENT;
 292 }
 293 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate ,u32 div_max)
 294 {
 295         u32 div;
 296         unsigned long new_rate;
 297         for (div = 0; div <div_max; div++) {
 298                 new_rate = rate / (div + 1);
 299                 if (new_rate <= rate_out) {
 300                         return div+1;
 301                 }
 302         }
 303         return div_max?div_max:1;
 304 }
 305 struct clk *get_freediv_parents_div(struct clk *clk,unsigned long rate,u32 *div_out)
 306 {
 307         u32 div[2]={0,0};
 308         unsigned long new_rate[2]={0,0};
 309         u32 i;
 310
 311         if(clk->rate==rate)
 312                 return clk->parent;
 313         for(i=0;i<2;i++)
 314         {
 315                 div[i]=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
 316                 new_rate[i] = clk->parents[i]->rate/div[i];
 317                 if(new_rate[i]==rate)
 318                 {
 319                         *div_out=div[i];
 320                         return clk->parents[i];
 321                 }
 322         }
 323         if(new_rate[0]<new_rate[1])
 324                 i=1;
 325         else
 326                 i=0;
 327         *div_out=div[i];
 328         return clk->parents[i];
 329 }
 330
 331 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 332 {
 333         struct clk *p_clk;
 334         u32 div,old_div;
 335         int ret=0;
 336         if(clk->rate==rate)
 337                 return 0;
 338         p_clk=get_freediv_parents_div(clk,rate,&div);
 339
 340         if(!p_clk)
 341                 return -ENOENT;
 342
 343         CRU_PRINTK_DBG("%s %lu,form %s\n",clk->name,rate,p_clk->name);
 344         if (clk->parent != p_clk)
 345         {
 346                 old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),clk->div_shift,clk->div_mask)+1;
 347
 348                 if(div>old_div)
 349                 {
 350                         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 351                 }
 352                 ret=clk_set_parent_nolock(clk,p_clk);
 353                 if(ret)
 354                 {
 355                         CRU_PRINTK_ERR("%s can't set %lu,reparent err\n",clk->name,rate);
 356                         return -ENOENT;
 357                 }
 358         }
 359         //set div
 360         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 361         return 0;
 362 }
 363
 364 //rate==div rate //hdmi
 365 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 366 {
 367         struct clk *p_clk;
 368         u32 div,old_div;
 369         int ret;
 370         p_clk=get_freediv_parents_div(clk,rate,&div);
 371
 372         if(!p_clk)
 373         return -ENOENT;
 374
 375         if((p_clk->rate/div)!=rate||(p_clk->rate%div))
 376         return -ENOENT;
 377
 378         if (clk->parent != p_clk)
 379         {
 380                 old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
 381                                                                         clk->div_shift,clk->div_mask)+1;
 382                 if(div>old_div)
 383                 {
 384                         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 385                 }
 386                 ret=clk_set_parent_nolock(clk,p_clk);
 387                 if (ret)
 388                 {
 389                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
 390                         return ret;
 391                 }
 392         }
 393         //set div
 394         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 395         return 0;
 396 }
 397
 398 /***************************round********************************/
 399
 400 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 401 {
 402         return clk->parent->rate/clk_get_freediv(rate,clk->parent->rate,clk->div_max);
 403 }
 404
 405 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 406 {
 407         u32 div;
 408         struct clk *p_clk;
 409         if(clk->rate == rate)
 410                 return clk->rate;
 411         p_clk=get_freediv_parents_div(clk,rate,&div);
 412         if(!p_clk)
 413                 return 0;
 414         return p_clk->rate/div;
 415 }
 416
 417 /**************************************others seting************************************/
 418
 419 static struct clk* clksel_get_parent(struct clk *clk)
 420 {
 421         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 422 }
 423 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 424 {
 425         u32 i;
 426         if (unlikely(!clk->parents))
 427                 return -EINVAL;
 428         for (i = 0; (i <clk->parents_num); i++) {
 429                 if (clk->parents[i]!= parent)
 430                         continue;
 431                 set_cru_bits_w_msk(i,clk->src_mask,clk->src_shift,clk->clksel_con);
 432                 return 0;
 433         }
 434         return -EINVAL;
 435 }
 436
 437 static int gate_mode(struct clk *clk, int on)
 438 {
 439         int idx = clk->gate_idx;
 440         if (idx >= CLK_GATE_MAX)
 441                 return -EINVAL;
 442         if(on)
 443         {
 444                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 445                 //CRU_PRINTK_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 446                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 447         }
 448         else
 449         {
 450                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 451         //      CRU_PRINTK_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 452                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 453         }
 454         return 0;
 455 }
 456 /*****************************frac set******************************************/
 457
 458 static unsigned long clksel_recalc_frac(struct clk *clk)
 459 {
 460         unsigned long rate;
 461         u64 rate64;
 462         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 463         if (r == 0) // FPGA ?
 464                 return clk->parent->rate;
 465         numerator = r >> 16;
 466         denominator = r & 0xFFFF;
 467         rate64 = (u64)clk->parent->rate * numerator;
 468         do_div(rate64, denominator);
 469         rate = rate64;
 470         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 471         return rate;
 472 }
 473
 474 static u32 clk_gcd(u32 numerator, u32 denominator)
 475 {
 476         u32 a, b;
 477
 478         if (!numerator || !denominator)
 479                 return 0;
 480         if (numerator > denominator) {
 481                 a = numerator;
 482                 b = denominator;
 483         } else {
 484                 a = denominator;
 485                 b = numerator;
 486         }
 487         while (b != 0) {
 488                 int r = b;
 489                 b = a % b;
 490                 a = r;
 491         }
 492
 493         return a;
 494 }
 495
 496 static int frac_div_get_seting(unsigned long rate_out,unsigned long rate,
 497         u32 *numerator,u32 *denominator)
 498 {
 499         u32 gcd_vl;
 500         gcd_vl = clk_gcd(rate, rate_out);
 501         CRU_PRINTK_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n",rate_out,rate, gcd_vl);
 502
 503         if (!gcd_vl) {
 504                 CRU_PRINTK_ERR("gcd=0, i2s frac div is not be supported\n");
 505                 return -ENOENT;
 506         }
 507
 508         *numerator = rate_out / gcd_vl;
 509         *denominator = rate/ gcd_vl;
 510
 511         CRU_PRINTK_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 512                         *numerator, *denominator, *denominator / *numerator);
 513
 514         if (*numerator > 0xffff || *denominator > 0xffff||
 515                 (*denominator/(*numerator))<20) {
 516                 CRU_PRINTK_ERR("can't get a available nume and deno\n");
 517                 return -ENOENT;
 518         }
 519
 520         return 0;
 521
 522 }
 523 /* *********************pll **************************/
 524
 525 #define rk30_clock_udelay(a) udelay(a);
 526
 527 /*********************pll lock status**********************************/
 528 //#define GRF_SOC_CON0       0x15c
 529 static void pll_wait_lock(int pll_idx)
 530 {
 531         u32 pll_state[4]={1,0,2,3};
 532         u32 bit = 0x10u << pll_state[pll_idx];
 533         int delay = 24000000;
 534         while (delay > 0) {
 535                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 536                         break;
 537                 delay--;
 538         }
 539         if (delay == 0) {
 540                 CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
 541                 while(1);
 542         }
 543 }
 544
 545
 546
 547 /***************************pll function**********************************/
 548 static unsigned long pll_clk_recalc(u32 pll_id,unsigned long parent_rate)
 549 {
 550         unsigned long rate;
 551
 552         if (PLLS_IN_NORM(pll_id)) {
 553                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id,0));
 554                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id,1));
 555
 556
 557                 u64 rate64 = (u64)parent_rate*PLL_NF(pll_con1);
 558
 559                 /*
 560                 CRU_PRINTK_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 561                         ,PLL_CONS(pll_id,1),pll_con1, rate64);
 562                 */
 563
 564
 565                 //CRU_PRINTK_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 566         //CRU_PRINTK_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 567                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 568
 569                 do_div(rate64, PLL_NR(pll_con0));
 570                 do_div(rate64, PLL_NO(pll_con0));
 571
 572                 rate = rate64;
 573                 /*
 574                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 575                         pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 576                 */
 577         } else {
 578                 rate = parent_rate;
 579                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n",pll_id,rate);
 580         }
 581         return rate;
 582 }
 583 static unsigned long plls_clk_recalc(struct clk *clk)
 584 {
 585         return pll_clk_recalc(clk->pll->id,clk->parent->rate);
 586 }
 587
 588 static int pll_clk_set_rate(struct pll_clk_set *clk_set,u8 pll_id)
 589 {
 590         //enter slowmode
 591         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 592         //enter rest
 593         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 594         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id,0));
 595         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id,1));
 596         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2));
 597         rk30_clock_udelay(5);
 598
 599         //return form rest
 600         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 601
 602         //wating lock state
 603         rk30_clock_udelay(clk_set->rst_dly);
 604         pll_wait_lock(pll_id);
 605
 606         //return form slow
 607         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 608
 609         /*
 610         CRU_PRINTK_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 611                 cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 612         */
 613
 614
 615         return 0;
 616 }
 617 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 618 {
 619         struct _pll_data *pll_data=c->pll;
 620         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 621
 622         while(clk_set->rate)
 623         {
 624                 if (clk_set->rate == rate) {
 625                         break;
 626                 }
 627                 clk_set++;
 628         }
 629         if(clk_set->rate== rate)
 630         {
 631                 pll_clk_set_rate(clk_set,pll_data->id);
 632                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 633         }
 634         else
 635         {
 636                 CRU_PRINTK_ERR("gpll is no corresponding rate=%lu\n", rate);
 637                 return -1;
 638         }
 639         return 0;
 640 }
 641
 642 #define PLL_FREF_MIN (183*KHZ)
 643 #define PLL_FREF_MAX (1500*MHZ)
 644
 645 #define PLL_FVCO_MIN (300*MHZ)
 646 #define PLL_FVCO_MAX (1500*MHZ)
 647
 648 #define PLL_FOUT_MIN (18750*KHZ)
 649 #define PLL_FOUT_MAX (1500*MHZ)
 650
 651 #define PLL_NF_MAX (4096)
 652 #define PLL_NR_MAX (64)
 653 #define PLL_NO_MAX (16)
 654
 655 static int pll_clk_get_set(unsigned long fin_hz,unsigned long fout_hz,u32 *clk_nr,u32 *clk_nf,u32 *clk_no)
 656 {
 657         u32 nr,nf,no,nonr;
 658         u32 n;
 659         u32 YFfenzi;
 660         u32 YFfenmu;
 661         unsigned long fref,fvco,fout;
 662         u32 gcd_val=0;
 663
 664         CRU_PRINTK_DBG("pll_clk_get_set fin=%lu,fout=%lu\n",fin_hz,fout_hz);
 665         if(!fin_hz||!fout_hz||fout_hz==fin_hz)
 666                 return 0;
 667         gcd_val=clk_gcd(fin_hz,fout_hz);
 668         YFfenzi=fout_hz/gcd_val;
 669         YFfenmu=fin_hz/gcd_val;
 670
 671         for(n=1;;n++)
 672         {
 673                 nf=YFfenzi*n;
 674                 nonr=YFfenmu*n;
 675                 if(nf>PLL_NF_MAX||nonr>(PLL_NO_MAX*PLL_NR_MAX))
 676                  break;
 677                 for(no=1;no<=PLL_NO_MAX;no++)
 678                 {
 679                         if(!(no==1||!(no%2)))
 680                                 continue;
 681
 682                         if(nonr%no)
 683                                 continue;
 684                         nr=nonr/no;
 685
 686                         if(nr>PLL_NR_MAX)//PLL_NR_MAX
 687                                 continue;
 688
 689                         fref=fin_hz/nr;
 690                         if(fref<PLL_FREF_MIN||fref>PLL_FREF_MAX)
 691                                 continue;
 692
 693                         fvco=(fin_hz/nr)*nf;
 694                         if(fvco<PLL_FVCO_MIN||fvco>PLL_FVCO_MAX)
 695                                 continue;
 696                         fout=fvco/no;
 697                         if(fout<PLL_FOUT_MIN||fout>PLL_FOUT_MAX)
 698                                 continue;
 699                         *clk_nr=nr;
 700                         *clk_no=no;
 701                         *clk_nf=nf;
 702                         return 1;
 703
 704                 }
 705
 706         }
 707         return 0;
 708 }
 709
 710 static int pll_clk_mode(struct clk *clk, int on)
 711 {
 712         u8 pll_id=clk->pll->id;
 713         u32 nr=PLL_NR(cru_readl(PLL_CONS(pll_id,0)));
 714         u32 dly= (nr*500)/24+1;
 715         CRU_PRINTK_DBG("pll_mode %s(%d)",clk->name,on);
 716         if (on) {
 717                 cru_writel(PLL_PWR_ON|PLL_PWR_DN_W_MSK,PLL_CONS(pll_id,3));
 718                 rk30_clock_udelay(dly);
 719                 pll_wait_lock(pll_id);
 720                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 721         } else {
 722                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 723                 cru_writel(PLL_PWR_DN|PLL_PWR_DN_W_MSK, PLL_CONS(pll_id,3));
 724         }
 725         return 0;
 726 }
 727
 728 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 729 {
 730         struct _pll_data *pll_data=c->pll;
 731         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 732         struct pll_clk_set temp_clk_set;
 733         u32 clk_nr,clk_nf,clk_no;
 734
 735
 736         while(clk_set->rate)
 737         {
 738                 if (clk_set->rate == rate) {
 739                         break;
 740                 }
 741                 clk_set++;
 742         }
 743         if(clk_set->rate==rate)
 744         {
 745                 CRU_PRINTK_DBG("cpll get a rate\n");
 746                 pll_clk_set_rate(clk_set,pll_data->id);
 747
 748         }
 749         else
 750         {
 751                 CRU_PRINTK_DBG("cpll get auto calc a rate\n");
 752                 if(pll_clk_get_set(c->parent->rate,rate,&clk_nr,&clk_nf,&clk_no)==0)
 753                 {
 754                         pr_err("cpll auto set rate error\n");
 755                         return -ENOENT;
 756                 }
 757                 CRU_PRINTK_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n",clk_nr,clk_nf,clk_no);
 758                 temp_clk_set.pllcon0=PLL_CLKR_SET(clk_nr)|PLL_CLKOD_SET(clk_no);
 759                 temp_clk_set.pllcon1=PLL_CLKF_SET(clk_nf);
 760                 temp_clk_set.pllcon2=PLL_CLK_BWADJ_SET(clk_nf/2-1);
 761                 temp_clk_set.rst_dly=(clk_nr*500)/24+1;
 762                 pll_clk_set_rate(&temp_clk_set,pll_data->id);
 763
 764         }
 765         return 0;
 766 }
 767
 768
 769 /* ******************fixed input clk ***********************************************/
 770 static struct clk xin24m = {
 771         .name           = "xin24m",
 772         .rate           = 24 * MHZ,
 773         .flags          = RATE_FIXED,
 774 };
 775 static struct clk xin27m = {
 776         .name           = "xin27m",
 777         .rate           = 27 * MHZ,
 778         //CLK_GATE_XIN27M
 779         .flags          = RATE_FIXED,
 780
 781 };
 782 static struct clk clk_12m = {
 783         .name           = "clk_12m",
 784         .parent         =&xin24m,
 785         .rate           = 12 * MHZ,
 786         .flags          = RATE_FIXED,
 787 };
 788
 789 /************************************pll func***************************/
 790 static const struct apll_clk_set* arm_pll_clk_get_best_pll_set(unsigned long rate,
 791         struct apll_clk_set *tables)
 792 {
 793         const struct apll_clk_set *ps, *pt;
 794
 795         /* find the arm_pll we want. */
 796         ps = pt = tables;
 797         while (pt->rate) {
 798                 if (pt->rate == rate) {
 799                         ps = pt;
 800                         break;
 801                 }
 802                 // we are sorted, and ps->rate > pt->rate.
 803                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 804                         ps = pt;
 805                 if (pt->rate < rate)
 806                         break;
 807                 pt++;
 808         }
 809         //CRU_PRINTK_DBG("arm pll best rate=%lu\n",ps->rate);
 810         return ps;
 811 }
 812 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 813 {
 814         return arm_pll_clk_get_best_pll_set(rate,clk->pll->table)->rate;
 815 }
 816 #if 1
 817 struct arm_clks_div_set {
 818         u32 rate;
 819         u32     clksel0;
 820         u32     clksel1;
 821 };
 822
 823 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 824         { \
 825         .rate    =_mhz,\
 826         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 827         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 828         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 829         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 830         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 831 }
 832 struct arm_clks_div_set arm_clk_div_tlb[]={
 833         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 834         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 835         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 836         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 837         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
 838         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
 839         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
 840 };
 841 struct arm_clks_div_set * arm_clks_get_div(u32 rate)
 842 {
 843         int i=0;
 844         for(i=0;arm_clk_div_tlb[i].rate!=0;i++)
 845         {
 846                 if(arm_clk_div_tlb[i].rate>=rate)
 847                         return &arm_clk_div_tlb[i];
 848         }
 849         return NULL;
 850 }
 851
 852 #endif
 853
 854 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 855 {
 856         unsigned long flags;
 857         const struct apll_clk_set *ps;
 858         u32 pll_id=clk->pll->id;
 859         u32 temp_div;
 860         u32 old_aclk_div=0,new_aclk_div,gpll_arm_aclk_div;
 861         struct arm_clks_div_set *temp_clk_div;
 862         unsigned long arm_gpll_rate, arm_gpll_lpj;
 863
 864         ps = arm_pll_clk_get_best_pll_set(rate,(struct apll_clk_set *)clk->pll->table);
 865
 866         old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
 867         new_aclk_div=GET_CORE_ACLK_VAL(ps->clksel1&CORE_ACLK_MSK);
 868
 869         CRU_PRINTK_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
 870                 ps->rate,ps->pllcon0,ps->pllcon1,ps->pllcon2,ps->clksel0,ps->clksel1);
 871
 872         //rk30_l2_cache_latency(ps->rate/MHZ);
 873
 874         if(general_pll_clk.rate>clk->rate)
 875         {
 876                 temp_div=clk_get_freediv(clk->rate,general_pll_clk.rate,10);
 877         }
 878         else
 879         {
 880                 temp_div=1;
 881         }
 882         //sel gpll
 883         //cru_writel(CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 884
 885         arm_gpll_rate=general_pll_clk.rate/temp_div;
 886         arm_gpll_lpj = lpj_gpll / temp_div;
 887         temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
 888         if(!temp_clk_div)
 889                 temp_clk_div=&arm_clk_div_tlb[4];
 890
 891         gpll_arm_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
 892
 893         CRU_PRINTK_LOG("gpll_arm_rate=%lu,sel rate%u,sel0%x,sel1%x\n",arm_gpll_rate,temp_clk_div->rate,
 894                                         temp_clk_div->clksel0,temp_clk_div->clksel1);
 895
 896         local_irq_save(flags);
 897         //new div max first
 898         if(gpll_arm_aclk_div>=old_aclk_div)
 899         {
 900                 if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
 901                 {
 902                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 903                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 904                         cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
 905                                                                                                 CRU_CLKSELS_CON(0));
 906                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 907                 }
 908                 else
 909                 {
 910                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 911                         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
 912                                                                                 CRU_CLKSELS_CON(0));
 913                 }
 914         }
 915         // open gpu gpll path
 916         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 917         cru_writel(CORE_SEL_GPLL|CORE_SEL_PLL_W_MSK, CRU_CLKSELS_CON(0));
 918         loops_per_jiffy = arm_gpll_lpj;
 919         smp_wmb();
 920         //new div max late
 921         if(gpll_arm_aclk_div<old_aclk_div)
 922         {
 923                 if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
 924                 {
 925                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 926                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 927                         cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
 928                                                                                                 CRU_CLKSELS_CON(0));
 929                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 930                 }
 931                 else
 932                 {
 933                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 934                         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
 935                                                                                 CRU_CLKSELS_CON(0));
 936                 }
 937         }
 938
 939         /*if core src don't select gpll ,apll neet to enter slow mode */
 940         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 941
 942         //enter rest
 943         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 944         cru_writel(ps->pllcon0, PLL_CONS(pll_id,0));
 945         cru_writel(ps->pllcon1, PLL_CONS(pll_id,1));
 946         cru_writel(ps->pllcon2, PLL_CONS(pll_id,2));
 947
 948         rk30_clock_udelay(5);
 949
 950         //return form rest
 951         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 952
 953         //wating lock state
 954         ///rk30_clock_udelay(ps->rst_dly);//lcdc flash
 955
 956         pll_wait_lock(pll_id);
 957
 958         //return form slow
 959         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 960         //a/h/p clk sel
 961    if(new_aclk_div>=gpll_arm_aclk_div)
 962    {
 963                 if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
 964                 {
 965                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 966                         cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
 967                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 968                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 969                 }
 970                 else
 971                 {
 972                         cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
 973                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 974                 }
 975         }
 976
 977         //reparent to apll
 978         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_APLL, CRU_CLKSELS_CON(0));
 979         loops_per_jiffy = ps->lpj;
 980         smp_wmb();
 981
 982    if(new_aclk_div<gpll_arm_aclk_div)
 983    {
 984                 if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
 985                 {
 986                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 987                         cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
 988                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 989                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 990                 }
 991                 else
 992                 {
 993                         cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
 994                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 995                 }
 996         }
 997         //CRU_PRINTK_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
 998
 999         local_irq_restore(flags);
1000
1001         //gate gpll path
1002         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1003         , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1004
1005         CRU_PRINTK_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n",cru_readl(PLL_CONS(pll_id,0)),
1006                 cru_readl(PLL_CONS(pll_id,1)),cru_readl(PLL_CONS(pll_id,2)),
1007                 cru_readl(PLL_CONS(pll_id,3)),cru_readl(CRU_CLKSELS_CON(0)),
1008                 cru_readl(CRU_CLKSELS_CON(1)));
1009         return 0;
1010 }
1011
1012
1013 /************************************pll clocks***************************/
1014
1015 static const struct apll_clk_set apll_clks[] = {
1016         //rate, nr ,nf ,no,core_div,peri,axi,hclk,pclk,_ahb2apb
1017         //_APLL_SET_CLKS(1800, 1, 75, 1, 8, 41,  41,  81,21),
1018         //_APLL_SET_CLKS(1752, 1, 73, 1, 8, 41,  41,  81,21),
1019         //_APLL_SET_CLKS(1704, 1, 71, 1, 8, 41,  41,  81,21),
1020         //_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41,  41,  81,21),
1021         _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 21, 41, 21),
1022         _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 21, 41, 21),
1023         _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 21, 41, 21),
1024         _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 21, 41, 21),
1025         _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 21, 41, 21),
1026         _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 21, 41, 21),
1027         _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 21, 41, 21),
1028         _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 21, 41, 21),
1029         _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 21, 41, 21),
1030         _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 21, 41, 21),
1031         _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 21, 41, 21),
1032         _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 21, 41, 21),
1033         _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 21, 41, 21),
1034         _APLL_SET_CLKS(1008, 1, 42, 1, 8, 31, 21, 41, 21),
1035         _APLL_SET_CLKS(888,  1, 37, 1, 8, 31, 21, 41, 21),
1036         _APLL_SET_CLKS(816 , 1, 34, 1, 8, 31, 21, 41, 21),
1037         _APLL_SET_CLKS(792 , 1, 33, 1, 8, 31, 21, 41, 21),
1038         _APLL_SET_CLKS(696 , 1, 29, 1, 8, 31, 21, 41, 21),
1039         _APLL_SET_CLKS(600 , 1, 25, 1, 4, 31, 21, 41, 21),
1040         _APLL_SET_CLKS(504 , 1, 21, 1, 4, 21, 21, 41, 21),
1041         _APLL_SET_CLKS(408 , 1, 17, 1, 4, 21, 21, 41, 21),
1042         _APLL_SET_CLKS(312 , 1, 13, 1, 2, 21, 21, 21, 11),
1043         _APLL_SET_CLKS(252 , 1, 21, 2, 2, 21, 21, 21, 11),
1044         _APLL_SET_CLKS(216 , 1, 18, 2, 2, 21, 21, 21, 11),
1045         _APLL_SET_CLKS(126 , 1, 21, 4, 2, 21, 11, 11, 11),
1046         _APLL_SET_CLKS(48  , 1, 16, 8, 2, 11, 11, 11, 11),
1047         _APLL_SET_CLKS(0   , 1, 21, 4, 2, 21, 21, 41, 21),
1048
1049 };
1050 static struct _pll_data apll_data=SET_PLL_DATA(APLL_ID,(void *)apll_clks);
1051 static struct clk arm_pll_clk ={
1052         .name           = "arm_pll",
1053         .parent         = &xin24m,
1054         .mode = pll_clk_mode,
1055         .recalc         = plls_clk_recalc,
1056         .set_rate       = arm_pll_clk_set_rate,
1057         .round_rate     = arm_pll_clk_round_rate,
1058         .pll=&apll_data,
1059  };
1060
1061 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1062 {
1063         /* do nothing here */
1064         return 0;
1065 }
1066 static struct _pll_data dpll_data=SET_PLL_DATA(DPLL_ID,NULL);
1067 static struct clk ddr_pll_clk = {
1068         .name           = "ddr_pll",
1069         .parent         = &xin24m,
1070         .recalc         = plls_clk_recalc,
1071         .set_rate       = ddr_pll_clk_set_rate,
1072         .pll=&dpll_data,
1073 };
1074
1075 static const struct pll_clk_set cpll_clks[] = {
1076         _PLL_SET_CLKS(360000, 1,  15, 1),
1077         _PLL_SET_CLKS(408000, 1,  17, 1),
1078         _PLL_SET_CLKS(456000, 1,  19, 1),
1079         _PLL_SET_CLKS(504000, 1,  21, 1),
1080         _PLL_SET_CLKS(552000, 1,  23, 1),
1081         _PLL_SET_CLKS(600000, 1,  25, 1),
1082         _PLL_SET_CLKS(742500, 8,  495, 2),
1083         _PLL_SET_CLKS(798000, 4,  133, 1),
1084         _PLL_SET_CLKS(1188000,2,  99,   1),
1085         _PLL_SET_CLKS(     0, 4,  133, 1),
1086 };
1087 static struct _pll_data cpll_data=SET_PLL_DATA(CPLL_ID,(void *)cpll_clks);
1088 static struct clk codec_pll_clk = {
1089         .name           = "codec_pll",
1090         .parent         = &xin24m,
1091         .mode           = pll_clk_mode,
1092         .recalc         = plls_clk_recalc,
1093         .set_rate       = cpll_clk_set_rate,
1094         .pll= &cpll_data,
1095 };
1096
1097 static const struct pll_clk_set gpll_clks[] = {
1098         _PLL_SET_CLKS(148500,   4,      99,     4),
1099         _PLL_SET_CLKS(297000,   2,      99,     4),
1100         _PLL_SET_CLKS(300000,   1,      25,     2),
1101         _PLL_SET_CLKS(1188000,  2,      99,     1),
1102         _PLL_SET_CLKS(0,        0,       0,     0),
1103 };
1104 static struct _pll_data gpll_data=SET_PLL_DATA(GPLL_ID,(void *)gpll_clks);
1105 static struct clk general_pll_clk = {
1106         .name           = "general_pll",
1107         .parent         = &xin24m,
1108         .recalc         = plls_clk_recalc,
1109         .set_rate       = gpll_clk_set_rate,
1110         .pll= &gpll_data
1111 };
1112 /********************************clocks***********************************/
1113 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1114 {
1115         return 0;
1116 }
1117
1118 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
1119 static struct clk clk_ddr = {
1120         .name           = "ddr",
1121         .parent         = &ddr_pll_clk,
1122         .recalc         = clksel_recalc_shift,
1123         .set_rate       = ddr_clk_set_rate,
1124         .clksel_con     = CRU_CLKSELS_CON(26),
1125         //CRU_DIV_SET(0x3,0,4),
1126         //CRU_SRC_SET(1,8),
1127         //CRU_PARENTS_SET(clk_ddr_parents),
1128 };
1129 static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
1130 {
1131         int ret;
1132         //set arm pll div 1
1133         //set_cru_bits_w_msk(0,c->div_mask,c->div_shift,c->clksel_con);
1134
1135         ret = clk_set_rate_nolock(c->parent, rate);
1136         if (ret) {
1137                 CRU_PRINTK_ERR("Failed to change clk pll %s to %lu\n",c->name,rate);
1138                 return ret;
1139         }
1140         return 0;
1141 }
1142 static unsigned long arm_core_clk_get_rate(struct clk *c)
1143 {
1144         u32 div=(get_cru_bits(c->clksel_con,c->div_mask,c->div_shift)+1);
1145         //c->parent->rate=c->parent->recalc(c->parent);
1146         return c->parent->rate/div;
1147 }
1148 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1149 {
1150         u32 div=(get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1);
1151         return clk_round_rate_nolock(clk->parent,rate)/div;
1152 }
1153
1154 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1155 {
1156
1157         u32 temp_div;
1158         struct clk *old_prt;
1159
1160         if(clk->parent==new_prt)
1161                 return 0;
1162         if (unlikely(!clk->parents))
1163                 return -EINVAL;
1164         CRU_PRINTK_DBG("%s,reparent %s\n",clk->name,new_prt->name);
1165         //arm
1166         old_prt=clk->parent;
1167
1168         if(clk->parents[0]==new_prt)
1169         {
1170                 new_prt->set_rate(new_prt,300*MHZ);
1171                 set_cru_bits_w_msk(0,clk->div_mask,clk->div_shift,clk->clksel_con);
1172         }
1173         else if(clk->parents[1]==new_prt)
1174         {
1175
1176                 if(new_prt->rate>old_prt->rate)
1177                 {
1178                         temp_div=clk_get_freediv(old_prt->rate,new_prt->rate,clk->div_max);
1179                         set_cru_bits_w_msk(temp_div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
1180                 }
1181                 set_cru_bits_w_msk(1,clk->src_mask,clk->src_shift,clk->clksel_con);
1182                 new_prt->set_rate(new_prt,300*MHZ);
1183         }
1184         else
1185                 return -1;
1186
1187
1188         return 0;
1189
1190 }
1191
1192 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1193 {
1194         unsigned long flags;
1195         u32 pll_id=APLL_ID;
1196         u32 temp_div;
1197         u32 old_aclk_div=0,new_aclk_div;
1198         struct arm_clks_div_set *temp_clk_div;
1199         unsigned long arm_gpll_rate, arm_gpll_lpj;
1200         temp_div=clk_get_freediv(rate,c->parent->rate,c->div_max);
1201         arm_gpll_rate=c->parent->rate/temp_div;
1202
1203         temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
1204         if(!temp_clk_div)
1205                 temp_clk_div=&arm_clk_div_tlb[4];
1206
1207         old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1208         new_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
1209         if(c->rate>=rate)
1210         {
1211                 arm_gpll_lpj = lpj_gpll / temp_div;
1212                 set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
1213         }
1214
1215         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1216         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
1217                                                                 CRU_CLKSELS_CON(0));
1218         if((c->rate<rate))
1219         {
1220                 arm_gpll_lpj = lpj_gpll / temp_div;
1221                 set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
1222         }
1223         return 0;
1224 }
1225 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1226 {
1227         return c->parent->rate;
1228 }
1229
1230 static struct clk clk_cpu_gpll_path = {
1231         .name   =  "cpu_gpll_path",
1232         .parent =  &general_pll_clk,
1233         .recalc =  arm_core_gpll_clk_get_rate,
1234         .set_rate = core_gpll_clk_set_rate,
1235         CRU_DIV_SET(0x1f,0,32),
1236         CRU_GATE_MODE_SET(gate_mode,CLK_GATE_CPU_GPLL_PATH),
1237 };
1238
1239
1240 static struct clk *clk_cpu_parents[2] = {&arm_pll_clk,&clk_cpu_gpll_path};
1241
1242 static struct clk clk_cpu = {
1243         .name   =  "cpu",
1244         .parent =  &arm_pll_clk,
1245         .set_rate =     arm_core_clk_set_rate,
1246         .recalc =  arm_core_clk_get_rate,
1247         .round_rate     = core_clk_round_rate,
1248         .set_parent = core_clksel_set_parent,
1249         .clksel_con     = CRU_CLKSELS_CON(0),
1250         CRU_DIV_SET(0x1f,0,32),
1251         CRU_SRC_SET(1,8),
1252         CRU_PARENTS_SET(clk_cpu_parents),
1253 };
1254 static unsigned long aclk_cpu_recalc(struct clk *clk)
1255 {
1256         unsigned long rate;
1257         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
1258
1259         BUG_ON(div > 5);
1260         if (div >= 5)
1261                 div = 8;
1262         rate = clk->parent->rate / div;
1263         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1264
1265         return rate;
1266 };
1267 static struct clk core_periph = {
1268         .name           = "core_periph",
1269         .parent         = &clk_cpu,
1270         .recalc         = clksel_recalc_shift_2,
1271         .clksel_con     = CRU_CLKSELS_CON(0),
1272         CRU_DIV_SET(0x3,6,16),
1273 };
1274
1275 static struct clk aclk_cpu = {
1276         .name           = "aclk_cpu",
1277         .parent         = &clk_cpu,
1278         .recalc         = aclk_cpu_recalc,
1279         .clksel_con     = CRU_CLKSELS_CON(1),
1280         CRU_DIV_SET(0x7,0,8),
1281 };
1282
1283 static struct clk hclk_cpu = {
1284         .name           = "hclk_cpu",
1285         .parent         = &aclk_cpu,
1286         .recalc         = clksel_recalc_shift,
1287         //.set_rate     = clksel_set_rate_shift,
1288         .clksel_con     = CRU_CLKSELS_CON(1),
1289         CRU_DIV_SET(0x3,8,4),
1290
1291 };
1292
1293 static struct clk pclk_cpu = {
1294         .name           = "pclk_cpu",
1295         .parent         = &aclk_cpu,
1296         .recalc         = clksel_recalc_shift,
1297         //.set_rate     = clksel_set_rate_shift,
1298         .clksel_con     = CRU_CLKSELS_CON(1),
1299         CRU_DIV_SET(0x3,12,8),
1300 };
1301 static struct clk ahb2apb_cpu = {
1302         .name           = "ahb2apb",
1303         .parent         = &hclk_cpu,
1304         .recalc         = clksel_recalc_shift,
1305         .clksel_con     = CRU_CLKSELS_CON(1),
1306         CRU_DIV_SET(0x3,14,4),
1307 };
1308
1309
1310 static struct clk atclk_cpu = {
1311         .name           = "atclk_cpu",
1312         .parent         = &pclk_cpu,
1313 };
1314
1315 static struct clk *clk_i2s_div_parents[]={&general_pll_clk,&codec_pll_clk};
1316 static struct clk clk_i2s_pll = {
1317         .name           = "i2s_pll",
1318         .parent         = &general_pll_clk,
1319         .clksel_con     = CRU_CLKSELS_CON(2),
1320         CRU_SRC_SET(0x1,16),
1321         CRU_PARENTS_SET(clk_i2s_div_parents),
1322 };
1323
1324 static struct clk clk_i2s0_div = {
1325         .name           = "i2s0_div",
1326         .parent = &clk_i2s_pll,
1327         .mode           = gate_mode,
1328         .recalc         = clksel_recalc_div,
1329         .set_rate       = clksel_set_rate_freediv,
1330         .round_rate     =clksel_freediv_round_rate,
1331         .gate_idx       = CLK_GATE_I2S0,
1332         .clksel_con     = CRU_CLKSELS_CON(2),
1333         CRU_DIV_SET(0x7f,0,64),
1334 };
1335
1336 static struct clk clk_i2s1_div = {
1337         .name           = "i2s1_div",
1338         .parent = &clk_i2s_pll,
1339         .recalc         = clksel_recalc_div,
1340         .set_rate       = clksel_set_rate_freediv,
1341         .round_rate     =clksel_freediv_round_rate,
1342         .mode           = gate_mode,
1343         .gate_idx       = CLK_GATE_I2S1,
1344         .clksel_con     = CRU_CLKSELS_CON(3),
1345         CRU_DIV_SET(0x7f,0,64),
1346 };
1347
1348
1349 static struct clk clk_i2s2_div = {
1350         .name           = "i2s2_div",
1351         .parent = &clk_i2s_pll,
1352         .recalc         = clksel_recalc_div,
1353         .set_rate       = clksel_set_rate_freediv,
1354         .round_rate     =clksel_freediv_round_rate,
1355         .mode           = gate_mode,
1356         .gate_idx       = CLK_GATE_I2S2,
1357         .clksel_con     = CRU_CLKSELS_CON(4),
1358         CRU_DIV_SET(0x7f,0,64),
1359 };
1360 static struct clk clk_spdif_div = {
1361         .name           = "spdif_div",
1362         .parent = &clk_i2s_pll,
1363         .recalc         = clksel_recalc_div,
1364         .set_rate       = clksel_set_rate_freediv,
1365         .round_rate     =clksel_freediv_round_rate,
1366         .mode           = gate_mode,
1367         .gate_idx       = CLK_GATE_SPDIF,
1368         .clksel_con     = CRU_CLKSELS_CON(5),
1369         CRU_DIV_SET(0x7f,0,64),
1370 };
1371 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1372 {
1373         u32 numerator, denominator;
1374         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1375         //clk->parent->parent
1376         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1377                         &numerator,&denominator)==0)
1378         {
1379                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1380                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1381                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1382         }
1383         else
1384         {
1385                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1386                 return -ENOENT;
1387         }
1388         return 0;
1389 }
1390
1391
1392 static struct clk clk_i2s0_frac_div = {
1393         .name           = "i2s0_frac_div",
1394         .parent         = &clk_i2s0_div,
1395         .mode           = gate_mode,
1396         .gate_idx       = CLK_GATE_I2S0_FRAC,
1397         .recalc         = clksel_recalc_frac,
1398         .set_rate       = clk_i2s_fracdiv_set_rate,
1399         .clksel_con     = CRU_CLKSELS_CON(6),
1400 };
1401
1402 static struct clk clk_i2s1_frac_div = {
1403         .name           = "i2s1_frac_div",
1404         .parent         = &clk_i2s1_div,
1405         .mode           = gate_mode,
1406         .gate_idx       = CLK_GATE_I2S1_FRAC,
1407         .recalc         = clksel_recalc_frac,
1408         .set_rate       = clk_i2s_fracdiv_set_rate,
1409         .clksel_con     = CRU_CLKSELS_CON(7),
1410 };
1411
1412 static struct clk clk_i2s2_frac_div = {
1413         .name           = "i2s2_frac_div",
1414         .mode           = gate_mode,
1415         .gate_idx       = CLK_GATE_I2S2_FRAC,
1416         .parent         = &clk_i2s2_div,
1417         .recalc         = clksel_recalc_frac,
1418         .set_rate       = clk_i2s_fracdiv_set_rate,
1419         .clksel_con     = CRU_CLKSELS_CON(8),
1420 };
1421 static struct clk clk_spdif_frac_div = {
1422         .name           = "spdif_frac_div",
1423         .parent         = &clk_spdif_div,
1424         .mode           = gate_mode,
1425         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1426         .recalc         = clksel_recalc_frac,
1427         .set_rate       = clk_i2s_fracdiv_set_rate,
1428         .clksel_con     = CRU_CLKSELS_CON(9),
1429 };
1430
1431 #define I2S_SRC_DIV  (0x0)
1432 #define I2S_SRC_FRAC  (0x1)
1433 #define I2S_SRC_12M  (0x2)
1434
1435 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1436 {
1437         int ret = -EINVAL;
1438         struct clk *parent;
1439
1440         if (rate == clk->parents[I2S_SRC_12M]->rate){
1441                 parent = clk->parents[I2S_SRC_12M];
1442         }else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV],rate)==rate)
1443         {
1444                 parent = clk->parents[I2S_SRC_DIV];
1445         }
1446         else
1447         {
1448                 parent =clk->parents[I2S_SRC_FRAC];
1449         }
1450
1451         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1452                 clk->name,rate,parent->name,clk->parent->name);
1453
1454         if(parent!=clk->parents[I2S_SRC_12M])
1455         {
1456                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
1457                 if (ret)
1458                 {
1459                         CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
1460                         return ret;
1461                 }
1462         }
1463
1464         if (clk->parent != parent)
1465         {
1466                 ret = clk_set_parent_nolock(clk, parent);
1467                 if (ret)
1468                 {
1469                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1470                         return ret;
1471                 }
1472         }
1473
1474         return ret;
1475 };
1476
1477 static struct clk *clk_i2s0_parents[3]={&clk_i2s0_div,&clk_i2s0_frac_div,&clk_12m};
1478
1479 static struct clk clk_i2s0 = {
1480         .name           = "i2s0",
1481         .set_rate       = i2s_set_rate,
1482         .clksel_con     = CRU_CLKSELS_CON(2),
1483         CRU_SRC_SET(0x3,8),
1484         CRU_PARENTS_SET(clk_i2s0_parents),
1485 };
1486
1487 static struct clk *clk_i2s1_parents[3]={&clk_i2s1_div,&clk_i2s1_frac_div,&clk_12m};
1488
1489 static struct clk clk_i2s1 = {
1490         .name           = "i2s1",
1491         .set_rate       = i2s_set_rate,
1492         .clksel_con     = CRU_CLKSELS_CON(3),
1493         CRU_SRC_SET(0x3,8),
1494         CRU_PARENTS_SET(clk_i2s1_parents),
1495 };
1496
1497 static struct clk *clk_i2s2_parents[3]={&clk_i2s2_div,&clk_i2s2_frac_div,&clk_12m};
1498
1499 static struct clk clk_i2s2 = {
1500         .name           = "i2s2",
1501         .set_rate       = i2s_set_rate,
1502         .clksel_con     = CRU_CLKSELS_CON(4),
1503         CRU_SRC_SET(0x3,8),
1504         CRU_PARENTS_SET(clk_i2s2_parents),
1505 };
1506
1507 static struct clk *clk_spdif_parents[3]={&clk_spdif_div,&clk_spdif_frac_div,&clk_12m};
1508
1509 static struct clk clk_spdif = {
1510         .name           = "spdif",
1511         .parent         = &clk_spdif_frac_div,
1512         .set_rate       = i2s_set_rate,
1513         .clksel_con = CRU_CLKSELS_CON(5),
1514         CRU_SRC_SET(0x3,8),
1515         CRU_PARENTS_SET(clk_spdif_parents),
1516 };
1517
1518 static struct clk *aclk_periph_parents[2]={&general_pll_clk,&codec_pll_clk};
1519
1520 static struct clk aclk_periph = {
1521         .name           = "aclk_periph",
1522         .parent         = &general_pll_clk,
1523         .mode           = gate_mode,
1524         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1525         .recalc         = clksel_recalc_div,
1526         .set_rate       = clksel_set_rate_freediv,
1527         .clksel_con     = CRU_CLKSELS_CON(10),
1528         CRU_DIV_SET(0x1f,0,32),
1529         CRU_SRC_SET(1,15),
1530         CRU_PARENTS_SET(aclk_periph_parents),
1531 };
1532 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1533
1534 static struct clk pclk_periph = {
1535         .name           = "pclk_periph",
1536         .parent         = &aclk_periph,
1537         .mode           = gate_mode,
1538         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1539         .recalc         = clksel_recalc_shift,
1540         .set_rate       = clksel_set_rate_shift,
1541         .clksel_con     = CRU_CLKSELS_CON(10),
1542         CRU_DIV_SET(0x3,12,8),
1543 };
1544
1545 static struct clk hclk_periph = {
1546         .name           = "hclk_periph",
1547         .parent         = &aclk_periph,
1548         .mode           = gate_mode,
1549         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1550         .recalc         = clksel_recalc_shift,
1551         .set_rate       = clksel_set_rate_shift,
1552         .clksel_con = CRU_CLKSELS_CON(10),
1553         CRU_DIV_SET(0x3,8,4),
1554 };
1555
1556 static struct clk clk_spi0 = {
1557         .name           = "spi0",
1558         .parent         = &pclk_periph,
1559         .mode           = gate_mode,
1560         .recalc         = clksel_recalc_div,
1561         .set_rate       = clksel_set_rate_freediv,
1562         .gate_idx       = CLK_GATE_SPI0,
1563         .clksel_con     = CRU_CLKSELS_CON(25),
1564         CRU_DIV_SET(0x7f,0,128),
1565 };
1566
1567 static struct clk clk_spi1 = {
1568         .name           = "spi1",
1569         .parent         = &pclk_periph,
1570         .mode           = gate_mode,
1571         .recalc         = clksel_recalc_div,
1572         .set_rate       = clksel_set_rate_freediv,
1573         .gate_idx       = CLK_GATE_SPI1,
1574         .clksel_con     = CRU_CLKSELS_CON(25),
1575         CRU_DIV_SET(0x7f,8,128),
1576 };
1577
1578 static struct clk clk_saradc = {
1579         .name           = "saradc",
1580         .parent         = &xin24m,
1581         .mode           = gate_mode,
1582         .recalc         = clksel_recalc_div,
1583         .set_rate       = clksel_set_rate_freediv,
1584         .gate_idx       =  CLK_GATE_SARADC,
1585         .clksel_con     =CRU_CLKSELS_CON(24),
1586         CRU_DIV_SET(0xff,8,256),
1587 };
1588 static struct clk clk_tsadc = {
1589         .name           = "tsadc",
1590         .parent         = &xin24m,
1591         .mode           = gate_mode,
1592         .recalc         = clksel_recalc_div,
1593         .set_rate       = clksel_set_rate_freediv,
1594         .gate_idx       = CLK_GATE_TSADC,
1595         .clksel_con =CRU_CLKSELS_CON(34),
1596         CRU_DIV_SET(0xffff,0,65536),
1597 };
1598 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1599 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1600
1601
1602 GATE_CLK(smc, pclk_periph, SMC);//smc
1603
1604 static struct clk clk_sdmmc = {
1605         .name           = "sdmmc",
1606         .parent         = &hclk_periph,
1607         .mode           = gate_mode,
1608         .recalc         = clksel_recalc_div,
1609         .set_rate       = clksel_set_rate_freediv,
1610         .gate_idx       = CLK_GATE_MMC0,
1611         .clksel_con =CRU_CLKSELS_CON(11),
1612         CRU_DIV_SET(0x3f,0,64),
1613 };
1614
1615 static struct clk clk_sdio = {
1616         .name           = "sdio",
1617         .parent         = &hclk_periph,
1618         .mode           = gate_mode,
1619         .recalc         = clksel_recalc_div,
1620         .set_rate       = clksel_set_rate_freediv,
1621         .gate_idx       = CLK_GATE_SDIO,
1622         .clksel_con =CRU_CLKSELS_CON(12),
1623         CRU_DIV_SET(0x3f,0,64),
1624
1625 };
1626
1627 static struct clk clk_emmc = {
1628         .name           = "emmc",
1629         .parent         = &hclk_periph,
1630         .mode           = gate_mode,
1631         .recalc         = clksel_recalc_div,
1632         .set_rate       = clksel_set_rate_freediv,
1633         .gate_idx       = CLK_GATE_EMMC,
1634         .clksel_con =CRU_CLKSELS_CON(12),
1635         CRU_DIV_SET(0x3f,8,64),
1636 };
1637
1638 static struct clk *clk_uart_src_parents[2]={&general_pll_clk,&codec_pll_clk};
1639 static struct clk clk_uart_pll = {
1640         .name           = "uart_pll",
1641         .parent         = &general_pll_clk,
1642         .clksel_con =CRU_CLKSELS_CON(12),
1643         CRU_SRC_SET(0x1,15),
1644         CRU_PARENTS_SET(clk_uart_src_parents),
1645 };
1646 static struct clk clk_uart0_div = {
1647         .name           = "uart0_div",
1648         .parent         = &clk_uart_pll,
1649         .mode           = gate_mode,
1650         .gate_idx       = CLK_GATE_UART0,
1651         .recalc         = clksel_recalc_div,
1652         .set_rate       = clksel_set_rate_freediv,
1653         .round_rate     =clksel_freediv_round_rate,
1654         .clksel_con     = CRU_CLKSELS_CON(13),
1655         CRU_DIV_SET(0x7f,0,64),
1656 };
1657 static struct clk clk_uart1_div = {
1658         .name           = "uart1_div",
1659         .parent         = &clk_uart_pll,
1660         .mode           = gate_mode,
1661         .gate_idx       = CLK_GATE_UART1,
1662         .recalc         = clksel_recalc_div,
1663         .round_rate     =clksel_freediv_round_rate,
1664         .set_rate       = clksel_set_rate_freediv,
1665         .clksel_con     = CRU_CLKSELS_CON(14),
1666         CRU_DIV_SET(0x7f,0,64),
1667 };
1668
1669 static struct clk clk_uart2_div = {
1670         .name           = "uart2_div",
1671         .parent         = &clk_uart_pll,
1672         .mode           = gate_mode,
1673         .gate_idx       = CLK_GATE_UART2,
1674         .recalc         = clksel_recalc_div,
1675         .round_rate     =clksel_freediv_round_rate,
1676         .set_rate       = clksel_set_rate_freediv,
1677         .clksel_con     = CRU_CLKSELS_CON(15),
1678         CRU_DIV_SET(0x7f,0,64),
1679 };
1680
1681 static struct clk clk_uart3_div = {
1682         .name           = "uart3_div",
1683         .parent         = &clk_uart_pll,
1684         .mode           = gate_mode,
1685         .gate_idx       = CLK_GATE_UART3,
1686         .recalc         = clksel_recalc_div,
1687         .round_rate     =clksel_freediv_round_rate,
1688         .set_rate       = clksel_set_rate_freediv,
1689         .clksel_con     = CRU_CLKSELS_CON(16),
1690         CRU_DIV_SET(0x7f,0,64),
1691 };
1692 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1693 {
1694         u32 numerator, denominator;
1695         //clk_uart0_div->clk_uart_pll->gpll/cpll
1696         //clk->parent->parent
1697         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1698                         &numerator,&denominator)==0)
1699         {
1700                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1701
1702                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1703
1704                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1705         }
1706         else
1707         {
1708                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1709                 return -ENOENT;
1710         }
1711         return 0;
1712 }
1713
1714 static struct clk clk_uart0_frac_div = {
1715         .name           = "uart0_frac_div",
1716         .parent         = &clk_uart0_div,
1717         .mode           = gate_mode,
1718         .recalc         = clksel_recalc_frac,
1719         .set_rate       = clk_uart_fracdiv_set_rate,
1720         .gate_idx       = CLK_GATE_FRAC_UART0,
1721         .clksel_con     = CRU_CLKSELS_CON(17),
1722 };
1723 static struct clk clk_uart1_frac_div = {
1724         .name           = "uart1_frac_div",
1725         .parent         = &clk_uart1_div,
1726         .mode           = gate_mode,
1727         .recalc         = clksel_recalc_frac,
1728         .set_rate       = clk_uart_fracdiv_set_rate,
1729         .gate_idx       = CLK_GATE_FRAC_UART1,
1730         .clksel_con     = CRU_CLKSELS_CON(18),
1731 };
1732 static struct clk clk_uart2_frac_div = {
1733         .name           = "uart2_frac_div",
1734         .mode           = gate_mode,
1735         .parent         = &clk_uart2_div,
1736         .recalc         = clksel_recalc_frac,
1737         .set_rate       = clk_uart_fracdiv_set_rate,
1738         .gate_idx       = CLK_GATE_FRAC_UART2,
1739         .clksel_con     = CRU_CLKSELS_CON(19),
1740 };
1741 static struct clk clk_uart3_frac_div = {
1742         .name           = "uart3_frac_div",
1743         .parent         = &clk_uart3_div,
1744         .mode           = gate_mode,
1745         .recalc         = clksel_recalc_frac,
1746         .set_rate       = clk_uart_fracdiv_set_rate,
1747         .gate_idx       = CLK_GATE_FRAC_UART3,
1748         .clksel_con     = CRU_CLKSELS_CON(20),
1749 };
1750
1751
1752 #define UART_SRC_DIV 0
1753 #define UART_SRC_FRAC 1
1754 #define UART_SRC_24M 2
1755
1756 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1757 {
1758         int ret = 0;
1759         struct clk *parent;
1760
1761         if(rate==clk->parents[UART_SRC_24M]->rate)//24m
1762         {
1763                 parent = clk->parents[UART_SRC_24M];
1764         }
1765         else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate)==rate)
1766         {
1767                 parent = clk->parents[UART_SRC_DIV];
1768         }
1769         else
1770         {
1771                 parent = clk->parents[UART_SRC_FRAC];
1772         }
1773
1774
1775
1776         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1777                 clk->name,rate,parent->name,clk->parent->name);
1778
1779
1780         if(parent!=clk->parents[UART_SRC_24M])
1781         {
1782                 ret = clk_set_rate_nolock(parent,rate);
1783                 if (ret)
1784                 {
1785                         CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
1786                         return ret;
1787                 }
1788         }
1789
1790         if (clk->parent != parent)
1791         {
1792                 ret = clk_set_parent_nolock(clk, parent);
1793                 if (ret)
1794                 {
1795                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1796                         return ret;
1797                 }
1798         }
1799
1800
1801         return ret;
1802 }
1803
1804
1805 static struct clk *clk_uart0_parents[3]={&clk_uart0_div,&clk_uart0_frac_div,&xin24m};
1806 static struct clk clk_uart0 = {
1807         .name           = "uart0",
1808         .set_rate       = clk_uart_set_rate,
1809         .clksel_con     = CRU_CLKSELS_CON(13),
1810         CRU_SRC_SET(0x3,8),
1811         CRU_PARENTS_SET(clk_uart0_parents),
1812 };
1813
1814 static struct clk *clk_uart1_parents[3]={&clk_uart1_div,&clk_uart1_frac_div,&xin24m};
1815 static struct clk clk_uart1 = {
1816         .name           = "uart1",
1817         .set_rate       = clk_uart_set_rate,
1818         .clksel_con     = CRU_CLKSELS_CON(14),
1819         CRU_SRC_SET(0x3,8),
1820         CRU_PARENTS_SET(clk_uart1_parents),
1821 };
1822
1823 static struct clk *clk_uart2_parents[3]={&clk_uart2_div,&clk_uart2_frac_div,&xin24m};
1824 static struct clk clk_uart2 = {
1825         .name           = "uart2",
1826         .set_rate       = clk_uart_set_rate,
1827         .clksel_con     = CRU_CLKSELS_CON(15),
1828         CRU_SRC_SET(0x3,8),
1829         CRU_PARENTS_SET(clk_uart2_parents),
1830 };
1831 static struct clk *clk_uart3_parents[3]={&clk_uart3_div,&clk_uart3_frac_div,&xin24m};
1832 static struct clk clk_uart3 = {
1833         .name           = "uart3",
1834         .set_rate       = clk_uart_set_rate,
1835         .clksel_con     = CRU_CLKSELS_CON(16),
1836         CRU_SRC_SET(0x3,8),
1837         CRU_PARENTS_SET(clk_uart3_parents),
1838 };
1839
1840 GATE_CLK(timer0, xin24m, TIMER0);
1841 GATE_CLK(timer1, xin24m, TIMER1);
1842 GATE_CLK(timer2, xin24m, TIMER2);
1843
1844 static struct clk rmii_clkin = {
1845         .name           = "rmii_clkin",
1846 };
1847 static struct clk *clk_mac_ref_div_parents[2]={&general_pll_clk,&ddr_pll_clk};
1848 static struct clk clk_mac_pll_div = {
1849         .name           = "mac_pll_div",
1850         .parent         = &ddr_pll_clk,
1851         .mode           = gate_mode,
1852         .gate_idx       = CLK_GATE_MAC,
1853         .recalc         = clksel_recalc_div,
1854         .set_rate       =clksel_set_rate_freediv,
1855         //.set_rate     = clksel_set_rate_freediv,
1856         .clksel_con     =CRU_CLKSELS_CON(21),
1857         CRU_DIV_SET(0x1f,8,32),
1858         CRU_SRC_SET(0x1,0),
1859         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1860 };
1861
1862 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1863 {
1864
1865         if(clk->parent==clk->parents[1])
1866         {
1867                 CRU_PRINTK_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1868                 return -ENOENT;
1869         }
1870         else if(clk->parent==clk->parents[0])
1871         {
1872         return clk_set_rate_nolock(clk->parents[0],rate);
1873         }
1874         return -ENOENT;
1875 }
1876
1877 static struct clk *clk_mac_ref_parents[2]={&clk_mac_pll_div,&rmii_clkin};
1878
1879 static struct clk clk_mac_ref = {
1880         .name           = "mac_ref",
1881         .parent         = &clk_mac_pll_div,
1882         .set_rate       = clksel_mac_ref_set_rate,
1883         .clksel_con =CRU_CLKSELS_CON(21),
1884         CRU_SRC_SET(0x1,4),
1885         CRU_PARENTS_SET(clk_mac_ref_parents),
1886 };
1887
1888 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1889 {
1890         return clk_set_parent_nolock(clk->parent,parent);
1891 }
1892
1893 static struct clk clk_mii_tx = {
1894         .name           = "mii_tx",
1895         .parent         = &clk_mac_ref,
1896         //.set_parent   = clk_set_mii_tx_parent,
1897         .mode           = gate_mode,
1898         .gate_idx       = CLK_GATE_MAC_LBTEST,//???
1899 };
1900
1901 static struct clk *clk_hsadc_pll_parents[2]={&general_pll_clk,&codec_pll_clk};
1902 static struct clk clk_hsadc_pll_div = {
1903         .name           = "hsadc_pll_div",
1904         .parent         = &general_pll_clk,
1905         .mode           = gate_mode,
1906         .gate_idx       = CLK_GATE_SARADC,
1907         .recalc         = clksel_recalc_div,
1908         .round_rate     =clk_freediv_round_autosel_parents_rate,
1909         .set_rate       = clkset_rate_freediv_autosel_parents,
1910         //.round_rate =clksel_freediv_round_rate,
1911         //.set_rate     = clksel_set_rate_freediv,
1912         .clksel_con =CRU_CLKSELS_CON(22),
1913         CRU_DIV_SET(0xff,8,256),
1914         CRU_SRC_SET(0x1,0),
1915         CRU_PARENTS_SET(clk_hsadc_pll_parents),
1916 };
1917
1918 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
1919 {
1920         u32 numerator, denominator;
1921         //        clk_hsadc_pll_div->gpll/cpll
1922         //clk->parent->parent
1923         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1924                         &numerator,&denominator)==0)
1925         {
1926                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1927
1928                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1929
1930                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1931         }
1932         else
1933         {
1934                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1935                 return -ENOENT;
1936         }
1937         return 0;
1938 }
1939 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
1940 {
1941         u32 numerator, denominator;
1942         u32 i,ret=0;
1943         //        clk_hsadc_pll_div->gpll/cpll
1944         //clk->parent->parent
1945         for(i=0;i<2;i++)
1946         {
1947                 if(frac_div_get_seting(rate,clk->parent->parents[i]->rate,
1948                         &numerator,&denominator)==0)
1949                         break;
1950         }
1951         if(i>=2)
1952                 return -ENOENT;
1953
1954         if(clk->parent->parent!=clk->parent->parents[i])
1955                 ret=clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
1956         if(ret==0)
1957         {
1958                 clk_set_rate_nolock(clk->parent,clk->parent->parents[i]->rate);//PLL:DIV 1:
1959
1960                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1961
1962                 CRU_PRINTK_DBG("clk_frac_div %s, rate=%lu\n",clk->name,rate);
1963         }
1964         else
1965         {
1966                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1967                 return -ENOENT;
1968         }
1969         return 0;
1970 }
1971
1972 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
1973 {
1974         u32 numerator, denominator;
1975
1976         CRU_PRINTK_ERR("clk_hsadc_fracdiv_round_rate\n");
1977         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1978                         &numerator,&denominator)==0)
1979                 return rate;
1980
1981         return 0;
1982 }
1983 static struct clk clk_hsadc_frac_div = {
1984         .name           = "hsadc_frac_div",
1985         .parent         = &clk_hsadc_pll_div,
1986         .mode           = gate_mode,
1987         .recalc         = clksel_recalc_frac,
1988         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
1989         .round_rate     =clk_hsadc_fracdiv_round_rate,
1990         .gate_idx       = CLK_GATE_HSADC_FRAC,
1991         .clksel_con     = CRU_CLKSELS_CON(23),
1992 };
1993
1994 #define HSADC_SRC_DIV 0x0
1995 #define HSADC_SRC_FRAC 0x1
1996 #define HSADC_SRC_EXT 0x2
1997 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
1998 {
1999         int ret = -EINVAL;
2000         struct clk *parent;
2001
2002         if(clk->parent == clk->parents[HSADC_SRC_EXT]){
2003                 CRU_PRINTK_DBG("hsadc clk is form ext\n");
2004                 return 0;
2005         }
2006         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV],rate)==rate)
2007         {
2008                 parent =clk->parents[HSADC_SRC_DIV];
2009         }
2010         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC],rate)==rate)
2011         {
2012                 parent = clk->parents[HSADC_SRC_FRAC];
2013         }
2014         else
2015                 parent =clk->parents[HSADC_SRC_DIV];
2016
2017         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
2018                 clk->name,rate,parent->name,clk->parent->name);
2019
2020         ret = clk_set_rate_nolock(parent,rate);
2021         if (ret)
2022         {
2023                 CRU_PRINTK_ERR("%s set rate%lu err\n",clk->name,rate);
2024                 return ret;
2025         }
2026         if (clk->parent != parent)
2027         {
2028                 ret = clk_set_parent_nolock(clk, parent);
2029                 if (ret)
2030                 {
2031                         CRU_PRINTK_ERR("%s can't get rate%lu,reparent err\n",clk->name,rate);
2032                         return ret;
2033                 }
2034         }
2035         return ret;
2036 }
2037
2038 static struct clk clk_hsadc_ext = {
2039         .name           = "hsadc_ext",
2040 };
2041
2042 static struct clk *clk_hsadc_parents[3]={&clk_hsadc_pll_div,&clk_hsadc_frac_div,&clk_hsadc_ext};
2043 static struct clk clk_hsadc = {
2044         .name           = "hsadc",
2045         .parent         = &clk_hsadc_pll_div,
2046         .set_rate       = clk_hsadc_set_rate,
2047         .clksel_con     = CRU_CLKSELS_CON(22),
2048         CRU_SRC_SET(0x3,4),
2049         CRU_PARENTS_SET(clk_hsadc_parents),
2050 };
2051
2052 static struct clk *dclk_lcdc_div_parents[]={&codec_pll_clk,&general_pll_clk};
2053 static struct clk dclk_lcdc0_div = {
2054         .name           = "dclk_lcdc0_div",
2055         .parent         = &general_pll_clk,
2056         .recalc         = clksel_recalc_div,
2057         .set_rate       = clkset_rate_freediv_autosel_parents,
2058         .clksel_con     = CRU_CLKSELS_CON(27),
2059         CRU_DIV_SET(0xff,8,256),
2060         CRU_SRC_SET(0x1,0),
2061         CRU_PARENTS_SET(dclk_lcdc_div_parents),
2062 };
2063
2064 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
2065 {
2066         u32 div,old_div;
2067         int i;
2068         unsigned long new_rate;
2069         int ret=0;
2070
2071         if(clk->rate==rate)
2072                 return 0;
2073         for(i=0;i<2;i++)
2074         {
2075                 div=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
2076                 new_rate= clk->parents[i]->rate/div;
2077                 if((rate==new_rate)&&!(clk->parents[i]->rate%div))
2078                 {
2079                         break;
2080                 }
2081         }
2082         if(i>=2)
2083         {
2084                 CRU_PRINTK_ERR("%s can't set fixed rate%lu\n",clk->name,rate);
2085                 return -1;
2086         }
2087
2088         //CRU_PRINTK_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
2089
2090         old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
2091                                                                                 clk->div_shift,clk->div_mask)+1;
2092         if(div>old_div)
2093                 set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
2094
2095         if(clk->parents[i]!=clk->parent)
2096         {
2097                 ret=clk_set_parent_nolock(clk,clk->parents[i]);
2098         }
2099
2100         if (ret)
2101         {
2102                 CRU_PRINTK_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
2103                         clk->name,rate,clk->parents[i]->name,clk->parent->name);
2104                 return ret;
2105         }
2106         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
2107         return 0;
2108 }
2109 //hdmi
2110 static struct clk dclk_lcdc1_div = {
2111         .name           = "dclk_lcdc1_div",
2112         .parent         = &general_pll_clk,
2113         .recalc         = clksel_recalc_div,
2114         .set_rate       = clksel_set_rate_hdmi,//clk_freediv_autosel_parents_set_fixed_rate
2115         .clksel_con     = CRU_CLKSELS_CON(28),
2116         CRU_DIV_SET(0xff,8,256),
2117         CRU_SRC_SET(0x1,0),
2118         CRU_PARENTS_SET(dclk_lcdc_div_parents),
2119 };
2120
2121 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
2122 {
2123         int ret = 0;
2124         struct clk *parent;
2125
2126         if (rate == 27 * MHZ&&(rk30_clock_flags&CLK_FLG_EXT_27MHZ)) {
2127                 parent =clk->parents[1];
2128                 //CRU_PRINTK_DBG(" %s from=%s\n",clk->name,parent->name);
2129         } else {
2130                 parent=clk->parents[0];
2131         }
2132         //CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
2133                         //clk->name,rate,parent->name,clk->parent->name);
2134
2135         if(parent!=clk->parents[1])
2136         {
2137                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
2138                 if (ret)
2139                 {
2140                         CRU_PRINTK_DBG("%s set rate=%lu err\n",clk->name,rate);
2141                         return ret;
2142                 }
2143         }
2144         if (clk->parent != parent)
2145         {
2146                 ret = clk_set_parent_nolock(clk, parent);
2147                 if (ret)
2148                 {
2149                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
2150                         return ret;
2151                 }
2152         }
2153         return ret;
2154 }
2155
2156 static struct clk *dclk_lcdc0_parents[2]={&dclk_lcdc0_div,&xin27m};
2157 static struct clk dclk_lcdc0 = {
2158         .name           = "dclk_lcdc0",
2159         .mode           = gate_mode,
2160         .set_rate       = dclk_lcdc_set_rate,
2161         .gate_idx       = CLK_GATE_DCLK_LCDC0,
2162         .clksel_con     = CRU_CLKSELS_CON(27),
2163         CRU_SRC_SET(0x1,4),
2164         CRU_PARENTS_SET(dclk_lcdc0_parents),
2165 };
2166
2167 static struct clk *dclk_lcdc1_parents[2]={&dclk_lcdc1_div,&xin27m};
2168 static struct clk dclk_lcdc1 = {
2169         .name           = "dclk_lcdc1",
2170         .mode           = gate_mode,
2171         .set_rate       = dclk_lcdc_set_rate,
2172         .gate_idx       = CLK_GATE_DCLK_LCDC1,
2173         .clksel_con     = CRU_CLKSELS_CON(28),
2174         CRU_SRC_SET(0x1,4),
2175         CRU_PARENTS_SET(dclk_lcdc1_parents),
2176 };
2177
2178 static struct clk *cifout_sel_pll_parents[2]={&codec_pll_clk,&general_pll_clk};
2179 static struct clk cif_out_pll = {
2180         .name           = "cif_out_pll",
2181         .parent         = &general_pll_clk,
2182         .clksel_con     = CRU_CLKSELS_CON(29),
2183         CRU_SRC_SET(0x1,0),
2184         CRU_PARENTS_SET(cifout_sel_pll_parents),
2185 };
2186
2187 static struct clk cif0_out_div = {
2188         .name           = "cif0_out_div",
2189         .parent         = &cif_out_pll,
2190         .mode           = gate_mode,
2191         .recalc         = clksel_recalc_div,
2192         .set_rate       = clksel_set_rate_freediv,
2193         .gate_idx       =CLK_GATE_CIF0_OUT,
2194         .clksel_con     = CRU_CLKSELS_CON(29),
2195         CRU_DIV_SET(0x1f,1,32),
2196 };
2197
2198 static struct clk cif1_out_div = {
2199         .name           = "cif1_out_div",
2200         .parent         = &cif_out_pll,
2201         .mode           = gate_mode,
2202         .recalc         = clksel_recalc_div,
2203         .set_rate       = clksel_set_rate_freediv,
2204         .gate_idx       =       CLK_GATE_CIF1_OUT,
2205         .clksel_con     = CRU_CLKSELS_CON(29),
2206         CRU_DIV_SET(0x1f,8,32),
2207 };
2208
2209
2210 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
2211 {
2212         int ret = 0;
2213         struct clk *parent;
2214
2215         if (rate == 24 * MHZ) {
2216                 parent =clk->parents[1];
2217         } else {
2218                 parent=clk->parents[0];
2219                 ret = clk_set_rate_nolock(parent, rate);
2220                 if (ret)
2221                         return ret;
2222         }
2223         if (clk->parent != parent)
2224                 ret = clk_set_parent_nolock(clk, parent);
2225
2226         return ret;
2227 }
2228
2229 static struct clk *cif0_out_parents[2]={&cif0_out_div,&xin24m};
2230 static struct clk cif0_out = {
2231         .name           = "cif0_out",
2232         .parent         = &cif0_out_div,
2233         .set_rate       = cif_out_set_rate,
2234         .clksel_con     = CRU_CLKSELS_CON(29),
2235         CRU_SRC_SET(0x1,7),
2236         CRU_PARENTS_SET(cif0_out_parents),
2237 };
2238 static struct clk *cif1_out_parents[2]={&cif1_out_div,&xin24m};
2239
2240 static struct clk cif1_out = {
2241         .name           = "cif1_out",
2242         .parent         = &cif1_out_div,
2243         .set_rate       = cif_out_set_rate,
2244         .clksel_con     = CRU_CLKSELS_CON(29),
2245         CRU_SRC_SET(0x1,15),
2246         CRU_PARENTS_SET(cif1_out_parents),
2247 };
2248
2249 static struct clk pclkin_cif0 = {
2250         .name           = "pclkin_cif0",
2251         .mode           = gate_mode,
2252         .gate_idx       =CLK_GATE_PCLKIN_CIF0,
2253 };
2254
2255 static struct clk inv_cif0 = {
2256         .name           = "inv_cif0",
2257         .parent         = &pclkin_cif0,
2258 };
2259
2260 static struct clk *cif0_in_parents[2]={&pclkin_cif0,&inv_cif0};
2261 static struct clk cif0_in = {
2262         .name           = "cif0_in",
2263         .parent         = &pclkin_cif0,
2264         .clksel_con     = CRU_CLKSELS_CON(30),
2265         CRU_SRC_SET(0x1,8),
2266         CRU_PARENTS_SET(cif0_in_parents),
2267 };
2268
2269 static struct clk pclkin_cif1 = {
2270         .name           = "pclkin_cif1",
2271         .mode           = gate_mode,
2272         .gate_idx       =CLK_GATE_PCLKIN_CIF1,
2273 };
2274
2275 static struct clk inv_cif1 = {
2276         .name           = "inv_cif1",
2277         .parent         = &pclkin_cif1,
2278 };
2279 static struct clk *cif1_in_parents[2]={&pclkin_cif1,&inv_cif1};
2280
2281 static struct clk cif1_in = {
2282         .name           = "cif1_in",
2283         .parent         = &pclkin_cif1,
2284         .clksel_con     = CRU_CLKSELS_CON(30),
2285         CRU_SRC_SET(0x1,12),
2286         CRU_PARENTS_SET(cif1_in_parents),
2287 };
2288
2289 static struct clk *aclk_lcdc0_ipp_parents[]={&codec_pll_clk,&general_pll_clk};
2290
2291 static struct clk aclk_lcdc0_ipp_parent = {
2292         .name           = "aclk_lcdc0_ipp_parent",
2293         .parent         = &codec_pll_clk,
2294         .mode           = gate_mode,
2295         .recalc         = clksel_recalc_div,
2296         .set_rate       = clkset_rate_freediv_autosel_parents,
2297         //.set_rate     = clksel_set_rate_freediv,
2298         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
2299         .clksel_con     = CRU_CLKSELS_CON(31),
2300         CRU_DIV_SET(0x1f,0,32),
2301         CRU_SRC_SET(0x1,7),
2302         CRU_PARENTS_SET(aclk_lcdc0_ipp_parents),
2303 };
2304
2305 static struct clk *aclk_lcdc1_rga_parents[]={&codec_pll_clk,&general_pll_clk};
2306
2307 static struct clk aclk_lcdc1_rga_parent = {
2308         .name           = "aclk_lcdc1_rga_parent",
2309         .parent         = &codec_pll_clk,
2310         .mode           = gate_mode,
2311         .recalc         = clksel_recalc_div,
2312         .set_rate       = clkset_rate_freediv_autosel_parents,
2313         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
2314         .clksel_con     = CRU_CLKSELS_CON(31),
2315         CRU_DIV_SET(0x1f,8,32),
2316         CRU_SRC_SET(0x1,15),
2317         CRU_PARENTS_SET(aclk_lcdc1_rga_parents),
2318 };
2319
2320
2321 //for free div
2322 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
2323 {
2324         unsigned long rate = clk->parent->rate / 4;
2325         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
2326         return rate;
2327 }
2328
2329 static struct clk *aclk_vepu_parents[2]={&codec_pll_clk,&general_pll_clk};
2330
2331 static struct clk aclk_vepu = {
2332         .name           = "aclk_vepu",
2333         .parent         = &codec_pll_clk,
2334         .mode           = gate_mode,
2335         .recalc         = clksel_recalc_div,
2336         //.set_rate     = clksel_set_rate_freediv,
2337         .set_rate       =clkset_rate_freediv_autosel_parents,
2338         .clksel_con     = CRU_CLKSELS_CON(32),
2339         .gate_idx       = CLK_GATE_ACLK_VEPU,
2340         CRU_DIV_SET(0x1f,0,32),
2341         CRU_SRC_SET(0x1,7),
2342         CRU_PARENTS_SET(aclk_vepu_parents),
2343 };
2344
2345 static struct clk hclk_vepu = {
2346         .name           = "hclk_vepu",
2347         .parent         = &aclk_vepu,
2348         .mode           = gate_mode,
2349         .recalc         = clksel_recalc_vpu_hclk,
2350         .clksel_con     = CRU_CLKSELS_CON(32),
2351         .gate_idx       = CLK_GATE_HCLK_VEPU,
2352 };
2353
2354 static struct clk *aclk_vdpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2355
2356 static struct clk aclk_vdpu = {
2357         .name           = "aclk_vdpu",
2358         .mode           = gate_mode,
2359         .recalc         = clksel_recalc_div,
2360         //.set_rate     = clksel_set_rate_freediv,
2361         .set_rate       =clkset_rate_freediv_autosel_parents,
2362         .clksel_con     = CRU_CLKSELS_CON(32),
2363         .gate_idx       = CLK_GATE_ACLK_VDPU,
2364         CRU_DIV_SET(0x1f,8,32),
2365         CRU_SRC_SET(0x1,15),
2366         CRU_PARENTS_SET(aclk_vdpu_parents),
2367 };
2368 static struct clk hclk_vdpu = {
2369         .name           = "hclk_vdpu",
2370         .parent         = &aclk_vdpu,
2371         .mode           = gate_mode,
2372         .recalc         = clksel_recalc_vpu_hclk,
2373         .clksel_con     = CRU_CLKSELS_CON(32),
2374         .gate_idx       = CLK_GATE_HCLK_VDPU,
2375 };
2376
2377
2378 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
2379 {
2380         unsigned long max_rate = rate / 100 * 105;      /* +5% */
2381         return clkset_rate_freediv_autosel_parents(clk,max_rate);
2382 };
2383
2384 static struct clk *gpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2385
2386 static struct clk clk_gpu = {
2387         .name           = "gpu",
2388         .mode           = gate_mode,
2389         .recalc         = clksel_recalc_div,
2390         .round_rate     = clk_freediv_round_autosel_parents_rate,
2391         .set_rate       = clkset_rate_freediv_autosel_parents,
2392         .clksel_con = CRU_CLKSELS_CON(33),
2393         .gate_idx       =  CLK_GATE_GPU_SRC,
2394         CRU_DIV_SET(0x1f,0,32),
2395         CRU_SRC_SET(0x1,8),
2396         CRU_PARENTS_SET(gpu_parents),
2397 };
2398
2399 /*********************power domain*******************************/
2400 #ifdef RK30_CLK_OFFBOARD_TEST
2401 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on){};
2402         #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2403 #else
2404 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2405         #define _pmu_set_power_domain pmu_set_power_domain
2406 #endif
2407 static int pm_off_mode(struct clk *clk, int on)
2408 {
2409          _pmu_set_power_domain(clk->gate_idx,on);//on 1
2410          return 0;
2411 }
2412 static struct clk pd_peri = {
2413         .name   = "pd_peri",
2414         .flags  = IS_PD,
2415         .mode   = pm_off_mode,
2416         .gate_idx       = PD_PERI,
2417 };
2418
2419 static int pd_display_mode(struct clk *clk, int on)
2420 {
2421         u32 gate[10];
2422
2423         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2424         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2425         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2426         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2427         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2428         gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2429         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2430         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2431         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2432         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2433         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2434         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2435         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2436         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2437         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2438         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2439         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2440         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2441         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2442         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2443         pmu_set_power_domain(PD_VIO, on);
2444         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2445         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2446         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2447         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2448         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2449         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2450         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2451         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2452         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2453         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2454
2455         return 0;
2456 }
2457
2458 static struct clk pd_display = {
2459         .name   = "pd_display",
2460         .flags  = IS_PD,
2461         .mode   = pd_display_mode,
2462         .gate_idx       = PD_VIO,
2463 };
2464
2465 static struct clk pd_lcdc0 = {
2466         .parent = &pd_display,
2467         .name   = "pd_lcdc0",
2468 };
2469 static struct clk pd_lcdc1 = {
2470         .parent = &pd_display,
2471         .name   = "pd_lcdc1",
2472 };
2473 static struct clk pd_cif0 = {
2474         .parent = &pd_display,
2475         .name   = "pd_cif0",
2476 };
2477 static struct clk pd_cif1 = {
2478         .parent = &pd_display,
2479         .name   = "pd_cif1",
2480 };
2481 static struct clk pd_rga = {
2482         .parent = &pd_display,
2483         .name   = "pd_rga",
2484 };
2485 static struct clk pd_ipp = {
2486         .parent = &pd_display,
2487         .name   = "pd_ipp",
2488 };
2489
2490 static int pd_video_mode(struct clk *clk, int on)
2491 {
2492         u32 gate[3];
2493
2494         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2495         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2496         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2497         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2498         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2499         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2500         pmu_set_power_domain(PD_VIDEO, on);
2501         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2502         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2503         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2504
2505         return 0;
2506 }
2507
2508 static struct clk pd_video = {
2509         .name   = "pd_video",
2510         .flags  = IS_PD,
2511         .mode   = pd_video_mode,
2512         .gate_idx       = PD_VIDEO,
2513 };
2514
2515 static int pd_gpu_mode(struct clk *clk, int on)
2516 {
2517         u32 gate[2];
2518
2519         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2520         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2521         cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2522         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2523         pmu_set_power_domain(PD_GPU, on);
2524         cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2525         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2526
2527         return 0;
2528 }
2529
2530 static struct clk pd_gpu = {
2531         .name   = "pd_gpu",
2532         .flags  = IS_PD,
2533         .mode   = pd_gpu_mode,
2534         .gate_idx       = PD_GPU,
2535 };
2536 static struct clk pd_dbg = {
2537         .name   = "pd_dbg",
2538         .flags  = IS_PD,
2539         .mode   = pm_off_mode,
2540         .gate_idx       = PD_DBG,
2541 };
2542
2543 #define PD_CLK(name) \
2544 {\
2545         .dev_id = NULL,\
2546         .con_id = #name,\
2547         .clk = &name,\
2548 }
2549
2550
2551 /************************rk30 fixed div clock****************************************/
2552
2553 /*************************aclk_cpu***********************/
2554
2555 GATE_CLK(dma1, aclk_cpu,        ACLK_DMAC1);
2556 GATE_CLK(l2mem_con, aclk_cpu,   ACLK_L2MEM_CON);
2557 GATE_CLK(intmem, aclk_cpu,      ACLK_INTMEM);
2558 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2559
2560 /*************************hclk_cpu***********************/
2561
2562 GATE_CLK(rom, hclk_cpu, HCLK_ROM);
2563 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2564 GATE_CLK(hclk_i2s1_2ch, hclk_cpu,       HCLK_I2S1_2CH);
2565 GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
2566 GATE_CLK(hclk_i2s_8ch, hclk_cpu, HCLK_I2S_8CH);
2567 GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
2568 GATE_CLK(hclk_ahb2apb,  hclk_cpu, HCLK_AHB2APB);
2569 GATE_CLK(hclk_vio_bus,  hclk_cpu, HCLK_VIO_BUS);
2570 GATE_CLK(hclk_lcdc0,    hclk_cpu, HCLK_LCDC0);
2571 GATE_CLK(hclk_lcdc1,    hclk_cpu, HCLK_LCDC1);
2572 GATE_CLK(hclk_cif0,     hclk_cpu, HCLK_CIF0);
2573 GATE_CLK(hclk_cif1,     hclk_cpu, HCLK_CIF1);
2574 GATE_CLK(hclk_ipp,              hclk_cpu, HCLK_IPP);
2575 GATE_CLK(hclk_rga,              hclk_cpu, HCLK_RGA);
2576 GATE_CLK(hclk_hdmi,     hclk_cpu, HCLK_HDMI);
2577 //GATE_CLK(hclk_vidoe_h2h,      hclk_cpu, ); ???
2578 /*************************pclk_cpu***********************/
2579 GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2580 //GATE_CLK(pclk_pwm1,   pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2581 GATE_CLK(pclk_timer0,   pclk_cpu, PCLK_TIMER0);
2582 GATE_CLK(pclk_timer1,   pclk_cpu, PCLK_TIMER1);
2583 GATE_CLK(pclk_timer2,   pclk_cpu, PCLK_TIMER2);
2584 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2585 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2586 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2587 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2588 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2589 GATE_CLK(gpio6, pclk_cpu, PCLK_GPIO6);
2590 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2591 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2592 GATE_CLK(pclk_uart0,    pclk_cpu, PCLK_UART0);
2593 GATE_CLK(pclk_uart1,    pclk_cpu, PCLK_UART1);
2594 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2595 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2596 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2597 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2598 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2599
2600 /*************************aclk_periph***********************/
2601
2602 GATE_CLK(dma2, aclk_periph,ACLK_DMAC2);
2603 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2604 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2605 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2606 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2607
2608 /*************************hclk_periph***********************/
2609 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2610 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2611 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2612 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2613 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2614 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2615 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2616 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2617 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2618 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2619 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2620 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2621 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2622 /*************************pclk_periph***********************/
2623 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2624 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2625 //GATE_CLK(pclk_pwm3, pclk_periph, PCLK_PWM3);
2626 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2627 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2628 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2629 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2630 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2631 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2632 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2633 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2634 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2635 GATE_CLK(gpio4, pclk_periph, PCLK_GPIO4);
2636 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2637 GATE_CLK(pclk_tsadc, pclk_periph, PCLK_TSADC);
2638 /*************************aclk_lcdc0***********************/
2639 GATE_CLK(aclk_lcdc0, aclk_lcdc0_ipp_parent, ACLK_LCDC0);
2640 GATE_CLK(aclk_vio0, aclk_lcdc0_ipp_parent, ACLK_VIO0);
2641 GATE_CLK(aclk_cif0, aclk_lcdc0_ipp_parent, ACLK_CIF0);
2642 GATE_CLK(aclk_ipp,  aclk_lcdc0_ipp_parent, ACLK_IPP);
2643
2644 /*************************aclk_lcdc0***********************/
2645
2646 GATE_CLK(aclk_lcdc1, aclk_lcdc1_rga_parent, ACLK_LCDC1);
2647 GATE_CLK(aclk_vio1, aclk_lcdc1_rga_parent, ACLK_VIO1);
2648 GATE_CLK(aclk_cif1, aclk_lcdc1_rga_parent, ACLK_CIF0);
2649 GATE_CLK(aclk_rga,  aclk_lcdc1_rga_parent, ACLK_RGA);
2650
2651
2652 #if 1
2653 #define CLK(dev, con, ck) \
2654  {\
2655         .dev_id = dev,\
2656         .con_id = con,\
2657         .clk = ck,\
2658  }
2659
2660
2661 #define CLK1(name) \
2662         {\
2663         .dev_id = NULL,\
2664         .con_id = #name,\
2665         .clk = &clk_##name,\
2666         }
2667
2668 #endif
2669
2670
2671
2672
2673 static struct clk_lookup clks[] = {
2674         CLK(NULL, "xin24m", &xin24m),
2675         CLK(NULL, "xin27m", &xin27m),
2676         CLK(NULL, "xin12m", &clk_12m),
2677         CLK(NULL, "arm_pll", &arm_pll_clk),
2678         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2679         CLK(NULL, "codec_pll", &codec_pll_clk),
2680         CLK(NULL, "general_pll", &general_pll_clk),
2681
2682         CLK(NULL, "ddr", &clk_ddr),
2683         //CLK(NULL, "core_gpll_path", &clk_cpu_gpll_path),
2684         CLK(NULL, "cpu", &clk_cpu),
2685         CLK(NULL, "arm_gpll", &clk_cpu_gpll_path),
2686         CLK("smp_twd", NULL, &core_periph),
2687         CLK(NULL, "aclk_cpu", &aclk_cpu),
2688         CLK(NULL, "hclk_cpu", &hclk_cpu),
2689         CLK(NULL, "pclk_cpu", &pclk_cpu),
2690         CLK(NULL, "atclk_cpu", &atclk_cpu),
2691
2692
2693         CLK1(i2s_pll),
2694         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2695         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2696         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2697         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s_8ch),
2698
2699         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
2700         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
2701         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
2702         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2703
2704         CLK("rk29_i2s.2", "i2s_div", &clk_i2s2_div),
2705         CLK("rk29_i2s.2", "i2s_frac_div", &clk_i2s2_frac_div),
2706         CLK("rk29_i2s.2", "i2s", &clk_i2s2),
2707         CLK("rk29_i2s.2", "hclk_i2s", &clk_hclk_i2s1_2ch),
2708
2709         CLK1(spdif_div),
2710         CLK1(spdif_frac_div),
2711         CLK1(spdif),
2712         CLK1(hclk_spdif),
2713
2714         CLK(NULL, "aclk_periph", &aclk_periph),
2715         CLK(NULL, "pclk_periph", &pclk_periph),
2716         CLK(NULL, "hclk_periph", &hclk_periph),
2717
2718         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2719         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2720
2721         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2722         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2723
2724         CLK1(saradc),
2725         CLK1(pclk_saradc),
2726         CLK1(tsadc),
2727         CLK1(pclk_tsadc),
2728         CLK1(otgphy0),
2729         CLK1(otgphy1),
2730         CLK1(hclk_usb_peri),
2731         CLK1(hclk_otg0),
2732         CLK1(hclk_otg1),
2733
2734
2735
2736
2737
2738         CLK1(smc),
2739         CLK1(aclk_smc),
2740
2741         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2742         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2743         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2744         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2745
2746         CLK1(emmc),
2747         CLK1(hclk_emmc),
2748
2749
2750         CLK1(uart_pll),
2751         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2752         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2753         CLK("rk_serial.0", "uart", &clk_uart0),
2754         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2755         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2756         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2757         CLK("rk_serial.1", "uart", &clk_uart1),
2758         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2759         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2760         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2761         CLK("rk_serial.2", "uart", &clk_uart2),
2762         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2763         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2764         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2765         CLK("rk_serial.3", "uart", &clk_uart3),
2766         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2767
2768         CLK1(timer0),
2769         CLK1(pclk_timer0),
2770
2771         CLK1(timer1),
2772         CLK1(pclk_timer1),
2773
2774         CLK1(timer2),
2775         CLK1(pclk_timer2),
2776
2777         CLK(NULL, "rmii_clkin", &rmii_clkin),
2778         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2779         CLK1(mac_ref),
2780         CLK1(mii_tx),
2781         CLK1(hsadc_pll_div),
2782         CLK1(hsadc_frac_div),
2783         CLK1(hsadc_ext),
2784         CLK1(hsadc),
2785         CLK1(hclk_hsadc),
2786
2787         CLK(NULL, "aclk_lcdc0_ipp_parent", &aclk_lcdc0_ipp_parent),
2788         CLK(NULL, "aclk_lcdc1_rga_parent", &aclk_lcdc1_rga_parent),
2789
2790         CLK(NULL, "dclk_lcdc0_div", &dclk_lcdc0_div),
2791         CLK(NULL, "dclk_lcdc1_div", &dclk_lcdc1_div),
2792
2793         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2794         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2795         CLK1(hclk_lcdc0),
2796
2797         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2798         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2799         CLK1(hclk_lcdc1),
2800
2801         CLK(NULL, "cif_out_pll", &cif_out_pll),
2802         CLK(NULL, "cif0_out_div", &cif0_out_div),
2803         CLK(NULL, "cif1_out_div", &cif1_out_div),
2804
2805         CLK(NULL, "cif0_out", &cif0_out),
2806         CLK1(hclk_cif0),
2807
2808         CLK(NULL, "cif1_out", &cif1_out),
2809         CLK1(hclk_cif1),
2810
2811         CLK1(hclk_ipp),
2812         CLK1(hclk_rga),
2813         CLK1(hclk_hdmi),
2814
2815         CLK(NULL, "pclkin_cif0",        &pclkin_cif0),
2816         CLK(NULL, "inv_cif0",                   &inv_cif0),
2817         CLK(NULL, "cif0_in",                    &cif0_in),
2818         CLK(NULL, "pclkin_cif1", &pclkin_cif1),
2819         CLK(NULL, "inv_cif1",   &inv_cif1),
2820         CLK(NULL, "cif1_in",    &cif1_in),
2821         //CLK(NULL, "aclk_lcdc0",       &aclk_lcdc0),
2822         //CLK(NULL, "aclk_lcdc1",       &aclk_lcdc1),
2823         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2824         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2825         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2826         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2827         CLK1(gpu),
2828         CLK1(dma1),
2829         CLK1(l2mem_con),
2830         CLK1(intmem),
2831
2832         CLK1(aclk_strc_sys),
2833
2834         /*************************hclk_cpu***********************/
2835
2836         CLK1(rom),
2837         //CLK1(hclk_i2s0_2ch),
2838         //CLK1(hclk_i2s1_2ch),
2839         //CLK1(hclk_spdif),
2840         //CLK1(hclk_i2s_8ch),
2841         CLK1(hclk_cpubus),
2842         CLK1(hclk_ahb2apb),
2843         CLK1(hclk_vio_bus),
2844         //CLK1(hclk_lcdc0),
2845         //CLK1(hclk_lcdc1),
2846         //CLK1(hclk_cif0),
2847         //CLK1(hclk_cif1),
2848         //CLK1(hclk_ipp),
2849         //CLK1(hclk_rga),
2850         //CLK1(hclk_hdmi),
2851         //CLK1(hclk_vidoe_h2h,  hclk_cpu, ); ???
2852         /*************************pclk_cpu***********************/
2853         CLK1(pwm01),//pwm 0¡¢1
2854
2855         //CLK1(pclk_timer0),
2856         //CLK1(pclk_timer1),
2857         //CLK1(pclk_timer2),
2858
2859         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2860         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2861
2862         CLK1(gpio0),
2863         CLK1(gpio1),
2864         CLK1(gpio2),
2865         CLK1(gpio6),
2866         CLK1(efuse),
2867         CLK1(tzpc),
2868         //CLK1(pclk_uart0),
2869         //CLK1(pclk_uart1),
2870         CLK1(pclk_ddrupctl),
2871         CLK1(pclk_ddrpubl),
2872         CLK1(dbg),
2873         CLK1(grf),
2874         CLK1(pmu),
2875
2876         /*************************aclk_periph***********************/
2877
2878         CLK1(dma2),
2879         //CLK1(aclk_smc),
2880         CLK1(aclk_peri_niu),
2881         CLK1(aclk_cpu_peri),
2882         CLK1(aclk_peri_axi_matrix),
2883
2884         /*************************hclk_periph***********************/
2885         CLK1(hclk_peri_axi_matrix),
2886         CLK1(hclk_peri_ahb_arbi),
2887         CLK1(hclk_emem_peri),
2888         CLK1(hclk_mac),
2889         CLK1(nandc),
2890         //CLK1(hclk_usb_peri),
2891         //CLK1(hclk_usbotg0),
2892         //CLK1(hclk_usbotg1),
2893         //CLK1(hclk_hsadc),
2894         CLK1(hclk_pidfilter),
2895
2896         //CLK1(hclk_emmc),
2897         /*************************pclk_periph***********************/
2898         CLK1(pclk_peri_axi_matrix),
2899         CLK1(pwm23),
2900
2901         CLK1(wdt),
2902         //CLK1(pclk_spi0),
2903         //CLK1(pclk_spi1),
2904         //CLK1(pclk_uart2),
2905         //CLK1(pclk_uart3),
2906
2907         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2908         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2909         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2910
2911         CLK1(gpio3),
2912         CLK1(gpio4),
2913
2914         /*************************aclk_lcdc0***********************/
2915         //CLK1(aclk_vio0),
2916         CLK1(aclk_cif0),
2917         CLK1(aclk_ipp),
2918
2919         /*************************aclk_lcdc0***********************/
2920         //CLK1(aclk_vio1),
2921         CLK1(aclk_cif1),
2922         CLK1(aclk_rga),
2923         /************************power domain**********************/
2924         PD_CLK(pd_peri),
2925         PD_CLK(pd_display),
2926         PD_CLK(pd_video),
2927         PD_CLK(pd_lcdc0),
2928         PD_CLK(pd_lcdc1),
2929         PD_CLK(pd_cif0),
2930         PD_CLK(pd_cif1),
2931         PD_CLK(pd_rga),
2932         PD_CLK(pd_ipp),
2933         PD_CLK(pd_video),
2934         PD_CLK(pd_gpu),
2935         PD_CLK(pd_dbg),
2936 };
2937 static void __init rk30_init_enable_clocks(void)
2938 {
2939                 //clk_enable_nolock(&xin24m);
2940                 //clk_enable_nolock(&xin27m);
2941                 //clk_enable_nolock(&clk_12m);
2942                 //clk_enable_nolock(&arm_pll_clk);
2943                 //clk_enable_nolock(&ddr_pll_clk);
2944                 //clk_enable_nolock(&codec_pll_clk);
2945                 //clk_enable_nolock(&general_pll_clk);
2946                 //clk_enable_nolock(&clk_ddr);
2947
2948                 clk_enable_nolock(&clk_cpu);
2949                 clk_enable_nolock(&core_periph);
2950                 clk_enable_nolock(&aclk_cpu);
2951                 clk_enable_nolock(&hclk_cpu);
2952                 clk_enable_nolock(&pclk_cpu);
2953                 clk_enable_nolock(&atclk_cpu);
2954
2955                 #if 0
2956                 clk_enable_nolock(&clk_i2s_pll);
2957                 clk_enable_nolock(&clk_i2s0_div);
2958                 clk_enable_nolock(&clk_i2s0_frac_div);
2959                 clk_enable_nolock(&clk_i2s0);
2960                 clk_enable_nolock(&clk_hclk_i2s_8ch);
2961
2962                 clk_enable_nolock(&clk_i2s1_div);
2963                 clk_enable_nolock(&clk_i2s1_frac_div);
2964                 clk_enable_nolock(&clk_i2s1);
2965                 clk_enable_nolock(&clk_hclk_i2s0_2ch);
2966
2967                 clk_enable_nolock(&clk_i2s2_div);
2968                 clk_enable_nolock(&clk_i2s2_frac_div);
2969                 clk_enable_nolock(&clk_i2s2);
2970                 clk_enable_nolock(&clk_hclk_i2s1_2ch);
2971
2972                 clk_enable_nolock(&clk_spdif_div);
2973                 clk_enable_nolock(&clk_spdif_frac_div);
2974                 clk_enable_nolock(&clk_spdif);
2975                 clk_enable_nolock(&clk_hclk_spdif);
2976                 #endif
2977                 clk_enable_nolock(&aclk_periph);
2978                 clk_enable_nolock(&pclk_periph);
2979                 clk_enable_nolock(&hclk_periph);
2980
2981                 #if 0
2982                 clk_enable_nolock(&clk_spi0);
2983                 clk_enable_nolock(&clk_pclk_spi0);
2984
2985                 clk_enable_nolock(&clk_spi1);
2986                 clk_enable_nolock(&clk_pclk_spi1);
2987                 clk_enable_nolock(&clk_saradc);
2988                 clk_enable_nolock(&clk_pclk_saradc);
2989                 clk_enable_nolock(&clk_tsadc);
2990                 clk_enable_nolock(&clk_pclk_tsadc);
2991                 #endif
2992                 #if 0
2993                 clk_enable_nolock(&clk_otgphy0);
2994                 clk_enable_nolock(&clk_otgphy1);
2995                 clk_enable_nolock(&clk_hclk_usb_peri);
2996                 clk_enable_nolock(&clk_hclk_otg0);
2997                 clk_enable_nolock(&clk_hclk_otg1);
2998                 #endif
2999                 #if 0
3000                 clk_enable_nolock(&clk_smc);
3001                 clk_enable_nolock(&clk_aclk_smc);
3002
3003                 clk_enable_nolock(&clk_sdmmc);
3004                 clk_enable_nolock(&clk_hclk_sdmmc);
3005                 clk_enable_nolock(&clk_sdio);
3006                 clk_enable_nolock(&clk_hclk_sdio);
3007
3008                 clk_enable_nolock(&clk_emmc);
3009                 clk_enable_nolock(&clk_hclk_emmc);
3010
3011                 #endif
3012
3013         #if CONFIG_RK_DEBUG_UART == 0
3014                 clk_enable_nolock(&clk_uart0);
3015                 clk_enable_nolock(&clk_pclk_uart0);
3016         #elif CONFIG_RK_DEBUG_UART == 1
3017                 clk_enable_nolock(&clk_uart1);
3018                 clk_enable_nolock(&clk_pclk_uart1);
3019
3020         #elif CONFIG_RK_DEBUG_UART == 2
3021                 clk_enable_nolock(&clk_uart2);
3022                 clk_enable_nolock(&clk_pclk_uart2);
3023
3024         #elif CONFIG_RK_DEBUG_UART == 3
3025                 clk_enable_nolock(&clk_uart3);
3026                 clk_enable_nolock(&clk_pclk_uart3);
3027
3028         #endif
3029
3030                 #if 0
3031                 clk_enable_nolock(&clk_timer0);
3032                 clk_enable_nolock(&clk_pclk_timer0);
3033
3034                 clk_enable_nolock(&clk_timer1);
3035                 clk_enable_nolock(&clk_pclk_timer1);
3036
3037                 clk_enable_nolock(&clk_timer2);
3038                 clk_enable_nolock(&clk_pclk_timer2);
3039                 #endif
3040                 #if 0
3041                 clk_enable_nolock(&rmii_clkin);
3042                 clk_enable_nolock(&clk_mac_pll_div);
3043                 clk_enable_nolock(&clk_mac_ref);
3044                 clk_enable_nolock(&clk_mii_tx);
3045                 #endif
3046
3047                 #if 0
3048                 clk_enable_nolock(&clk_hsadc_pll_div);
3049                 clk_enable_nolock(&clk_hsadc_frac_div);
3050                 clk_enable_nolock(&clk_hsadc_ext);
3051                 clk_enable_nolock(&clk_hsadc);
3052                 clk_enable_nolock(&clk_hclk_hsadc);
3053                 #endif
3054
3055                 #if 0
3056                 clk_enable_nolock(&aclk_lcdc0_ipp_parent);
3057                 clk_enable_nolock(&aclk_lcdc1_rga_parent);
3058
3059                 clk_enable_nolock(&dclk_lcdc0_div);
3060                 clk_enable_nolock(&dclk_lcdc1_div);
3061
3062                 clk_enable_nolock(&dclk_lcdc0);
3063                 clk_enable_nolock(&clk_aclk_lcdc0);
3064                 clk_enable_nolock(&clk_hclk_lcdc0);
3065
3066                 clk_enable_nolock(&dclk_lcdc1);
3067                 clk_enable_nolock(&clk_aclk_lcdc1);
3068                 clk_enable_nolock(&clk_hclk_lcdc1);
3069
3070                 clk_enable_nolock(&cif_out_pll);
3071                 clk_enable_nolock(&cif0_out_div);
3072                 clk_enable_nolock(&cif1_out_div);
3073
3074                 clk_enable_nolock(&cif0_out);
3075                 clk_enable_nolock(&clk_hclk_cif0);
3076
3077                 clk_enable_nolock(&cif1_out);
3078                 clk_enable_nolock(&clk_hclk_cif1);
3079
3080                 clk_enable_nolock(&clk_hclk_ipp);
3081                 clk_enable_nolock(&clk_hclk_rga);
3082                 clk_enable_nolock(&clk_hclk_hdmi);
3083
3084                 clk_enable_nolock(&pclkin_cif0);
3085                 clk_enable_nolock(&inv_cif0);
3086                 clk_enable_nolock(&cif0_in);
3087                 clk_enable_nolock(&pclkin_cif1);
3088                 clk_enable_nolock(&inv_cif1);
3089                 clk_enable_nolock(&cif1_in);
3090                 //CLK(NULL, "aclk_lcdc0",       &aclk_lcdc0),
3091                 //CLK(NULL, "aclk_lcdc1",       &aclk_lcdc1),
3092                 clk_enable_nolock(&aclk_vepu);
3093                 clk_enable_nolock(&hclk_vepu);
3094                 clk_enable_nolock(&aclk_vdpu);
3095                 clk_enable_nolock(&hclk_vdpu);
3096                 clk_enable_nolock(&clk_gpu);
3097                 #endif
3098
3099                 clk_enable_nolock(&clk_dma1);
3100                 clk_enable_nolock(&clk_l2mem_con);
3101                 clk_enable_nolock(&clk_intmem);
3102
3103                 clk_enable_nolock(&clk_aclk_strc_sys);
3104
3105                 /*************************hclk_cpu***********************/
3106
3107                 clk_enable_nolock(&clk_rom);
3108
3109                 clk_enable_nolock(&clk_hclk_cpubus);
3110                 clk_enable_nolock(&clk_hclk_ahb2apb);
3111                 clk_enable_nolock(&clk_hclk_vio_bus);
3112
3113                 /*************************pclk_cpu***********************/
3114
3115                 //clk_enable_nolock(&clk_pwm01);//pwm 0¡¢1
3116                 #if 0
3117
3118
3119                 clk_enable_nolock(&clk_i2c0);
3120                 clk_enable_nolock(&clk_i2c1);
3121
3122                 clk_enable_nolock(&clk_gpio0);
3123                 clk_enable_nolock(&clk_gpio1);
3124                 clk_enable_nolock(&clk_gpio2);
3125                 clk_enable_nolock(&clk_gpio6);
3126                 clk_enable_nolock(&clk_efuse);
3127                 #endif
3128                 clk_enable_nolock(&clk_tzpc);
3129
3130                 //CLK1(pclk_uart0),
3131                 //CLK1(pclk_uart1),
3132                 clk_enable_nolock(&clk_pclk_ddrupctl);
3133                 clk_enable_nolock(&clk_pclk_ddrpubl);
3134                 clk_enable_nolock(&clk_dbg);
3135                 clk_enable_nolock(&clk_grf);
3136                 clk_enable_nolock(&clk_pmu);
3137
3138                 /*************************aclk_periph***********************/
3139
3140                 clk_enable_nolock(&clk_dma2);
3141                 //CLK1(aclk_smc),
3142                 clk_enable_nolock(&clk_aclk_peri_niu);
3143                 clk_enable_nolock(&clk_aclk_cpu_peri);
3144                 clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3145
3146                 /*************************hclk_periph***********************/
3147                 clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3148                 clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3149                 clk_enable_nolock(&clk_hclk_emem_peri);
3150                 clk_enable_nolock(&clk_hclk_mac);
3151                 clk_enable_nolock(&clk_nandc);
3152                 //CLK1(hclk_usb_peri),
3153                 //CLK1(hclk_usbotg0),
3154                 //CLK1(hclk_usbotg1),
3155                 //CLK1(hclk_hsadc),
3156                 clk_enable_nolock(&clk_hclk_pidfilter);
3157
3158                 /*************************pclk_periph***********************/
3159                 clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3160                 //clk_enable_nolock(&clk_pwm23);
3161
3162                 //clk_enable_nolock(&clk_wdt);
3163
3164                 #if 0
3165
3166                 clk_enable_nolock(&clk_i2c2);
3167                 clk_enable_nolock(&clk_i2c3);
3168                 clk_enable_nolock(&clk_i2c4);
3169
3170                 clk_enable_nolock(&clk_gpio3);
3171                 clk_enable_nolock(&clk_gpio4);
3172                 #endif
3173                 /*************************aclk_lcdc0***********************/
3174                 //clk_enable_nolock(&clk_aclk_vio0);
3175                 //clk_enable_nolock(&clk_aclk_cif0);
3176                 //clk_enable_nolock(&clk_aclk_ipp);
3177
3178                 /*************************aclk_lcdc0***********************/
3179                 //clk_enable_nolock(&clk_aclk_vio1);
3180                 //clk_enable_nolock(&clk_aclk_cif1);
3181                 //clk_enable_nolock(&clk_aclk_rga);
3182                 /************************power domain**********************/
3183 }
3184 static void periph_clk_set_init(void)
3185 {
3186         unsigned long aclk_p, hclk_p, pclk_p;
3187         unsigned long ppll_rate=general_pll_clk.rate;
3188         //aclk 148.5
3189
3190         /* general pll */
3191         switch (ppll_rate) {
3192         case 148500* KHZ:
3193                 aclk_p = 148500*KHZ;
3194                 hclk_p = aclk_p>>1;
3195                 pclk_p = aclk_p>>2;
3196                 break;
3197         case 1188*MHZ:
3198                 aclk_p = aclk_p>>3;// 0
3199                 hclk_p = aclk_p>>1;
3200                 pclk_p = aclk_p>>2;
3201
3202         case 297 * MHZ:
3203                 aclk_p = ppll_rate>>1;
3204                 hclk_p = aclk_p>>0;
3205                 pclk_p = aclk_p>>1;
3206                 break;
3207
3208         case 300 * MHZ:
3209                 aclk_p = ppll_rate>>1;
3210                 hclk_p = aclk_p>>0;
3211                 pclk_p = aclk_p>>1;
3212                 break;
3213         default:
3214                 aclk_p = 150 * MHZ;
3215                 hclk_p = 150 * MHZ;
3216                 pclk_p = 75 * MHZ;
3217                 break;
3218         }
3219         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3220         clk_set_rate_nolock(&aclk_periph, aclk_p);
3221         clk_set_rate_nolock(&hclk_periph, hclk_p);
3222         clk_set_rate_nolock(&pclk_periph, pclk_p);
3223 }
3224
3225
3226 void rk30_clock_common_i2s_init(void)
3227 {
3228         struct clk *max_clk,*min_clk;
3229         unsigned long i2s_rate;
3230         //20 times
3231         if(rk30_clock_flags&CLK_FLG_MAX_I2S_49152KHZ)
3232         {
3233                 i2s_rate=49152000;
3234         }else if(rk30_clock_flags&CLK_FLG_MAX_I2S_24576KHZ)
3235         {
3236                 i2s_rate=24576000;
3237         }
3238         else if(rk30_clock_flags&CLK_FLG_MAX_I2S_22579_2KHZ)
3239         {
3240                 i2s_rate=22579000;
3241         }
3242         else if(rk30_clock_flags&CLK_FLG_MAX_I2S_12288KHZ)
3243         {
3244                 i2s_rate=12288000;
3245         }
3246         else
3247         {
3248                 i2s_rate=49152000;
3249         }
3250
3251         if(((i2s_rate*20)<=general_pll_clk.rate)||!(general_pll_clk.rate%i2s_rate))
3252         {
3253                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3254         }
3255         else if(((i2s_rate*20)<=codec_pll_clk.rate)||!(codec_pll_clk.rate%i2s_rate))
3256         {
3257                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3258         }
3259         else
3260         {
3261                 if(general_pll_clk.rate>codec_pll_clk.rate)
3262                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3263                 else
3264                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3265         }
3266
3267
3268
3269
3270
3271
3272 }
3273 static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long cpll_rate)
3274 {
3275
3276         clk_set_rate_nolock(&clk_cpu, 816*MHZ);//816
3277         //general
3278         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3279         //code pll
3280         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3281
3282         //periph clk
3283         periph_clk_set_init();
3284
3285         //i2s
3286         rk30_clock_common_i2s_init();
3287
3288         // spi
3289         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3290         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3291
3292         // uart
3293         #if 0
3294         clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3295         #else
3296         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3297         #endif
3298         //mac
3299         if(!(gpll_rate%(50*MHZ)))
3300                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3301         else if(!(ddr_pll_clk.rate%(50*MHZ)))
3302                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3303         else
3304                 CRU_PRINTK_ERR("mac can't get 50mhz\n");
3305
3306         //hsadc
3307         //auto pll sel
3308         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3309
3310         //lcdc1  hdmi
3311         clk_set_parent_nolock(&dclk_lcdc1_div, &general_pll_clk);
3312
3313         //lcdc0 lcd auto sel pll
3314         //clk_set_parent_nolock(&dclk_lcdc0_div, &general_pll_clk);
3315
3316         //cif
3317         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3318
3319         //axi lcdc auto sel
3320         //clk_set_parent_nolock(&aclk_lcdc0, &general_pll_clk);
3321         //clk_set_parent_nolock(&aclk_lcdc1, &general_pll_clk);
3322         clk_set_rate_nolock(&aclk_lcdc0_ipp_parent, 300*MHZ);
3323         clk_set_rate_nolock(&aclk_lcdc1_rga_parent, 300*MHZ);
3324
3325         //axi vepu auto sel
3326         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3327         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3328
3329         clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
3330         clk_set_rate_nolock(&aclk_vdpu, 300*MHZ);
3331         //gpu auto sel
3332         //clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
3333 }
3334
3335 static struct clk def_ops_clk={
3336         .get_parent=clksel_get_parent,
3337         .set_parent=clksel_set_parent,
3338 };
3339
3340 #ifdef CONFIG_PROC_FS
3341 struct clk_dump_ops dump_ops;
3342 #endif
3343
3344 static void clk_dump_regs(void);
3345
3346 void __init _rk30_clock_data_init(unsigned long gpll,unsigned long cpll,int flags)
3347 {
3348         struct clk_lookup *lk;
3349
3350         clk_register_dump_ops(&dump_ops);
3351         clk_register_default_ops_clk(&def_ops_clk);
3352         rk30_clock_flags=flags;
3353         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3354                 #ifdef RK30_CLK_OFFBOARD_TEST
3355                         rk30_clkdev_add(lk);
3356                 #else
3357                         clkdev_add(lk);
3358                 #endif
3359                 clk_register(lk->clk);
3360         }
3361         clk_recalculate_root_clocks_nolock();
3362
3363         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3364
3365         /*
3366          * Only enable those clocks we will need, let the drivers
3367          * enable other clocks as necessary
3368          */
3369         rk30_init_enable_clocks();
3370
3371         /*
3372          * Disable any unused clocks left on by the bootloader
3373          */
3374         //clk_disable_unused();
3375         rk30_clock_common_init(gpll,cpll);
3376         preset_lpj = loops_per_jiffy;
3377
3378         //gpio6_b7
3379         //regfile_writel(0xc0004000,0x10c);
3380         //cru_writel(0x07000000,CRU_MISC_CON);
3381
3382 }
3383
3384 void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags)
3385 {
3386         _rk30_clock_data_init(gpll,cpll,flags);
3387         rk30_dvfs_init();
3388 }
3389
3390 /*
3391  * You can override arm_clk rate with armclk= cmdline option.
3392  */
3393 static int __init armclk_setup(char *str)
3394 {
3395         get_option(&str, &armclk);
3396
3397         if (!armclk)
3398                 return 0;
3399         if (armclk < 10000)
3400                 armclk *= MHZ;
3401         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3402         return 0;
3403 }
3404 #ifndef RK30_CLK_OFFBOARD_TEST
3405 early_param("armclk", armclk_setup);
3406 #endif
3407
3408
3409
3410 #ifdef CONFIG_PROC_FS
3411
3412 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks)
3413 {
3414         struct clk* ck;
3415         int i;
3416         unsigned long rate = clk->rate;
3417         //CRU_PRINTK_DBG("dump_clock %s\n",clk->name);
3418         for (i = 0; i < deep; i++)
3419                 seq_printf(s, "    ");
3420
3421         seq_printf(s, "%-11s ", clk->name);
3422 #ifndef RK30_CLK_OFFBOARD_TEST
3423         if (clk->flags & IS_PD) {
3424                         seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3425         }
3426 #endif
3427         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3428                 int idx = clk->gate_idx;
3429                 u32 v;
3430                 v = cru_readl(CLK_GATE_CLKID_CONS(idx))&((0x1)<<(idx%16));
3431                 seq_printf(s, "%s ", v ? "off" : "on ");
3432         }
3433
3434         if (clk->pll)
3435         {
3436                 u32 pll_mode;
3437                 u32 pll_id=clk->pll->id;
3438                 pll_mode=cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3439                 if(pll_mode==PLL_MODE_SLOW(pll_id))
3440                         seq_printf(s, "slow   ");
3441                 else if(pll_mode==PLL_MODE_NORM(pll_id))
3442                         seq_printf(s, "normal ");
3443                 else if(pll_mode==PLL_MODE_DEEP(pll_id))
3444                         seq_printf(s, "deep   ");
3445
3446                 if(cru_readl(PLL_CONS(pll_id,3)) & PLL_BYPASS)
3447                         seq_printf(s, "bypass ");
3448         }
3449         else if(clk == &clk_ddr) {
3450                 rate = clk->recalc(clk);
3451         }
3452
3453         if (rate >= MHZ) {
3454                 if (rate % MHZ)
3455                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3456                 else
3457                         seq_printf(s, "%ld MHz", rate / MHZ);
3458         } else if (rate >= KHZ) {
3459                 if (rate % KHZ)
3460                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3461                 else
3462                         seq_printf(s, "%ld KHz", rate / KHZ);
3463         } else {
3464                 seq_printf(s, "%ld Hz", rate);
3465         }
3466
3467         seq_printf(s, " usecount = %d", clk->usecount);
3468
3469         if (clk->parent)
3470                 seq_printf(s, " parent = %s", clk->parent->name);
3471
3472         seq_printf(s, "\n");
3473
3474         list_for_each_entry(ck, root_clocks, node) {
3475                 if (ck->parent == clk)
3476                         dump_clock(s, ck, deep + 1,root_clocks);
3477         }
3478 }
3479
3480 static void dump_regs(struct seq_file *s)
3481 {
3482         int i=0;
3483         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3484         seq_printf(s, "\nPLLRegisters:\n");
3485         for(i=0;i<END_PLL_ID;i++)
3486         {
3487                 seq_printf(s,"pll%d        :cons:%x,%x,%x,%x\n",i,
3488                         cru_readl(PLL_CONS(i,0)),
3489                         cru_readl(PLL_CONS(i,1)),
3490                         cru_readl(PLL_CONS(i,2)),
3491                         cru_readl(PLL_CONS(i,3))
3492                         );
3493         }
3494                 seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3495
3496         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
3497         {
3498                 seq_printf(s,"CLKSEL%d     :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
3499         }
3500         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
3501         {
3502                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
3503         }
3504         seq_printf(s,"GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
3505         seq_printf(s,"GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
3506
3507         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
3508         {
3509                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
3510         }
3511         seq_printf(s,"CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
3512         seq_printf(s,"GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
3513
3514 }
3515
3516 void rk30_clk_dump_regs(void)
3517 {
3518         int i=0;
3519         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3520         printk("\nPLLRegisters:\n");
3521         for(i=0;i<END_PLL_ID;i++)
3522         {
3523                 printk("pll%d        :cons:%x,%x,%x,%x\n",i,
3524                         cru_readl(PLL_CONS(i,0)),
3525                         cru_readl(PLL_CONS(i,1)),
3526                         cru_readl(PLL_CONS(i,2)),
3527                         cru_readl(PLL_CONS(i,3))
3528                         );
3529         }
3530                 printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3531
3532         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
3533         {
3534                 printk("CLKSEL%d           :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
3535         }
3536         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
3537         {
3538                 printk("CLKGATE%d         :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
3539         }
3540         printk("GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
3541         printk("GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
3542
3543         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
3544         {
3545                 printk("SOFTRST%d         :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
3546         }
3547         printk("CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
3548         printk("GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
3549
3550 }
3551
3552
3553 #ifdef CONFIG_PROC_FS
3554 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
3555 struct clk_dump_ops dump_ops={
3556         .dump_clk=dump_clock,
3557         .dump_regs=dump_regs,
3558 };
3559 #endif
3560
3561
3562 #endif /* CONFIG_PROC_FS */
3563
3564
3565
3566
3567 #ifdef RK30_CLK_OFFBOARD_TEST
3568 struct clk *test_get_parent(struct clk *clk)
3569 {
3570         return clk->parent;
3571 }
3572
3573 void i2s_test(void)
3574 {
3575         struct clk *i2s_clk=&clk_i2s0;
3576
3577         clk_enable_nolock(i2s_clk);
3578
3579         clk_set_rate_nolock(i2s_clk, 12288000);
3580         printk("int %s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3581         clk_set_rate_nolock(i2s_clk, 297*MHZ/2);
3582         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3583         clk_set_rate_nolock(i2s_clk, 12*MHZ);
3584         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3585
3586 }
3587
3588 void uart_test(void)
3589 {
3590         struct clk *uart_clk=&clk_uart0;
3591
3592         clk_enable_nolock(uart_clk);
3593
3594         clk_set_rate_nolock(uart_clk, 12288000);
3595         printk("int %s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3596         clk_set_rate_nolock(uart_clk, 297*MHZ/2);
3597         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3598         clk_set_rate_nolock(uart_clk, 12*MHZ);
3599         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3600
3601 }
3602 void hsadc_test(void)
3603 {
3604         struct clk *hsadc_clk=&clk_hsadc;
3605
3606         printk("******************hsadc_test**********************\n");
3607         clk_enable_nolock(hsadc_clk);
3608
3609         clk_set_rate_nolock(hsadc_clk, 12288000);
3610         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3611
3612
3613         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3614         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3615
3616         clk_set_rate_nolock(hsadc_clk, 300*MHZ/2);
3617
3618         clk_set_rate_nolock(hsadc_clk, 296*MHZ/2);
3619
3620         printk("******************hsadc out clock**********************\n");
3621
3622         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3623         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3624         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3625         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3626
3627
3628
3629 }
3630
3631 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3632 {
3633         //arm
3634         printk("*********arm_pll_clk***********\n");
3635         clk_set_rate_nolock(&arm_pll_clk, 816*MHZ);
3636
3637         printk("*********set clk_cpu parent***********\n");
3638         clk_set_parent_nolock(&clk_cpu, &arm_pll_clk);
3639         clk_set_rate_nolock(&clk_cpu, 504*MHZ);
3640
3641         //general
3642         printk("*********general_pll_clk***********\n");
3643         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3644
3645         //code pll
3646         printk("*********codec_pll_clk***********\n");
3647         clk_set_rate_nolock(&codec_pll_clk, 600*MHZ);
3648
3649
3650         printk("*********periph_clk_set_init***********\n");
3651         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3652         periph_clk_set_init();
3653
3654         #if 0 //
3655                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3656         #else
3657                 printk("*********clk i2s***********\n");
3658                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3659                 printk("common %s parent is %s\n",clk_i2s_pll.name,test_get_parent(&clk_i2s_pll)->name);
3660                 i2s_test();
3661         #endif
3662 // spi
3663         clk_enable_nolock(&clk_spi0);
3664         clk_set_rate_nolock(&clk_spi0, 30*MHZ);
3665         printk("common %s parent is %s\n",clk_spi0.name,test_get_parent(&clk_spi0)->name);
3666 //saradc
3667         clk_enable_nolock(&clk_saradc);
3668         clk_set_rate_nolock(&clk_saradc, 6*MHZ);
3669         printk("common %s parent is %s\n",clk_saradc.name,test_get_parent(&clk_saradc)->name);
3670 //sdio
3671         clk_enable_nolock(&clk_sdio);
3672         clk_set_rate_nolock(&clk_sdio, 50*MHZ);
3673         printk("common %s parent is %s\n",clk_sdio.name,test_get_parent(&clk_sdio)->name);
3674 // uart
3675         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3676         uart_test();
3677 //mac
3678         printk("*********mac***********\n");
3679
3680         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3681         printk("common %s parent is %s\n",clk_mac_pll_div.name,test_get_parent(&clk_mac_pll_div)->name);
3682
3683         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3684         clk_set_rate_nolock(&clk_mac_ref, 50*MHZ);
3685         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3686
3687         printk("*********mac mii set***********\n");
3688         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3689         clk_set_rate_nolock(&clk_mac_ref, 20*MHZ);
3690         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3691 //hsadc
3692         printk("*********hsadc 1***********\n");
3693         //auto pll
3694         hsadc_test();
3695 //lcdc
3696         clk_enable_nolock(&dclk_lcdc0);
3697
3698         clk_set_rate_nolock(&dclk_lcdc0, 60*MHZ);
3699         clk_set_rate_nolock(&dclk_lcdc0, 27*MHZ);
3700
3701 //cif
3702         clk_enable_nolock(&cif0_out);
3703
3704         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3705         printk("common %s parent is %s\n",cif_out_pll.name,test_get_parent(&cif_out_pll)->name);
3706
3707         clk_set_rate_nolock(&cif0_out, 60*MHZ);
3708         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3709
3710         clk_set_rate_nolock(&cif0_out, 24*MHZ);
3711         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3712 //cif_in
3713         clk_enable_nolock(&cif0_in);
3714         clk_set_rate_nolock(&cif0_in, 24*MHZ);
3715 //axi lcdc
3716         clk_enable_nolock(&aclk_lcdc0);
3717         clk_set_rate_nolock(&aclk_lcdc0, 150*MHZ);
3718         printk("common %s parent is %s\n",aclk_lcdc0.name,test_get_parent(&aclk_lcdc0)->name);
3719 //axi vepu
3720         clk_enable_nolock(&aclk_vepu);
3721         clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
3722         printk("common %s parent is %s\n",aclk_vepu.name,test_get_parent(&aclk_vepu)->name);
3723
3724         clk_set_rate_nolock(&hclk_vepu, 300*MHZ);
3725         printk("common %s parent is %s\n",hclk_vepu.name,test_get_parent(&hclk_vepu)->name);
3726
3727         printk("test end\n");
3728
3729         /* arm pll
3730         clk_set_rate_nolock(&arm_pll_clk, armclk);
3731         clk_set_rate_nolock(&clk_cpu,   armclk);//pll:core =1:1
3732         */
3733         //
3734         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3735         //
3736         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3737         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3738
3739 }
3740
3741
3742
3743
3744
3745 static LIST_HEAD(rk30_clocks);
3746 static DEFINE_MUTEX(rk30_clocks_mutex);
3747
3748 static inline int __rk30clk_get(struct clk *clk)
3749 {
3750         return 1;
3751 }
3752 void rk30_clkdev_add(struct clk_lookup *cl)
3753 {
3754         mutex_lock(&rk30_clocks_mutex);
3755         list_add_tail(&cl->node, &rk30_clocks);
3756         mutex_unlock(&rk30_clocks_mutex);
3757 }
3758 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id)
3759 {
3760         struct clk_lookup *p, *cl = NULL;
3761         int match, best = 0;
3762
3763         list_for_each_entry(p, &rk30_clocks, node) {
3764                 match = 0;
3765                 if (p->dev_id) {
3766                         if (!dev_id || strcmp(p->dev_id, dev_id))
3767                                 continue;
3768                         match += 2;
3769                 }
3770                 if (p->con_id) {
3771                         if (!con_id || strcmp(p->con_id, con_id))
3772                                 continue;
3773                         match += 1;
3774                 }
3775
3776                 if (match > best) {
3777                         cl = p;
3778                         if (match != 3)
3779                                 best = match;
3780                         else
3781                                 break;
3782                 }
3783         }
3784         return cl;
3785 }
3786
3787 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id)
3788 {
3789         struct clk_lookup *cl;
3790
3791         mutex_lock(&rk30_clocks_mutex);
3792         cl = rk30_clk_find(dev_id, con_id);
3793         if (cl && !__rk30clk_get(cl->clk))
3794                 cl = NULL;
3795         mutex_unlock(&rk30_clocks_mutex);
3796
3797         return cl ? cl->clk : ERR_PTR(-ENOENT);
3798 }
3799 //EXPORT_SYMBOL(rk30_clk_get_sys);
3800
3801 struct clk *rk30_clk_get(struct device *dev, const char *con_id)
3802 {
3803         const char *dev_id = dev ? dev_name(dev) : NULL;
3804         return rk30_clk_get_sys(dev_id, con_id);
3805 }
3806 //EXPORT_SYMBOL(rk30_clk_get);
3807
3808
3809 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3810
3811 void rk30_clocks_test(void)
3812 {
3813     struct clk *test_gpll;
3814         test_gpll=rk30_clk_get(NULL,"general_pll");
3815         if(test_gpll)
3816         {
3817                 rk30_clk_set_rate(test_gpll,297*2*MHZ);
3818                 printk("gpll rate=%lu\n",test_gpll->rate);
3819         }
3820         //while(1);
3821 }
3822
3823 void __init rk30_clock_init_test(void){
3824
3825         rk30_clock_init(periph_pll_297mhz,codec_pll_360mhz,max_i2s_12288khz);
3826         //while(1);
3827 }
3828
3829
3830 #endif
3831
3832