arch/arm/mach-rk30/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include "clock.h"
  27
  28 #ifndef RK30_CLK_OFFBOARD_TEST
  29 #include <mach/pmu.h>
  30 #endif
  31
  32
  33 #define MHZ                     (1000*1000)
  34 #define KHZ                     (1000)
  35
  36 //#define CLK_LPJ_CALC
  37 #ifdef CLK_LPJ_CALC
  38 static unsigned long _clk_loops_per_jiffy;
  39 static unsigned long _clk_loops_rate_ref;
  40
  41 #define CLK_LOOPS_JIFFY_REF _clk_loops_per_jiffy
  42 #define CLK_LOOPS_RARE_REF      _clk_loops_rate_ref
  43
  44 #else
  45
  46 #define CLK_LOOPS_JIFFY_REF 2*2998368ULL
  47 #define CLK_LOOPS_RARE_REF (600*MHZ)
  48
  49 #endif
  50 //define CLK_LOOPS_RECALC(new_rate) cpufreq_scale(CLK_LOOPS_JIFFY_REF,CLK_LOOPS_RARE_REF,(new_rate))
  51 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RARE_REF)
  52
  53 struct apll_clk_set {
  54         unsigned long rate;
  55         u32     pllcon0;
  56         u32     pllcon1;
  57         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  58         u32 rst_dly;//us
  59         u32     clksel0;
  60         u32     clksel1;
  61         unsigned long lpj;
  62 };
  63 struct pll_clk_set {
  64         unsigned long rate;
  65         u32     pllcon0;
  66         u32     pllcon1;
  67         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  68         u32 rst_dly;//us
  69 };
  70
  71 #define SET_PLL_DATA(_pll_id,_table) \
  72 {\
  73         .id=(_pll_id),\
  74         .table=(_table),\
  75 }
  76
  77
  78 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  79 { \
  80         .rate   = (_mhz) * KHZ, \
  81         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  82         .pllcon1 = PLL_CLKF_SET(nf),\
  83         .pllcon2 = PLL_CLK_BWADJ_SET(nf/2-1),\
  84         .rst_dly=((nr*500)/24+1),\
  85         }
  86 #ifndef CLK_LPJ_CALC
  87 #define _APLL_SET_LPJ(_mhz) \
  88         .lpj= CLK_LOOPS_JIFFY_REF * _mhz/CLK_LOOPS_RARE_REF
  89 #else
  90 #define _APLL_SET_LPJ(_mhz) \
  91         .lpj=0
  92 #endif
  93
  94 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,_axi_div, _ahb_div, _apb_div) \
  95         { \
  96         .rate   = _mhz * MHZ, \
  97         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no),\
  98         .pllcon1 = PLL_CLKF_SET(nf),\
  99         .pllcon2 = PLL_CLK_BWADJ_SET(nf>>1),\
 100         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 101         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div|\
 102         ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div,\
 103         ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div,\
 104         _APLL_SET_LPJ(_mhz),\
 105         .rst_dly=((nr*500)/24+1),\
 106         }
 107
 108 #define CRU_DIV_SET(mask,shift,max) \
 109         .div_mask=(mask),\
 110         .div_shift=(shift),\
 111         .div_max=(max)
 112
 113
 114 #define CRU_SRC_SET(mask,shift ) \
 115         .src_mask=(mask),\
 116         .src_shift=(shift)
 117
 118 #define CRU_PARENTS_SET(parents_array) \
 119         .parents=(parents_array),\
 120         .parents_num=ARRAY_SIZE((parents_array))
 121
 122 #define CRU_GATE_MODE_SET(_func,_IDX) \
 123         .mode=_func,\
 124         .gate_idx=(_IDX)
 125
 126 struct clk_src_sel {
 127         struct clk      *parent;
 128         u8      value;//crt bit
 129         u8      flag;
 130 //selgate
 131 };
 132
 133 #define GATE_CLK(NAME,PARENT,ID) \
 134 static struct clk clk_##NAME = { \
 135         .name           = #NAME, \
 136         .parent         = &PARENT, \
 137         .mode           = gate_mode, \
 138         .gate_idx       = CLK_GATE_##ID, \
 139 }
 140
 141
 142 #ifdef RK30_CLK_OFFBOARD_TEST
 143 fsdfdsf
 144 u32 TEST_GRF_REG[0x240];
 145 u32 TEST_CRU_REG[0x240];
 146 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 147
 148 u32 cru_writel_is_pr(u32 offset)
 149 {
 150         return (offset==0x4000);
 151 }
 152 void cru_writel(u32 v, u32 offset)
 153 {
 154
 155         u32 mask_v=v>>16;
 156         TEST_CRU_REG[offset/4]&=(~mask_v);
 157
 158         v&=(mask_v);
 159
 160         TEST_CRU_REG[offset/4]|=v;
 161         TEST_CRU_REG[offset/4]&=0x0000ffff;
 162
 163         if(cru_writel_is_pr(offset))
 164         {
 165                 printk("cru w offset=%d,set=%x,reg=%x\n",offset,v,TEST_CRU_REG[offset/4]);
 166
 167         }
 168
 169 }
 170 void cru_writel_i2s(u32 v, u32 offset)
 171 {
 172         TEST_CRU_REG[offset/4]=v;
 173 }
 174 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 175
 176 #define regfile_readl(offset)   (0xffffffff)
 177 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 178 void rk30_clkdev_add(struct clk_lookup *cl);
 179 #else
 180 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 181 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 182 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 183
 184 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 185 #endif
 186
 187
 188 #define CRU_PRINTK_DBG(fmt, args...) printk(fmt, ## args);
 189 #define CRU_PRINTK_ERR(fmt, args...) printk(fmt, ## args);
 190
 191
 192 #define get_cru_bits(con,mask,shift)\
 193         ((cru_readl((con)) >> (shift)) & (mask))
 194
 195 #define set_cru_bits_w_msk(val,mask,shift,con)\
 196         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 197
 198
 199 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 200         &&!(PLL_CONS(pll_id,3)&PLL_BYPASS))
 201
 202
 203
 204 static struct clk codec_pll_clk;
 205 static struct clk general_pll_clk;
 206 static struct clk arm_pll_clk;
 207 static unsigned long lpj_gpll;
 208 static unsigned int __initdata armclk = 504*MHZ;
 209
 210
 211 /************************calc_lpj*********************************/
 212
 213 void calc_lpj_ref(void)
 214 {
 215
 216 #ifdef CLK_LPJ_CALC
 217         arm_pll_clk.rate=arm_pll_clk.recalc(&arm_pll_clk);
 218         calibrate_delay();
 219         _clk_loops_per_jiffy=loops_per_jiffy;
 220         _clk_loops_rate_ref=arm_pll_clk.rate;
 221         CRU_PRINTK_DBG("loops_per_jiffy=%lu,rate=%lu\n",_clk_loops_per_jiffy,_clk_loops_rate_ref);
 222 #endif
 223 }
 224
 225
 226 /************************clk recalc div rate*********************************/
 227
 228 //for free div
 229 static unsigned long clksel_recalc_div(struct clk *clk)
 230 {
 231         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift) + 1;
 232
 233         unsigned long rate = clk->parent->rate / div;
 234         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 235         return rate;
 236 }
 237
 238 //for div 1 2 4 2^n
 239 static unsigned long clksel_recalc_shift(struct clk *clk)
 240 {
 241         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
 242         unsigned long rate = clk->parent->rate >> shift;
 243         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 244         return rate;
 245 }
 246
 247
 248 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 249 {
 250         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
 251         unsigned long rate = clk->parent->rate >> shift;
 252         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 253         return rate;
 254 }
 255
 256 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 257 {
 258         unsigned long rate = clk->parent->rate;
 259         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 260         return rate;
 261 }
 262 /********************************set div rate***********************************/
 263
 264 //for free div
 265 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 266 {
 267         u32 div;
 268         for (div = 0; div < clk->div_max; div++) {
 269                 u32 new_rate = clk->parent->rate / (div + 1);
 270                 if (new_rate <= rate) {
 271                         set_cru_bits_w_msk(div,clk->div_mask,clk->div_shift,clk->clksel_con);
 272                         //clk->rate = new_rate;
 273                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 274                         return 0;
 275                 }
 276         }
 277         return -ENOENT;
 278 }
 279
 280 //for div 1 2 4 2^n
 281 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 282 {
 283         u32 shift;
 284         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 285                 u32 new_rate = clk->parent->rate >> shift;
 286                 if (new_rate <= rate) {
 287                         set_cru_bits_w_msk(shift,clk->div_mask,clk->div_shift,clk->clksel_con);
 288                         clk->rate = new_rate;
 289                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 290                         return 0;
 291                 }
 292         }
 293         return -ENOENT;
 294 }
 295
 296 //for div 2 4 2^n
 297 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 298 {
 299         u32 shift;
 300
 301         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 302                 u32 new_rate = clk->parent->rate >> shift;
 303                 if (new_rate <= rate) {
 304                         set_cru_bits_w_msk(shift-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 305                         clk->rate = new_rate;
 306                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 307                         return 0;
 308                 }
 309         }
 310         return -ENOENT;
 311 }
 312 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate ,u32 div_max)
 313 {
 314         u32 div;
 315         unsigned long new_rate;
 316         for (div = 0; div <div_max; div++) {
 317                 new_rate = rate / (div + 1);
 318                 if (new_rate <= rate_out) {
 319                         return div+1;
 320                 }
 321         }
 322         return div_max?div_max:1;
 323 }
 324 struct clk *get_freediv_parents_div(struct clk *clk,unsigned long rate,u32 *div_out)
 325 {
 326         u32 div[2]={0,0};
 327         unsigned long new_rate[2]={0,0};
 328         u32 i;
 329
 330         if(clk->rate==rate)
 331                 return 0;
 332         for(i=0;i<2;i++)
 333         {
 334                 div[i]=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
 335                 new_rate[i] = clk->parents[i]->rate/div[i];
 336                 if(new_rate[i]==rate)
 337                 {
 338                         *div_out=div[i];
 339                         return clk->parents[i];
 340                 }
 341         }
 342         if(new_rate[0]<new_rate[1])
 343                 i=1;
 344         else
 345                 i=0;
 346         *div_out=div[i];
 347         return clk->parents[i];
 348 }
 349
 350 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 351 {
 352         struct clk *p_clk;
 353         u32 div;
 354         int ret=0;
 355         p_clk=get_freediv_parents_div(clk,rate,&div);
 356
 357         CRU_PRINTK_ERR("%s %lu,form %s\n",clk->name,rate,p_clk->name);
 358         if(!p_clk)
 359                 return -ENOENT;
 360
 361         if (clk->parent != p_clk)
 362         {
 363                 ret=clk_set_parent_nolock(clk,p_clk);
 364                 if(ret)
 365                 {
 366                         CRU_PRINTK_ERR("%s can't set %lu,reparent err\n",clk->name,rate);
 367                         return -ENOENT;
 368                 }
 369         }
 370         //set div
 371         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 372         return 0;
 373 }
 374
 375 //rate==div rate //hdmi
 376 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 377 {
 378         struct clk *p_clk;
 379         u32 div;
 380         p_clk=get_freediv_parents_div(clk,rate,&div);
 381
 382         if(!p_clk)
 383         return -ENOENT;
 384
 385         if((p_clk->rate/div)!=rate||(p_clk->rate%div))
 386         return -ENOENT;
 387
 388         if (clk->parent != p_clk)
 389         return clk_set_parent_nolock(clk,p_clk);
 390         //set div
 391         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 392         return 0;
 393 }
 394
 395 /***************************round********************************/
 396
 397 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 398 {
 399         return clk->parent->rate/clk_get_freediv(rate,clk->parent->rate,clk->div_max);
 400 }
 401
 402 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 403 {
 404         u32 div;
 405         struct clk *p_clk;
 406         p_clk=get_freediv_parents_div(clk,rate,&div);
 407         if(!p_clk)
 408                 return 0;
 409         return p_clk->rate/div;
 410 }
 411
 412 /**************************************others seting************************************/
 413
 414 static struct clk* clksel_get_parent(struct clk *clk)
 415 {
 416         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 417 }
 418 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 419 {
 420         u32 i;
 421         if (unlikely(!clk->parents))
 422                 return -EINVAL;
 423         for (i = 0; (i <clk->parents_num); i++) {
 424                 if (clk->parents[i]!= parent)
 425                 continue;
 426                 set_cru_bits_w_msk(i,clk->src_mask,clk->src_shift,clk->clksel_con);
 427                 return 0;
 428         }
 429         return -EINVAL;
 430 }
 431 /* Work around CRU_CLKGATE3_CON bit21~20 bug */
 432 static int gate_mode(struct clk *clk, int on)
 433 {
 434         unsigned long flags;
 435
 436         int idx = clk->gate_idx;
 437         if (idx >= CLK_GATE_MAX)
 438                 return -EINVAL;
 439         /* ddr reconfig may change gate */
 440         local_irq_save(flags);
 441         if(on)
 442                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 443         else
 444                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 445         local_irq_restore(flags);
 446         return 0;
 447 }
 448 /*****************************frac set******************************************/
 449
 450 static unsigned long clksel_recalc_frac(struct clk *clk)
 451 {
 452         unsigned long rate;
 453         u64 rate64;
 454         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 455         if (r == 0) // FPGA ?
 456                 return clk->parent->rate;
 457         numerator = r >> 16;
 458         denominator = r & 0xFFFF;
 459         rate64 = (u64)clk->parent->rate * numerator;
 460         do_div(rate64, denominator);
 461         rate = rate64;
 462         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 463         return rate;
 464 }
 465
 466 static u32 clk_gcd(u32 numerator, u32 denominator)
 467 {
 468         u32 a, b;
 469
 470         if (!numerator || !denominator)
 471                 return 0;
 472         if (numerator > denominator) {
 473                 a = numerator;
 474                 b = denominator;
 475         } else {
 476                 a = denominator;
 477                 b = numerator;
 478         }
 479         while (b != 0) {
 480                 int r = b;
 481                 b = a % b;
 482                 a = r;
 483         }
 484
 485         return a;
 486 }
 487
 488 static int frac_div_get_seting(unsigned long rate_out,unsigned long rate,
 489         u32 *numerator,u32 *denominator)
 490 {
 491         u32 gcd_vl;
 492         gcd_vl = clk_gcd(rate, rate_out);
 493         CRU_PRINTK_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n",rate_out,rate, gcd_vl);
 494
 495         if (!gcd_vl) {
 496                 CRU_PRINTK_ERR("gcd=0, i2s frac div is not be supported\n");
 497                 return -ENOENT;
 498         }
 499
 500         *numerator = rate_out / gcd_vl;
 501         *denominator = rate/ gcd_vl;
 502
 503         CRU_PRINTK_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 504                         *numerator, *denominator, *denominator / *numerator);
 505
 506         if (*numerator > 0xffff || *denominator > 0xffff||
 507                 (*denominator/(*numerator))<20) {
 508                 CRU_PRINTK_ERR("can't get a available nume and deno\n");
 509                 return -ENOENT;
 510         }
 511
 512         return 0;
 513
 514 }
 515 /* *********************pll **************************/
 516
 517 #define rk30_clock_udelay(a) udelay(a);
 518
 519 /*********************pll lock status**********************************/
 520 //#define GRF_SOC_CON0       0x15c
 521 static void pll_wait_lock(int pll_idx)
 522 {
 523         u32 pll_state[4]={1,0,2,3};
 524         u32 bit = 0x10u << pll_state[pll_idx];
 525         int delay = 2400000;
 526         while (delay > 0) {
 527                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 528                         break;
 529                 delay--;
 530         }
 531         if (delay == 0) {
 532                 CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
 533         }
 534 }
 535
 536
 537
 538 /***************************pll function**********************************/
 539 static unsigned long pll_clk_recalc(u32 pll_id,unsigned long parent_rate)
 540 {
 541         unsigned long rate;
 542
 543         if (PLLS_IN_NORM(pll_id)) {
 544                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id,0));
 545                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id,1));
 546
 547
 548                 u64 rate64 = (u64)parent_rate*PLL_NF(pll_con1);
 549
 550
 551                 CRU_PRINTK_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 552                         ,PLL_CONS(pll_id,1),pll_con1, rate64);
 553
 554
 555
 556                 //CRU_PRINTK_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 557         //CRU_PRINTK_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 558                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 559
 560                 do_div(rate64, PLL_NR(pll_con0));
 561                 do_div(rate64, PLL_NO(pll_con0));
 562
 563                 rate = rate64;
 564
 565                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 566                         pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 567
 568         } else {
 569                 rate = parent_rate;
 570                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n",pll_id,rate);
 571         }
 572         return rate;
 573 }
 574 static unsigned long plls_clk_recalc(struct clk *clk)
 575 {
 576         return pll_clk_recalc(clk->pll->id,clk->parent->rate);
 577 }
 578
 579 static int pll_clk_set_rate(struct pll_clk_set *clk_set,u8 pll_id)
 580 {
 581         //enter slowmode
 582         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 583         //enter rest
 584         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 585         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id,0));
 586         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id,1));
 587         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2));
 588         rk30_clock_udelay(5);
 589
 590         //return form rest
 591         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 592
 593         //wating lock state
 594         rk30_clock_udelay(clk_set->rst_dly);
 595         pll_wait_lock(pll_id);
 596
 597         //return form slow
 598         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 599
 600         /*
 601         CRU_PRINTK_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 602                 cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 603         */
 604
 605
 606         return 0;
 607 }
 608 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 609 {
 610         struct _pll_data *pll_data=c->pll;
 611         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 612
 613         while(clk_set->rate)
 614         {
 615                 if (clk_set->rate == rate) {
 616                         break;
 617                 }
 618                 clk_set++;
 619         }
 620         if(clk_set->rate== rate)
 621         {
 622                 pll_clk_set_rate(clk_set,pll_data->id);
 623                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 624         }
 625         else
 626         {
 627                 CRU_PRINTK_ERR("gpll is no corresponding rate=%lu\n", rate);
 628                 return -1;
 629         }
 630         return 0;
 631 }
 632
 633 #define PLL_FREF_MIN (183*KHZ)
 634 #define PLL_FREF_MAX (1500*MHZ)
 635
 636 #define PLL_FVCO_MIN (300*MHZ)
 637 #define PLL_FVCO_MAX (1500*MHZ)
 638
 639 #define PLL_FOUT_MIN (18750*KHZ)
 640 #define PLL_FOUT_MAX (1500*MHZ)
 641
 642 #define PLL_NF_MAX (4096)
 643 #define PLL_NR_MAX (64)
 644 #define PLL_NO_MAX (16)
 645
 646 static int pll_clk_get_set(unsigned long fin_hz,unsigned long fout_hz,u32 *clk_nr,u32 *clk_nf,u32 *clk_no)
 647 {
 648         u32 nr,nf,no,nonr;
 649         u32 n;
 650         u32 YFfenzi;
 651         u32 YFfenmu;
 652         unsigned long fref,fvco,fout;
 653         u32 gcd_val=0;
 654
 655         CRU_PRINTK_DBG("pll_clk_get_set fin=%lu,fout=%lu\n",fin_hz,fout_hz);
 656         if(!fin_hz||!fout_hz||fout_hz==fin_hz)
 657                 return 0;
 658         gcd_val=clk_gcd(fin_hz,fout_hz);
 659         YFfenzi=fout_hz/gcd_val;
 660         YFfenmu=fin_hz/gcd_val;
 661
 662         for(n=1;;n++)
 663         {
 664                 nf=YFfenzi*n;
 665                 nonr=YFfenmu*n;
 666                 if(nf>PLL_NF_MAX||nonr>(PLL_NO_MAX*PLL_NR_MAX))
 667                  break;
 668                 for(no=1;no<=PLL_NO_MAX;no++)
 669                 {
 670                         if(!(no==1||!(no%2)))
 671                                 continue;
 672
 673                         if(nonr%no)
 674                                 continue;
 675                         nr=nonr/no;
 676
 677                         if(nr>PLL_NR_MAX)//PLL_NR_MAX
 678                                 continue;
 679
 680                         fref=fin_hz/nr;
 681                         if(fref<PLL_FREF_MIN||fref>PLL_FREF_MAX)
 682                                 continue;
 683
 684                         fvco=(fin_hz/nr)*nf;
 685                         if(fvco<PLL_FVCO_MIN||fvco>PLL_FVCO_MAX)
 686                                 continue;
 687                         fout=fvco/no;
 688                         if(fout<PLL_FOUT_MIN||fout>PLL_FOUT_MAX)
 689                                 continue;
 690                         *clk_nr=nr;
 691                         *clk_no=no;
 692                         *clk_nf=nf;
 693                         return 1;
 694
 695                 }
 696
 697         }
 698         return 0;
 699 }
 700
 701 static int pll_clk_mode(struct clk *clk, int on)
 702 {
 703         u8 pll_id=clk->pll->id;
 704         u32 nr=PLL_NR(cru_readl(PLL_CONS(pll_id,0)));
 705         u32 dly= (nr*500)/24+1;
 706
 707         if (on) {
 708                 cru_writel(PLL_PWR_ON|PLL_PWR_DN_W_MSK,PLL_CONS(pll_id,3));
 709                 rk30_clock_udelay(dly);
 710                 pll_wait_lock(pll_id);
 711                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 712         } else {
 713                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 714                 cru_writel(PLL_PWR_DN|PLL_PWR_DN_W_MSK, PLL_CONS(pll_id,3));
 715         }
 716         return 0;
 717 }
 718
 719 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 720 {
 721         struct _pll_data *pll_data=c->pll;
 722         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 723         struct pll_clk_set temp_clk_set;
 724         u32 clk_nr,clk_nf,clk_no;
 725
 726
 727         while(clk_set->rate)
 728         {
 729                 if (clk_set->rate == rate) {
 730                         break;
 731                 }
 732                 clk_set++;
 733         }
 734         if(clk_set->rate==rate)
 735         {
 736                 CRU_PRINTK_DBG("cpll get a rate\n");
 737                 pll_clk_set_rate(clk_set,pll_data->id);
 738
 739         }
 740         else
 741         {
 742                 CRU_PRINTK_DBG("cpll get auto calc a rate\n");
 743                 if(pll_clk_get_set(c->parent->rate,rate,&clk_nr,&clk_nf,&clk_no)==0)
 744                 {
 745                         pr_err("cpll auto set rate error\n");
 746                         return -ENOENT;
 747                 }
 748                 CRU_PRINTK_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n",clk_nr,clk_nf,clk_no);
 749                 temp_clk_set.pllcon0=PLL_CLKR_SET(clk_nr)|PLL_CLKOD_SET(clk_no);
 750                 temp_clk_set.pllcon1=PLL_CLKF_SET(clk_nf);
 751                 temp_clk_set.pllcon2=PLL_CLK_BWADJ_SET(clk_nf/2-1);
 752                 temp_clk_set.rst_dly=(clk_nr*500)/24+1;
 753                 pll_clk_set_rate(&temp_clk_set,pll_data->id);
 754
 755         }
 756         return 0;
 757 }
 758
 759
 760 /* ******************fixed input clk ***********************************************/
 761 static struct clk xin24m = {
 762         .name           = "xin24m",
 763         .rate           = 24 * MHZ,
 764         .flags          = RATE_FIXED,
 765 };
 766 static struct clk xin27m = {
 767         .name           = "xin27m",
 768         .rate           = 27 * MHZ,
 769         //CLK_GATE_XIN27M
 770         .flags          = RATE_FIXED,
 771
 772 };
 773 static struct clk clk_12m = {
 774         .name           = "clk_12m",
 775         .parent         =&xin24m,
 776         .rate           = 12 * MHZ,
 777         .flags          = RATE_FIXED,
 778 };
 779
 780 /************************************pll func***************************/
 781 static const struct apll_clk_set* arm_pll_clk_get_best_pll_set(unsigned long rate,
 782         struct apll_clk_set *tables)
 783 {
 784         const struct apll_clk_set *ps, *pt;
 785
 786         /* find the arm_pll we want. */
 787         ps = pt = tables;
 788         while (pt->rate) {
 789                 if (pt->rate == rate) {
 790                         ps = pt;
 791                         break;
 792                 }
 793                 // we are sorted, and ps->rate > pt->rate.
 794                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 795                         ps = pt;
 796                 if (pt->rate < rate)
 797                         break;
 798                 pt++;
 799         }
 800
 801         CRU_PRINTK_DBG("arm pll best rate=%lu\n",ps->rate);
 802         return ps;
 803 }
 804 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 805 {
 806         return arm_pll_clk_get_best_pll_set(rate,clk->pll->table)->rate;
 807 }
 808
 809 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 810 {
 811         unsigned long flags;
 812         const struct apll_clk_set *ps;
 813         u32 pll_id=clk->pll->id;
 814         u32 temp_div=0;
 815
 816
 817
 818         ps = arm_pll_clk_get_best_pll_set(rate,(struct apll_clk_set *)clk->pll->table);
 819
 820         printk("sel %x,%x\n",ps->clksel0,ps->clksel1);
 821
 822         if(general_pll_clk.rate>clk->rate)
 823         {
 824                 temp_div=general_pll_clk.rate/clk->rate+1;
 825                 cru_writel(CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 826         }
 827
 828         // open gpu gpll path
 829         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH)
 830                 , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 831
 832
 833         local_irq_save(flags);
 834         cru_writel(CORE_SEL_GPLL|CORE_SEL_PLL_W_MSK, CRU_CLKSELS_CON(0));
 835         //loops_per_jiffy = lpj_gpll;
 836
 837         /*if core src don't select gpll ,apll neet to enter slow mode */
 838         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 839
 840         //enter rest
 841         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 842         cru_writel(ps->pllcon0, PLL_CONS(pll_id,0));
 843         cru_writel(ps->pllcon1, PLL_CONS(pll_id,1));
 844         cru_writel(ps->pllcon2, PLL_CONS(pll_id,2));// ÏµÍ³ÓÐÎÊÌâ
 845
 846         local_irq_restore(flags);
 847         rk30_clock_udelay(5);
 848
 849         //return form rest
 850         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 851
 852         //wating lock state
 853         rk30_clock_udelay(ps->rst_dly);
 854         pll_wait_lock(pll_id);
 855
 856         local_irq_save(flags);
 857
 858         //return form slow
 859         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 860
 861         //a/h/p clk sel
 862         cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
 863         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 864
 865         //reparent to apll
 866         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_APLL, CRU_CLKSELS_CON(0));
 867         #ifndef CLK_LPJ_CALC
 868         //loops_per_jiffy = ps->lpj;
 869         #else
 870         //loops_per_jiffy = CLK_LOOPS_RECALC(rate);
 871         #endif
 872         local_irq_restore(flags);
 873
 874         //gate gpll path
 875         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
 876                 , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 877
 878 /*
 879         printk("apll %x,%x,%x,%x\n",cru_readl(PLL_CONS(pll_id,0)),
 880                 cru_readl(PLL_CONS(pll_id,1)),cru_readl(PLL_CONS(pll_id,2)),
 881                 cru_readl(PLL_CONS(pll_id,3)));
 882
 883         printk("sel %x,%x\n",cru_readl(CRU_CLKSELS_CON(0)),
 884                         cru_readl(CRU_CLKSELS_CON(1)));
 885 */
 886
 887         return 0;
 888 }
 889
 890
 891 /************************************pll clocks***************************/
 892
 893 static const struct apll_clk_set apll_clks[] = {
 894         _APLL_SET_CLKS(1416, 1, 59, 1, 8, 31, 21, 81),
 895         _APLL_SET_CLKS(1200, 1, 50, 1, 8, 31, 21, 81),
 896         _APLL_SET_CLKS(1008, 1, 42, 1, 8, 21, 21, 81),
 897         //_APLL_SET_CLKS(816 , 1, 34, 1, 8, 21, 21, 81),
 898         _APLL_SET_CLKS(800 , 24, 800, 1, 8, 41, 21, 81),
 899         _APLL_SET_CLKS(504 , 1, 21, 1, 4, 21, 21, 81),
 900         _APLL_SET_CLKS(252 , 1, 21, 2, 2, 21, 21, 41),
 901         _APLL_SET_CLKS(126 , 1, 21, 4, 2, 21, 21, 41),
 902         _APLL_SET_CLKS(0   , 1, 21, 4, 2, 21, 21, 41),
 903 };
 904 static struct _pll_data apll_data=SET_PLL_DATA(APLL_ID,(void *)apll_clks);
 905 static struct clk arm_pll_clk ={
 906         .name           = "arm_pll",
 907         .parent         = &xin24m,
 908         .recalc         = plls_clk_recalc,
 909         .set_rate       = arm_pll_clk_set_rate,
 910         .round_rate     = arm_pll_clk_round_rate,
 911         .pll=&apll_data,
 912  };
 913
 914 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 915 {
 916         /* do nothing here */
 917         return 0;
 918 }
 919 static struct _pll_data dpll_data=SET_PLL_DATA(DPLL_ID,NULL);
 920 static struct clk ddr_pll_clk = {
 921         .name           = "ddr_pll",
 922         .parent         = &xin24m,
 923         .recalc         = plls_clk_recalc,
 924         //.set_rate     = ddr_pll_clk_set_rate,
 925         .pll=&dpll_data,
 926 };
 927
 928 static const struct pll_clk_set cpll_clks[] = {
 929         _PLL_SET_CLKS(360000, 1,  15, 1),
 930         _PLL_SET_CLKS(408000, 1,  17, 1),
 931         _PLL_SET_CLKS(456000, 1,  19, 1),
 932         _PLL_SET_CLKS(504000, 1,  21, 1),
 933         _PLL_SET_CLKS(552000, 1,  23, 1),
 934         _PLL_SET_CLKS(600000, 1,  25, 1),
 935         _PLL_SET_CLKS(     0, 1,  23, 1),
 936 };
 937 static struct _pll_data cpll_data=SET_PLL_DATA(CPLL_ID,(void *)cpll_clks);
 938 static struct clk codec_pll_clk = {
 939         .name           = "codec_pll",
 940         .parent         = &xin24m,
 941         //.mode         = pll_clk_mode,
 942         .recalc         = plls_clk_recalc,
 943         .set_rate       = cpll_clk_set_rate,
 944         .pll= &cpll_data,
 945 };
 946
 947 static const struct pll_clk_set gpll_clks[] = {
 948         _PLL_SET_CLKS(148500,   4,      99,     4),
 949         _PLL_SET_CLKS(297000,   4,      99,     2),
 950         _PLL_SET_CLKS(1188000,  2,      99,     2),
 951         _PLL_SET_CLKS(0,                0,       0,     0),
 952 };
 953 static struct _pll_data gpll_data=SET_PLL_DATA(GPLL_ID,(void *)gpll_clks);
 954 static struct clk general_pll_clk = {
 955         .name           = "general_pll",
 956         .parent         = &xin24m,
 957         .recalc         = plls_clk_recalc,
 958         .set_rate       = gpll_clk_set_rate,
 959         .pll= &gpll_data
 960 };
 961 /********************************clocks***********************************/
 962
 963 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
 964 static struct clk clk_ddr = {
 965         .name           = "ddr",
 966         .parent         = &ddr_pll_clk,
 967         .recalc         = clksel_recalc_shift,
 968         .clksel_con     = CRU_CLKSELS_CON(26),
 969         //CRU_DIV_SET(0x3,0,4),
 970         //CRU_SRC_SET(1,8),
 971         //CRU_PARENTS_SET(clk_ddr_parents),
 972 };
 973 static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
 974 {
 975         int ret;
 976         //set arm pll div 1
 977         set_cru_bits_w_msk(0,c->div_mask,c->div_shift,c->clksel_con);
 978
 979         ret = clk_set_rate_nolock(c->parent, rate);
 980         if (ret) {
 981                 CRU_PRINTK_ERR("Failed to change clk pll %s to %lu\n",c->name,rate);
 982                 return ret;
 983         }
 984         return 0;
 985 }
 986 static unsigned long arm_core_clk_get_rate(struct clk *c)
 987 {
 988         u32 div=(get_cru_bits(c->clksel_con,c->div_mask,c->div_shift)+1);
 989         //c->parent->rate=c->parent->recalc(c->parent);
 990         return c->parent->rate/div;
 991 }
 992 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
 993 {
 994         u32 div=(get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1);
 995         return clk_round_rate_nolock(clk->parent,rate)/div;
 996 }
 997
 998 /*
 999 static struct clk clk_cpu_gpll_path = {
1000         .name   =  "core_gpll_path",
1001         .parent =  &general_pll_clk,
1002         CRU_GATE_MODE_SET(gate_mode,CLK_GATE_CPU_GPLL_PATH),
1003 };
1004 */
1005 //static struct clk *clk_cpu_parents[2] = {&arm_pll_clk,&clk_cpu_gpll_path};
1006
1007 static struct clk clk_cpu = {
1008         .name   =  "cpu",
1009         .parent =  &arm_pll_clk,
1010         .set_rate =     arm_core_clk_set_rate,
1011         .recalc =  arm_core_clk_get_rate,
1012         .round_rate     = core_clk_round_rate,
1013         .clksel_con     = CRU_CLKSELS_CON(0),
1014         //CRU_DIV_SET(0x1f,0,32),
1015         //CRU_SRC_SET(1,8),
1016         //CRU_PARENTS_SET(clk_cpu_parents),
1017 };
1018 static unsigned long aclk_cpu_recalc(struct clk *clk)
1019 {
1020         unsigned long rate;
1021         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
1022
1023         BUG_ON(div > 5);
1024         if (div >= 5)
1025                 div = 8;
1026         rate = clk->parent->rate / div;
1027         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1028
1029         return rate;
1030 };
1031 static struct clk core_periph = {
1032         .name           = "core_periph",
1033         .parent         = &clk_cpu,
1034         .recalc         = clksel_recalc_shift_2,
1035         .clksel_con     = CRU_CLKSELS_CON(0),
1036         CRU_DIV_SET(0x3,6,16),
1037 };
1038
1039 static struct clk aclk_cpu = {
1040         .name           = "aclk_cpu",
1041         .parent         = &clk_cpu,
1042         .recalc         = aclk_cpu_recalc,
1043         .clksel_con     = CRU_CLKSELS_CON(1),
1044         CRU_DIV_SET(0x7,0,8),
1045 };
1046
1047 static struct clk hclk_cpu = {
1048         .name           = "hclk_cpu",
1049         .parent         = &aclk_cpu,
1050         .recalc         = clksel_recalc_shift,
1051         //.set_rate     = clksel_set_rate_shift,
1052         .clksel_con     = CRU_CLKSELS_CON(1),
1053         CRU_DIV_SET(0x3,8,4),
1054
1055 };
1056
1057 static struct clk pclk_cpu = {
1058         .name           = "pclk_cpu",
1059         .parent         = &aclk_cpu,
1060         .recalc         = clksel_recalc_shift,
1061         //.set_rate     = clksel_set_rate_shift,
1062         .clksel_con     = CRU_CLKSELS_CON(1),
1063         CRU_DIV_SET(0x3,12,8),
1064 };
1065
1066 static struct clk atclk_cpu = {
1067         .name           = "atclk_cpu",
1068         .parent         = &pclk_cpu,
1069 };
1070
1071 static struct clk *clk_i2s_div_parents[]={&general_pll_clk,&codec_pll_clk};
1072 static struct clk clk_i2s_pll = {
1073         .name           = "i2s_pll",
1074         .parent         = &general_pll_clk,
1075         .clksel_con     = CRU_CLKSELS_CON(2),
1076         CRU_SRC_SET(0x1,16),
1077         CRU_PARENTS_SET(clk_i2s_div_parents),
1078 };
1079
1080 static struct clk clk_i2s0_div = {
1081         .name           = "i2s0_div",
1082         .parent = &clk_i2s_pll,
1083         .mode           = gate_mode,
1084         .recalc         = clksel_recalc_div,
1085         .set_rate       = clksel_set_rate_freediv,
1086         .round_rate     =clksel_freediv_round_rate,
1087         .gate_idx       = CLK_GATE_I2S0,
1088         .clksel_con     = CRU_CLKSELS_CON(2),
1089         CRU_DIV_SET(0x7f,0,64),
1090 };
1091
1092 static struct clk clk_i2s1_div = {
1093         .name           = "i2s1_div",
1094         .parent = &clk_i2s_pll,
1095         .recalc         = clksel_recalc_div,
1096         .set_rate       = clksel_set_rate_freediv,
1097         .round_rate     =clksel_freediv_round_rate,
1098         .mode           = gate_mode,
1099         .gate_idx       = CLK_GATE_I2S1,
1100         .clksel_con     = CRU_CLKSELS_CON(3),
1101         CRU_DIV_SET(0x7f,0,64),
1102 };
1103
1104
1105 static struct clk clk_i2s2_div = {
1106         .name           = "i2s2_div",
1107         .parent = &clk_i2s_pll,
1108         .recalc         = clksel_recalc_div,
1109         .set_rate       = clksel_set_rate_freediv,
1110         .round_rate     =clksel_freediv_round_rate,
1111         .mode           = gate_mode,
1112         .gate_idx       = CLK_GATE_I2S2,
1113         .clksel_con     = CRU_CLKSELS_CON(4),
1114         CRU_DIV_SET(0x7f,0,64),
1115 };
1116 static struct clk clk_spdif_div = {
1117         .name           = "spdif_div",
1118         .parent = &clk_i2s_pll,
1119         .recalc         = clksel_recalc_div,
1120         .set_rate       = clksel_set_rate_freediv,
1121         .round_rate     =clksel_freediv_round_rate,
1122         .mode           = gate_mode,
1123         .gate_idx       = CLK_GATE_SPDIF,
1124         .clksel_con     = CRU_CLKSELS_CON(5),
1125         CRU_DIV_SET(0x7f,0,64),
1126 };
1127 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1128 {
1129         u32 numerator, denominator;
1130         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1131         //clk->parent->parent
1132         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1133                         &numerator,&denominator)==0)
1134         {
1135                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1136                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1137                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1138         }
1139         else
1140         {
1141                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1142                 return -ENOENT;
1143         }
1144         return 0;
1145 }
1146
1147
1148 static struct clk clk_i2s0_frac_div = {
1149         .name           = "i2s0_frac_div",
1150         .parent         = &clk_i2s0_div,
1151         .mode           = gate_mode,
1152         .gate_idx       = CLK_GATE_I2S0_FRAC,
1153         .recalc         = clksel_recalc_frac,
1154         .set_rate       = clk_i2s_fracdiv_set_rate,
1155         .clksel_con     = CRU_CLKSELS_CON(6),
1156 };
1157
1158 static struct clk clk_i2s1_frac_div = {
1159         .name           = "i2s1_frac_div",
1160         .parent         = &clk_i2s1_div,
1161         .mode           = gate_mode,
1162         .gate_idx       = CLK_GATE_I2S1_FRAC,
1163         .recalc         = clksel_recalc_frac,
1164         .set_rate       = clk_i2s_fracdiv_set_rate,
1165         .clksel_con     = CRU_CLKSELS_CON(7),
1166 };
1167
1168 static struct clk clk_i2s2_frac_div = {
1169         .name           = "i2s2_frac_div",
1170         .mode           = gate_mode,
1171         .gate_idx       = CLK_GATE_I2S2_FRAC,
1172         .parent         = &clk_i2s2_div,
1173         .recalc         = clksel_recalc_frac,
1174         .set_rate       = clk_i2s_fracdiv_set_rate,
1175         .clksel_con     = CRU_CLKSELS_CON(7),
1176 };
1177 static struct clk clk_spdif_frac_div = {
1178         .name           = "spdif_frac_div",
1179         .parent         = &clk_spdif_div,
1180         .mode           = gate_mode,
1181         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1182         .recalc         = clksel_recalc_frac,
1183         .set_rate       = clk_i2s_fracdiv_set_rate,
1184         .clksel_con     = CRU_CLKSELS_CON(9),
1185 };
1186
1187 #define I2S_SRC_DIV  (0x0)
1188 #define I2S_SRC_FRAC  (0x1)
1189 #define I2S_SRC_12M  (0x2)
1190
1191 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1192 {
1193         int ret = -EINVAL;
1194         struct clk *parent;
1195
1196         if (rate == clk->parents[I2S_SRC_12M]->rate){
1197                 parent = clk->parents[I2S_SRC_12M];
1198         }else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV],rate)==rate)
1199         {
1200                 parent = clk->parents[I2S_SRC_DIV];
1201         }
1202         else
1203         {
1204                 parent =clk->parents[I2S_SRC_FRAC];
1205         }
1206
1207         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1208                 clk->name,rate,parent->name,clk->parent->name);
1209
1210         if (clk->parent != parent)
1211         {
1212                 ret = clk_set_parent_nolock(clk, parent);
1213                 if (ret)
1214                 {
1215                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1216                         return ret;
1217                 }
1218         }
1219         if(parent!=clk->parents[I2S_SRC_12M])
1220         {
1221                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
1222         }
1223
1224         return ret;
1225 };
1226
1227 static struct clk *clk_i2s0_parents[3]={&clk_i2s0_div,&clk_i2s0_frac_div,&clk_12m};
1228
1229 static struct clk clk_i2s0 = {
1230         .name           = "i2s0",
1231         .set_rate       = i2s_set_rate,
1232         .clksel_con     = CRU_CLKSELS_CON(2),
1233         CRU_SRC_SET(0x3,8),
1234         CRU_PARENTS_SET(clk_i2s0_parents),
1235 };
1236
1237 static struct clk *clk_i2s1_parents[3]={&clk_i2s1_div,&clk_i2s1_frac_div,&clk_12m};
1238
1239 static struct clk clk_i2s1 = {
1240         .name           = "i2s1",
1241         .set_rate       = i2s_set_rate,
1242         .clksel_con     = CRU_CLKSELS_CON(3),
1243         CRU_SRC_SET(0x3,8),
1244         CRU_PARENTS_SET(clk_i2s1_parents),
1245 };
1246
1247 static struct clk *clk_i2s2_parents[3]={&clk_i2s2_div,&clk_i2s2_frac_div,&clk_12m};
1248
1249 static struct clk clk_i2s2 = {
1250         .name           = "i2s2",
1251         .set_rate       = i2s_set_rate,
1252         .clksel_con     = CRU_CLKSELS_CON(3),
1253         CRU_SRC_SET(0x3,8),
1254         CRU_PARENTS_SET(clk_i2s2_parents),
1255 };
1256
1257 static struct clk *clk_spdif_parents[3]={&clk_spdif_div,&clk_spdif_frac_div,&clk_12m};
1258
1259 static struct clk clk_spdif = {
1260         .name           = "spdif",
1261         .parent         = &clk_spdif_frac_div,
1262         .set_rate       = i2s_set_rate,
1263         .clksel_con = CRU_CLKSELS_CON(4),
1264         CRU_SRC_SET(0x3,8),
1265         CRU_PARENTS_SET(clk_spdif_parents),
1266 };
1267
1268 static struct clk *aclk_periph_parents[2]={&general_pll_clk,&codec_pll_clk};
1269
1270 static struct clk aclk_periph = {
1271         .name           = "aclk_periph",
1272         .parent         = &general_pll_clk,
1273         .mode           = gate_mode,
1274         .gate_idx       = CLK_GATE_ACLK_PEIRPH,
1275         .recalc         = clksel_recalc_div,
1276         .set_rate       = clksel_set_rate_freediv,
1277         .clksel_con     = CRU_CLKSELS_CON(10),
1278         CRU_DIV_SET(0x1f,0,32),
1279         CRU_SRC_SET(1,15),
1280         CRU_PARENTS_SET(aclk_periph_parents),
1281 };
1282
1283 static struct clk pclk_periph = {
1284         .name           = "pclk_periph",
1285         .parent         = &aclk_periph,
1286         .mode           = gate_mode,
1287         .gate_idx       = CLK_GATE_PCLK_PEIRPH,
1288         .recalc         = clksel_recalc_shift,
1289         .set_rate       = clksel_set_rate_shift,
1290         .clksel_con     = CRU_CLKSELS_CON(10),
1291         CRU_DIV_SET(0x3,12,8),
1292 };
1293
1294 static struct clk hclk_periph = {
1295         .name           = "hclk_periph",
1296         .parent         = &aclk_periph,
1297         .mode           = gate_mode,
1298         .gate_idx       = CLK_GATE_HCLK_PEIRPH,
1299         .recalc         = clksel_recalc_shift,
1300         .set_rate       = clksel_set_rate_shift,
1301         .clksel_con = CRU_CLKSELS_CON(10),
1302         CRU_DIV_SET(0x3,8,4),
1303 };
1304
1305 static struct clk clk_spi0 = {
1306         .name           = "spi0",
1307         .parent         = &pclk_periph,
1308         .mode           = gate_mode,
1309         .recalc         = clksel_recalc_div,
1310         .set_rate       = clksel_set_rate_freediv,
1311         .gate_idx       = CLK_GATE_SPI0,
1312         .clksel_con     = CRU_CLKSELS_CON(25),
1313         CRU_DIV_SET(0x7f,0,128),
1314 };
1315
1316 static struct clk clk_spi1 = {
1317         .name           = "spi1",
1318         .parent         = &pclk_periph,
1319         .mode           = gate_mode,
1320         .recalc         = clksel_recalc_div,
1321         .set_rate       = clksel_set_rate_freediv,
1322         .gate_idx       = CLK_GATE_SPI1,
1323         .clksel_con     = CRU_CLKSELS_CON(25),
1324         CRU_DIV_SET(0x7f,8,128),
1325 };
1326
1327 static struct clk clk_saradc = {
1328         .name           = "saradc",
1329         .parent         = &xin24m,
1330         .mode           = gate_mode,
1331         .recalc         = clksel_recalc_div,
1332         .set_rate       = clksel_set_rate_freediv,
1333         .gate_idx       =  CLK_GATE_SARADC,
1334         .clksel_con     =CRU_CLKSELS_CON(24),
1335         CRU_DIV_SET(0xff,8,256),
1336 };
1337 static struct clk clk_tsadc = {
1338         .name           = "tsadc",
1339         .parent         = &xin24m,
1340         .mode           = gate_mode,
1341         .recalc         = clksel_recalc_div,
1342         .set_rate       = clksel_set_rate_freediv,
1343         .gate_idx       = CLK_GATE_TSADC,
1344         .clksel_con =CRU_CLKSELS_CON(34),
1345         CRU_DIV_SET(0xffff,0,65536),
1346 };
1347 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1348 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1349
1350
1351 GATE_CLK(smc, pclk_periph, SMC);//smc
1352
1353 static struct clk clk_sdmmc = {
1354         .name           = "sdmmc",
1355         .parent         = &hclk_periph,
1356         .mode           = gate_mode,
1357         .recalc         = clksel_recalc_div,
1358         .set_rate       = clksel_set_rate_freediv,
1359         .gate_idx       = CLK_GATE_MMC0,
1360         .clksel_con =CRU_CLKSELS_CON(11),
1361         CRU_DIV_SET(0x3f,0,64),
1362 };
1363
1364 static struct clk clk_sdio = {
1365         .name           = "sdio",
1366         .parent         = &hclk_periph,
1367         .mode           = gate_mode,
1368         .recalc         = clksel_recalc_div,
1369         .set_rate       = clksel_set_rate_freediv,
1370         .gate_idx       = CLK_GATE_SDIO,
1371         .clksel_con =CRU_CLKSELS_CON(12),
1372         CRU_DIV_SET(0x3f,0,64),
1373
1374 };
1375
1376 static struct clk clk_emmc = {
1377         .name           = "emmc",
1378         .parent         = &hclk_periph,
1379         .mode           = gate_mode,
1380         .recalc         = clksel_recalc_div,
1381         .set_rate       = clksel_set_rate_freediv,
1382         .gate_idx       = CLK_GATE_EMMC,
1383         .clksel_con =CRU_CLKSELS_CON(12),
1384         CRU_DIV_SET(0x3f,8,64),
1385 };
1386
1387 static struct clk *clk_uart_src_parents[2]={&general_pll_clk,&codec_pll_clk};
1388 static struct clk clk_uart_pll = {
1389         .name           = "uart_pll",
1390         .parent         = &general_pll_clk,
1391         .clksel_con =CRU_CLKSELS_CON(12),
1392         CRU_SRC_SET(0x1,15),
1393         CRU_PARENTS_SET(clk_uart_src_parents),
1394 };
1395 static struct clk clk_uart0_div = {
1396         .name           = "uart0_div",
1397         .parent         = &clk_uart_pll,
1398         .mode           = gate_mode,
1399         .gate_idx       = CLK_GATE_UART0,
1400         .recalc         = clksel_recalc_div,
1401         .set_rate       = clksel_set_rate_freediv,
1402         .round_rate     =clksel_freediv_round_rate,
1403         .clksel_con     = CRU_CLKSELS_CON(13),
1404         CRU_DIV_SET(0x7f,0,64),
1405 };
1406 static struct clk clk_uart1_div = {
1407         .name           = "uart1_div",
1408         .parent         = &clk_uart_pll,
1409         .mode           = gate_mode,
1410         .gate_idx       = CLK_GATE_UART1,
1411         .recalc         = clksel_recalc_div,
1412         .round_rate     =clksel_freediv_round_rate,
1413         .set_rate       = clksel_set_rate_freediv,
1414         .clksel_con     = CRU_CLKSELS_CON(14),
1415         CRU_DIV_SET(0x7f,0,64),
1416 };
1417
1418 static struct clk clk_uart2_div = {
1419         .name           = "uart2_div",
1420         .parent         = &clk_uart_pll,
1421         .mode           = gate_mode,
1422         .gate_idx       = CLK_GATE_UART2,
1423         .recalc         = clksel_recalc_div,
1424         .round_rate     =clksel_freediv_round_rate,
1425         .set_rate       = clksel_set_rate_freediv,
1426         .clksel_con     = CRU_CLKSELS_CON(15),
1427         CRU_DIV_SET(0x7f,0,64),
1428 };
1429
1430 static struct clk clk_uart3_div = {
1431         .name           = "uart3_div",
1432         .parent         = &clk_uart_pll,
1433         .mode           = gate_mode,
1434         .gate_idx       = CLK_GATE_UART3,
1435         .recalc         = clksel_recalc_div,
1436         .round_rate     =clksel_freediv_round_rate,
1437         .set_rate       = clksel_set_rate_freediv,
1438         .clksel_con     = CRU_CLKSELS_CON(16),
1439         CRU_DIV_SET(0x7f,0,64),
1440 };
1441 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1442 {
1443         u32 numerator, denominator;
1444         //clk_uart0_div->clk_uart_pll->gpll/cpll
1445         //clk->parent->parent
1446         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1447                         &numerator,&denominator)==0)
1448         {
1449                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1450
1451                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1452
1453                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1454         }
1455         else
1456         {
1457                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1458                 return -ENOENT;
1459         }
1460         return 0;
1461 }
1462
1463 static struct clk clk_uart0_frac_div = {
1464         .name           = "uart0_frac_div",
1465         .parent         = &clk_uart0_div,
1466         .mode           = gate_mode,
1467         .recalc         = clksel_recalc_frac,
1468         .set_rate       = clk_uart_fracdiv_set_rate,
1469         .gate_idx       = CLK_GATE_FRAC_UART0,
1470         .clksel_con     = CRU_CLKSELS_CON(17),
1471 };
1472 static struct clk clk_uart1_frac_div = {
1473         .name           = "uart1_frac_div",
1474         .parent         = &clk_uart1_div,
1475         .mode           = gate_mode,
1476         .recalc         = clksel_recalc_frac,
1477         .set_rate       = clk_uart_fracdiv_set_rate,
1478         .gate_idx       = CLK_GATE_FRAC_UART1,
1479         .clksel_con     = CRU_CLKSELS_CON(18),
1480 };
1481 static struct clk clk_uart2_frac_div = {
1482         .name           = "uart2_frac_div",
1483         .mode           = gate_mode,
1484         .parent         = &clk_uart2_div,
1485         .recalc         = clksel_recalc_frac,
1486         .set_rate       = clk_uart_fracdiv_set_rate,
1487         .gate_idx       = CLK_GATE_FRAC_UART2,
1488         .clksel_con     = CRU_CLKSELS_CON(19),
1489 };
1490 static struct clk clk_uart3_frac_div = {
1491         .name           = "uart3_frac_div",
1492         .parent         = &clk_uart3_div,
1493         .mode           = gate_mode,
1494         .recalc         = clksel_recalc_frac,
1495         .set_rate       = clk_uart_fracdiv_set_rate,
1496         .gate_idx       = CLK_GATE_FRAC_UART3,
1497         .clksel_con     = CRU_CLKSELS_CON(20),
1498 };
1499
1500
1501 #define UART_SRC_DIV 0
1502 #define UART_SRC_FRAC 1
1503 #define UART_SRC_24M 2
1504
1505 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1506 {
1507         int ret = 0;
1508         struct clk *parent;
1509
1510         if(rate==clk->parents[UART_SRC_24M]->rate)//24m
1511         {
1512                 parent = clk->parents[UART_SRC_24M];
1513         }
1514         else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate)==rate)
1515         {
1516                 parent = clk->parents[UART_SRC_DIV];
1517         }
1518         else
1519         {
1520                 parent = clk->parents[UART_SRC_FRAC];
1521         }
1522
1523
1524
1525         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1526                 clk->name,rate,parent->name,clk->parent->name);
1527
1528
1529         if (clk->parent != parent)
1530         {
1531                 ret = clk_set_parent_nolock(clk, parent);
1532                 if (ret)
1533                 {
1534                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1535                         return ret;
1536                 }
1537         }
1538
1539         if(parent!=clk->parents[UART_SRC_24M])
1540         {
1541                 ret = clk_set_rate_nolock(parent,rate);
1542         }
1543
1544         return ret;
1545 }
1546
1547
1548 static struct clk *clk_uart0_parents[3]={&clk_uart0_div,&clk_uart0_frac_div,&xin24m};
1549 static struct clk clk_uart0 = {
1550         .name           = "uart0",
1551         .set_rate       = clk_uart_set_rate,
1552         .clksel_con     = CRU_CLKSELS_CON(13),
1553         CRU_SRC_SET(0x3,8),
1554         CRU_PARENTS_SET(clk_uart0_parents),
1555 };
1556
1557 static struct clk *clk_uart1_parents[3]={&clk_uart1_div,&clk_uart1_frac_div,&xin24m};
1558 static struct clk clk_uart1 = {
1559         .name           = "uart1",
1560         .set_rate       = clk_uart_set_rate,
1561         .clksel_con     = CRU_CLKSELS_CON(14),
1562         CRU_SRC_SET(0x3,8),
1563         CRU_PARENTS_SET(clk_uart1_parents),
1564 };
1565
1566 static struct clk *clk_uart2_parents[3]={&clk_uart2_div,&clk_uart2_frac_div,&xin24m};
1567 static struct clk clk_uart2 = {
1568         .name           = "uart2",
1569         .set_rate       = clk_uart_set_rate,
1570         .clksel_con     = CRU_CLKSELS_CON(15),
1571         CRU_SRC_SET(0x3,8),
1572         CRU_PARENTS_SET(clk_uart2_parents),
1573 };
1574 static struct clk *clk_uart3_parents[3]={&clk_uart3_div,&clk_uart3_frac_div,&xin24m};
1575 static struct clk clk_uart3 = {
1576         .name           = "uart3",
1577         .set_rate       = clk_uart_set_rate,
1578         .clksel_con     = CRU_CLKSELS_CON(16),
1579         CRU_SRC_SET(0x3,8),
1580         CRU_PARENTS_SET(clk_uart3_parents),
1581 };
1582
1583 GATE_CLK(timer0, xin24m, TIMER0);
1584 GATE_CLK(timer1, xin24m, TIMER1);
1585 GATE_CLK(timer2, xin24m, TIMER2);
1586
1587 static struct clk rmii_clkin = {
1588         .name           = "rmii_clkin",
1589 };
1590 static struct clk *clk_mac_ref_div_parents[2]={&general_pll_clk,&ddr_pll_clk};
1591 static struct clk clk_mac_pll_div = {
1592         .name           = "mac_pll_div",
1593         .parent         = &ddr_pll_clk,
1594         .mode           = gate_mode,
1595         .gate_idx       = CLK_GATE_MAC,
1596         .recalc         = clksel_recalc_div,
1597         .set_rate       =clksel_set_rate_freediv,
1598         //.set_rate     = clksel_set_rate_freediv,
1599         .clksel_con     =CRU_CLKSELS_CON(21),
1600         CRU_DIV_SET(0x1f,8,32),
1601         CRU_SRC_SET(0x1,0),
1602         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1603 };
1604
1605 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1606 {
1607
1608         if(clk->parent==clk->parents[1])
1609         {
1610                 CRU_PRINTK_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1611                 return -ENOENT;
1612         }
1613         else if(clk->parent==clk->parents[0])
1614         {
1615         return clk_set_rate_nolock(clk->parents[0],rate);
1616         }
1617         return -ENOENT;
1618 }
1619
1620 static struct clk *clk_mac_ref_parents[2]={&clk_mac_pll_div,&rmii_clkin};
1621
1622 static struct clk clk_mac_ref = {
1623         .name           = "mac_ref",
1624         .parent         = &clk_mac_pll_div,
1625         .set_rate       = clksel_mac_ref_set_rate,
1626         .clksel_con =CRU_CLKSELS_CON(21),
1627         CRU_SRC_SET(0x1,4),
1628         CRU_PARENTS_SET(clk_mac_ref_parents),
1629 };
1630
1631 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1632 {
1633         return clk_set_parent_nolock(clk->parent,parent);
1634 }
1635
1636 static struct clk clk_mii_tx = {
1637         .name           = "mii_tx",
1638         .parent         = &clk_mac_ref,
1639         //.set_parent   = clk_set_mii_tx_parent,
1640         .mode           = gate_mode,
1641         .gate_idx       = CLK_GATE_MAC_LBTEST,//???
1642 };
1643
1644 static struct clk *clk_hsadc_pll_parents[2]={&general_pll_clk,&codec_pll_clk};
1645 static struct clk clk_hsadc_pll_div = {
1646         .name           = "hsadc_pll_div",
1647         .parent         = &general_pll_clk,
1648         .mode           = gate_mode,
1649         .gate_idx       = CLK_GATE_SARADC,
1650         .recalc         = clksel_recalc_div,
1651         .round_rate     =clk_freediv_round_autosel_parents_rate,
1652         .set_rate       = clkset_rate_freediv_autosel_parents,
1653         //.round_rate =clksel_freediv_round_rate,
1654         //.set_rate     = clksel_set_rate_freediv,
1655         .clksel_con =CRU_CLKSELS_CON(22),
1656         CRU_DIV_SET(0xff,8,256),
1657         CRU_SRC_SET(0x1,0),
1658         CRU_PARENTS_SET(clk_hsadc_pll_parents),
1659 };
1660
1661 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
1662 {
1663         u32 numerator, denominator;
1664         //        clk_hsadc_pll_div->gpll/cpll
1665         //clk->parent->parent
1666         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1667                         &numerator,&denominator)==0)
1668         {
1669                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1670
1671                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1672
1673                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1674         }
1675         else
1676         {
1677                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1678                 return -ENOENT;
1679         }
1680         return 0;
1681 }
1682 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
1683 {
1684         u32 numerator, denominator;
1685         u32 i,ret=0;
1686         //        clk_hsadc_pll_div->gpll/cpll
1687         //clk->parent->parent
1688         for(i=0;i<2;i++)
1689         {
1690                 if(frac_div_get_seting(rate,clk->parent->parents[i]->rate,
1691                         &numerator,&denominator)==0)
1692                         break;
1693         }
1694         if(i>=2)
1695                 return -ENOENT;
1696
1697         if(clk->parent->parent!=clk->parent->parents[i])
1698                 ret=clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
1699         if(ret==0)
1700         {
1701                 clk_set_rate_nolock(clk->parent,clk->parent->parents[i]->rate);//PLL:DIV 1:
1702
1703                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1704
1705                 CRU_PRINTK_DBG("clk_frac_div %s, rate=%lu\n",clk->name,rate);
1706         }
1707         else
1708         {
1709                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1710                 return -ENOENT;
1711         }
1712         return 0;
1713 }
1714
1715 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
1716 {
1717         u32 numerator, denominator;
1718
1719         CRU_PRINTK_ERR("clk_hsadc_fracdiv_round_rate\n");
1720         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1721                         &numerator,&denominator)==0)
1722                 return rate;
1723
1724         return 0;
1725 }
1726 static struct clk clk_hsadc_frac_div = {
1727         .name           = "hsadc_frac_div",
1728         .parent         = &clk_hsadc_pll_div,
1729         .mode           = gate_mode,
1730         .recalc         = clksel_recalc_frac,
1731         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
1732         .round_rate     =clk_hsadc_fracdiv_round_rate,
1733         .gate_idx       = CLK_GATE_HSADC_FRAC,
1734         .clksel_con     = CRU_CLKSELS_CON(23),
1735 };
1736
1737 #define HSADC_SRC_DIV 0x0
1738 #define HSADC_SRC_FRAC 0x1
1739 #define HSADC_SRC_EXT 0x2
1740 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
1741 {
1742         int ret = -EINVAL;
1743         struct clk *parent;
1744
1745         if(clk->parent == clk->parents[HSADC_SRC_EXT]){
1746                 CRU_PRINTK_DBG("hsadc clk is form ext\n");
1747                 return 0;
1748         }
1749         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV],rate)==rate)
1750         {
1751                 parent =clk->parents[HSADC_SRC_DIV];
1752         }
1753         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC],rate)==rate)
1754         {
1755                 parent = clk->parents[HSADC_SRC_FRAC];
1756         }
1757         else
1758                 parent =clk->parents[HSADC_SRC_DIV];
1759
1760         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1761                 clk->name,rate,parent->name,clk->parent->name);
1762
1763         if (clk->parent != parent)
1764         {
1765                 ret = clk_set_parent_nolock(clk, parent);
1766                 if (ret)
1767                 {
1768                         CRU_PRINTK_ERR("%s can't get rate%lu,reparent err\n",clk->name,rate);
1769                         return ret;
1770                 }
1771         }
1772         ret = clk_set_rate_nolock(parent,rate);
1773         return ret;
1774 }
1775
1776 static struct clk clk_hsadc_ext = {
1777         .name           = "hsadc_ext",
1778 };
1779
1780 static struct clk *clk_hsadc_parents[3]={&clk_hsadc_pll_div,&clk_hsadc_frac_div,&clk_hsadc_ext};
1781 static struct clk clk_hsadc = {
1782         .name           = "hsadc",
1783         .parent         = &clk_hsadc_pll_div,
1784         .set_rate       = clk_hsadc_set_rate,
1785         .clksel_con     = CRU_CLKSELS_CON(22),
1786         CRU_SRC_SET(0x3,4),
1787         CRU_PARENTS_SET(clk_hsadc_parents),
1788 };
1789
1790 static struct clk *dclk_lcdc_div_parents[]={&codec_pll_clk,&general_pll_clk};
1791 static struct clk dclk_lcdc0_div = {
1792         .name           = "dclk_lcdc0_div",
1793         .parent         = &general_pll_clk,
1794         .recalc         = clksel_recalc_div,
1795         .set_rate       = clkset_rate_freediv_autosel_parents,
1796         .clksel_con     = CRU_CLKSELS_CON(27),
1797         CRU_DIV_SET(0xff,8,256),
1798         CRU_SRC_SET(0x1,0),
1799         CRU_PARENTS_SET(dclk_lcdc_div_parents),
1800 };
1801
1802 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1803 {
1804         u32 div;
1805         div=clk_get_freediv(rate,clk->parent->rate,clk->div_max);
1806         if(rate==(clk->parent->rate/div)&&!(clk->parent->rate%div))
1807                 return 0;
1808         return -ENOENT;
1809 }
1810 //hdmi
1811 static struct clk dclk_lcdc1_div = {
1812         .name           = "dclk_lcdc1_div",
1813         .parent         = &general_pll_clk,
1814         .recalc         = clksel_recalc_div,
1815         .set_rate       = clksel_set_rate_hdmi,//clk_freediv_autosel_parents_set_fixed_rate
1816         .clksel_con     = CRU_CLKSELS_CON(28),
1817         CRU_DIV_SET(0xff,8,256),
1818         CRU_SRC_SET(0x1,0),
1819         CRU_PARENTS_SET(dclk_lcdc_div_parents),
1820 };
1821
1822 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1823 {
1824         int ret = 0;
1825         struct clk *parent;
1826
1827         if (rate == 27 * MHZ) {
1828                 parent =clk->parents[1];
1829         } else {
1830                 parent=clk->parents[0];
1831
1832         }
1833         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1834                         clk->name,rate,parent->name,clk->parent->name);
1835
1836         if (clk->parent != parent)
1837         {
1838                 ret = clk_set_parent_nolock(clk, parent);
1839                 if (ret)
1840                 {
1841                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1842                         return ret;
1843                 }
1844         }
1845         if(parent!=clk->parents[1])
1846         {
1847                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
1848         }
1849         return ret;
1850 }
1851
1852 static struct clk *dclk_lcdc0_parents[2]={&dclk_lcdc0_div,&xin27m};
1853 static struct clk dclk_lcdc0 = {
1854         .name           = "dclk_lcdc0",
1855         .mode           = gate_mode,
1856         .set_rate       = dclk_lcdc_set_rate,
1857         .gate_idx       = CLK_GATE_DCLK_LCDC0,
1858         .clksel_con     = CRU_CLKSELS_CON(27),
1859         CRU_SRC_SET(0x1,4),
1860         CRU_PARENTS_SET(dclk_lcdc0_parents),
1861 };
1862
1863 static struct clk *dclk_lcdc1_parents[2]={&dclk_lcdc1_div,&xin27m};
1864 static struct clk dclk_lcdc1 = {
1865         .name           = "dclk_lcdc1",
1866         .mode           = gate_mode,
1867         .set_rate       = dclk_lcdc_set_rate,
1868         .gate_idx       = CLK_GATE_DCLK_LCDC1,
1869         .clksel_con     = CRU_CLKSELS_CON(28),
1870         CRU_SRC_SET(0x1,4),
1871         CRU_PARENTS_SET(dclk_lcdc1_parents),
1872 };
1873
1874
1875 static struct clk *cifout_sel_pll_parents[2]={&codec_pll_clk,&general_pll_clk};
1876 static struct clk cif_out_pll = {
1877         .name           = "cif_out_pll",
1878         .parent         = &general_pll_clk,
1879         .clksel_con     = CRU_CLKSELS_CON(29),
1880         CRU_SRC_SET(0x1,0),
1881         CRU_PARENTS_SET(cifout_sel_pll_parents),
1882 };
1883
1884 static struct clk cif0_out_div = {
1885         .name           = "cif0_out_div",
1886         .parent         = &cif_out_pll,
1887         .mode           = gate_mode,
1888         .recalc         = clksel_recalc_div,
1889         .set_rate       = clksel_set_rate_freediv,
1890         .gate_idx       =CLK_GATE_CIF0_OUT,
1891         .clksel_con     = CRU_CLKSELS_CON(29),
1892         CRU_DIV_SET(0x1f,1,32),
1893 };
1894
1895 static struct clk cif1_out_div = {
1896         .name           = "cif1_out_div",
1897         .parent         = &cif_out_pll,
1898         .mode           = gate_mode,
1899         .recalc         = clksel_recalc_div,
1900         .set_rate       = clksel_set_rate_freediv,
1901         .gate_idx       =       CLK_GATE_CIF1_OUT,
1902         .clksel_con     = CRU_CLKSELS_CON(29),
1903         CRU_DIV_SET(0x1f,8,32),
1904 };
1905
1906
1907 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1908 {
1909         int ret = 0;
1910         struct clk *parent;
1911
1912         if (rate == 24 * MHZ) {
1913                 parent =clk->parents[1];
1914         } else {
1915                 parent=clk->parents[0];
1916                 ret = clk_set_rate_nolock(parent, rate);
1917                 if (ret)
1918                         return ret;
1919         }
1920         if (clk->parent != parent)
1921                 ret = clk_set_parent_nolock(clk, parent);
1922
1923         return ret;
1924 }
1925
1926 static struct clk *cif0_out_parents[2]={&cif0_out_div,&xin24m};
1927 static struct clk cif0_out = {
1928         .name           = "cif0_out",
1929         .parent         = &cif0_out_div,
1930         .set_rate       = cif_out_set_rate,
1931         .clksel_con     = CRU_CLKSELS_CON(29),
1932         CRU_SRC_SET(0x1,7),
1933         CRU_PARENTS_SET(cif0_out_parents),
1934 };
1935 static struct clk *cif1_out_parents[2]={&cif1_out_div,&xin24m};
1936
1937 static struct clk cif1_out = {
1938         .name           = "cif1_out",
1939         .parent         = &cif1_out_div,
1940         .set_rate       = cif_out_set_rate,
1941         .clksel_con     = CRU_CLKSELS_CON(29),
1942         CRU_SRC_SET(0x1,15),
1943         CRU_PARENTS_SET(cif1_out_parents),
1944 };
1945
1946 static struct clk pclkin_cif0 = {
1947         .name           = "pclkin_cif0",
1948         .mode           = gate_mode,
1949         .gate_idx       =CLK_GATE_PCLKIN_CIF0,
1950 };
1951
1952 static struct clk inv_cif0 = {
1953         .name           = "inv_cif0",
1954         .parent         = &pclkin_cif0,
1955 };
1956
1957 static struct clk *cif0_in_parents[2]={&pclkin_cif0,&inv_cif0};
1958 static struct clk cif0_in = {
1959         .name           = "cif0_in",
1960         .parent         = &pclkin_cif0,
1961         .clksel_con     = CRU_CLKSELS_CON(30),
1962         CRU_SRC_SET(0x1,8),
1963         CRU_PARENTS_SET(cif0_in_parents),
1964 };
1965
1966 static struct clk pclkin_cif1 = {
1967         .name           = "pclkin_cif1",
1968         .mode           = gate_mode,
1969         .gate_idx       =CLK_GATE_PCLKIN_CIF1,
1970 };
1971
1972 static struct clk inv_cif1 = {
1973         .name           = "inv_cif1",
1974         .parent         = &pclkin_cif1,
1975 };
1976 static struct clk *cif1_in_parents[2]={&pclkin_cif1,&inv_cif1};
1977
1978 static struct clk cif1_in = {
1979         .name           = "cif1_in",
1980         .parent         = &pclkin_cif1,
1981         .clksel_con     = CRU_CLKSELS_CON(30),
1982         CRU_SRC_SET(0x1,12),
1983         CRU_PARENTS_SET(cif1_in_parents),
1984 };
1985
1986 static struct clk *aclk_lcdc0_parents[]={&codec_pll_clk,&general_pll_clk};
1987
1988 static struct clk aclk_lcdc0 = {
1989         .name           = "aclk_lcdc0",
1990         .parent         = &codec_pll_clk,
1991         .mode           = gate_mode,
1992         .recalc         = clksel_recalc_div,
1993         .set_rate       = clkset_rate_freediv_autosel_parents,
1994         //.set_rate     = clksel_set_rate_freediv,
1995         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1996         .clksel_con     = CRU_CLKSELS_CON(31),
1997         CRU_DIV_SET(0x1f,0,32),
1998         CRU_SRC_SET(0x1,7),
1999         CRU_PARENTS_SET(aclk_lcdc0_parents),
2000 };
2001
2002 static struct clk *aclk_lcdc1_parents[]={&codec_pll_clk,&general_pll_clk};
2003
2004 static struct clk aclk_lcdc1 = {
2005         .name           = "aclk_lcdc1",
2006         .parent         = &codec_pll_clk,
2007         .mode           = gate_mode,
2008         .recalc         = clksel_recalc_div,
2009         .set_rate       = clkset_rate_freediv_autosel_parents,
2010         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
2011         .clksel_con     = CRU_CLKSELS_CON(31),
2012         CRU_DIV_SET(0x1f,8,32),
2013         CRU_SRC_SET(0x1,15),
2014         CRU_PARENTS_SET(aclk_lcdc1_parents),
2015 };
2016
2017
2018 //for free div
2019 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
2020 {
2021         unsigned long rate = clk->parent->rate / 4;
2022         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
2023         return rate;
2024 }
2025
2026 static struct clk *aclk_vepu_parents[2]={&codec_pll_clk,&general_pll_clk};
2027
2028 static struct clk aclk_vepu = {
2029         .name           = "aclk_vepu",
2030         .parent         = &codec_pll_clk,
2031         .mode           = gate_mode,
2032         .recalc         = clksel_recalc_div,
2033         //.set_rate     = clksel_set_rate_freediv,
2034         .set_rate       =clkset_rate_freediv_autosel_parents,
2035         .clksel_con     = CRU_CLKSELS_CON(32),
2036         .gate_idx       = CLK_GATE_ACLK_VEPU,
2037         CRU_DIV_SET(0x1f,0,32),
2038         CRU_SRC_SET(0x1,7),
2039         CRU_PARENTS_SET(aclk_vepu_parents),
2040 };
2041
2042 static struct clk hclk_vepu = {
2043         .name           = "hclk_vepu",
2044         .parent         = &aclk_vepu,
2045         .mode           = gate_mode,
2046         .recalc         = clksel_recalc_vpu_hclk,
2047         .clksel_con     = CRU_CLKSELS_CON(32),
2048         .gate_idx       = CLK_GATE_HCLK_VEPU,
2049 };
2050
2051 static struct clk *aclk_vdpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2052
2053 static struct clk aclk_vdpu = {
2054         .name           = "aclk_vdpu",
2055         .mode           = gate_mode,
2056         .recalc         = clksel_recalc_div,
2057         //.set_rate     = clksel_set_rate_freediv,
2058         .set_rate       =clkset_rate_freediv_autosel_parents,
2059         .clksel_con     = CRU_CLKSELS_CON(32),
2060         .gate_idx       = CLK_GATE_ACLK_VDPU,
2061         CRU_DIV_SET(0x1f,8,32),
2062         CRU_SRC_SET(0x1,15),
2063         CRU_PARENTS_SET(aclk_vdpu_parents),
2064 };
2065 static struct clk hclk_vdpu = {
2066         .name           = "hclk_vdpu",
2067         .parent         = &aclk_vdpu,
2068         .mode           = gate_mode,
2069         .recalc         = clksel_recalc_vpu_hclk,
2070         .clksel_con     = CRU_CLKSELS_CON(32),
2071         .gate_idx       = CLK_GATE_HCLK_VDPU,
2072 };
2073
2074
2075 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
2076 {
2077         unsigned long max_rate = rate / 100 * 105;      /* +5% */
2078         return clkset_rate_freediv_autosel_parents(clk,max_rate);
2079 };
2080
2081 static struct clk *gpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2082
2083 static struct clk clk_gpu = {
2084         .name           = "gpu",
2085         .mode           = gate_mode,
2086         .recalc         = clksel_recalc_div,
2087         .set_rate       = clkset_rate_freediv_autosel_parents,
2088         .clksel_con = CRU_CLKSELS_CON(33),
2089         .gate_idx       =  CLK_GATE_GPU_SRC,
2090         CRU_DIV_SET(0x1f,0,32),
2091         CRU_SRC_SET(0x1,8),
2092         CRU_PARENTS_SET(gpu_parents),
2093 };
2094
2095 /*********************power domain*******************************/
2096 #ifdef RK30_CLK_OFFBOARD_TEST
2097 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on){};
2098         #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2099 #else
2100 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2101         #define _pmu_set_power_domain pmu_set_power_domain
2102 #endif
2103 static int pm_off_mode(struct clk *clk, int on)
2104 {
2105          _pmu_set_power_domain(clk->gate_idx,1);//on 1
2106          return 0;
2107 }
2108 static struct clk pd_peri = {
2109         .name   = "pd_peri",
2110         .flags  = IS_PD,
2111         .mode   = pm_off_mode,
2112         .gate_idx       = PD_PERI,
2113 };
2114 static struct clk pd_display = {
2115         .name   = "pd_display",
2116         .flags  = IS_PD,
2117         .mode   = pm_off_mode,
2118         .gate_idx       = PD_VIO,
2119 };
2120
2121 static struct clk pd_lcdc0 = {
2122         .parent         = &pd_display,
2123         .name   = "pd_lcdc0",
2124         .flags  = IS_PD,
2125 };
2126 static struct clk pd_lcdc1 = {
2127         .parent         = &pd_display,
2128         .name   = "pd_lcdc1",
2129         .flags  = IS_PD,
2130 };
2131 static struct clk pd_cif0 = {
2132         .parent         = &pd_display,
2133         .name   = "pd_cif0",
2134         .flags  = IS_PD,
2135 };
2136 static struct clk pd_cif1 = {
2137         .parent         = &pd_display,
2138         .name   = "pd_cif1",
2139         .flags  = IS_PD,
2140 };
2141 static struct clk pd_rga = {
2142         .parent         = &pd_display,
2143         .name   = "pd_rga",
2144         .flags  = IS_PD,
2145 };
2146 static struct clk pd_ipp = {
2147         .parent         = &pd_display,
2148         .name   = "pd_ipp",
2149         .flags  = IS_PD,
2150 };
2151
2152 static struct clk pd_video = {
2153         .name   = "pd_video",
2154         .flags  = IS_PD,
2155         .mode   = pm_off_mode,
2156         .gate_idx       = PD_VIDEO,
2157 };
2158 static struct clk pd_gpu = {
2159         .name   = "pd_gpu",
2160         .flags  = IS_PD,
2161         .mode   = pm_off_mode,
2162         .gate_idx       = PD_GPU,
2163 };
2164 static struct clk pd_dbg = {
2165         .name   = "pd_dbg",
2166         .flags  = IS_PD,
2167         .mode   = pm_off_mode,
2168         .gate_idx       = PD_DBG,
2169 };
2170
2171 #define PD_CLK(name) \
2172 {\
2173         .dev_id = NULL,\
2174         .con_id = #name,\
2175         .clk = &name,\
2176 }
2177
2178
2179 /************************rk30 fixed div clock****************************************/
2180
2181 /*************************aclk_cpu***********************/
2182
2183 GATE_CLK(dma1, aclk_cpu,        ACLK_DMAC1);
2184 GATE_CLK(l2mem_con, aclk_cpu,   ACLK_L2MEM_CON);
2185 GATE_CLK(intmem, aclk_cpu,      ACLK_INTMEM);
2186 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2187
2188 /*************************hclk_cpu***********************/
2189
2190 GATE_CLK(rom, hclk_cpu, HCLK_ROM);
2191 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2192 GATE_CLK(hclk_i2s1_2ch, hclk_cpu,       HCLK_I2S1_2CH);
2193 GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
2194 GATE_CLK(hclk_i2s_8ch, hclk_cpu, HCLK_I2S_8CH);
2195 GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
2196 GATE_CLK(hclk_ahb2apb,  hclk_cpu, HCLK_AHB2APB);
2197 GATE_CLK(hclk_vio_bus,  hclk_cpu, HCLK_VIO_BUS);
2198 GATE_CLK(hclk_lcdc0,    hclk_cpu, HCLK_LCDC0);
2199 GATE_CLK(hclk_lcdc1,    hclk_cpu, HCLK_LCDC1);
2200 GATE_CLK(hclk_cif0,     hclk_cpu, HCLK_CIF0);
2201 GATE_CLK(hclk_cif1,     hclk_cpu, HCLK_CIF1);
2202 GATE_CLK(hclk_ipp,              hclk_cpu, HCLK_IPP);
2203 GATE_CLK(hclk_rga,              hclk_cpu, HCLK_RGA);
2204 GATE_CLK(hclk_hdmi,     hclk_cpu, HCLK_HDMI);
2205 //GATE_CLK(hclk_vidoe_h2h,      hclk_cpu, ); ???
2206 /*************************pclk_cpu***********************/
2207 GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2208 //GATE_CLK(pclk_pwm1,   pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2209 GATE_CLK(pclk_timer0,   pclk_cpu, PCLK_TIMER0);
2210 GATE_CLK(pclk_timer1,   pclk_cpu, PCLK_TIMER1);
2211 GATE_CLK(pclk_timer2,   pclk_cpu, PCLK_TIMER2);
2212 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2213 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2214 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2215 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2216 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2217 GATE_CLK(gpio6, pclk_cpu, PCLK_GPIO6);
2218 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2219 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2220 GATE_CLK(pclk_uart0,    pclk_cpu, PCLK_UART0);
2221 GATE_CLK(pclk_uart1,    pclk_cpu, PCLK_UART1);
2222 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2223 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2224 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2225 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2226 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2227
2228 /*************************aclk_periph***********************/
2229
2230 GATE_CLK(dma2, aclk_periph,ACLK_DMAC2);
2231 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2232 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2233 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2234 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2235
2236 /*************************hclk_periph***********************/
2237 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2238 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2239 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2240 GATE_CLK(hclk_emac, hclk_periph, HCLK_EMAC);
2241 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2242 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2243 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2244 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2245 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2246 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2247 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2248 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2249 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2250 /*************************pclk_periph***********************/
2251 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2252 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2253 //GATE_CLK(pclk_pwm3, pclk_periph, PCLK_PWM3);
2254 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2255 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2256 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2257 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2258 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2259 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2260 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2261 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2262 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2263 GATE_CLK(gpio4, pclk_periph, PCLK_GPIO4);
2264 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2265 GATE_CLK(pclk_tsadc, pclk_periph, PCLK_TSADC);
2266 /*************************aclk_lcdc0***********************/
2267 GATE_CLK(aclk_vio0, aclk_lcdc0, ACLK_VIO0);
2268 GATE_CLK(aclk_cif0, aclk_lcdc0, ACLK_CIF0);
2269 GATE_CLK(aclk_ipp, aclk_lcdc0, ACLK_IPP);
2270
2271 /*************************aclk_lcdc0***********************/
2272 GATE_CLK(aclk_vio1, aclk_lcdc1, ACLK_VIO1);
2273 GATE_CLK(aclk_cif1, aclk_lcdc1, ACLK_CIF0);
2274 GATE_CLK(aclk_rga, aclk_lcdc1, ACLK_RGA);
2275
2276
2277 #if 1
2278 #define CLK(dev, con, ck) \
2279  {\
2280         .dev_id = dev,\
2281         .con_id = con,\
2282         .clk = ck,\
2283  }
2284
2285
2286 #define CLK1(name) \
2287         {\
2288         .dev_id = NULL,\
2289         .con_id = #name,\
2290         .clk = &clk_##name,\
2291         }
2292
2293 #endif
2294
2295
2296
2297
2298 static struct clk_lookup clks[] = {
2299 #if 1
2300         CLK(NULL, "xin24m", &xin24m),
2301         CLK(NULL, "xin27m", &xin27m),
2302         CLK(NULL, "xin12m", &clk_12m),
2303         CLK(NULL, "arm_pll", &arm_pll_clk),
2304         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2305         CLK(NULL, "codec_pll", &codec_pll_clk),
2306         CLK(NULL, "general_pll", &general_pll_clk),
2307
2308         CLK(NULL, "ddr", &clk_ddr),
2309         //CLK(NULL, "core_gpll_path", &clk_cpu_gpll_path),
2310         CLK(NULL, "cpu", &clk_cpu),
2311         CLK(NULL, "smp_twd", &core_periph),
2312         CLK(NULL, "aclk_cpu", &aclk_cpu),
2313         CLK(NULL, "hclk_cpu", &hclk_cpu),
2314         CLK(NULL, "pclk_cpu", &pclk_cpu),
2315         CLK(NULL, "atclk_cpu", &atclk_cpu),
2316
2317
2318         CLK1(i2s_pll),
2319         CLK("rk30_i2s.0", "i2s_div", &clk_i2s0_div),
2320         CLK("rk30_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2321         CLK("rk30_i2s.0", "i2s", &clk_i2s0),
2322         CLK("rk30_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2323
2324         CLK("rk30_i2s.1", "i2s_div", &clk_i2s1_div),
2325         CLK("rk30_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
2326         CLK("rk30_i2s.1", "i2s", &clk_i2s1),
2327         CLK("rk30_i2s.1", "hclk_i2s", &clk_hclk_i2s1_2ch),
2328
2329         CLK("rk30_i2s.2", "i2s_div", &clk_i2s2_div),
2330         CLK("rk30_i2s.2", "i2s_frac_div", &clk_i2s2_frac_div),
2331         CLK("rk30_i2s.2", "i2s", &clk_i2s2),
2332         CLK("rk30_i2s.2", "hclk_i2s", &clk_hclk_i2s_8ch),
2333
2334         CLK1(spdif_div),
2335         CLK1(spdif_frac_div),
2336         CLK1(spdif),
2337         CLK1(hclk_spdif),
2338
2339         CLK(NULL, "aclk_periph", &aclk_periph),
2340         CLK(NULL, "pclk_periph", &pclk_periph),
2341         CLK(NULL, "hclk_periph", &hclk_periph),
2342
2343         CLK("rk30xx_spim.0", "spi", &clk_spi0),
2344         CLK("rk30xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2345
2346         CLK("rk30xx_spim.1", "spi", &clk_spi1),
2347         CLK("rk30xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2348
2349         CLK1(saradc),
2350         CLK1(pclk_saradc),
2351         CLK1(tsadc),
2352         CLK1(pclk_tsadc),
2353         CLK1(otgphy0),
2354         CLK1(otgphy1),
2355         CLK1(hclk_usb_peri),
2356         CLK1(hclk_otg0),
2357         CLK1(hclk_otg1),
2358
2359
2360
2361
2362
2363         CLK1(smc),
2364         CLK1(aclk_smc),
2365
2366         CLK1(sdmmc),
2367         CLK1(hclk_sdmmc),
2368
2369         CLK1(sdio),
2370         CLK1(hclk_sdio),
2371
2372         CLK1(emmc),
2373         CLK1(hclk_emmc),
2374
2375
2376         CLK1(uart_pll),
2377         CLK("rk30_serial.0", "uart_div", &clk_uart0_div),
2378         CLK("rk30_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2379         CLK("rk30_serial.0", "uart", &clk_uart0),
2380         CLK("rk30_serial.0", "pclk_uart", &clk_pclk_uart0),
2381         CLK("rk30_serial.1", "uart_div", &clk_uart1_div),
2382         CLK("rk30_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2383         CLK("rk30_serial.1", "uart", &clk_uart1),
2384         CLK("rk30_serial.1", "pclk_uart", &clk_pclk_uart1),
2385         CLK("rk30_serial.2", "uart_div", &clk_uart2_div),
2386         CLK("rk30_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2387         CLK("rk30_serial.2", "uart", &clk_uart2),
2388         CLK("rk30_serial.2", "pclk_uart", &clk_pclk_uart2),
2389         CLK("rk30_serial.3", "uart_div", &clk_uart3_div),
2390         CLK("rk30_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2391         CLK("rk30_serial.3", "uart", &clk_uart3),
2392         CLK("rk30_serial.3", "pclk_uart", &clk_pclk_uart3),
2393
2394         CLK1(timer0),
2395         CLK1(pclk_timer0),
2396
2397         CLK1(timer1),
2398         CLK1(pclk_timer1),
2399
2400         CLK1(timer2),
2401         CLK1(pclk_timer2),
2402
2403         CLK(NULL, "rmii_clkin", &rmii_clkin),
2404         CLK1(mac_pll_div),
2405         CLK1(mac_ref),
2406         CLK1(mii_tx),
2407         CLK1(hsadc_pll_div),
2408         CLK1(hsadc_frac_div),
2409         CLK1(hsadc_ext),
2410         CLK1(hsadc),
2411         CLK1(hclk_hsadc),
2412
2413
2414         CLK(NULL, "dclk_lcdc0_div", &dclk_lcdc0_div),
2415         CLK(NULL, "dclk_lcdc1_div", &dclk_lcdc1_div),
2416
2417         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2418         CLK(NULL, "aclk_lcdc0", &aclk_lcdc0),
2419         CLK1(hclk_lcdc0),
2420
2421         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2422         CLK(NULL, "aclk_lcdc1", &aclk_lcdc1),
2423         CLK1(hclk_lcdc1),
2424
2425         CLK(NULL, "cif_out_pll", &cif_out_pll),
2426         CLK(NULL, "cif0_out_div", &cif0_out_div),
2427         CLK(NULL, "cif1_out_div", &cif1_out_div),
2428
2429         CLK(NULL, "cif0_out", &cif0_out),
2430         CLK1(hclk_cif0),
2431
2432         CLK(NULL, "cif1_out", &cif1_out),
2433         CLK1(hclk_cif1),
2434
2435         CLK1(hclk_ipp),
2436         CLK1(hclk_rga),
2437         CLK1(hclk_hdmi),
2438
2439         CLK(NULL, "pclkin_cif0",        &pclkin_cif0),
2440         CLK(NULL, "inv_cif0",                   &inv_cif0),
2441         CLK(NULL, "cif0_in",                    &cif0_in),
2442         CLK(NULL, "pclkin_cif1", &pclkin_cif1),
2443         CLK(NULL, "inv_cif1",   &inv_cif1),
2444         CLK(NULL, "cif1_in",    &cif1_in),
2445         //CLK(NULL, "aclk_lcdc0",       &aclk_lcdc0),
2446         //CLK(NULL, "aclk_lcdc1",       &aclk_lcdc1),
2447         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2448         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2449         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2450         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2451         CLK1(gpu),
2452         CLK1(dma1),
2453         CLK1(l2mem_con),
2454         CLK1(intmem),
2455
2456         CLK1(aclk_strc_sys),
2457
2458         /*************************hclk_cpu***********************/
2459
2460         CLK1(rom),
2461         //CLK1(hclk_i2s0_2ch),
2462         //CLK1(hclk_i2s1_2ch),
2463         //CLK1(hclk_spdif),
2464         //CLK1(hclk_i2s_8ch),
2465         CLK1(hclk_cpubus),
2466         CLK1(hclk_ahb2apb),
2467         CLK1(hclk_vio_bus),
2468         //CLK1(hclk_lcdc0),
2469         //CLK1(hclk_lcdc1),
2470         //CLK1(hclk_cif0),
2471         //CLK1(hclk_cif1),
2472         //CLK1(hclk_ipp),
2473         //CLK1(hclk_rga),
2474         //CLK1(hclk_hdmi),
2475         //CLK1(hclk_vidoe_h2h,  hclk_cpu, ); ???
2476         /*************************pclk_cpu***********************/
2477         CLK1(pwm01),//pwm 0¡¢1
2478
2479         //CLK1(pclk_timer0),
2480         //CLK1(pclk_timer1),
2481         //CLK1(pclk_timer2),
2482
2483         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2484         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2485
2486         CLK1(gpio0),
2487         CLK1(gpio1),
2488         CLK1(gpio2),
2489         CLK1(gpio6),
2490         CLK1(efuse),
2491         CLK1(tzpc),
2492         //CLK1(pclk_uart0),
2493         //CLK1(pclk_uart1),
2494         CLK1(pclk_ddrupctl),
2495         CLK1(pclk_ddrpubl),
2496         CLK1(dbg),
2497         CLK1(grf),
2498         CLK1(pmu),
2499
2500         /*************************aclk_periph***********************/
2501
2502         CLK1(dma2),
2503         //CLK1(aclk_smc),
2504         CLK1(aclk_peri_niu),
2505         CLK1(aclk_cpu_peri),
2506         CLK1(aclk_peri_axi_matrix),
2507
2508         /*************************hclk_periph***********************/
2509         CLK1(hclk_peri_axi_matrix),
2510         CLK1(hclk_peri_ahb_arbi),
2511         CLK1(hclk_emem_peri),
2512         CLK1(hclk_emac),
2513         CLK1(nandc),
2514         //CLK1(hclk_usb_peri),
2515         //CLK1(hclk_usbotg0),
2516         //CLK1(hclk_usbotg1),
2517         //CLK1(hclk_hsadc),
2518         CLK1(hclk_pidfilter),
2519
2520         //CLK1(hclk_emmc),
2521         /*************************pclk_periph***********************/
2522         CLK1(pclk_peri_axi_matrix),
2523         CLK1(pwm23),
2524
2525         CLK1(wdt),
2526         //CLK1(pclk_spi0),
2527         //CLK1(pclk_spi1),
2528         //CLK1(pclk_uart2),
2529         //CLK1(pclk_uart3),
2530
2531         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2532         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2533         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2534
2535         CLK1(gpio3),
2536         CLK1(gpio4),
2537
2538         /*************************aclk_lcdc0***********************/
2539         CLK1(aclk_vio0),
2540         CLK1(aclk_cif0),
2541         CLK1(aclk_ipp),
2542
2543         /*************************aclk_lcdc0***********************/
2544         CLK1(aclk_vio1),
2545         CLK1(aclk_cif1),
2546         CLK1(aclk_rga),
2547         /************************power domain**********************/
2548         #if 0
2549         PD_CLK(pd_peri),
2550         PD_CLK(pd_display),
2551         PD_CLK(pd_video),
2552         PD_CLK(pd_gpu),
2553         PD_CLK(pd_dbg),
2554         #endif
2555         #endif
2556 };
2557 static void __init rk30_init_enable_clocks(void)
2558 {
2559 /**************************************/
2560         clk_enable_nolock(&pd_peri);
2561         clk_enable_nolock(&pd_display);
2562         clk_enable_nolock(&pd_video);
2563         clk_enable_nolock(&pd_dbg);
2564 /****************clocks*****************/
2565         //ddr pll
2566         clk_enable_nolock(&clk_ddr);
2567
2568
2569         //apll
2570         clk_enable_nolock(&core_periph);
2571         clk_enable_nolock(&hclk_cpu);
2572         clk_enable_nolock(&pclk_cpu);
2573         clk_enable_nolock(&atclk_cpu);
2574
2575         //usb
2576         clk_enable_nolock(&clk_otgphy0);
2577         clk_enable_nolock(&clk_otgphy1);
2578
2579
2580         //periph clk
2581         clk_enable_nolock(&hclk_periph);
2582         clk_enable_nolock(&pclk_periph);
2583
2584         //uart
2585         #if 1
2586         clk_enable_nolock(&clk_uart0);
2587         clk_enable_nolock(&clk_pclk_uart0);
2588         clk_enable_nolock(&clk_uart0_frac_div);
2589
2590         clk_enable_nolock(&clk_uart1);
2591         clk_enable_nolock(&clk_pclk_uart1);
2592         clk_enable_nolock(&clk_uart1_frac_div);
2593
2594         clk_enable_nolock(&clk_uart2);
2595         clk_enable_nolock(&clk_pclk_uart2);
2596         clk_enable_nolock(&clk_uart2_frac_div);
2597
2598         clk_enable_nolock(&clk_uart3);
2599         clk_enable_nolock(&clk_pclk_uart3);
2600         clk_enable_nolock(&clk_uart3_frac_div);
2601         #endif
2602
2603
2604         // timer ???
2605         clk_enable_nolock(&clk_timer0);
2606         clk_enable_nolock(&clk_timer1);
2607         clk_enable_nolock(&clk_timer2);
2608         clk_enable_nolock(&clk_pclk_timer0);
2609         clk_enable_nolock(&clk_pclk_timer1);
2610         clk_enable_nolock(&clk_pclk_timer2);
2611
2612
2613
2614         // aclk cpu
2615         clk_enable_nolock(&clk_dma1);
2616         clk_enable_nolock(&clk_l2mem_con);
2617         clk_enable_nolock(&clk_intmem);
2618         clk_enable_nolock(&clk_aclk_strc_sys);
2619         //hclk cpu
2620         clk_enable_nolock(&clk_rom);
2621         clk_enable_nolock(&clk_hclk_cpubus);
2622         clk_enable_nolock(&clk_hclk_ahb2apb);
2623         clk_enable_nolock(&clk_hclk_vio_bus);
2624         //pclk_cpu
2625         clk_enable_nolock(&clk_tzpc);
2626         clk_enable_nolock(&clk_pclk_ddrupctl);
2627         clk_enable_nolock(&clk_pclk_ddrpubl);
2628
2629         clk_enable_nolock(&clk_dbg);
2630         clk_enable_nolock(&clk_grf);
2631         clk_enable_nolock(&clk_pmu);
2632
2633         //hclk periph
2634         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
2635         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
2636         clk_enable_nolock(&clk_hclk_emem_peri);
2637         clk_enable_nolock(&clk_nandc);
2638         clk_enable_nolock(&clk_hclk_otg0);
2639         clk_enable_nolock(&clk_hclk_otg1);
2640         //aclk periph
2641         clk_enable_nolock(&clk_dma2);
2642         clk_enable_nolock(&clk_aclk_peri_niu);
2643         clk_enable_nolock(&clk_aclk_cpu_peri);
2644         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
2645         //pclk periph
2646         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
2647
2648
2649         clk_enable_nolock(&clk_hclk_hdmi);
2650         clk_enable_nolock(&clk_hclk_rga);
2651         clk_enable_nolock(&clk_hclk_ipp);
2652         clk_enable_nolock(&clk_hclk_cif1);
2653         clk_enable_nolock(&clk_hclk_cif0);
2654
2655         clk_enable_nolock(&cif1_out);
2656         clk_enable_nolock(&cif0_out);
2657         clk_enable_nolock(&cif1_in);
2658         clk_enable_nolock(&cif0_in);
2659
2660
2661
2662
2663
2664 }
2665 static void periph_clk_set_init(void)
2666 {
2667         unsigned long aclk_p, hclk_p, pclk_p;
2668         unsigned long ppll_rate=general_pll_clk.rate;
2669         //aclk 148.5
2670
2671         /* general pll */
2672         switch (ppll_rate) {
2673         case 148500* KHZ:
2674                 aclk_p = 148500*KHZ;
2675                 hclk_p = aclk_p>>1;
2676                 pclk_p = aclk_p>>2;
2677                 break;
2678         case 1188*MHZ:
2679                 aclk_p = aclk_p>>3;// 0
2680                 hclk_p = aclk_p>>1;
2681                 pclk_p = aclk_p>>2;
2682         default:
2683                 ppll_rate = 297 * MHZ;
2684         case 297 * MHZ:
2685                 aclk_p = ppll_rate>>1;
2686                 hclk_p = aclk_p>>0;
2687                 pclk_p = aclk_p>>1;
2688                 break;
2689         }
2690
2691         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2692         clk_set_rate_nolock(&aclk_periph, aclk_p);
2693         clk_set_rate_nolock(&hclk_periph, hclk_p);
2694         clk_set_rate_nolock(&pclk_periph, pclk_p);
2695 }
2696
2697
2698 void rk30_clock_common_i2s_init(unsigned long i2s_rate)
2699 {
2700         if(i2s_rate<=i2s_12288khz||general_pll_clk.rate>=codec_pll_clk.rate)
2701                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
2702         else
2703         {
2704                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
2705         }
2706 }
2707 static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long cpll_rate,
2708                                         unsigned long i2s_rate)
2709 {
2710
2711         //clk_set_rate_nolock(&clk_cpu, 816*MHZ);//816
2712         //general
2713         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
2714         //code pll
2715         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
2716
2717         //periph clk
2718         periph_clk_set_init();
2719
2720         //i2s
2721         rk30_clock_common_i2s_init(i2s_rate);
2722
2723         // uart
2724         #if 0
2725         clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
2726         #else
2727         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
2728         #endif
2729
2730         //mac
2731         clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
2732
2733         //hsadc
2734         //auto pll sel
2735         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
2736
2737         //lcdc1  hdmi
2738         clk_set_parent_nolock(&dclk_lcdc1_div, &general_pll_clk);
2739
2740         //lcdc0 lcd auto sel pll
2741         //clk_set_parent_nolock(&dclk_lcdc0_div, &general_pll_clk);
2742
2743         //cif
2744         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
2745
2746         //axi lcdc auto sel
2747         //clk_set_parent_nolock(&aclk_lcdc0, &general_pll_clk);
2748         //clk_set_parent_nolock(&aclk_lcdc1, &general_pll_clk);
2749
2750         //axi vepu auto sel
2751         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
2752         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
2753
2754         //gpu auto sel
2755         //clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
2756
2757 }
2758
2759 static struct clk def_ops_clk={
2760         .get_parent=clksel_get_parent,
2761         .set_parent=clksel_set_parent,
2762 };
2763
2764 #ifdef CONFIG_PROC_FS
2765 struct clk_dump_ops dump_ops;
2766 #endif
2767
2768 static void clk_dump_regs(void);
2769
2770 void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,unsigned long max_i2s_rate)
2771 {
2772         struct clk_lookup *lk;
2773
2774         clk_register_dump_ops(&dump_ops);
2775         clk_register_default_ops_clk(&def_ops_clk);
2776
2777         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2778                 #ifdef RK30_CLK_OFFBOARD_TEST
2779                 fdsf
2780                         rk30_clkdev_add(lk);
2781                 #else
2782                         clkdev_add(lk);
2783                 #endif
2784                 clk_register(lk->clk);
2785         }
2786         clk_recalculate_root_clocks_nolock();
2787         calc_lpj_ref();
2788         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
2789
2790         /*
2791          * Only enable those clocks we will need, let the drivers
2792          * enable other clocks as necessary
2793          */
2794         rk30_init_enable_clocks();
2795
2796         /*
2797          * Disable any unused clocks left on by the bootloader
2798          */
2799         //clk_disable_unused();
2800         rk30_clock_common_init(gpll,cpll,max_i2s_rate);
2801         //preset_lpj = loops_per_jiffy;
2802         //clk_dump_regs();
2803 }
2804 extern int rk30_dvfs_init(void);
2805
2806 /*
2807  * You can override arm_clk rate with armclk= cmdline option.
2808  */
2809 static int __init armclk_setup(char *str)
2810 {
2811         get_option(&str, &armclk);
2812
2813         if (!armclk)
2814                 return 0;
2815         if (armclk < 10000)
2816                 armclk *= MHZ;
2817         //clk_set_rate_nolock(&arm_pll_clk, armclk);
2818         return 0;
2819 }
2820 #ifndef RK30_CLK_OFFBOARD_TEST
2821 early_param("armclk", armclk_setup);
2822 #endif
2823
2824
2825
2826 #ifdef CONFIG_PROC_FS
2827
2828 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks)
2829 {
2830         struct clk* ck;
2831         int i;
2832         unsigned long rate = clk->rate;
2833         //CRU_PRINTK_DBG("dump_clock %s\n",clk->name);
2834         for (i = 0; i < deep; i++)
2835                 seq_printf(s, "    ");
2836
2837         seq_printf(s, "%-11s ", clk->name);
2838 #ifndef RK30_CLK_OFFBOARD_TEST
2839         if (clk->flags & IS_PD) {
2840                         seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
2841         }
2842 #endif
2843         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
2844                 int idx = clk->gate_idx;
2845                 u32 v;
2846                 v = cru_readl(CLK_GATE_CLKID_CONS(idx))&((0x1)<<(idx%16));
2847                 seq_printf(s, "%s ", v ? "off" : "on ");
2848         }
2849
2850         if (clk->pll)
2851         {
2852                 u32 pll_mode;
2853                 u32 pll_id=clk->pll->id;
2854                 pll_mode=cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
2855                 if(pll_mode==PLL_MODE_SLOW(pll_id))
2856                         seq_printf(s, "slow   ");
2857                 else if(pll_mode==PLL_MODE_NORM(pll_id))
2858                         seq_printf(s, "normal ");
2859                 else if(pll_mode==PLL_MODE_DEEP(pll_id))
2860                         seq_printf(s, "deep   ");
2861
2862                 if(cru_readl(PLL_CONS(pll_id,3)) & PLL_BYPASS)
2863                         seq_printf(s, "bypass ");
2864         }
2865         else if(clk == &clk_ddr) {
2866                 rate = clk->recalc(clk);
2867         }
2868
2869         if (rate >= MHZ) {
2870                 if (rate % MHZ)
2871                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2872                 else
2873                         seq_printf(s, "%ld MHz", rate / MHZ);
2874         } else if (rate >= KHZ) {
2875                 if (rate % KHZ)
2876                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2877                 else
2878                         seq_printf(s, "%ld KHz", rate / KHZ);
2879         } else {
2880                 seq_printf(s, "%ld Hz", rate);
2881         }
2882
2883         seq_printf(s, " usecount = %d", clk->usecount);
2884
2885         if (clk->parent)
2886                 seq_printf(s, " parent = %s", clk->parent->name);
2887
2888         seq_printf(s, "\n");
2889
2890         list_for_each_entry(ck, root_clocks, node) {
2891                 if (ck->parent == clk)
2892                         dump_clock(s, ck, deep + 1,root_clocks);
2893         }
2894 }
2895
2896 static void dump_regs(struct seq_file *s)
2897 {
2898         int i=0;
2899         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
2900         seq_printf(s, "\nPLLRegisters:\n");
2901         for(i=0;i<END_PLL_ID;i++)
2902         {
2903                 seq_printf(s,"pll%d        :cons:%x,%x,%x,%x\n",i,
2904                         cru_readl(PLL_CONS(i,0)),
2905                         cru_readl(PLL_CONS(i,1)),
2906                         cru_readl(PLL_CONS(i,2)),
2907                         cru_readl(PLL_CONS(i,3))
2908                         );
2909         }
2910                 seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
2911
2912         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
2913         {
2914                 seq_printf(s,"CLKSEL%d     :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
2915         }
2916         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
2917         {
2918                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
2919         }
2920         seq_printf(s,"GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
2921         seq_printf(s,"GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
2922
2923         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
2924         {
2925                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
2926         }
2927         seq_printf(s,"CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
2928         seq_printf(s,"GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
2929
2930 }
2931
2932 static void clk_dump_regs(void)
2933 {
2934         int i=0;
2935         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
2936         printk("\nPLLRegisters:\n");
2937         for(i=0;i<END_PLL_ID;i++)
2938         {
2939                 printk("pll%d        :cons:%x,%x,%x,%x\n",i,
2940                         cru_readl(PLL_CONS(i,0)),
2941                         cru_readl(PLL_CONS(i,1)),
2942                         cru_readl(PLL_CONS(i,2)),
2943                         cru_readl(PLL_CONS(i,3))
2944                         );
2945         }
2946                 printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
2947
2948         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
2949         {
2950                 printk("CLKSEL%d           :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
2951         }
2952         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
2953         {
2954                 printk("CLKGATE%d         :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
2955         }
2956         printk("GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
2957         printk("GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
2958
2959         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
2960         {
2961                 printk("CLKGATE%d         :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
2962         }
2963         printk("CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
2964         printk("GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
2965
2966 }
2967
2968
2969 #ifdef CONFIG_PROC_FS
2970 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
2971 struct clk_dump_ops dump_ops={
2972         .dump_clk=dump_clock,
2973         .dump_regs=dump_regs,
2974 };
2975 #endif
2976
2977
2978 #endif /* CONFIG_PROC_FS */
2979
2980
2981
2982
2983 #ifdef RK30_CLK_OFFBOARD_TEST
2984 struct clk *test_get_parent(struct clk *clk)
2985 {
2986         return clk->parent;
2987 }
2988
2989 void i2s_test(void)
2990 {
2991         struct clk *i2s_clk=&clk_i2s0;
2992
2993         clk_enable_nolock(i2s_clk);
2994
2995         clk_set_rate_nolock(i2s_clk, 12288000);
2996         printk("int %s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
2997         clk_set_rate_nolock(i2s_clk, 297*MHZ/2);
2998         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
2999         clk_set_rate_nolock(i2s_clk, 12*MHZ);
3000         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3001
3002 }
3003
3004 void uart_test(void)
3005 {
3006         struct clk *uart_clk=&clk_uart0;
3007
3008         clk_enable_nolock(uart_clk);
3009
3010         clk_set_rate_nolock(uart_clk, 12288000);
3011         printk("int %s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3012         clk_set_rate_nolock(uart_clk, 297*MHZ/2);
3013         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3014         clk_set_rate_nolock(uart_clk, 12*MHZ);
3015         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3016
3017 }
3018 void hsadc_test(void)
3019 {
3020         struct clk *hsadc_clk=&clk_hsadc;
3021
3022         printk("******************hsadc_test**********************\n");
3023         clk_enable_nolock(hsadc_clk);
3024
3025         clk_set_rate_nolock(hsadc_clk, 12288000);
3026         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3027
3028
3029         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3030         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3031
3032         clk_set_rate_nolock(hsadc_clk, 300*MHZ/2);
3033
3034         clk_set_rate_nolock(hsadc_clk, 296*MHZ/2);
3035
3036         printk("******************hsadc out clock**********************\n");
3037
3038         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3039         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3040         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3041         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3042
3043
3044
3045 }
3046
3047 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3048 {
3049         //arm
3050         printk("*********arm_pll_clk***********\n");
3051         clk_set_rate_nolock(&arm_pll_clk, 816*MHZ);
3052
3053         printk("*********set clk_cpu parent***********\n");
3054         clk_set_parent_nolock(&clk_cpu, &arm_pll_clk);
3055         clk_set_rate_nolock(&clk_cpu, 504*MHZ);
3056
3057         //general
3058         printk("*********general_pll_clk***********\n");
3059         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3060
3061         //code pll
3062         printk("*********codec_pll_clk***********\n");
3063         clk_set_rate_nolock(&codec_pll_clk, 600*MHZ);
3064
3065
3066         printk("*********periph_clk_set_init***********\n");
3067         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3068         periph_clk_set_init();
3069
3070         #if 0 //
3071                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3072         #else
3073                 printk("*********clk i2s***********\n");
3074                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3075                 printk("common %s parent is %s\n",clk_i2s_pll.name,test_get_parent(&clk_i2s_pll)->name);
3076                 i2s_test();
3077         #endif
3078 // spi
3079         clk_enable_nolock(&clk_spi0);
3080         clk_set_rate_nolock(&clk_spi0, 30*MHZ);
3081         printk("common %s parent is %s\n",clk_spi0.name,test_get_parent(&clk_spi0)->name);
3082 //saradc
3083         clk_enable_nolock(&clk_saradc);
3084         clk_set_rate_nolock(&clk_saradc, 6*MHZ);
3085         printk("common %s parent is %s\n",clk_saradc.name,test_get_parent(&clk_saradc)->name);
3086 //sdio
3087         clk_enable_nolock(&clk_sdio);
3088         clk_set_rate_nolock(&clk_sdio, 50*MHZ);
3089         printk("common %s parent is %s\n",clk_sdio.name,test_get_parent(&clk_sdio)->name);
3090 // uart
3091         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3092         uart_test();
3093 //mac
3094         printk("*********mac***********\n");
3095
3096         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3097         printk("common %s parent is %s\n",clk_mac_pll_div.name,test_get_parent(&clk_mac_pll_div)->name);
3098
3099         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3100         clk_set_rate_nolock(&clk_mac_ref, 50*MHZ);
3101         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3102
3103         printk("*********mac mii set***********\n");
3104         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3105         clk_set_rate_nolock(&clk_mac_ref, 20*MHZ);
3106         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3107 //hsadc
3108         printk("*********hsadc 1***********\n");
3109         //auto pll
3110         hsadc_test();
3111 //lcdc
3112         clk_enable_nolock(&dclk_lcdc0);
3113
3114         clk_set_rate_nolock(&dclk_lcdc0, 60*MHZ);
3115         clk_set_rate_nolock(&dclk_lcdc0, 27*MHZ);
3116
3117 //cif
3118         clk_enable_nolock(&cif0_out);
3119
3120         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3121         printk("common %s parent is %s\n",cif_out_pll.name,test_get_parent(&cif_out_pll)->name);
3122
3123         clk_set_rate_nolock(&cif0_out, 60*MHZ);
3124         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3125
3126         clk_set_rate_nolock(&cif0_out, 24*MHZ);
3127         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3128 //cif_in
3129         clk_enable_nolock(&cif0_in);
3130         clk_set_rate_nolock(&cif0_in, 24*MHZ);
3131 //axi lcdc
3132         clk_enable_nolock(&aclk_lcdc0);
3133         clk_set_rate_nolock(&aclk_lcdc0, 150*MHZ);
3134         printk("common %s parent is %s\n",aclk_lcdc0.name,test_get_parent(&aclk_lcdc0)->name);
3135 //axi vepu
3136         clk_enable_nolock(&aclk_vepu);
3137         clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
3138         printk("common %s parent is %s\n",aclk_vepu.name,test_get_parent(&aclk_vepu)->name);
3139
3140         clk_set_rate_nolock(&hclk_vepu, 300*MHZ);
3141         printk("common %s parent is %s\n",hclk_vepu.name,test_get_parent(&hclk_vepu)->name);
3142
3143         printk("test end\n");
3144
3145         /* arm pll
3146         clk_set_rate_nolock(&arm_pll_clk, armclk);
3147         clk_set_rate_nolock(&clk_cpu,   armclk);//pll:core =1:1
3148         */
3149         //
3150         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3151         //
3152         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3153         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3154
3155 }
3156
3157
3158
3159
3160
3161 static LIST_HEAD(rk30_clocks);
3162 static DEFINE_MUTEX(rk30_clocks_mutex);
3163
3164 static inline int __rk30clk_get(struct clk *clk)
3165 {
3166         return 1;
3167 }
3168 void rk30_clkdev_add(struct clk_lookup *cl)
3169 {
3170         mutex_lock(&rk30_clocks_mutex);
3171         list_add_tail(&cl->node, &rk30_clocks);
3172         mutex_unlock(&rk30_clocks_mutex);
3173 }
3174 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id)
3175 {
3176         struct clk_lookup *p, *cl = NULL;
3177         int match, best = 0;
3178
3179         list_for_each_entry(p, &rk30_clocks, node) {
3180                 match = 0;
3181                 if (p->dev_id) {
3182                         if (!dev_id || strcmp(p->dev_id, dev_id))
3183                                 continue;
3184                         match += 2;
3185                 }
3186                 if (p->con_id) {
3187                         if (!con_id || strcmp(p->con_id, con_id))
3188                                 continue;
3189                         match += 1;
3190                 }
3191
3192                 if (match > best) {
3193                         cl = p;
3194                         if (match != 3)
3195                                 best = match;
3196                         else
3197                                 break;
3198                 }
3199         }
3200         return cl;
3201 }
3202
3203 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id)
3204 {
3205         struct clk_lookup *cl;
3206
3207         mutex_lock(&rk30_clocks_mutex);
3208         cl = rk30_clk_find(dev_id, con_id);
3209         if (cl && !__rk30clk_get(cl->clk))
3210                 cl = NULL;
3211         mutex_unlock(&rk30_clocks_mutex);
3212
3213         return cl ? cl->clk : ERR_PTR(-ENOENT);
3214 }
3215 //EXPORT_SYMBOL(rk30_clk_get_sys);
3216
3217 struct clk *rk30_clk_get(struct device *dev, const char *con_id)
3218 {
3219         const char *dev_id = dev ? dev_name(dev) : NULL;
3220         return rk30_clk_get_sys(dev_id, con_id);
3221 }
3222 //EXPORT_SYMBOL(rk30_clk_get);
3223
3224
3225 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3226
3227 void rk30_clocks_test(void)
3228 {
3229     struct clk *test_gpll;
3230         test_gpll=rk30_clk_get(NULL,"general_pll");
3231         if(test_gpll)
3232         {
3233                 rk30_clk_set_rate(test_gpll,297*2*MHZ);
3234                 printk("gpll rate=%lu\n",test_gpll->rate);
3235         }
3236         //while(1);
3237 }
3238
3239 void __init rk30_clock_init_test(void){
3240
3241         rk30_clock_init(periph_pll_297mhz,codec_pll_360mhz,max_i2s_12288khz);
3242         //while(1);
3243 }
3244
3245
3246 #endif
3247
3248