arch/arm/mach-rk30/clock.c

   1 #include <linux/clk.h>
   2 #include <linux/clkdev.h>
   3 #include <linux/err.h>
   4 #include <linux/init.h>
   5 #include <linux/kernel.h>
   6 #include <linux/module.h>
   7
   8 #include <mach/board.h>
   9
  10 /* Clock flags */
  11 /* bit 0 is free */
  12 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  13 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  14 #define IS_PD                   (1 << 2)        /* Power Domain */
  15
  16 #define MHZ                     (1000*1000)
  17 #define KHZ                     1000
  18
  19 struct clk {
  20         struct list_head        node;
  21         const char              *name;
  22         struct clk              *parent;
  23         struct list_head        children;
  24         struct list_head        sibling;        /* node for children */
  25         unsigned long           rate;
  26         u32                     flags;
  27         int                     (*mode)(struct clk *clk, int on);
  28         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  29         int                     (*set_rate)(struct clk *, unsigned long);
  30         long                    (*round_rate)(struct clk *, unsigned long);
  31         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
  32         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
  33         s16                     usecount;
  34         u16                     notifier_count;
  35         u8                      gate_idx;
  36         u8                      pll_idx;
  37         u8                      clksel_con;
  38         u8                      clksel_mask;
  39         u8                      clksel_shift;
  40         u8                      clksel_maxdiv;
  41         u8                      clksel_parent_mask;
  42         u8                      clksel_parent_shift;
  43         struct clk              **parents;
  44 };
  45
  46 static struct clk xin24m = {
  47         .name           = "xin24m",
  48         .rate           = 24 * MHZ,
  49         .flags          = RATE_FIXED,
  50 };
  51
  52 #define CLK(dev, con, ck) \
  53         { \
  54                 .dev_id = dev, \
  55                 .con_id = con, \
  56                 .clk = ck, \
  57         }
  58
  59 static struct clk_lookup clks[] = {
  60         CLK("rk30_i2c.0", "i2c", &xin24m),
  61         CLK("rk30_i2c.1", "i2c", &xin24m),
  62         CLK("rk30_i2c.2", "i2c", &xin24m),
  63         CLK("rk30_i2c.3", "i2c", &xin24m),
  64         CLK("rk30_i2c.4", "i2c", &xin24m),
  65         CLK("rk29xx_spim.0", "spi", &xin24m),
  66         CLK("rk29xx_spim.1", "spi", &xin24m),
  67 };
  68
  69 void __init rk30_clock_init(void)
  70 {
  71         struct clk_lookup *lk;
  72
  73         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
  74                 clkdev_add(lk);
  75         }
  76 }
  77
  78 int clk_enable(struct clk *clk)
  79 {
  80         int ret = 0;
  81
  82         if (clk == NULL || IS_ERR(clk))
  83                 return -EINVAL;
  84
  85         return ret;
  86 }
  87 EXPORT_SYMBOL(clk_enable);
  88
  89 void clk_disable(struct clk *clk)
  90 {
  91         if (clk == NULL || IS_ERR(clk))
  92                 return;
  93 }
  94 EXPORT_SYMBOL(clk_disable);
  95
  96 unsigned long clk_get_rate(struct clk *clk)
  97 {
  98         return 24000000;
  99 }
 100 EXPORT_SYMBOL(clk_get_rate);
 101
 102 int clk_set_rate(struct clk *clk, unsigned long rate)
 103 {
 104         int ret = -EINVAL;
 105
 106         if (clk == NULL || IS_ERR(clk))
 107                 return ret;
 108
 109         return ret;
 110 }
 111 EXPORT_SYMBOL(clk_set_rate);