2 #include <mach/board.h>
4 #include <mach/iomux.h>
9 #define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
10 #define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
12 #if defined(CONFIG_RK30_I2C_INSRAM)
14 /******************need set when you use i2c*************************/
16 #define I2C_SADDR (0x2D) /* slave address ,wm8310 addr is 0x34*/
17 #define SRAM_I2C_CH 1 //CH==0, i2c0,CH==1, i2c1,CH==2, i2c2,CH==3, i2c3
18 #if defined (CONFIG_MACH_RK2928_SDK)
19 #define SRAM_I2C_ADDRBASE (RK2928_RKI2C1_BASE )//RK29_I2C0_BASE\RK29_I2C2_BASE\RK29_I2C3_BASE
21 #define SRAM_I2C_ADDRBASE (RK2928_RKI2C0_BASE )
24 #define I2C_SLAVE_ADDR_LEN 1 // 2:slav addr is 10bit ,1:slav addr is 7bit
25 #define I2C_SLAVE_REG_LEN 1 // 2:slav reg addr is 16 bit ,1:is 8 bit
26 #define SRAM_I2C_DATA_BYTE 1 //i2c transmission data is 1bit(8wei) or 2bit(16wei)
27 #define GRF_GPIO_IOMUX 0xd4 //GRF_GPIO2D_IOMUX
28 /*ch=0:GRF_GPIO2L_IOMUX,ch=1:GRF_GPIO1L_IOMUX,ch=2:GRF_GPIO5H_IOMUX,ch=3:GRF_GPIO2L_IOMUX*/
29 #define I2C_GRF_GPIO_IOMUX (0x01<<14)|(0x01<<12)
30 /*CH=0:(~(0x03<<30))&(~(0x03<<28))|(0x01<<30)|(0x01<<28),CH=1:(~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12),
31 CH=2:(~(0x03<<24))&(~(0x03<<22))|(0x01<<24)|(0x01<<22),CH=3:(~(0x03<<26))&(~(0x03<<24))|(0x02<<26)|(0x02<<24)*/
32 /***************************************/
34 #define I2C_SLAVE_TYPE (((I2C_SLAVE_ADDR_LEN-1)<<4)|((I2C_SLAVE_REG_LEN-1)))
36 #define uint8 unsigned char
37 #define uint16 unsigned short
38 #define uint32 unsigned int
39 uint32 __sramdata data[5];
40 uint8 __sramdata arm_voltage = 0;
42 #define CRU_CLKGATE0_CON 0xd0
43 #define CRU_CLKGATE8_CON 0xf0
44 #define CRU_CLKSEL1_CON 0x48
45 #define GRF_GPIO5H_IOMUX 0x74
46 #define GRF_GPIO2L_IOMUX 0x58
47 #define GRF_GPIO1L_IOMUX 0x50
49 #define COMPLETE_READ (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
50 #define COMPLETE_WRITE (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
52 /* Control register */
53 #define I2C_CON 0x0000
54 #define I2C_CON_EN (1 << 0)
55 #define I2C_CON_MOD(mod) ((mod) << 1)
56 #define I2C_CON_MASK (3 << 1)
63 #define I2C_CON_START (1 << 3)
64 #define I2C_CON_STOP (1 << 4)
65 #define I2C_CON_LASTACK (1 << 5)
66 #define I2C_CON_ACTACK (1 << 6)
68 /* Clock dividor register */
69 #define I2C_CLKDIV 0x0004
70 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
71 #define rk30_ceil(x, y) \
72 ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; })
74 /* the slave address accessed for master rx mode */
75 #define I2C_MRXADDR 0x0008
76 #define I2C_MRXADDR_LOW (1 << 24)
77 #define I2C_MRXADDR_MID (1 << 25)
78 #define I2C_MRXADDR_HIGH (1 << 26)
80 /* the slave register address accessed for master rx mode */
81 #define I2C_MRXRADDR 0x000c
82 #define I2C_MRXRADDR_LOW (1 << 24)
83 #define I2C_MRXRADDR_MID (1 << 25)
84 #define I2C_MRXRADDR_HIGH (1 << 26)
87 #define I2C_MTXCNT 0x0010
90 #define I2C_MRXCNT 0x0014
92 /* interrupt enable register */
93 #define I2C_IEN 0x0018
94 #define I2C_BTFIEN (1 << 0)
95 #define I2C_BRFIEN (1 << 1)
96 #define I2C_MBTFIEN (1 << 2)
97 #define I2C_MBRFIEN (1 << 3)
98 #define I2C_STARTIEN (1 << 4)
99 #define I2C_STOPIEN (1 << 5)
100 #define I2C_NAKRCVIEN (1 << 6)
101 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
102 #define IRQ_ALL_DISABLE 0
104 /* interrupt pending register */
105 #define I2C_IPD 0x001c
106 #define I2C_BTFIPD (1 << 0)
107 #define I2C_BRFIPD (1 << 1)
108 #define I2C_MBTFIPD (1 << 2)
109 #define I2C_MBRFIPD (1 << 3)
110 #define I2C_STARTIPD (1 << 4)
111 #define I2C_STOPIPD (1 << 5)
112 #define I2C_NAKRCVIPD (1 << 6)
113 #define I2C_IPD_ALL_CLEAN 0x7f
116 #define I2C_FCNT 0x0020
118 /* I2C tx data register */
119 #define I2C_TXDATA_BASE 0X0100
121 /* I2C rx data register */
122 #define I2C_RXDATA_BASE 0x0200
124 void __sramfunc sram_i2c_enable(void);
125 void __sramfunc sram_i2c_disenable(void);
127 void __sramfunc sram_printch(char byte);
128 void __sramfunc sram_printhex(unsigned int hex);
130 #define sram_udelay(usecs) SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
132 /*-------------------------------------------------------------------------------------------------------
134 Desc : initialize the necessary registers
135 Params : channel-determine which I2C bus we used
137 ------------------------------------------------------------------------------------------------------*/
139 void __sramfunc sram_i2c_init()
141 unsigned int div, divl, divh;
142 //enable cru_clkgate8 clock
143 data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8)));
145 #if defined (CONFIG_MACH_RK2928_SDK)
146 cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1),
147 CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
149 cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C0)|CLK_UN_GATE(CLK_GATE_PCLK_I2C0),
150 CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C0));
153 data[2] = readl_relaxed(RK2928_GRF_BASE + GRF_GPIO_IOMUX);
154 writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK2928_GRF_BASE + GRF_GPIO_IOMUX);
158 writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV);
159 data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV);
164 /*-------------------------------------------------------------------------------------------------------
165 Name : sram_i2c_deinit
166 Desc : de-initialize the necessary registers
169 ------------------------------------------------------------------------------------------------------*/
170 void __sramfunc sram_i2c_deinit(void)
173 writel_relaxed(data[2], RK2928_GRF_BASE + GRF_GPIO_IOMUX);
175 //restore scu clock reg
176 cru_writel(data[1], CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
181 /*-------------------------------------------------------------------------------------------------------
182 Name : sram_i2c_start
186 ------------------------------------------------------------------------------------------------------*/
187 void __sramfunc sram_i2c_read_enable(void)
189 writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(1)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
191 void __sramfunc sram_i2c_write_enable(void)
193 writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(0)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
196 void __sramfunc sram_i2c_disenable(void)
198 writel_relaxed(0, SRAM_I2C_ADDRBASE + I2C_CON);
201 void __sramfunc sram_i2c_clean_start(void)
203 unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
205 con = (con & (~I2C_CON_START)) ;
206 writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
208 void __sramfunc sram_i2c_send_start(void)
210 unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
211 con |= I2C_CON_START;
212 if(con & I2C_CON_STOP)
214 writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
216 void __sramfunc sram_i2c_send_stop(void)
218 unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
219 con &= ~I2C_CON_START;
221 if(con & I2C_CON_START)
223 writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
225 void __sramfunc sram_i2c_clean_stop(void)
227 unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
229 con = (con & (~I2C_CON_STOP)) ;
230 writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
233 void __sramfunc sram_i2c_get_ipd_event(int type)
236 unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
237 writel_relaxed(type, SRAM_I2C_ADDRBASE + I2C_IEN);
240 con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
241 }while(((--time) & (~(con & type))));
242 writel_relaxed(type,SRAM_I2C_ADDRBASE + I2C_IPD);
249 void __sramfunc sram_i2c_write_prepare(uint8 I2CSlaveAddr, uint8 regAddr,uint8 pdata)
252 unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
254 data = (addr | (regAddr << 8))|(pdata << 16);
255 writel_relaxed(data , SRAM_I2C_ADDRBASE + I2C_TXDATA_BASE);
256 writel_relaxed(3, SRAM_I2C_ADDRBASE + I2C_MTXCNT);
258 uint8 __sramfunc sram_i2c_read_prepare(uint8 I2CSlaveAddr, uint8 regAddr)
260 unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
262 writel_relaxed(addr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXADDR);
263 writel_relaxed(regAddr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXRADDR);
264 writel_relaxed(SRAM_I2C_DATA_BYTE, SRAM_I2C_ADDRBASE + I2C_MRXCNT);
268 uint8 __sramfunc sram_i2c_read_get_data(uint8 I2CSlaveAddr, uint8 regAddr)
271 ret = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_RXDATA_BASE);
272 ret = ret & 0x000000ff;
276 uint8 __sramfunc sram_i2c_write(uint8 I2CSlaveAddr, uint8 regAddr,uint8 data)
278 sram_i2c_write_enable();
279 sram_i2c_get_ipd_event(I2C_STARTIPD);
280 sram_i2c_clean_start();
282 sram_i2c_write_prepare(I2CSlaveAddr,regAddr,data);
283 sram_i2c_get_ipd_event(I2C_MBTFIPD);
285 sram_i2c_send_stop();
286 sram_i2c_get_ipd_event(I2C_STOPIPD);
287 sram_i2c_clean_stop();
288 sram_i2c_disenable();
293 uint8 __sramfunc sram_i2c_read(uint8 I2CSlaveAddr, uint8 regAddr)
296 sram_i2c_read_enable();
297 sram_i2c_get_ipd_event(I2C_STARTIPD);
298 sram_i2c_clean_start();
300 sram_i2c_read_prepare(I2CSlaveAddr,regAddr);
301 sram_i2c_get_ipd_event(I2C_MBRFIPD);
303 data = sram_i2c_read_get_data(I2CSlaveAddr,regAddr);
305 sram_i2c_send_stop();
306 sram_i2c_get_ipd_event(I2C_STOPIPD);
307 sram_i2c_clean_stop();
308 sram_i2c_disenable();
312 void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
317 uint8 rtc_status_reg = 0x11;
318 sram_i2c_init(); //init i2c device
319 #if defined(CONFIG_MFD_TPS65910)
320 if(pmic_is_tps65910())
322 slaveaddr = 0x2d; //slave device addr
323 slavereg = 0x22; // reg addr
324 data = 0x23; //set arm 1.0v
326 ret = sram_i2c_read(slaveaddr, rtc_status_reg);
327 sram_i2c_write(slaveaddr, rtc_status_reg, ret);
328 arm_voltage = sram_i2c_read(slaveaddr, slavereg);
329 //sram_printhex(ret);
330 sram_i2c_write(slaveaddr, slavereg, data);//
334 #if defined(CONFIG_REGULATOR_ACT8931)
335 if(pmic_is_act8931())
337 slaveaddr = 0x5b; //slave device addr
338 slavereg = 0x40; // reg addr
339 data = 0x10; //set arm 1.0v
341 arm_voltage = sram_i2c_read(slaveaddr, slavereg);
342 //sram_printhex(ret);
343 sram_i2c_write(slaveaddr, slavereg, data);//
344 sram_i2c_write(slaveaddr,( slavereg+0x1), data);//
347 sram_i2c_deinit(); //deinit i2c device
351 void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
358 sram_i2c_init(); //init i2c device
359 #if defined(CONFIG_MFD_TPS65910)
360 if(pmic_is_tps65910())
362 slaveaddr = 0x2d; //slave device addr
363 slavereg = 0x22; // reg add
364 sram_i2c_write(slaveaddr, slavereg, data);
368 #if defined(CONFIG_REGULATOR_ACT8931)
369 if(pmic_is_act8931())
371 slaveaddr = 0x5b; //slave device addr
372 slavereg = 0x40; // reg addr
373 sram_i2c_write(slaveaddr, slavereg, data);
374 sram_i2c_write(slaveaddr, (slavereg+0x1), data);
378 sram_i2c_deinit(); //deinit i2c device
381 int __sramfunc act8931_dc_det(unsigned int vol)
387 slaveaddr = 0x5b; //slave device addr
388 slavereg = 0x78; // reg addr
390 sram_i2c_init(); //init i2c device
391 ret = sram_i2c_read(slaveaddr,slavereg);
392 data = (ret & (1<<1) )? 1:0;
393 sram_i2c_deinit(); //deinit i2c device
398 void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
402 void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
406 int __sramfunc act8931_dc_det(unsigned int vol)