arch/arm/mach-rk29/spi_sram.c

   1 /***************************************spi **************************************************/
   2 #include <mach/rk29_iomap.h>
   3 #include <mach/board.h>
   4 #include <mach/sram.h>
   5 #include <mach/iomux.h>
   6 #include <mach/cru.h>
   7 #include <asm/io.h>
   8 #include <mach/gpio.h>
   9
  10 #include <asm/vfp.h>
  11
  12 #if 1
  13 void __sramfunc sram_printch(char byte);
  14 void __sramfunc printhex(unsigned int hex);
  15 #define sram_printHX(a)
  16 #else
  17 #define sram_printch(a)
  18 #define sram_printHX(a)
  19 #endif
  20
  21 #define grf_readl(offset) readl(RK29_GRF_BASE + offset)
  22 #define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
  23
  24 #define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
  25
  26 #if defined(CONFIG_RK29_SPI_INSRAM)
  27
  28 #define SPI_KHZ (1000)
  29 #define SPI_MHZ (1000*1000)
  30 #define GPLL_SPEED (24*SPI_MHZ)
  31 #define SPI_SR_SPEED (2*SPI_MHZ)
  32
  33
  34 #if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)||defined(CONFIG_MACH_RK29_TD8801_V2)
  35
  36 #define SRAM_SPI_CH 1
  37 #define SRAM_SPI_CS 1
  38 #define SRAM_SPI_DATA_BYTE 2
  39 #define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE
  40 #define SPI_SPEED (500*SPI_KHZ)
  41 //#elif defined()
  42 #else
  43 #define SRAM_SPI_CH 1
  44 #define SRAM_SPI_CS 1
  45 #define SRAM_SPI_DATA_BYTE 2
  46 #define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE
  47 #define SPI_SPEED (500*SPI_KHZ)
  48 #endif
  49
  50 #define SRAM_SPI_SR_DIV (GPLL_SPEED/SPI_SR_SPEED-1)  //
  51 #define SRAM_SPI_DIV (SPI_SR_SPEED/SPI_SPEED)
  52 //#include <mach/spi_sram.h>
  53
  54 #define SPIM_ENR        0x0008
  55 #define SPIM_SER        0x000C
  56 #define SPIM_CTRLR0     0x0000
  57 #define SPIM_BAUDR      0x0010
  58 #define SPIM_TXFTLR     0x0014
  59 #define SPIM_RXFLR      0x0020
  60 #define cs1 1
  61 #define cs0 0
  62 #define spi1 1
  63 #define spi0 0
  64 #define SPIM_SR         0x0024
  65
  66 #define SPIM_IMR        0x002c
  67 #define SPIM_TXDR       0x400
  68 #define SPIM_RXDR       0x800
  69 /* Bit fields in rxflr, */
  70 #define RXFLR_MASK      (0x3f)
  71 /* Bit fields in SR, 7 bits */
  72 #define SR_MASK                         0x7f            /* cover 7 bits */
  73 #define SR_BUSY                         (1 << 0)
  74 #define SR_TF_FULL                  (1 << 1)
  75 #define SR_TF_EMPT                      (1 << 2)
  76 #define SR_RF_EMPT                  (1 << 3)
  77 #define SR_RF_FULL                      (1 << 4)
  78
  79 #define PM_GETGPIO_BASE(N) RK29_GPIO##N##_BASE
  80 #define PM_GPIO_DR 0
  81 #define PM_GPIO_DDR 0x4
  82 #define PM_GPIO_INTEN 0x30
  83
  84 #define wm831x_RD_MSK (0x1<<15)
  85 #define wm831x_RD_VOID (0x7FFF)
  86 #define spi_ctr0_mask 0x1fffc3
  87
  88
  89
  90 enum
  91 {
  92 GRF_IOM50=0,
  93 GRF_IOM5c,
  94 CLKGATE1,
  95 CLKGATE2,
  96 CLKSEL6,
  97 SPI_CTRLR0,
  98 SPI_BAUDR,
  99 SPI_SER,
 100 DATE_END,
 101 };
 102  static u32 __sramdata spi_data[DATE_END]={};
 103
 104 #define sram_spi_dis()  spi_writel(spi_readl(SPIM_ENR)&~(0x1<<0),SPIM_ENR)
 105 #define sram_spi_en()  spi_writel(spi_readl(SPIM_ENR)|(0x1<<0),SPIM_ENR)
 106 #define sram_spi_cs_dis()  spi_writel(spi_readl(SPIM_SER)&~0x3,SPIM_SER)
 107 #define sram_spi_cs_en()  spi_writel((spi_readl(SPIM_SER)&~0x3)|(0x1<<SRAM_SPI_CS),SPIM_SER)
 108 #define sram_spi_busy() (spi_readl(SPIM_SR)&SR_BUSY)
 109
 110 #define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset)
 111 #define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE+ offset)
 112
 113
 114 #define SPI_GATE1_MASK 0xCF
 115
 116 void  interface_ctr_reg_pread()
 117 {
 118         unsigned int temp,temp2;
 119
 120         temp=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
 121     temp2=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
 122
 123     writel(temp&~(SPI_GATE1_MASK),RK29_CRU_BASE + CRU_CLKGATE1_CON);
 124     writel(temp2&~(1<<(15+SRAM_SPI_CH)),RK29_CRU_BASE + CRU_CLKGATE2_CON);             //spi clock enable
 125
 126     readl(SRAM_SPI_ADDRBASE);
 127
 128     writel(temp2,RK29_CRU_BASE + CRU_CLKGATE2_CON);
 129     writel(temp,RK29_CRU_BASE + CRU_CLKGATE1_CON);
 130         readl(RK29_GPIO0_BASE);
 131         readl(RK29_GPIO1_BASE);
 132         readl(RK29_GPIO2_BASE);
 133         readl(RK29_GPIO3_BASE);
 134         readl(RK29_GPIO4_BASE);
 135         readl(RK29_GPIO5_BASE);
 136         readl(RK29_GPIO6_BASE);
 137
 138
 139 }
 140
 141
 142 static void  __sramfunc sram_spi_deinit(void)
 143 {
 144          sram_spi_dis();
 145
 146          spi_writel(spi_data[SPI_CTRLR0],SPIM_CTRLR0);
 147          spi_writel(spi_data[SPI_BAUDR],SPIM_BAUDR);
 148          spi_writel(spi_data[SPI_SER],SPIM_SER);
 149
 150
 151          writel(spi_data[GRF_IOM5c],RK29_GRF_BASE + 0x5c);
 152          writel(spi_data[GRF_IOM50],RK29_GRF_BASE +0x50);
 153
 154          writel(spi_data[CLKSEL6], RK29_CRU_BASE + CRU_CLKSEL6_CON);
 155          writel(spi_data[CLKGATE2],RK29_CRU_BASE + CRU_CLKGATE2_CON);
 156          writel(spi_data[CLKGATE1],RK29_CRU_BASE + CRU_CLKGATE1_CON);
 157 }
 158
 159 static void __sramfunc sram_spi_init(void)
 160 {
 161
 162         //sram_printch('V');
 163         /***************prihp clk*******************/
 164         spi_data[CLKGATE1]=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
 165         writel(spi_data[CLKGATE1]&~(SPI_GATE1_MASK),RK29_CRU_BASE + CRU_CLKGATE1_CON);
 166
 167         /***************spi sr clk speed*******************/
 168         spi_data[CLKSEL6]=readl(RK29_CRU_BASE + CRU_CLKSEL6_CON);
 169         writel((spi_data[CLKSEL6]&~(0x7f<<(2+SRAM_SPI_CH*9)))|(SRAM_SPI_SR_DIV<<(2+SRAM_SPI_CH*9)),
 170                 RK29_CRU_BASE + CRU_CLKSEL6_CON);//spi sr clk speed
 171
 172
 173         /***************spi clk enable*******************/
 174         spi_data[CLKGATE2]=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
 175         writel(spi_data[CLKGATE2]&~(1<<(15+SRAM_SPI_CH)),RK29_CRU_BASE + CRU_CLKGATE2_CON);//spi clk enable
 176
 177         /***************spi iomox*******************/
 178         spi_data[GRF_IOM50]=readl(RK29_GRF_BASE +0x50);
 179         spi_data[GRF_IOM5c]=readl(RK29_GRF_BASE +0x5c);
 180         if(SRAM_SPI_CS)
 181                 writel((spi_data[GRF_IOM50]&~(0x3<<(8-2*SRAM_SPI_CH)))|(0x2<<(8-2*SRAM_SPI_CH)),RK29_GRF_BASE +0x50);    //spi cs1  iomux
 182         else
 183                 writel((spi_data[GRF_IOM5c]&~(0x3<<(2+8*SRAM_SPI_CH)))|(0x1<<(2+8*SRAM_SPI_CH)),RK29_GRF_BASE +0x5c);   //spi cs0 iomux
 184
 185         writel((spi_data[GRF_IOM5c]&~(0xf3<<(SRAM_SPI_CH*8)))
 186                 |(0x51<<(SRAM_SPI_CH*8)),RK29_GRF_BASE +0x5c);  //spi clk\txd\rxd iomux
 187
 188
 189         /***************spi ctr*******************/
 190
 191         //spibase=spi_base[ch];
 192         //sram_spi_cs=cs;
 193
 194         sram_spi_dis();// disable spi
 195
 196         spi_data[SPI_CTRLR0] = spi_readl(SPIM_CTRLR0);
 197         spi_data[SPI_BAUDR] = spi_readl(SPIM_BAUDR);
 198         spi_writel((spi_data[SPI_CTRLR0]&~0x1fffc3)|0x1<<11|(SRAM_SPI_DATA_BYTE),SPIM_CTRLR0);//spi setting
 199         spi_writel((spi_data[SPI_BAUDR]&(~0xffff))|SRAM_SPI_DIV,SPIM_BAUDR);//setting spi speed
 200         spi_data[SPI_SER]=spi_readl(SPIM_SER);//spi cs
 201
 202 }
 203
 204 static void __sramfunc sram_spi_write(unsigned short add,unsigned short data)
 205 {
 206         sram_spi_cs_en();
 207         sram_udelay(10,24);
 208         sram_spi_en();
 209
 210         spi_writel(add,SPIM_TXDR);
 211         spi_writel(data,SPIM_TXDR);
 212         //delay_test(100);
 213
 214         sram_udelay(100,24);
 215
 216         //while(sram_spi_busy())
 217         //{
 218                 sram_udelay(1,24);
 219                 //sram_printch('B');
 220         //}
 221
 222         sram_spi_dis();
 223         sram_udelay(10,24);
 224         sram_spi_cs_dis();
 225 }
 226
 227 static unsigned short __sramfunc sram_spi_read(unsigned short add,unsigned short data){
 228         unsigned short ret=-1,ret1;
 229
 230         sram_spi_cs_en();
 231         sram_udelay(10,24);
 232         sram_spi_en();
 233
 234         spi_writel(add,SPIM_TXDR);
 235         //delay_test(100);
 236         spi_writel(data,SPIM_TXDR);
 237
 238         //while(sram_spi_busy())
 239         //{
 240                 sram_udelay(1,24);
 241                 //sram_printch('B');
 242         //}
 243
 244         sram_udelay(100,24);
 245
 246         ret1=spi_readl(SPIM_RXDR);
 247         ret=spi_readl(SPIM_RXDR);
 248
 249         //while(sram_spi_busy())
 250         //{
 251                 sram_udelay(1,24);
 252                 //sram_printch('B');
 253         //}
 254
 255         sram_spi_dis();
 256         sram_udelay(10,24);
 257         sram_spi_cs_dis();
 258         return ret;
 259 }
 260
 261
 262 unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
 263 {
 264 #if 0 //test
 265         unsigned short addr_4003=0x4003,addr_405d=0x405d,
 266                 addr_4059=0x4059,addr_405e=0x405e,addr_4063=0x4063;
 267         unsigned short data_4003,data_405d,
 268                 data_405e,data_4059,data_4063;
 269
 270         sram_printch('s');
 271         sram_spi_init();
 272         sram_printch('\n');
 273         sram_printch('M');
 274         data_4059=sram_spi_read(addr_4059|wm831x_RD_MSK,wm831x_RD_VOID);
 275         sram_printHX(data_4059);//dc1 sleep
 276
 277         data_405e=sram_spi_read(addr_405e|wm831x_RD_MSK,wm831x_RD_VOID);
 278         sram_printHX(data_405e);//dc2 sleep
 279
 280         data_4063=sram_spi_read(addr_4063|wm831x_RD_MSK,wm831x_RD_VOID);
 281         sram_printHX(data_405e);//dc3 sleep
 282
 283
 284
 285         data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
 286         sram_printHX(data_4003);//sleep ctr
 287
 288
 289
 290
 291
 292         sram_printch('N');
 293
 294         data_4059=(data_4059&~(0x7f))|0x68;
 295         sram_spi_write(addr_4059,data_4059);//dc1 sleep 3.0v
 296
 297         data_405e=(data_405e&~(0x7f))|0x28;//1.2 0x38 / 1.0 0x28,1.3 0x40
 298         sram_spi_write(addr_405e,data_405e);//dc2 sleep
 299
 300         data_4063=(data_4063&~(0x7f))|0x56;
 301         sram_spi_write(addr_4063,data_4063);//dc3 sleep 1.8V
 302
 303
 304
 305         sram_printch('J');
 306         data_4003|=(0x1<<14);
 307         sram_spi_write(addr_4003,data_4003);// sleep
 308
 309         sram_printch('L');
 310         data_4059=sram_spi_read(addr_4059|wm831x_RD_MSK,wm831x_RD_VOID);
 311         sram_printHX(data_4059);
 312
 313         data_405e=sram_spi_read(addr_405e|wm831x_RD_MSK,wm831x_RD_VOID);
 314         sram_printHX(data_405e);
 315
 316
 317         data_4063=sram_spi_read(addr_4063|wm831x_RD_MSK,wm831x_RD_VOID);
 318         sram_printHX(data_4063);
 319
 320         data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
 321         sram_printHX(data_4003);
 322
 323
 324
 325         sram_spi_deinit();
 326         #else
 327                 unsigned short addr_4003=0x4003;
 328                 unsigned short data_4003;
 329                 sram_spi_init();        //iomux  clk
 330                 data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
 331                 //sram_printHX(data_4003);//sleep ctr
 332                 //sram_printch('G');
 333                 sram_spi_write(addr_4003,data_4003|(0x1<<14));// sleep
 334                 data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
 335                 //sram_printHX(data_4003);//sleep ctr
 336                 sram_spi_deinit();
 337         #endif
 338         return 0;
 339 }
 340 void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
 341 {
 342
 343         unsigned short addr_4003=0x4003;
 344         unsigned short data_4003;
 345         sram_spi_init();    //iomux  clk
 346
 347         data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
 348         //sram_printHX(data_4003);//sleep ctr
 349
 350         //sram_printch('G');
 351         sram_spi_write(addr_4003,data_4003&~(0x1<<14));
 352
 353         data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
 354
 355         //sram_printHX(data_4003);//sleep ctr
 356
 357         sram_spi_deinit();
 358
 359         sram_udelay(100000, 24);
 360
 361
 362 }
 363 #endif
 364 /*******************************************gpio*********************************************/
 365 #ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
 366 #define PM_GETGPIO_BASE(N) RK29_GPIO##N##_BASE
 367 #define PM_GPIO_DR 0
 368 #define PM_GPIO_DDR 0x4
 369 #define PM_GPIO_INTEN 0x30
 370 __sramdata u32  pm_gpio_base[7]=
 371 {
 372 RK29_GPIO0_BASE,
 373 RK29_GPIO1_BASE,
 374 RK29_GPIO2_BASE,
 375 RK29_GPIO3_BASE,
 376 RK29_GPIO4_BASE,
 377 RK29_GPIO5_BASE,
 378 RK29_GPIO6_BASE
 379 };
 380
 381 #define pm_gpio_out_low(gpio) pm_gpio_set((gpio),GPIO_OUT,GPIO_LOW)
 382 #define pm_gpio_out_high(gpio) pm_gpio_set((gpio),GPIO_OUT,GPIO_HIGH)
 383
 384 void __sramfunc pm_gpio_set(unsigned gpio,eGPIOPinDirection_t direction,eGPIOPinLevel_t level)
 385 {
 386         unsigned group,pin,value;
 387         group=gpio/32;
 388         pin=gpio%32;
 389         if(group>6||pin>31)
 390                 return;
 391
 392         if(direction==GPIO_OUT)
 393         {
 394                 value=readl(pm_gpio_base[group]+PM_GPIO_DDR);
 395                 value|=0x1<<pin;
 396                 writel(value,pm_gpio_base[group]+PM_GPIO_DDR);
 397
 398                 value=readl(pm_gpio_base[group]+PM_GPIO_DR);
 399
 400                 if(level==GPIO_HIGH)
 401                         value|=0x1<<pin;
 402                 else
 403                         value&=~(0x1<<pin);
 404
 405                 writel(value,pm_gpio_base[group]+PM_GPIO_DR);
 406
 407
 408         }
 409         else
 410         {
 411                 value=readl(pm_gpio_base[group]+PM_GPIO_DDR);
 412                 value&=~(0x1<<pin);
 413                 writel(value,pm_gpio_base[group]+PM_GPIO_DDR);
 414
 415         }
 416 }
 417 #endif
 418 /*****************************************gpio ctr*********************************************/
 419 #if defined(CONFIG_RK29_GPIO_SUSPEND)
 420 #define GRF_GPIO0_DIR     0x000
 421 #define GRF_GPIO1_DIR     0x004
 422 #define GRF_GPIO2_DIR     0x008
 423 #define GRF_GPIO3_DIR     0x00c
 424 #define GRF_GPIO4_DIR     0x010
 425 #define GRF_GPIO5_DIR     0x014
 426
 427
 428 #define GRF_GPIO0_DO      0x018
 429 #define GRF_GPIO1_DO      0x01c
 430 #define GRF_GPIO2_DO      0x020
 431 #define GRF_GPIO3_DO      0x024
 432 #define GRF_GPIO4_DO      0x028
 433 #define GRF_GPIO5_DO      0x02c
 434
 435 #define GRF_GPIO0_EN      0x030
 436 #define GRF_GPIO1_EN      0x034
 437 #define GRF_GPIO2_EN      0x038
 438 #define GRF_GPIO3_EN      0x03c
 439 #define GRF_GPIO4_EN      0x040
 440 #define GRF_GPIO5_EN      0x044
 441
 442
 443 #define GRF_GPIO0L_IOMUX  0x048
 444 #define GRF_GPIO0H_IOMUX  0x04c
 445 #define GRF_GPIO1L_IOMUX  0x050
 446 #define GRF_GPIO1H_IOMUX  0x054
 447 #define GRF_GPIO2L_IOMUX  0x058
 448 #define GRF_GPIO2H_IOMUX  0x05c
 449 #define GRF_GPIO3L_IOMUX  0x060
 450 #define GRF_GPIO3H_IOMUX  0x064
 451 #define GRF_GPIO4L_IOMUX  0x068
 452 #define GRF_GPIO4H_IOMUX  0x06c
 453 #define GRF_GPIO5L_IOMUX  0x070
 454 #define GRF_GPIO5H_IOMUX  0x074
 455
 456 typedef struct GPIO_IOMUX
 457 {
 458     unsigned int GPIOL_IOMUX;
 459     unsigned int GPIOH_IOMUX;
 460 }GPIO_IOMUX_PM;
 461
 462 //GRF Registers
 463 typedef  struct REG_FILE_GRF
 464 {
 465    unsigned int GRF_GPIO_DIR[6];
 466    unsigned int GRF_GPIO_DO[6];
 467    unsigned int GRF_GPIO_EN[6];
 468    GPIO_IOMUX_PM GRF_GPIO_IOMUX[6];
 469    unsigned int GRF_GPIO_PULL[7];
 470 } GRF_REG_SAVE;
 471
 472
 473 static GRF_REG_SAVE  pm_grf;
 474 int __sramdata crumode;
 475  u32 __sramdata gpio2_pull,gpio6_pull;
 476 //static GRF_REG_SAVE __sramdata pm_grf;
 477 static void  pm_keygpio_prepare(void)
 478 {
 479         gpio6_pull = grf_readl(GRF_GPIO6_PULL);
 480         gpio2_pull = grf_readl(GRF_GPIO2_PULL);
 481 }
 482  void  pm_keygpio_sdk_suspend(void)
 483 {
 484     pm_keygpio_prepare();
 485         grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
 486         grf_writel(gpio2_pull|0x00000f30,GRF_GPIO2_PULL);
 487 }
 488  void  pm_keygpio_sdk_resume(void)
 489 {
 490         grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
 491         grf_writel(gpio2_pull,GRF_GPIO2_PULL);
 492 }
 493  void  pm_keygpio_a22_suspend(void)
 494 {
 495     pm_keygpio_prepare();
 496         grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
 497         grf_writel(gpio2_pull|0x00000900,GRF_GPIO2_PULL);
 498 }
 499  void  pm_keygpio_a22_resume(void)
 500 {
 501         grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
 502         grf_writel(gpio2_pull,GRF_GPIO2_PULL);
 503 }
 504
 505
 506 static void  pm_spi_gpio_prepare(void)
 507 {
 508         pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX = grf_readl(GRF_GPIO1L_IOMUX);
 509         pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX = grf_readl(GRF_GPIO2H_IOMUX);
 510
 511         pm_grf.GRF_GPIO_PULL[1] = grf_readl(GRF_GPIO1_PULL);
 512         pm_grf.GRF_GPIO_PULL[2] = grf_readl(GRF_GPIO2_PULL);
 513
 514         pm_grf.GRF_GPIO_EN[1] = grf_readl(GRF_GPIO1_EN);
 515         pm_grf.GRF_GPIO_EN[2] = grf_readl(GRF_GPIO2_EN);
 516 }
 517
 518  void  pm_spi_gpio_suspend(void)
 519 {
 520         int io1L_iomux;
 521         int io2H_iomux;
 522         int io1_pull,io2_pull;
 523         int io1_en,io2_en;
 524
 525         pm_spi_gpio_prepare();
 526
 527         io1L_iomux = grf_readl(GRF_GPIO1L_IOMUX);
 528         io2H_iomux = grf_readl(GRF_GPIO2H_IOMUX);
 529
 530         grf_writel(io1L_iomux&(~((0x03<<6)|(0x03 <<8))), GRF_GPIO1L_IOMUX);
 531         grf_writel(io2H_iomux&0xffff0000, GRF_GPIO2H_IOMUX);
 532
 533         io1_pull = grf_readl(GRF_GPIO1_PULL);
 534         io2_pull = grf_readl(GRF_GPIO2_PULL);
 535
 536         grf_writel(io1_pull|0x18,GRF_GPIO1_PULL);
 537         grf_writel(io2_pull|0x00ff0000,GRF_GPIO2_PULL);
 538
 539         io1_en = grf_readl(GRF_GPIO1_EN);
 540         io2_en = grf_readl(GRF_GPIO2_EN);
 541
 542         grf_writel(io1_en|0x18,GRF_GPIO1_EN);
 543         grf_writel(io2_en|0x00ff0000,GRF_GPIO2_EN);
 544 }
 545
 546  void  pm_spi_gpio_resume(void)
 547 {
 548         grf_writel(pm_grf.GRF_GPIO_EN[1],GRF_GPIO1_EN);
 549         grf_writel(pm_grf.GRF_GPIO_EN[2],GRF_GPIO2_EN);
 550         grf_writel(pm_grf.GRF_GPIO_PULL[1],GRF_GPIO1_PULL);
 551         grf_writel(pm_grf.GRF_GPIO_PULL[2],GRF_GPIO2_PULL);
 552
 553         grf_writel(pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX, GRF_GPIO1L_IOMUX);
 554         grf_writel(pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX, GRF_GPIO2H_IOMUX);
 555 }
 556
 557 void pm_gpio_suspend(void)
 558 {
 559         pm_spi_gpio_suspend(); // spi  pullup/pulldown  disable....
 560         #if defined(CONFIG_MACH_RK29_PHONESDK)
 561         {       pm_keygpio_sdk_suspend();// key  pullup/pulldown  disable.....
 562         }
 563         #endif
 564         #if defined(CONFIG_MACH_RK29_A22)
 565         {       pm_keygpio_a22_suspend();// key  pullup/pulldown  disable.....
 566         }
 567         #endif
 568 }
 569 void pm_gpio_resume(void)
 570 {
 571         pm_spi_gpio_resume(); // spi  pullup/pulldown  enable.....
 572         #if defined(CONFIG_MACH_RK29_PHONESDK)
 573         {       pm_keygpio_sdk_resume();// key  pullup/pulldown  enable.....
 574         }
 575         #endif
 576         #if defined(CONFIG_MACH_RK29_A22)
 577         {       pm_keygpio_a22_resume();// key  pullup/pulldown  enable.....
 578         }
 579         #endif
 580 }
 581 #else
 582 void pm_gpio_suspend(void)
 583 {}
 584 void pm_gpio_resume(void)
 585 {}
 586 #endif
 587 /*************************************neon powerdomain******************************/
 588 #define vfpreg(_vfp_) #_vfp_
 589
 590 #define fmrx(_vfp_) ({                  \
 591         u32 __v;                        \
 592         asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx   %0, " #_vfp_    \
 593             : "=r" (__v) : : "cc");     \
 594         __v;                            \
 595  })
 596
 597 #define fmxr(_vfp_,_var_)               \
 598         asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr   " #_vfp_ ", %0" \
 599            : : "r" (_var_) : "cc")
 600
 601 #define pmu_read(offset)                readl(RK29_PMU_BASE + (offset))
 602 #define pmu_write(offset, value)        writel((value), RK29_PMU_BASE + (offset))
 603 #define PMU_PG_CON 0x10
 604 extern void vfp_save_state(void *location, u32 fpexc);
 605 extern void vfp_load_state(void *location, u32 fpexc);
 606  static u64 __sramdata saveptr[33]={};
 607 void  neon_powerdomain_off(void)
 608 {
 609         int ret,i=0;
 610         int *p;
 611         p=&saveptr;
 612          unsigned int fpexc = fmrx(FPEXC);  //get neon Logic gate
 613
 614         fmxr(FPEXC, fpexc | FPEXC_EN);  //open neon Logic gate
 615         for(i=0;i<34;i++){
 616         vfp_save_state(p,fpexc);                        //save neon reg,32 D reg,2 control reg
 617         p++;
 618         }
 619         fmxr(FPEXC, fpexc & ~FPEXC_EN);    //close neon Logic gate
 620
 621          ret=pmu_read(PMU_PG_CON);                   //get power domain state
 622         pmu_write(PMU_PG_CON,ret|(0x1<<1));          //powerdomain off neon
 623
 624 }
 625 void   neon_powerdomain_on(void)
 626 {
 627         int ret,i=0;
 628         int *p;
 629         p=&saveptr;
 630
 631         ret=pmu_read(PMU_PG_CON);                   //get power domain state
 632         pmu_write(PMU_PG_CON,ret&~(0x1<<1));                //powerdomain on neon
 633         sram_udelay(5000,24);
 634
 635         unsigned int fpexc = fmrx(FPEXC);              //get neon Logic gate
 636         fmxr(FPEXC, fpexc | FPEXC_EN);                   //open neon Logic gate
 637         for(i=0;i<34;i++){
 638         vfp_load_state(p,fpexc);   //recovery neon reg, 32 D reg,2 control reg
 639         p++;
 640         }
 641         fmxr(FPEXC, fpexc | FPEXC_EN);      //open neon Logic gate
 642
 643 }
 644
 645
 646
 647
 648 /*************************************************32k**************************************/
 649
 650 #ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
 651 //static int __sramdata crumode;
 652 void __sramfunc pm_clk_switch_32k(void)
 653 {
 654         int vol;
 655         sram_printch('7');
 656
 657         #ifndef CONFIG_MACH_RK29_A22
 658         pm_gpio_out_high(RK29_PIN4_PC0);
 659         #endif
 660         //sram_udelay(10,30);
 661
 662         crumode=cru_readl(CRU_MODE_CON); //24M to 27M
 663         cru_writel((crumode&(~0x7fff))|0x2baa, CRU_MODE_CON);
 664         //sram_udelay(10,30);
 665
 666 //      pm_gpio_iomux(RK29_PIN4_PC5,0x0);// disable 24
 667         pm_gpio_out_high(RK29_PIN4_PC5);
 668
 669         //sram_udelay(10,30);
 670         dsb();
 671         asm("wfi");
 672
 673         pm_gpio_out_low(RK29_PIN4_PC5);//enable 24M
 674         sram_udelay(20,24);             //the system clock is 32.768K
 675         cru_writel(crumode, CRU_MODE_CON); //externel clk 24M
 676
 677         #ifndef CONFIG_MACH_RK29_A22
 678         pm_gpio_out_low(RK29_PIN4_PC0); //enable 27M
 679         #endif
 680         //sram_udelay(1000,27);
 681         sram_printch('7');
 682
 683
 684 }
 685
 686 #else
 687 void __sramfunc pm_clk_switch(void)
 688 {
 689
 690 }
 691 #endif