arch/arm/mach-rk29/pm.c

   1 #define DEBUG
   2
   3 #include <linux/clk.h>
   4 #include <linux/delay.h>
   5 #include <linux/err.h>
   6 #include <linux/kernel.h>
   7 #include <linux/init.h>
   8 #include <linux/pm.h>
   9 #include <linux/suspend.h>
  10 #include <linux/random.h>
  11 #include <linux/crc32.h>
  12 #include <linux/io.h>
  13 #include <linux/wakelock.h>
  14 #include <asm/tlbflush.h>
  15 #include <asm/hardware/gic.h>
  16
  17 #include <mach/rk29_iomap.h>
  18 #include <mach/cru.h>
  19 #include <mach/pmu.h>
  20 #include <mach/board.h>
  21 #include <mach/system.h>
  22 #include <mach/sram.h>
  23 #include <mach/gpio.h>
  24 #include <mach/ddr.h>
  25 #include <mach/memtester.h>
  26 #include <mach/iomux.h>
  27 #include <mach/pm-vol.h>
  28
  29 #include <asm/vfp.h>
  30
  31 #define grf_readl(offset) readl(RK29_GRF_BASE + offset)
  32 #define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
  33
  34 static unsigned long save_sp;
  35
  36 static inline void delay_500ns(void)
  37 {
  38         LOOP(LOOPS_PER_USEC);
  39 }
  40
  41 static inline void delay_300us(void)
  42 {
  43         LOOP(300 * LOOPS_PER_USEC);
  44 }
  45
  46 #ifdef DEBUG
  47  void/* inline*/ __sramfunc sram_printch(char byte)
  48 {
  49         unsigned long flags;
  50         u32 gate1, gate2;
  51
  52         local_irq_save(flags);
  53         gate1 = cru_readl(CRU_CLKGATE1_CON);
  54         gate2 = cru_readl(CRU_CLKGATE2_CON);
  55         cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
  56         cru_writel(gate2 & ~(1 << CLK_GATE_UART1 % 32), CRU_CLKGATE2_CON);
  57         delay_500ns();
  58
  59         writel(byte, RK29_UART1_BASE);
  60
  61         /* loop check LSR[6], Transmitter Empty bit */
  62         while (!(readl(RK29_UART1_BASE + 0x14) & 0x40))
  63                 barrier();
  64
  65         cru_writel(gate2, CRU_CLKGATE2_CON);
  66         cru_writel(gate1, CRU_CLKGATE1_CON);
  67         local_irq_restore(flags);
  68         if (byte == '\n')
  69                 sram_printch('\r');
  70 }
  71
  72  void __sramfunc sram_printascii(const char *s)
  73 {
  74         while (*s) {
  75                 if (*s == '\n')
  76                 {
  77                     sram_printch('\r');
  78                 }
  79             sram_printch(*s);
  80             s++;
  81         }
  82 }
  83 void print(const char *s)
  84 {
  85     sram_printascii(s);
  86 }
  87
  88 void __sramfunc print_Hex(unsigned int hex)
  89 {
  90         int i = 8;
  91         sram_printch('0');
  92         sram_printch('x');
  93         while (i--) {
  94                 unsigned char c = (hex & 0xF0000000) >> 28;
  95                 sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
  96                 hex <<= 4;
  97         }
  98 }
  99
 100 void __sramfunc print_Dec (uint32_t n)
 101 {
 102     if (n >= 10)
 103     {
 104         print_Dec(n / 10);
 105         n %= 10;
 106     }
 107     sram_printch((char)(n + '0'));
 108 }
 109
 110 void print_Dec_3(uint32_t value)
 111 {
 112     if(value<10)
 113     {
 114         print("  ");
 115     }
 116     else if(value<100)
 117     {
 118         print(" ");
 119     }
 120     else
 121     {
 122     }
 123     print_Dec(value);
 124 }
 125
 126 static void /* inline*/ __sramfunc printhex(unsigned int hex)
 127 {
 128         int i = 8;
 129         sram_printch('0');
 130         sram_printch('x');
 131         while (i--) {
 132                 unsigned char c = (hex & 0xF0000000) >> 28;
 133                 sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
 134                 hex <<= 4;
 135         }
 136 }
 137 #else
 138 static void inline sram_printch(char byte) {}
 139 static void inline sram_printascii(const char *s) {}
 140 static void inline printhex(unsigned int hex) {}
 141 #endif /* DEBUG */
 142
 143 /*volatile __sramdata */int ddr_debug;
 144 module_param(ddr_debug, int, 0644);
 145 #if 1
 146 static int inline calc_crc32(u32 addr, size_t len)
 147 {
 148      return crc32_le(~0,(const unsigned char *)addr,len);
 149 }
 150 void __sramfunc ddr_testmode(void)
 151 {
 152     int32_t g_crc1,g_crc2;
 153     uint32_t nMHz;
 154     uint32_t n = 0;
 155     extern char _stext[], _etext[];
 156     if(ddr_debug == 1)
 157     {
 158         for (;;)
 159         {
 160                 sram_printascii("change freq\n");
 161             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 162             nMHz = 333 + random32();
 163             nMHz %= 490;
 164             if(nMHz < 100)
 165                 nMHz = 100;
 166             nMHz = ddr_change_freq(nMHz);
 167                 printhex(nMHz);
 168                 sram_printch(' ');
 169                 printhex(n++);
 170                 sram_printch(' ');
 171             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 172             if (g_crc1!=g_crc2)
 173             {
 174                     sram_printascii("fail\n");
 175                 }
 176                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 177            //     sram_printascii("change freq success\n");
 178         }
 179     }
 180     else if(ddr_debug == 2)
 181     {
 182         for (;;)
 183         {
 184                 sram_printch(' ');
 185                 sram_printch('9');
 186                 sram_printch('9');
 187                 sram_printch('9');
 188                 sram_printch(' ');
 189             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 190             nMHz = (random32()>>13);// 16.7s max
 191             ddr_suspend();
 192             delayus(nMHz);
 193             ddr_resume();
 194                 printhex(nMHz);
 195                 sram_printch(' ');
 196                 printhex(n++);
 197             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 198             if (g_crc1!=g_crc2)
 199             {
 200                     sram_printch(' ');
 201                     sram_printch('f');
 202                     sram_printch('a');
 203                     sram_printch('i');
 204                     sram_printch('l');
 205                 }
 206               // ddr_print("check image crc32 fail!, count:%d\n", n++);
 207             //    sram_printascii("self refresh fail\n");
 208             //else
 209                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 210             //    sram_printascii("self refresh success\n");
 211         }
 212     }
 213     else if(ddr_debug == 3)
 214     {
 215         memtester();
 216     }
 217 }
 218 #else
 219 void __sramfunc ddr_testmode(void)
 220 {}
 221
 222 #endif
 223 void __sramfunc pm_clk_switch_32k(void);
 224
 225 void __sramfunc pm_wfi(void)
 226 {
 227         u32 clksel0;
 228         sram_printch('7');
 229         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 230         /* set arm clk 24MHz/32 = 750KHz */
 231         cru_writel(clksel0 | 0x1F, CRU_CLKSEL0_CON);
 232
 233         sram_printch('8');
 234         dsb();
 235         asm("wfi");
 236         sram_printch('8');
 237
 238         /* resume arm clk */
 239         cru_writel(clksel0, CRU_CLKSEL0_CON);
 240         sram_printch('7');
 241
 242
 243 }
 244
 245 static void __sramfunc rk29_sram_suspend(void)
 246 {
 247         u32 vol;
 248
 249         if (ddr_debug == 2)
 250                 ddr_testmode();
 251
 252         sram_printch('5');
 253         ddr_suspend();
 254
 255         sram_printch('6');
 256         vol=rk29_suspend_voltage_set(1000000);
 257 #ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
 258         pm_clk_switch_32k();
 259 #else
 260         pm_wfi();
 261 #endif
 262         rk29_suspend_voltage_resume(vol);
 263         sram_printch('6');
 264
 265         ddr_resume();
 266         sram_printch('5');
 267 }
 268
 269 static void noinline rk29_suspend(void)
 270 {
 271         DDR_SAVE_SP(save_sp);
 272         rk29_sram_suspend();
 273         DDR_RESTORE_SP(save_sp);
 274 }
 275
 276 static void dump_irq(void)
 277 {
 278         u32 irq_gpio = (readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8) >> 23) & 0x7F;
 279         printk("wakeup irq: %08x %08x %01x\n",
 280                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 4),
 281                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8),
 282                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 12) & 0xf);
 283         if (irq_gpio & 1)
 284                 printk("wakeup gpio0: %08x\n", readl(RK29_GPIO0_BASE + GPIO_INT_STATUS));
 285         if (irq_gpio & 2)
 286                 printk("wakeup gpio1: %08x\n", readl(RK29_GPIO1_BASE + GPIO_INT_STATUS));
 287         if (irq_gpio & 4)
 288                 printk("wakeup gpio2: %08x\n", readl(RK29_GPIO2_BASE + GPIO_INT_STATUS));
 289         if (irq_gpio & 8)
 290                 printk("wakeup gpio3: %08x\n", readl(RK29_GPIO3_BASE + GPIO_INT_STATUS));
 291         if (irq_gpio & 0x10)
 292                 printk("wakeup gpio4: %08x\n", readl(RK29_GPIO4_BASE + GPIO_INT_STATUS));
 293         if (irq_gpio & 0x20)
 294                 printk("wakeup gpio5: %08x\n", readl(RK29_GPIO5_BASE + GPIO_INT_STATUS));
 295         if (irq_gpio & 0x40)
 296                 printk("wakeup gpio6: %08x\n", readl(RK29_GPIO6_BASE + GPIO_INT_STATUS));
 297 }
 298
 299 #define DUMP_GPIO_INTEN(ID) \
 300 do { \
 301         u32 en = readl(RK29_GPIO##ID##_BASE + GPIO_INTEN); \
 302         if (en) { \
 303                 sram_printascii("GPIO" #ID "_INTEN: "); \
 304                 printhex(en); \
 305                 sram_printch('\n'); \
 306         } \
 307 } while (0)
 308
 309 static void dump_inten(void)
 310 {
 311         DUMP_GPIO_INTEN(0);
 312         DUMP_GPIO_INTEN(1);
 313         DUMP_GPIO_INTEN(2);
 314         DUMP_GPIO_INTEN(3);
 315         DUMP_GPIO_INTEN(4);
 316         DUMP_GPIO_INTEN(5);
 317         DUMP_GPIO_INTEN(6);
 318 }
 319
 320
 321
 322 #define DUMP_GPIO_PULL(ID) \
 323 do { \
 324         u32 state = readl(RK29_GRF_BASE + GRF_GPIO0_PULL + (ID<<2)); \
 325         sram_printascii("GPIO" #ID "_PULL: "); \
 326         printhex(state); \
 327         sram_printch('\n'); \
 328 } while (0)
 329
 330 static void dump_io_pull(void)
 331 {
 332         DUMP_GPIO_PULL(0);
 333         DUMP_GPIO_PULL(1);
 334         DUMP_GPIO_PULL(2);
 335         DUMP_GPIO_PULL(3);
 336         DUMP_GPIO_PULL(4);
 337         DUMP_GPIO_PULL(5);
 338         DUMP_GPIO_PULL(6);
 339 }
 340 #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 341 /*******************************neon powermain***********************/
 342 #define pmu_read(offset)                readl(RK29_PMU_BASE + (offset))
 343 #define pmu_write(offset, value)        writel((value), RK29_PMU_BASE + (offset))
 344 #define PMU_PG_CON 0x10
 345 #define vfpreg(_vfp_) #_vfp_
 346
 347 #define fmrx(_vfp_) ({                  \
 348         u32 __v;                        \
 349         asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx   %0, " #_vfp_    \
 350             : "=r" (__v) : : "cc");     \
 351         __v;                            \
 352  })
 353
 354 #define fmxr(_vfp_,_var_)               \
 355         asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr   " #_vfp_ ", %0" \
 356            : : "r" (_var_) : "cc")
 357 extern void vfp_save_state(void *location, u32 fpexc);
 358 extern void vfp_load_state(void *location, u32 fpexc);
 359 // extern  __sramdata u64  saveptr[33];
 360 static u32  saveptr[2][60]={};
 361 void  neon_powerdomain_off(void)
 362 {
 363         int ret,i=0;
 364         int *p;
 365         p=&saveptr[0][0];
 366
 367          unsigned int fpexc = fmrx(FPEXC);  //get neon Logic gate
 368
 369         fmxr(FPEXC, fpexc | FPEXC_EN);  //open neon Logic gate
 370         for(i=0;i<36;i++){
 371         vfp_save_state(p,fpexc);                        //save neon reg,32 D reg,2 control reg
 372         p++;
 373         }
 374         fmxr(FPEXC, fpexc & ~FPEXC_EN);    //close neon Logic gate
 375
 376          ret=pmu_read(PMU_PG_CON);                   //get power domain state
 377         pmu_write(PMU_PG_CON,ret|(0x1<<1));          //powerdomain off neon
 378         printk("neon powerdomain is off\n");
 379 }
 380 void   neon_powerdomain_on(void)
 381 {
 382         int ret,i=0;
 383         int *p;
 384         p=&saveptr[0][0];
 385
 386         ret=pmu_read(PMU_PG_CON);                   //get power domain state
 387         pmu_write(PMU_PG_CON,ret&~(0x1<<1));                //powerdomain on neon
 388         mdelay(4);
 389
 390         unsigned int fpexc = fmrx(FPEXC);              //get neon Logic gate
 391         fmxr(FPEXC, fpexc | FPEXC_EN);                   //open neon Logic gate
 392         for(i=0;i<36;i++){
 393         vfp_load_state(p,fpexc);   //recovery neon reg, 32 D reg,2 control reg
 394         p++;
 395         }
 396         fmxr(FPEXC, fpexc | FPEXC_EN);      //open neon Logic gate
 397         printk("neon powerdomain is on\n");
 398 }
 399 #endif
 400
 401 void pm_gpio_suspend(void);
 402 void pm_gpio_resume(void);
 403
 404 static int rk29_pm_enter(suspend_state_t state)
 405 {
 406         u32 apll, cpll, gpll, mode, clksel0;
 407         u32 clkgate[4];
 408
 409         #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 410         neon_powerdomain_off();
 411         #endif
 412
 413         // memory teseter
 414         if (ddr_debug != 2)
 415                 ddr_testmode();
 416
 417         // dump GPIO INTEN for debug
 418         dump_inten();
 419         // dump GPIO PULL state for debug
 420         //if you want to display the information, please enable the code.
 421 #if 0
 422         dump_io_pull();
 423 #endif
 424
 425         sram_printch('0');
 426         flush_tlb_all();
 427         interface_ctr_reg_pread();
 428
 429         /* disable clock */
 430         clkgate[0] = cru_readl(CRU_CLKGATE0_CON);
 431         clkgate[1] = cru_readl(CRU_CLKGATE1_CON);
 432         clkgate[2] = cru_readl(CRU_CLKGATE2_CON);
 433         clkgate[3] = cru_clkgate3_con_mirror;
 434         cru_writel(~((1 << CLK_GATE_CORE)
 435                    | (1 << CLK_GATE_ACLK_CPU)
 436                    | (1 << CLK_GATE_ACLK_CPU2)
 437                    | (1 << CLK_GATE_PCLK_CPU)
 438                    | (1 << CLK_GATE_GIC)
 439                    | (1 << CLK_GATE_INTMEM)
 440                    | (1 << CLK_GATE_DDR_PHY)
 441                    | (1 << CLK_GATE_DDR_REG)
 442                    | (1 << CLK_GATE_DDR_CPU)
 443                    | (1 << CLK_GATE_GPIO0)
 444                    | (1 << CLK_GATE_RTC)
 445                    | (1 << CLK_GATE_GRF)
 446 #ifdef CONFIG_RK29_JTAG
 447                    | (1 << CLK_GATE_PCLK_CORE)
 448                    | (1 << CLK_GATE_ATCLK_CORE)
 449                    | (1 << CLK_GATE_ATCLK_CPU)
 450                    | (1 << CLK_GATE_DEBUG)
 451                    | (1 << CLK_GATE_TPIU)
 452 #endif
 453                    ) | clkgate[0], CRU_CLKGATE0_CON);
 454         cru_writel(~0, CRU_CLKGATE1_CON);
 455         cru_writel(~((1 << CLK_GATE_GPIO1 % 32)
 456                    | (1 << CLK_GATE_GPIO2 % 32)
 457                    | (1 << CLK_GATE_GPIO3 % 32)
 458                    | (1 << CLK_GATE_GPIO4 % 32)
 459                    | (1 << CLK_GATE_GPIO5 % 32)
 460                    | (1 << CLK_GATE_GPIO6 % 32)
 461                    | (1 << CLK_GATE_PWM % 32)
 462 #ifdef CONFIG_RK29_JTAG
 463                    | (1 << CLK_GATE_JTAG % 32)
 464 #endif
 465                    ) | clkgate[2], CRU_CLKGATE2_CON);
 466         cru_writel(~0, CRU_CLKGATE3_CON);
 467         sram_printch('1');
 468
 469         mode = cru_readl(CRU_MODE_CON);
 470         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 471
 472         /* suspend arm pll */
 473         apll = cru_readl(CRU_APLL_CON);
 474         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 475         cru_writel(apll | PLL_BYPASS, CRU_APLL_CON);
 476         cru_writel(apll | PLL_PD | PLL_BYPASS, CRU_APLL_CON);
 477         delay_500ns();
 478         /* set core = aclk_cpu = hclk_cpu = pclk_cpu = 24MHz */
 479         cru_writel(clksel0 & 0xFFFFF000, CRU_CLKSEL0_CON);
 480         sram_printch('2');
 481
 482         /* suspend codec pll */
 483         cpll = cru_readl(CRU_CPLL_CON);
 484         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 485         cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 486         cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 487         delay_500ns();
 488         sram_printch('3');
 489
 490         /* suspend general pll */
 491         gpll = cru_readl(CRU_GPLL_CON);
 492         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 493         cru_writel(gpll | PLL_BYPASS, CRU_GPLL_CON);
 494         cru_writel(gpll | PLL_PD | PLL_BYPASS, CRU_GPLL_CON);
 495         delay_500ns();
 496         /* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
 497         cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
 498
 499         sram_printch('4');
 500
 501         rk29_suspend();
 502
 503         sram_printch('4');
 504
 505         /* resume general pll */
 506         cru_writel(gpll, CRU_GPLL_CON);
 507         delay_300us();
 508         /* restore aclk_periph/hclk_periph/pclk_periph */
 509         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0x7FC000), CRU_CLKSEL0_CON);
 510         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | (mode & CRU_GENERAL_MODE_MASK), CRU_MODE_CON);
 511         sram_printch('3');
 512
 513         /* resume codec pll */
 514         cru_writel(cpll, CRU_CPLL_CON);
 515         delay_300us();
 516         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | (mode & CRU_CODEC_MODE_MASK), CRU_MODE_CON);
 517         sram_printch('2');
 518
 519         /* resume arm pll */
 520         cru_writel(apll, CRU_APLL_CON);
 521         delay_300us();
 522         /* restore core/aclk_cpu/hclk_cpu/pclk_cpu */
 523         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0xFFF), CRU_CLKSEL0_CON);
 524         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | (mode & CRU_CPU_MODE_MASK), CRU_MODE_CON);
 525         sram_printch('1');
 526
 527         /* enable clock */
 528         cru_writel(clkgate[0], CRU_CLKGATE0_CON);
 529         cru_writel(clkgate[1], CRU_CLKGATE1_CON);
 530         cru_writel(clkgate[2], CRU_CLKGATE2_CON);
 531         cru_writel(clkgate[3], CRU_CLKGATE3_CON);
 532         sram_printascii("0\n");
 533
 534         dump_irq();
 535
 536         #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 537         neon_powerdomain_on();
 538         #endif
 539
 540         return 0;
 541 }
 542
 543 static int rk29_pm_prepare(void)
 544 {
 545         /* disable entering rk29_idle() by disable_hlt() */
 546         disable_hlt();
 547         return 0;
 548 }
 549
 550 static void rk29_pm_finish(void)
 551 {
 552         enable_hlt();
 553 }
 554
 555 static struct platform_suspend_ops rk29_pm_ops = {
 556         .enter          = rk29_pm_enter,
 557         .valid          = suspend_valid_only_mem,
 558         .prepare        = rk29_pm_prepare,
 559         .finish         = rk29_pm_finish,
 560 };
 561
 562 static void rk29_idle(void)
 563 {
 564         if (!need_resched()) {
 565                 int allow_sleep = 1;
 566 #ifdef CONFIG_HAS_WAKELOCK
 567                 allow_sleep = !has_wake_lock(WAKE_LOCK_IDLE);
 568 #endif
 569                 if (allow_sleep) {
 570                         u32 mode_con = cru_readl(CRU_MODE_CON);
 571                         cru_writel((mode_con & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 572                         arch_idle();
 573                         cru_writel(mode_con, CRU_MODE_CON);
 574                 } else {
 575                         arch_idle();
 576                 }
 577         }
 578         local_irq_enable();
 579 }
 580
 581 static int __init rk29_pm_init(void)
 582 {
 583         suspend_set_ops(&rk29_pm_ops);
 584
 585         /* set idle function */
 586         pm_idle = rk29_idle;
 587         ddr_debug = 0;
 588
 589 #ifdef CONFIG_EARLYSUSPEND
 590         pm_set_vt_switch(0); /* disable vt switch while suspend */
 591 #endif
 592
 593         return 0;
 594 }
 595 __initcall(rk29_pm_init);