3 * arch/arm/mach-rk29/include/mach/rk29_nand.h
5 * Copyright (C) 2010 RockChip, Inc.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #ifndef __ASM_ARCH_RK29_NAND_H
19 #define __ASM_ARCH_RK29_NAND_H
24 #define BCH_RST 0x0001
26 #define FL_RDY (0x1<<20)
27 #define FL_LBA_EN (0x1<<11)
28 #define FL_COR_EN (0x1<<10)
29 #define FL_INT_EN (0x1<<9)
30 #define FL_INTCLR (0x1<<8)
31 #define FL_STMOD (0x1<<7)
32 #define FL_TRCNT (0x3<<5)
33 #define FL_STADDR (0x1<<4)
34 #define FL_BYPASS (0x1<<3)
35 #define FL_START (0x1<<2)
36 #define FL_RDN (0x1<<1)
37 #define FL_RST (0x1<<0)
39 #define FMC_WP (0x1<<8)
40 #define FMC_FRDY (0x1<<9)
41 #define FMC_FRDY_INT_EN (0x1<<10)
42 #define FMC_FRDY_INT_CLR (0x1<<11)
43 #define FMC_WIDTH_16 (0x1<<12)
45 #define FMW_RWCS_OFFSET 0
46 #define FMW_RWPW_OFFSET 5
47 #define FMW_RDY (0x1<<11)
48 #define FMW_CSRW_OFFSET 12
49 #define FMW_DLY_OFFSET 24//16
51 struct rk29_nand_timing {
52 unsigned int tCH; /* Enable signal hold time */
53 unsigned int tCS; /* Enable signal setup time */
54 unsigned int tWH; /* ND_nWE high duration */
55 unsigned int tWP; /* ND_nWE pulse time */
56 unsigned int tRH; /* ND_nRE high duration */
57 unsigned int tRP; /* ND_nRE pulse width */
58 unsigned int tR; /* ND_nWE high to ND_nRE low for read */
59 unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
60 unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
63 struct rk29_nand_cmdset {
76 typedef volatile struct tagCHIP_IF
81 uint32_t RESERVED[0x3d];
85 typedef volatile struct tagNANDC
87 volatile uint32_t FMCTL;
88 volatile uint32_t FMWAIT;
89 volatile uint32_t FLCTL;
90 volatile uint32_t BCHCTL;
91 volatile uint32_t BCHST;
92 volatile uint32_t RESERVED1[(0x200-0x14)/4]; //FLR
93 volatile uint32_t spare[0x200/4];
94 volatile uint32_t FMCTL1;
95 volatile uint32_t FMWAIT1;
96 volatile uint32_t FLCTL1;
97 volatile uint32_t BCHCTL1;
98 volatile uint32_t BCHST1;
99 volatile uint32_t RESERVED2[(0x200-0x14)/4];
100 volatile uint32_t RESERVED3[0x200/4];
101 volatile CHIP_IF chip[8];
102 volatile uint32_t buf[0x800/4];
105 struct rk29_nand_flash {
106 const struct rk29_nand_timing *timing; /* NAND Flash timing */
107 const struct rk29_nand_cmdset *cmdset;
109 uint32_t page_per_block; /* Pages per block (PG_PER_BLK) */
110 uint32_t page_size; /* Page size in bytes (PAGE_SZ) */
111 uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */
112 uint32_t num_blocks; /* Number of physical blocks in Flash */
116 struct rk29_nand_platform_data {
118 int width; /* data bus width in bytes */
119 int hw_ecc; /* 1:hw ecc, 0: soft ecc */
120 struct mtd_partition *parts;
121 unsigned int nr_parts;
123 int (*io_init)(void);
124 int (*io_deinit)(void);
128 #endif /* __ASM_ARCH_RK29_NAND_H */