arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33 #include <mach/pmu.h>
  34 #include <mach/sram.h>
  35 #include <mach/board.h>
  36
  37
  38 /* Clock flags */
  39 /* bit 0 is free */
  40 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  41 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  42 #define IS_PD                   (1 << 2)        /* Power Domain */
  43
  44 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  45 #define pmu_readl(offset)       readl(RK29_PMU_BASE + offset)
  46
  47 #define MHZ                     (1000*1000)
  48 #define KHZ                     1000
  49
  50 struct clk {
  51         struct list_head        node;
  52         const char              *name;
  53         struct clk              *parent;
  54         struct list_head        children;
  55         struct list_head        sibling;        /* node for children */
  56         unsigned long           rate;
  57         u32                     flags;
  58         int                     (*mode)(struct clk *clk, int on);
  59         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  60         int                     (*set_rate)(struct clk *, unsigned long);
  61         long                    (*round_rate)(struct clk *, unsigned long);
  62         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
  63         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
  64         s32                     usecount;
  65         u8                      gate_idx;
  66         u8                      pll_idx;
  67         u8                      clksel_con;
  68         u8                      clksel_mask;
  69         u8                      clksel_shift;
  70         u8                      clksel_maxdiv;
  71         u8                      clksel_parent_mask;
  72         u8                      clksel_parent_shift;
  73         struct clk              **parents;
  74 };
  75
  76 static int clk_enable_nolock(struct clk *clk);
  77 static void clk_disable_nolock(struct clk *clk);
  78 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
  79 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
  80 static void __clk_reparent(struct clk *child, struct clk *parent);
  81 static void __propagate_rate(struct clk *tclk);
  82 static struct clk codec_pll_clk;
  83 static struct clk general_pll_clk;
  84
  85 static unsigned long clksel_recalc_div(struct clk *clk)
  86 {
  87         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
  88         unsigned long rate = clk->parent->rate / div;
  89         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
  90         return rate;
  91 }
  92
  93 static unsigned long clksel_recalc_shift(struct clk *clk)
  94 {
  95         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
  96         unsigned long rate = clk->parent->rate >> shift;
  97         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
  98         return rate;
  99 }
 100
 101 static unsigned long clksel_recalc_frac(struct clk *clk)
 102 {
 103         unsigned long rate;
 104         u64 rate64;
 105         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 106         if (r == 0) // FPGA ?
 107                 return clk->parent->rate;
 108         numerator = r >> 16;
 109         denominator = r & 0xFFFF;
 110         rate64 = (u64)clk->parent->rate * numerator;
 111         do_div(rate64, denominator);
 112         rate = rate64;
 113         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 114         return rate;
 115 }
 116
 117 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 118 {
 119         u32 div;
 120
 121         for (div = 0; div <= clk->clksel_mask; div++) {
 122                 u32 new_rate = clk->parent->rate / (div + 1);
 123                 if (new_rate <= rate) {
 124                         u32 v = cru_readl(clk->clksel_con);
 125                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 126                         v |= div << clk->clksel_shift;
 127                         cru_writel(v, clk->clksel_con);
 128                         clk->rate = new_rate;
 129                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 130                         return 0;
 131                 }
 132         }
 133
 134         return -ENOENT;
 135 }
 136
 137 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 138 {
 139         u32 shift;
 140
 141         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 142                 u32 new_rate = clk->parent->rate >> shift;
 143                 if (new_rate <= rate) {
 144                         u32 v = cru_readl(clk->clksel_con);
 145                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 146                         v |= shift << clk->clksel_shift;
 147                         cru_writel(v, clk->clksel_con);
 148                         clk->rate = new_rate;
 149                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 150                         return 0;
 151                 }
 152         }
 153
 154         return -ENOENT;
 155 }
 156
 157 static struct clk* clksel_get_parent(struct clk *clk)
 158 {
 159         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 160 }
 161
 162 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 163 {
 164         struct clk **p = clk->parents;
 165         u32 i;
 166
 167         if (unlikely(!p))
 168                 return -EINVAL;
 169         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 170                 u32 v;
 171                 if (*p != parent)
 172                         continue;
 173                 v = cru_readl(clk->clksel_con);
 174                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 175                 v |= (i << clk->clksel_parent_shift);
 176                 cru_writel(v, clk->clksel_con);
 177                 return 0;
 178         }
 179         return -EINVAL;
 180 }
 181
 182 /* Work around CRU_CLKGATE3_CON bit21~20 bug */
 183 volatile u32 cru_clkgate3_con_mirror;
 184
 185 static int gate_mode(struct clk *clk, int on)
 186 {
 187         u32 reg;
 188         int idx = clk->gate_idx;
 189         u32 v;
 190
 191         if (idx >= CLK_GATE_MAX)
 192                 return -EINVAL;
 193
 194         reg = CRU_CLKGATE0_CON;
 195         reg += (idx >> 5) << 2;
 196         idx &= 0x1F;
 197
 198         if (reg == CRU_CLKGATE3_CON)
 199                 v = cru_clkgate3_con_mirror;
 200         else
 201                 v = cru_readl(reg);
 202
 203         if (on)
 204                 v &= ~(1 << idx);       // clear bit
 205         else
 206                 v |= (1 << idx);        // set bit
 207
 208         if (reg == CRU_CLKGATE3_CON)
 209                 cru_clkgate3_con_mirror = v;
 210         cru_writel(v, reg);
 211
 212         return 0;
 213 }
 214
 215 /* Work around CRU_SOFTRST0_CON bit29~27 bug */
 216 static volatile u32 cru_softrst0_con_mirror;
 217
 218 void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 219 {
 220         unsigned long flags;
 221         u32 reg = CRU_SOFTRST0_CON + ((idx >> 5) << 2);
 222         u32 mask = 1 << (idx & 31);
 223         u32 v;
 224
 225         if (idx >= SOFT_RST_MAX)
 226                 return;
 227
 228         local_irq_save(flags);
 229
 230         if (reg == CRU_SOFTRST0_CON)
 231                 v = cru_softrst0_con_mirror;
 232         else
 233                 v = cru_readl(reg);
 234
 235         if (on)
 236                 v |= mask;
 237         else
 238                 v &= ~mask;
 239
 240         if (reg == CRU_SOFTRST0_CON)
 241                 cru_softrst0_con_mirror = v;
 242         cru_writel(v, reg);
 243
 244         local_irq_restore(flags);
 245 }
 246
 247 static struct clk xin24m = {
 248         .name           = "xin24m",
 249         .rate           = 24 * MHZ,
 250         .flags          = RATE_FIXED,
 251 };
 252
 253 static struct clk clk_12m = {
 254         .name           = "clk_12m",
 255         .rate           = 12 * MHZ,
 256         .parent         = &xin24m,
 257         .flags          = RATE_FIXED,
 258 };
 259
 260 static struct clk xin27m = {
 261         .name           = "xin27m",
 262         .rate           = 27 * MHZ,
 263         .flags          = RATE_FIXED,
 264 };
 265
 266 static struct clk otgphy0_clkin = {
 267         .name           = "otgphy0_clkin",
 268         .rate           = 480 * MHZ,
 269         .flags          = RATE_FIXED,
 270 };
 271
 272 static struct clk otgphy1_clkin = {
 273         .name           = "otgphy1_clkin",
 274         .rate           = 480 * MHZ,
 275         .flags          = RATE_FIXED,
 276 };
 277
 278
 279 static void delay_500ns(void)
 280 {
 281         int delay = 2000;
 282         while (delay--)
 283                 barrier();
 284 }
 285
 286 static void delay_300us(void)
 287 {
 288         int i;
 289         for (i = 0; i < 600; i++)
 290                 delay_500ns();
 291 }
 292
 293 #define GENERAL_PLL_IDX     0
 294 #define CODEC_PLL_IDX      1
 295 #define ARM_PLL_IDX        2
 296 #define DDR_PLL_IDX        3
 297
 298 #define GRF_SOC_CON0       0xbc
 299 static void pll_wait_lock(int pll_idx)
 300 {
 301         u32 bit = 0x2000000u << pll_idx;
 302         int delay = 2400000;
 303         while (delay > 0) {
 304                 if (regfile_readl(GRF_SOC_CON0) & bit)
 305                         break;
 306                 delay--;
 307         }
 308         if (delay == 0) {
 309                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 310         }
 311 }
 312
 313 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 314 {
 315         unsigned long rate;
 316
 317         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 318                 u32 v = cru_readl(CRU_APLL_CON);
 319                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 320                 do_div(rate64, PLL_NR(v));
 321                 rate = rate64 >> PLL_NO_SHIFT(v);
 322                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 323         } else {
 324                 rate = clk->parent->rate;
 325                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 326         }
 327
 328         return rate;
 329 }
 330
 331 struct arm_pll_set {
 332         unsigned long rate;
 333         u32 apll_con;
 334         u32 clksel0_con;
 335 };
 336
 337 #define CORE_ACLK_11    (0 << 5)
 338 #define CORE_ACLK_21    (1 << 5)
 339 #define CORE_ACLK_31    (2 << 5)
 340 #define CORE_ACLK_41    (3 << 5)
 341 #define CORE_ACLK_81    (4 << 5)
 342 #define CORE_ACLK_MASK  (7 << 5)
 343
 344 #define ACLK_HCLK_11    (0 << 8)
 345 #define ACLK_HCLK_21    (1 << 8)
 346 #define ACLK_HCLK_41    (2 << 8)
 347 #define ACLK_HCLK_MASK  (3 << 8)
 348
 349 #define ACLK_PCLK_11    (0 << 10)
 350 #define ACLK_PCLK_21    (1 << 10)
 351 #define ACLK_PCLK_41    (2 << 10)
 352 #define ACLK_PCLK_81    (3 << 10)
 353 #define ACLK_PCLK_MASK  (3 << 10)
 354
 355 #define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 356 { \
 357         .rate           = _mhz * MHZ, \
 358         .apll_con       = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 359         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 360 }
 361
 362 static const struct arm_pll_set arm_pll[] = {
 363         // rate = 24 * NF / (NR * NO)
 364         //      rate NR  NF NO adiv hdiv pdiv
 365         ARM_PLL(1200, 1, 50, 1, 41, 21, 81),
 366         ARM_PLL(1104, 1, 46, 1, 41, 21, 81),
 367         ARM_PLL(1008, 1, 42, 1, 41, 21, 81),
 368         ARM_PLL( 912, 1, 38, 1, 31, 21, 81),
 369         ARM_PLL( 888, 2, 74, 1, 31, 21, 81),
 370         ARM_PLL( 816, 1, 34, 1, 31, 21, 81),
 371         ARM_PLL( 696, 1, 58, 2, 31, 21, 81),
 372         ARM_PLL( 624, 1, 52, 2, 31, 21, 81),
 373         ARM_PLL( 600, 1, 50, 2, 21, 21, 81),
 374         ARM_PLL( 504, 1, 42, 2, 21, 21, 81),
 375         ARM_PLL( 408, 1, 34, 2, 21, 21, 81),
 376         ARM_PLL( 300, 1, 50, 4, 21, 21, 41),
 377         ARM_PLL( 204, 1, 34, 4, 21, 21, 41),
 378         ARM_PLL( 102, 1, 34, 8, 21, 21, 41),
 379         // last item, pll power down.
 380         ARM_PLL(  24, 1, 64, 8, 21, 21, 41),
 381 };
 382
 383 #define CORE_PARENT_MASK        (3 << 23)
 384 #define CORE_PARENT_ARM_PLL     (0 << 23)
 385 #define CORE_PARENT_GENERAL_PLL (1 << 23)
 386
 387 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 388 {
 389         const struct arm_pll_set *ps, *pt;
 390
 391         /* find the arm_pll we want. */
 392         ps = pt = &arm_pll[0];
 393         while (1) {
 394                 if (pt->rate == rate) {
 395                         ps = pt;
 396                         break;
 397                 }
 398                 // we are sorted, and ps->rate > pt->rate.
 399                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 400                         ps = pt;
 401                 if (pt->rate < rate || pt->rate == 24 * MHZ)
 402                         break;
 403                 pt++;
 404         }
 405
 406         /* make aclk safe & reparent to general pll */
 407         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_GENERAL_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 408
 409         /* enter slow mode */
 410         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 411
 412         /* power down */
 413         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 414
 415         delay_500ns();
 416
 417         cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
 418
 419         delay_500ns();
 420
 421         /* power up */
 422         cru_writel(ps->apll_con, CRU_APLL_CON);
 423
 424         delay_300us();
 425         pll_wait_lock(ARM_PLL_IDX);
 426
 427         /* reparent to arm pll & set aclk/hclk/pclk */
 428         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | ps->clksel0_con, CRU_CLKSEL0_CON);
 429
 430         /* enter normal mode */
 431         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 432
 433         return 0;
 434 }
 435
 436 static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
 437
 438 static struct clk arm_pll_clk = {
 439         .name           = "arm_pll",
 440         .parent         = &xin24m,
 441         .recalc         = arm_pll_clk_recalc,
 442         .set_rate       = arm_pll_clk_set_rate,
 443         .clksel_con     = CRU_MODE_CON,
 444         .clksel_parent_mask     = 1,
 445         .clksel_parent_shift    = 8,
 446         .parents        = arm_pll_parents,
 447 };
 448
 449 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 450 {
 451         unsigned long rate;
 452
 453         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 454                 u32 v = cru_readl(CRU_DPLL_CON);
 455                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 456                 do_div(rate64, PLL_NR(v));
 457                 rate = rate64 >> PLL_NO_SHIFT(v);
 458                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 459         } else {
 460                 rate = clk->parent->rate;
 461                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 462         }
 463
 464         return rate;
 465 }
 466
 467 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 468 {
 469         /* do nothing here */
 470         return 0;
 471 }
 472
 473 static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &general_pll_clk };
 474
 475 static struct clk ddr_pll_clk = {
 476         .name           = "ddr_pll",
 477         .parent         = &xin24m,
 478         .recalc         = ddr_pll_clk_recalc,
 479         .set_rate       = ddr_pll_clk_set_rate,
 480         .clksel_con     = CRU_MODE_CON,
 481         .clksel_parent_mask     = 3,
 482         .clksel_parent_shift    = 13,
 483         .parents        = ddr_pll_parents,
 484 };
 485
 486
 487 static int codec_pll_clk_mode(struct clk *clk, int on)
 488 {
 489         u32 cpll = cru_readl(CRU_CPLL_CON);
 490         if (on) {
 491                 cru_writel(cpll & ~(PLL_PD | PLL_BYPASS), CRU_CPLL_CON);
 492                 delay_300us();
 493                 pll_wait_lock(CODEC_PLL_IDX);
 494                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
 495         } else {
 496                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 497                 cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 498                 cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 499                 delay_500ns();
 500         }
 501         return 0;
 502 }
 503
 504 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 505 {
 506         unsigned long rate;
 507         u32 v = cru_readl(CRU_CPLL_CON);
 508         u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 509         do_div(rate64, PLL_NR(v));
 510         rate = rate64 >> PLL_NO_SHIFT(v);
 511         pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 512         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) != CRU_CODEC_MODE_NORMAL)
 513                 pr_debug("%s rate is %ld (slow mode) actually\n", clk->name, clk->parent->rate);
 514         return rate;
 515 }
 516
 517 #define CODEC_PLL_PARENT_MASK   (3 << 11)
 518 #define CODEC_PLL_PARENT_XIN24M (0 << 11)
 519 #define CODEC_PLL_PARENT_XIN27M (1 << 11)
 520 #define CODEC_PLL_PARENT_DDR_PLL        (2 << 11)
 521 #define CODEC_PLL_PARENT_GENERAL_PLL    (3 << 11)
 522
 523 struct codec_pll_set {
 524         unsigned long rate;
 525         u32 pll_con;
 526         u32 parent_con;
 527 };
 528
 529 #define CODEC_PLL(_mhz, _parent, band, nr, nf, no) \
 530 { \
 531         .rate           = _mhz * MHZ, \
 532         .pll_con        = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
 533         .parent_con     = CODEC_PLL_PARENT_XIN##_parent##M, \
 534 }
 535
 536 static const struct codec_pll_set codec_pll[] = {
 537         //      rate parent band NR NF NO
 538         CODEC_PLL(108, 24,  LOW, 1, 18, 4),     // for TV
 539         CODEC_PLL(648, 24, HIGH, 1, 27, 1),
 540         CODEC_PLL(297, 27,  LOW, 1, 22, 2),     // for HDMI
 541         CODEC_PLL(594, 27,  LOW, 1, 22, 1),
 542         CODEC_PLL(360, 24,  LOW, 1, 15, 1),     // for GPU
 543         CODEC_PLL(408, 24,  LOW, 1, 17, 1),
 544         CODEC_PLL(456, 24,  LOW, 1, 19, 1),
 545         CODEC_PLL(504, 24,  LOW, 1, 21, 1),
 546         CODEC_PLL(552, 24,  LOW, 1, 23, 1),
 547         CODEC_PLL(600, 24, HIGH, 1, 25, 1),
 548 };
 549
 550 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 551 {
 552         int i;
 553         u32 work_mode;
 554
 555         const struct codec_pll_set *ps = NULL;
 556
 557         for (i = 0; i < ARRAY_SIZE(codec_pll); i++) {
 558                 if (codec_pll[i].rate == rate) {
 559                         ps = &codec_pll[i];
 560                         break;
 561                 }
 562         }
 563         if (!ps)
 564                 return  -ENOENT;
 565
 566         work_mode = cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK;
 567
 568         /* enter slow mode */
 569         cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | ps->parent_con, CRU_MODE_CON);
 570
 571         /* power down */
 572         cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
 573
 574         delay_500ns();
 575
 576         cru_writel(ps->pll_con | PLL_PD, CRU_CPLL_CON);
 577
 578         delay_500ns();
 579
 580         /* power up */
 581         cru_writel(ps->pll_con, CRU_CPLL_CON);
 582
 583         delay_300us();
 584         pll_wait_lock(CODEC_PLL_IDX);
 585
 586         /* enter normal mode */
 587         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | work_mode, CRU_MODE_CON);
 588
 589         clk_set_parent_nolock(clk, ps->parent_con == CODEC_PLL_PARENT_XIN24M ? &xin24m : &xin27m);
 590
 591         return 0;
 592 }
 593
 594 static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &general_pll_clk };
 595
 596 static struct clk codec_pll_clk = {
 597         .name           = "codec_pll",
 598         .parent         = &xin24m,
 599         .mode           = codec_pll_clk_mode,
 600         .recalc         = codec_pll_clk_recalc,
 601         .set_rate       = codec_pll_clk_set_rate,
 602         .clksel_con     = CRU_MODE_CON,
 603         .clksel_parent_mask     = 3,
 604         .clksel_parent_shift    = 11,
 605         .parents        = codec_pll_parents,
 606 };
 607
 608
 609 static unsigned long general_pll_clk_recalc(struct clk *clk)
 610 {
 611         unsigned long rate;
 612
 613         if ((cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) == CRU_GENERAL_MODE_NORMAL) {
 614                 u32 v = cru_readl(CRU_GPLL_CON);
 615                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 616                 do_div(rate64, PLL_NR(v));
 617                 rate = rate64 >> PLL_NO_SHIFT(v);
 618                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 619         } else {
 620                 rate = clk->parent->rate;
 621                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 622         }
 623
 624         return rate;
 625 }
 626
 627 static int general_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 628 {
 629         u32 pll_con;
 630
 631         switch (rate) {
 632         case 96 * MHZ:
 633                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 634                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(16) | PLL_NO_4;
 635         break;
 636         case 144*MHZ:
 637                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 638                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_4;
 639         break;
 640         case 288 * MHZ:
 641                 /* 288M: low-band, NR=1, NF=24, NO=2 */
 642                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_2;
 643                 break;
 644         case 300 * MHZ:
 645                 /* 300M: low-band, NR=1, NF=25, NO=2 */
 646                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(25) | PLL_NO_2;
 647         break;
 648         case 624 * MHZ:
 649                 /* 624M: high-band, NR=1, NF=26, NO=1 */
 650                 pll_con = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 651                 break;
 652         default:
 653                 return -ENOENT;
 654                 break;
 655         }
 656
 657         /* enter slow mode */
 658         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 659
 660         /* power down */
 661         cru_writel(cru_readl(CRU_GPLL_CON) | PLL_PD, CRU_GPLL_CON);
 662
 663         delay_500ns();
 664
 665         cru_writel(pll_con | PLL_PD, CRU_GPLL_CON);
 666
 667         delay_500ns();
 668
 669         /* power up */
 670         cru_writel(pll_con, CRU_GPLL_CON);
 671
 672         delay_300us();
 673         pll_wait_lock(GENERAL_PLL_IDX);
 674
 675         /* enter normal mode */
 676         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_NORMAL, CRU_MODE_CON);
 677
 678         return 0;
 679 }
 680
 681 static struct clk *general_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
 682
 683 static struct clk general_pll_clk = {
 684         .name           = "general_pll",
 685         .parent         = &xin24m,
 686         .recalc         = general_pll_clk_recalc,
 687         .set_rate       = general_pll_clk_set_rate,
 688         .clksel_con     = CRU_MODE_CON,
 689         .clksel_parent_mask     = 3,
 690         .clksel_parent_shift    = 9,
 691         .parents        = general_pll_parents,
 692 };
 693
 694
 695 static struct clk *clk_core_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 696
 697 static struct clk clk_core = {
 698         .name           = "core",
 699         .parent         = &arm_pll_clk,
 700         .recalc         = clksel_recalc_div,
 701         .clksel_con     = CRU_CLKSEL0_CON,
 702         .clksel_mask    = 0x1F,
 703         .clksel_shift   = 0,
 704         .clksel_parent_mask     = 3,
 705         .clksel_parent_shift    = 23,
 706         .parents        = clk_core_parents,
 707 };
 708
 709 static unsigned long aclk_cpu_recalc(struct clk *clk)
 710 {
 711         unsigned long rate;
 712         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 713
 714         BUG_ON(div > 5);
 715         if (div >= 5)
 716                 div = 8;
 717         rate = clk->parent->rate / div;
 718         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 719
 720         return rate;
 721 }
 722
 723 static struct clk aclk_cpu = {
 724         .name           = "aclk_cpu",
 725         .parent         = &clk_core,
 726         .recalc         = aclk_cpu_recalc,
 727 };
 728
 729 static struct clk hclk_cpu = {
 730         .name           = "hclk_cpu",
 731         .parent         = &aclk_cpu,
 732         .recalc         = clksel_recalc_shift,
 733         .set_rate       = clksel_set_rate_shift,
 734         .clksel_con     = CRU_CLKSEL0_CON,
 735         .clksel_mask    = 3,
 736         .clksel_shift   = 8,
 737         .clksel_maxdiv  = 4,
 738 };
 739
 740 static struct clk pclk_cpu = {
 741         .name           = "pclk_cpu",
 742         .parent         = &aclk_cpu,
 743         .recalc         = clksel_recalc_shift,
 744         .set_rate       = clksel_set_rate_shift,
 745         .clksel_con     = CRU_CLKSEL0_CON,
 746         .clksel_mask    = 3,
 747         .clksel_shift   = 10,
 748         .clksel_maxdiv  = 8,
 749 };
 750
 751 static struct clk *aclk_periph_parents[4] = { &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
 752
 753 static struct clk aclk_periph = {
 754         .name           = "aclk_periph",
 755         .mode           = gate_mode,
 756         .gate_idx       = CLK_GATE_ACLK_PEIRPH,
 757         .recalc         = clksel_recalc_div,
 758         .set_rate       = clksel_set_rate_div,
 759         .clksel_con     = CRU_CLKSEL0_CON,
 760         .clksel_mask    = 0x1F,
 761         .clksel_shift   = 14,
 762         .clksel_parent_mask     = 3,
 763         .clksel_parent_shift    = 12,
 764         .parents        = aclk_periph_parents,
 765 };
 766
 767 static struct clk pclk_periph = {
 768         .name           = "pclk_periph",
 769         .mode           = gate_mode,
 770         .gate_idx       = CLK_GATE_PCLK_PEIRPH,
 771         .parent         = &aclk_periph,
 772         .recalc         = clksel_recalc_shift,
 773         .set_rate       = clksel_set_rate_shift,
 774         .clksel_con     = CRU_CLKSEL0_CON,
 775         .clksel_mask    = 3,
 776         .clksel_shift   = 19,
 777         .clksel_maxdiv  = 8,
 778 };
 779
 780 static struct clk hclk_periph = {
 781         .name           = "hclk_periph",
 782         .mode           = gate_mode,
 783         .gate_idx       = CLK_GATE_HCLK_PEIRPH,
 784         .parent         = &aclk_periph,
 785         .recalc         = clksel_recalc_shift,
 786         .set_rate       = clksel_set_rate_shift,
 787         .clksel_con     = CRU_CLKSEL0_CON,
 788         .clksel_mask    = 3,
 789         .clksel_shift   = 21,
 790         .clksel_maxdiv  = 4,
 791 };
 792
 793
 794 static unsigned long uhost_recalc(struct clk *clk)
 795 {
 796         unsigned long rate = clksel_recalc_div(clk);
 797         if (rate != 48 * MHZ) {
 798                 clksel_set_rate_div(clk, 48 * MHZ);
 799                 rate = clksel_recalc_div(clk);
 800         }
 801         return rate;
 802 }
 803
 804 static struct clk *clk_uhost_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 805
 806 static struct clk clk_uhost = {
 807         .name           = "uhost",
 808         .mode           = gate_mode,
 809         .recalc         = uhost_recalc,
 810         .set_rate       = clksel_set_rate_div,
 811         .gate_idx       = CLK_GATE_UHOST,
 812         .clksel_con     = CRU_CLKSEL1_CON,
 813         .clksel_mask    = 0x1F,
 814         .clksel_shift   = 16,
 815         .clksel_parent_mask     = 7,
 816         .clksel_parent_shift    = 13,
 817         .parents        = clk_uhost_parents,
 818 };
 819
 820 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 821
 822 static struct clk clk_otgphy0 = {
 823         .name           = "otgphy0",
 824         .mode           = gate_mode,
 825         .gate_idx       = CLK_GATE_USBPHY0,
 826         .clksel_con     = CRU_CLKSEL1_CON,
 827         .clksel_parent_mask     = 3,
 828         .clksel_parent_shift    = 9,
 829         .parents        = clk_otgphy_parents,
 830 };
 831
 832 static struct clk clk_otgphy1 = {
 833         .name           = "otgphy1",
 834         .mode           = gate_mode,
 835         .gate_idx       = CLK_GATE_USBPHY1,
 836         .clksel_con     = CRU_CLKSEL1_CON,
 837         .clksel_parent_mask     = 3,
 838         .clksel_parent_shift    = 11,
 839         .parents        = clk_otgphy_parents,
 840 };
 841
 842
 843 static struct clk rmii_clkin = {
 844         .name           = "rmii_clkin",
 845 };
 846
 847 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 848
 849 static struct clk clk_mac_ref_div = {
 850         .name           = "mac_ref_div",
 851         .recalc         = clksel_recalc_div,
 852         .set_rate       = clksel_set_rate_div,
 853         .clksel_con     = CRU_CLKSEL1_CON,
 854         .clksel_mask    = 0x1F,
 855         .clksel_shift   = 23,
 856         .clksel_parent_mask     = 3,
 857         .clksel_parent_shift    = 21,
 858         .parents        = clk_mac_ref_div_parents,
 859 };
 860
 861 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 862
 863 static struct clk clk_mac_ref = {
 864         .name           = "mac_ref",
 865         .mode           = gate_mode,
 866         .gate_idx       = CLK_GATE_MAC_REF,
 867         .clksel_con     = CRU_CLKSEL1_CON,
 868         .clksel_parent_mask     = 1,
 869         .clksel_parent_shift    = 28,
 870         .parents        = clk_mac_ref_parents,
 871 };
 872
 873
 874 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 875
 876 static struct clk clk_i2s0_div = {
 877         .name           = "i2s0_div",
 878         .recalc         = clksel_recalc_div,
 879         .set_rate       = clksel_set_rate_div,
 880         .clksel_con     = CRU_CLKSEL2_CON,
 881         .clksel_mask    = 0x1F,
 882         .clksel_shift   = 3,
 883         .clksel_parent_mask     = 7,
 884         .clksel_parent_shift    = 0,
 885         .parents        = clk_i2s_div_parents,
 886 };
 887
 888 static struct clk clk_i2s1_div = {
 889         .name           = "i2s1_div",
 890         .recalc         = clksel_recalc_div,
 891         .set_rate       = clksel_set_rate_div,
 892         .clksel_con     = CRU_CLKSEL2_CON,
 893         .clksel_mask    = 0x1F,
 894         .clksel_shift   = 13,
 895         .clksel_parent_mask     = 7,
 896         .clksel_parent_shift    = 10,
 897         .parents        = clk_i2s_div_parents,
 898 };
 899
 900 static struct clk clk_spdif_div = {
 901         .name           = "spdif_div",
 902         .recalc         = clksel_recalc_div,
 903         .set_rate       = clksel_set_rate_div,
 904         .clksel_con     = CRU_CLKSEL2_CON,
 905         .clksel_mask    = 0x1F,
 906         .clksel_shift   = 23,
 907         .clksel_parent_mask     = 7,
 908         .clksel_parent_shift    = 20,
 909         .parents        = clk_i2s_div_parents,
 910 };
 911
 912 static u32 clk_gcd(u32 numerator, u32 denominator)
 913 {
 914         u32 a, b;
 915
 916         if (!numerator || !denominator)
 917                 return 0;
 918         if (numerator > denominator) {
 919                 a = numerator;
 920                 b = denominator;
 921         } else {
 922                 a = denominator;
 923                 b = numerator;
 924         }
 925         while (b != 0) {
 926                 int r = b;
 927                 b = a % b;
 928                 a = r;
 929         }
 930
 931         return a;
 932 }
 933
 934 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 935 {
 936         u32 numerator, denominator;
 937         u32 gcd;
 938
 939         gcd = clk_gcd(rate, clk->parent->rate);
 940         pr_debug("i2s rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
 941         if (!gcd) {
 942                 pr_err("gcd=0, i2s frac div is not be supported\n");
 943                 return -ENOENT;
 944         }
 945
 946         numerator = rate / gcd;
 947         denominator = clk->parent->rate / gcd;
 948         pr_debug("i2s numerator=%d,denominator=%d,times=%d\n",
 949                 numerator, denominator, denominator / numerator);
 950         if (numerator > 0xffff || denominator > 0xffff) {
 951                 pr_err("i2s can't get a available nume and deno\n");
 952                 return -ENOENT;
 953         }
 954
 955         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 956         cru_writel(numerator << 16 | denominator, clk->clksel_con);
 957
 958         return 0;
 959 }
 960
 961 static struct clk clk_i2s0_frac_div = {
 962         .name           = "i2s0_frac_div",
 963         .parent         = &clk_i2s0_div,
 964         .recalc         = clksel_recalc_frac,
 965         .set_rate       = clk_i2s_frac_div_set_rate,
 966         .clksel_con     = CRU_CLKSEL3_CON,
 967 };
 968
 969 static struct clk clk_i2s1_frac_div = {
 970         .name           = "i2s1_frac_div",
 971         .parent         = &clk_i2s1_div,
 972         .recalc         = clksel_recalc_frac,
 973         .set_rate       = clk_i2s_frac_div_set_rate,
 974         .clksel_con     = CRU_CLKSEL4_CON,
 975 };
 976
 977 static struct clk clk_spdif_frac_div = {
 978         .name           = "spdif_frac_div",
 979         .parent         = &clk_spdif_div,
 980         .recalc         = clksel_recalc_frac,
 981         .set_rate       = clk_i2s_frac_div_set_rate,
 982         .clksel_con     = CRU_CLKSEL5_CON,
 983 };
 984
 985 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 986 {
 987         int ret;
 988         struct clk *parent;
 989
 990         if (rate == 12 * MHZ) {
 991                 parent = &clk_12m;
 992         } else {
 993                 parent = clk->parents[1]; /* frac div */
 994                 ret = clk_set_rate_nolock(parent, rate);
 995                 if (ret)
 996                         return ret;
 997         }
 998         if (clk->parent != parent)
 999                 clk_set_parent_nolock(clk, parent);
1000
1001         return ret;
1002 }
1003
1004 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
1005
1006 static struct clk clk_i2s0 = {
1007         .name           = "i2s0",
1008         .mode           = gate_mode,
1009         .gate_idx       = CLK_GATE_I2S0,
1010         .set_rate       = i2s_set_rate,
1011         .clksel_con     = CRU_CLKSEL2_CON,
1012         .clksel_parent_mask     = 3,
1013         .clksel_parent_shift    = 8,
1014         .parents        = clk_i2s0_parents,
1015 };
1016
1017 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
1018
1019 static struct clk clk_i2s1 = {
1020         .name           = "i2s1",
1021         .mode           = gate_mode,
1022         .gate_idx       = CLK_GATE_I2S1,
1023         .set_rate       = i2s_set_rate,
1024         .clksel_con     = CRU_CLKSEL2_CON,
1025         .clksel_parent_mask     = 3,
1026         .clksel_parent_shift    = 18,
1027         .parents        = clk_i2s1_parents,
1028 };
1029
1030 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
1031
1032 static struct clk clk_spdif = {
1033         .name           = "spdif",
1034         .mode           = gate_mode,
1035         .gate_idx       = CLK_GATE_SPDIF,
1036         .set_rate       = i2s_set_rate,
1037         .clksel_con     = CRU_CLKSEL2_CON,
1038         .clksel_parent_mask     = 3,
1039         .clksel_parent_shift    = 28,
1040         .parents        = clk_spdif_parents,
1041 };
1042
1043
1044 static struct clk *clk_spi_src_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1045
1046 static struct clk clk_spi_src = {
1047         .name           = "spi_src",
1048         .clksel_con     = CRU_CLKSEL6_CON,
1049         .clksel_parent_mask     = 3,
1050         .clksel_parent_shift    = 0,
1051         .parents        = clk_spi_src_parents,
1052 };
1053
1054 static struct clk clk_spi0 = {
1055         .name           = "spi0",
1056         .parent         = &clk_spi_src,
1057         .mode           = gate_mode,
1058         .recalc         = clksel_recalc_div,
1059         .set_rate       = clksel_set_rate_div,
1060         .gate_idx       = CLK_GATE_SPI0,
1061         .clksel_con     = CRU_CLKSEL6_CON,
1062         .clksel_mask    = 0x7F,
1063         .clksel_shift   = 2,
1064 };
1065
1066 static struct clk clk_spi1 = {
1067         .name           = "spi1",
1068         .parent         = &clk_spi_src,
1069         .mode           = gate_mode,
1070         .recalc         = clksel_recalc_div,
1071         .set_rate       = clksel_set_rate_div,
1072         .gate_idx       = CLK_GATE_SPI1,
1073         .clksel_con     = CRU_CLKSEL6_CON,
1074         .clksel_mask    = 0x7F,
1075         .clksel_shift   = 11,
1076 };
1077
1078
1079 static struct clk clk_saradc = {
1080         .name           = "saradc",
1081         .parent         = &pclk_periph,
1082         .mode           = gate_mode,
1083         .recalc         = clksel_recalc_div,
1084         .set_rate       = clksel_set_rate_div,
1085         .gate_idx       = CLK_GATE_SARADC,
1086         .clksel_con     = CRU_CLKSEL6_CON,
1087         .clksel_mask    = 0xFF,
1088         .clksel_shift   = 18,
1089 };
1090
1091
1092 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
1093
1094 static struct clk clk_timer0 = {
1095         .name           = "timer0",
1096         .mode           = gate_mode,
1097         .gate_idx       = CLK_GATE_TIMER0,
1098         .clksel_con     = CRU_CLKSEL6_CON,
1099         .clksel_parent_mask     = 1,
1100         .clksel_parent_shift    = 26,
1101         .parents        = clk_cpu_timer_parents,
1102 };
1103
1104 static struct clk clk_timer1 = {
1105         .name           = "timer1",
1106         .mode           = gate_mode,
1107         .gate_idx       = CLK_GATE_TIMER1,
1108         .clksel_con     = CRU_CLKSEL6_CON,
1109         .clksel_parent_mask     = 1,
1110         .clksel_parent_shift    = 27,
1111         .parents        = clk_cpu_timer_parents,
1112 };
1113
1114 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
1115
1116 static struct clk clk_timer2 = {
1117         .name           = "timer2",
1118         .mode           = gate_mode,
1119         .gate_idx       = CLK_GATE_TIMER2,
1120         .clksel_con     = CRU_CLKSEL6_CON,
1121         .clksel_parent_mask     = 1,
1122         .clksel_parent_shift    = 28,
1123         .parents        = clk_periph_timer_parents,
1124 };
1125
1126 static struct clk clk_timer3 = {
1127         .name           = "timer3",
1128         .mode           = gate_mode,
1129         .gate_idx       = CLK_GATE_TIMER3,
1130         .clksel_con     = CRU_CLKSEL6_CON,
1131         .clksel_parent_mask     = 1,
1132         .clksel_parent_shift    = 29,
1133         .parents        = clk_periph_timer_parents,
1134 };
1135
1136
1137 static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1138
1139 static struct clk clk_mmc_src = {
1140         .name           = "mmc_src",
1141         .clksel_con     = CRU_CLKSEL7_CON,
1142         .clksel_parent_mask     = 3,
1143         .clksel_parent_shift    = 0,
1144         .parents        = clk_mmc_src_parents,
1145 };
1146
1147 static struct clk clk_mmc0 = {
1148         .name           = "mmc0",
1149         .parent         = &clk_mmc_src,
1150         .mode           = gate_mode,
1151         .recalc         = clksel_recalc_div,
1152         .set_rate       = clksel_set_rate_div,
1153         .gate_idx       = CLK_GATE_MMC0,
1154         .clksel_con     = CRU_CLKSEL7_CON,
1155         .clksel_mask    = 0x3F,
1156         .clksel_shift   = 2,
1157 };
1158
1159 static struct clk clk_mmc1 = {
1160         .name           = "mmc1",
1161         .parent         = &clk_mmc_src,
1162         .mode           = gate_mode,
1163         .recalc         = clksel_recalc_div,
1164         .set_rate       = clksel_set_rate_div,
1165         .gate_idx       = CLK_GATE_MMC1,
1166         .clksel_con     = CRU_CLKSEL7_CON,
1167         .clksel_mask    = 0x3F,
1168         .clksel_shift   = 10,
1169 };
1170
1171 static struct clk clk_emmc = {
1172         .name           = "emmc",
1173         .parent         = &clk_mmc_src,
1174         .mode           = gate_mode,
1175         .recalc         = clksel_recalc_div,
1176         .set_rate       = clksel_set_rate_div,
1177         .gate_idx       = CLK_GATE_EMMC,
1178         .clksel_con     = CRU_CLKSEL7_CON,
1179         .clksel_mask    = 0x3F,
1180         .clksel_shift   = 18,
1181 };
1182
1183
1184 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &general_pll_clk, &codec_pll_clk, &arm_pll_clk };
1185
1186 static struct clk clk_ddr = {
1187         .name           = "ddr",
1188         .recalc         = clksel_recalc_shift,
1189         .clksel_con     = CRU_CLKSEL7_CON,
1190         .clksel_mask    = 7,
1191         .clksel_shift   = 26,
1192         .clksel_maxdiv  = 32,
1193         .clksel_parent_mask     = 3,
1194         .clksel_parent_shift    = 24,
1195         .parents        = clk_ddr_parents,
1196 };
1197
1198
1199 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1200 {
1201         int ret;
1202         struct clk *parent;
1203         struct clk *clk_div = clk->parents[0];
1204
1205         switch (rate) {
1206         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
1207                 parent = clk->parents[2]; /* xin24m */
1208                 break;
1209         case 19200*16:
1210         case 38400*16:
1211         case 57600*16:
1212         case 115200*16:
1213         case 230400*16:
1214         case 460800*16:
1215         case 576000*16:
1216                 parent = clk->parents[1]; /* frac div */
1217                 /* reset div to 1 */
1218                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1219                 if (ret)
1220                         return ret;
1221                 break;
1222         default:
1223                 parent = clk_div;
1224                 break;
1225         }
1226
1227         if (parent->set_rate) {
1228                 ret = clk_set_rate_nolock(parent, rate);
1229                 if (ret)
1230                         return ret;
1231         }
1232
1233         if (clk->parent != parent)
1234                 clk_set_parent_nolock(clk, parent);
1235
1236         return 0;
1237 }
1238
1239 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1240 {
1241         u32 numerator, denominator;
1242         u32 gcd;
1243
1244         gcd = clk_gcd(rate, clk->parent->rate);
1245         pr_debug("uart rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
1246         if (!gcd) {
1247                 pr_err("gcd=0, uart frac div is not be supported\n");
1248                 return -ENOENT;
1249         }
1250
1251         numerator = rate / gcd;
1252         denominator = clk->parent->rate / gcd;
1253         pr_debug("uart numerator=%d,denominator=%d,times=%d\n",
1254                 numerator, denominator, denominator / numerator);
1255         if (numerator > 0xffff || denominator > 0xffff) {
1256                 pr_err("uart_frac can't get a available nume and deno\n");
1257                 return -ENOENT;
1258         }
1259
1260         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1261         cru_writel(numerator << 16 | denominator, clk->clksel_con);
1262
1263         return 0;
1264 }
1265
1266 static struct clk *clk_uart_src_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1267
1268 static struct clk clk_uart01_src = {
1269         .name           = "uart01_src",
1270         .clksel_con     = CRU_CLKSEL8_CON,
1271         .clksel_parent_mask     = 7,
1272         .clksel_parent_shift    = 0,
1273         .parents        = clk_uart_src_parents,
1274 };
1275
1276 static struct clk clk_uart0_div = {
1277         .name           = "uart0_div",
1278         .parent         = &clk_uart01_src,
1279         .recalc         = clksel_recalc_div,
1280         .set_rate       = clksel_set_rate_div,
1281         .clksel_con     = CRU_CLKSEL8_CON,
1282         .clksel_mask    = 0x3F,
1283         .clksel_shift   = 3,
1284 };
1285
1286 static struct clk clk_uart0_frac_div = {
1287         .name           = "uart0_frac_div",
1288         .parent         = &clk_uart0_div,
1289         .recalc         = clksel_recalc_frac,
1290         .set_rate       = clk_uart_frac_div_set_rate,
1291         .clksel_con     = CRU_CLKSEL10_CON,
1292 };
1293
1294 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1295
1296 static struct clk clk_uart0 = {
1297         .name           = "uart0",
1298         .mode           = gate_mode,
1299         .set_rate       = clk_uart_set_rate,
1300         .gate_idx       = CLK_GATE_UART0,
1301         .clksel_con     = CRU_CLKSEL8_CON,
1302         .clksel_parent_mask     = 3,
1303         .clksel_parent_shift    = 9,
1304         .parents        = clk_uart0_parents,
1305 };
1306
1307 static struct clk clk_uart1_div = {
1308         .name           = "uart1_div",
1309         .parent         = &clk_uart01_src,
1310         .recalc         = clksel_recalc_div,
1311         .set_rate       = clksel_set_rate_div,
1312         .clksel_con     = CRU_CLKSEL8_CON,
1313         .clksel_mask    = 0x3F,
1314         .clksel_shift   = 14,
1315 };
1316
1317 static struct clk clk_uart1_frac_div = {
1318         .name           = "uart1_frac_div",
1319         .parent         = &clk_uart1_div,
1320         .recalc         = clksel_recalc_frac,
1321         .set_rate       = clk_uart_frac_div_set_rate,
1322         .clksel_con     = CRU_CLKSEL11_CON,
1323 };
1324
1325 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1326
1327 static struct clk clk_uart1 = {
1328         .name           = "uart1",
1329         .mode           = gate_mode,
1330         .set_rate       = clk_uart_set_rate,
1331         .gate_idx       = CLK_GATE_UART1,
1332         .clksel_con     = CRU_CLKSEL8_CON,
1333         .clksel_parent_mask     = 3,
1334         .clksel_parent_shift    = 20,
1335         .parents        = clk_uart1_parents,
1336 };
1337
1338 static struct clk clk_uart23_src = {
1339         .name           = "uart23_src",
1340         .clksel_con     = CRU_CLKSEL9_CON,
1341         .clksel_parent_mask     = 7,
1342         .clksel_parent_shift    = 0,
1343         .parents        = clk_uart_src_parents,
1344 };
1345
1346 static struct clk clk_uart2_div = {
1347         .name           = "uart2_div",
1348         .parent         = &clk_uart23_src,
1349         .recalc         = clksel_recalc_div,
1350         .set_rate       = clksel_set_rate_div,
1351         .clksel_con     = CRU_CLKSEL9_CON,
1352         .clksel_mask    = 0x3F,
1353         .clksel_shift   = 3,
1354 };
1355
1356 static struct clk clk_uart2_frac_div = {
1357         .name           = "uart2_frac_div",
1358         .parent         = &clk_uart2_div,
1359         .recalc         = clksel_recalc_frac,
1360         .set_rate       = clk_uart_frac_div_set_rate,
1361         .clksel_con     = CRU_CLKSEL12_CON,
1362 };
1363
1364 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1365
1366 static struct clk clk_uart2 = {
1367         .name           = "uart2",
1368         .mode           = gate_mode,
1369         .set_rate       = clk_uart_set_rate,
1370         .gate_idx       = CLK_GATE_UART2,
1371         .clksel_con     = CRU_CLKSEL9_CON,
1372         .clksel_parent_mask     = 3,
1373         .clksel_parent_shift    = 9,
1374         .parents        = clk_uart2_parents,
1375 };
1376
1377 static struct clk clk_uart3_div = {
1378         .name           = "uart3_div",
1379         .parent         = &clk_uart23_src,
1380         .recalc         = clksel_recalc_div,
1381         .set_rate       = clksel_set_rate_div,
1382         .clksel_con     = CRU_CLKSEL9_CON,
1383         .clksel_mask    = 0x3F,
1384         .clksel_shift   = 14,
1385 };
1386
1387 static struct clk clk_uart3_frac_div = {
1388         .name           = "uart3_frac_div",
1389         .parent         = &clk_uart3_div,
1390         .recalc         = clksel_recalc_frac,
1391         .set_rate       = clk_uart_frac_div_set_rate,
1392         .clksel_con     = CRU_CLKSEL13_CON,
1393 };
1394
1395 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1396
1397 static struct clk clk_uart3 = {
1398         .name           = "uart3",
1399         .mode           = gate_mode,
1400         .set_rate       = clk_uart_set_rate,
1401         .gate_idx       = CLK_GATE_UART3,
1402         .clksel_con     = CRU_CLKSEL9_CON,
1403         .clksel_parent_mask     = 3,
1404         .clksel_parent_shift    = 20,
1405         .parents        = clk_uart3_parents,
1406 };
1407
1408
1409 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1410
1411 static struct clk clk_hsadc_div = {
1412         .name           = "hsadc_div",
1413         .recalc         = clksel_recalc_div,
1414         .set_rate       = clksel_set_rate_div,
1415         .clksel_con     = CRU_CLKSEL14_CON,
1416         .clksel_mask    = 0xFF,
1417         .clksel_shift   = 10,
1418         .clksel_parent_mask     = 7,
1419         .clksel_parent_shift    = 7,
1420         .parents        = clk_hsadc_div_parents,
1421 };
1422
1423 static struct clk clk_hsadc_frac_div = {
1424         .name           = "hsadc_frac_div",
1425         .parent         = &clk_hsadc_div,
1426         .recalc         = clksel_recalc_frac,
1427         .clksel_con     = CRU_CLKSEL15_CON,
1428 };
1429
1430 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
1431
1432 static struct clk clk_demod = {
1433         .name           = "demod",
1434         .clksel_con     = CRU_CLKSEL14_CON,
1435         .clksel_parent_mask     = 3,
1436         .clksel_parent_shift    = 18,
1437         .parents        = clk_demod_parents,
1438 };
1439
1440 static struct clk gpsclk = {
1441         .name           = "gpsclk",
1442 };
1443
1444 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1445
1446 static struct clk clk_hsadc = {
1447         .name           = "hsadc",
1448         .mode           = gate_mode,
1449         .gate_idx       = CLK_GATE_HSADC,
1450         .clksel_con     = CRU_CLKSEL14_CON,
1451         .clksel_parent_mask     = 1,
1452         .clksel_parent_shift    = 21,
1453         .parents        = clk_hsadc_parents,
1454 };
1455
1456 static unsigned long div2_recalc(struct clk *clk)
1457 {
1458         return clk->parent->rate >> 1;
1459 }
1460
1461 static struct clk clk_hsadc_div2 = {
1462         .name           = "hsadc_div2",
1463         .parent         = &clk_demod,
1464         .recalc         = div2_recalc,
1465 };
1466
1467 static struct clk clk_hsadc_div2_inv = {
1468         .name           = "hsadc_div2_inv",
1469         .parent         = &clk_demod,
1470         .recalc         = div2_recalc,
1471 };
1472
1473 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1474
1475 static struct clk clk_hsadc_out = {
1476         .name           = "hsadc_out",
1477         .clksel_con     = CRU_CLKSEL14_CON,
1478         .clksel_parent_mask     = 1,
1479         .clksel_parent_shift    = 20,
1480         .parents        = clk_hsadc_out_parents,
1481 };
1482
1483
1484 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
1485
1486 static struct clk dclk_lcdc_div = {
1487         .name           = "dclk_lcdc_div",
1488         .recalc         = clksel_recalc_div,
1489         .set_rate       = clksel_set_rate_div,
1490         .clksel_con     = CRU_CLKSEL16_CON,
1491         .clksel_mask    = 0xFF,
1492         .clksel_shift   = 2,
1493         .clksel_parent_mask     = 3,
1494         .clksel_parent_shift    = 0,
1495         .parents        = dclk_lcdc_div_parents,
1496 };
1497
1498 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
1499
1500 static struct clk dclk_lcdc = {
1501         .name           = "dclk_lcdc",
1502         .mode           = gate_mode,
1503         .gate_idx       = CLK_GATE_DCLK_LCDC,
1504         .clksel_con     = CRU_CLKSEL16_CON,
1505         .clksel_parent_mask     = 1,
1506         .clksel_parent_shift    = 10,
1507         .parents        = dclk_lcdc_parents,
1508 };
1509
1510 static struct clk dclk_ebook = {
1511         .name           = "dclk_ebook",
1512         .mode           = gate_mode,
1513         .gate_idx       = CLK_GATE_DCLK_EBOOK,
1514         .recalc         = clksel_recalc_div,
1515         .set_rate       = clksel_set_rate_div,
1516         .clksel_con     = CRU_CLKSEL16_CON,
1517         .clksel_mask    = 0x1F,
1518         .clksel_shift   = 13,
1519         .clksel_parent_mask     = 3,
1520         .clksel_parent_shift    = 11,
1521         .parents        = dclk_lcdc_div_parents,
1522 };
1523
1524 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &general_pll_clk, &arm_pll_clk };
1525
1526 static struct clk aclk_lcdc = {
1527         .name           = "aclk_lcdc",
1528         .mode           = gate_mode,
1529         .gate_idx       = CLK_GATE_ACLK_LCDC,
1530         .recalc         = clksel_recalc_div,
1531         .set_rate       = clksel_set_rate_div,
1532         .clksel_con     = CRU_CLKSEL16_CON,
1533         .clksel_mask    = 0x1F,
1534         .clksel_shift   = 20,
1535         .clksel_parent_mask     = 3,
1536         .clksel_parent_shift    = 18,
1537         .parents        = aclk_lcdc_parents,
1538 };
1539
1540 static struct clk hclk_lcdc = {
1541         .name           = "hclk_lcdc",
1542         .mode           = gate_mode,
1543         .gate_idx       = CLK_GATE_HCLK_LCDC,
1544         .parent         = &aclk_lcdc,
1545         .clksel_con     = CRU_CLKSEL16_CON,
1546         .recalc         = clksel_recalc_shift,
1547         .set_rate       = clksel_set_rate_shift,
1548         .clksel_mask    = 3,
1549         .clksel_shift   = 25,
1550         .clksel_maxdiv  = 4,
1551 };
1552
1553 static struct clk *xpu_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1554
1555 static struct clk aclk_vepu = {
1556         .name           = "aclk_vepu",
1557         .mode           = gate_mode,
1558         .recalc         = clksel_recalc_div,
1559         .set_rate       = clksel_set_rate_div,
1560         .gate_idx       = CLK_GATE_ACLK_VEPU,
1561         .clksel_con     = CRU_CLKSEL17_CON,
1562         .clksel_mask    = 0x1F,
1563         .clksel_shift   = 2,
1564         .clksel_parent_mask     = 3,
1565         .clksel_parent_shift    = 0,
1566         .parents        = xpu_parents,
1567 };
1568
1569 static struct clk hclk_vepu = {
1570         .name           = "hclk_vepu",
1571         .parent         = &aclk_vepu,
1572         .mode           = gate_mode,
1573         .recalc         = clksel_recalc_shift,
1574         .set_rate       = clksel_set_rate_shift,
1575         .gate_idx       = CLK_GATE_HCLK_VEPU,
1576         .clksel_con     = CRU_CLKSEL17_CON,
1577         .clksel_mask    = 3,
1578         .clksel_shift   = 28,
1579         .clksel_maxdiv  = 4,
1580 };
1581
1582 static struct clk aclk_vdpu = {
1583         .name           = "aclk_vdpu",
1584         .parent         = &general_pll_clk,
1585         .mode           = gate_mode,
1586         .recalc         = clksel_recalc_div,
1587         .set_rate       = clksel_set_rate_div,
1588         .gate_idx       = CLK_GATE_ACLK_VDPU,
1589         .clksel_con     = CRU_CLKSEL17_CON,
1590         .clksel_mask    = 0x1F,
1591         .clksel_shift   = 9,
1592         .clksel_parent_mask     = 3,
1593         .clksel_parent_shift    = 7,
1594         .parents        = xpu_parents,
1595 };
1596
1597 static struct clk hclk_vdpu = {
1598         .name           = "hclk_vdpu",
1599         .parent         = &aclk_vdpu,
1600         .mode           = gate_mode,
1601         .recalc         = clksel_recalc_shift,
1602         .set_rate       = clksel_set_rate_shift,
1603         .gate_idx       = CLK_GATE_HCLK_VDPU,
1604         .clksel_con     = CRU_CLKSEL17_CON,
1605         .clksel_mask    = 3,
1606         .clksel_shift   = 30,
1607         .clksel_maxdiv  = 4,
1608 };
1609
1610 static struct clk clk_gpu = {
1611         .name           = "gpu",
1612         .mode           = gate_mode,
1613         .gate_idx       = CLK_GATE_GPU,
1614         .recalc         = clksel_recalc_div,
1615         .set_rate       = clksel_set_rate_div,
1616         .clksel_con     = CRU_CLKSEL17_CON,
1617         .clksel_mask    = 0x1F,
1618         .clksel_shift   = 16,
1619         .clksel_parent_mask     = 3,
1620         .clksel_parent_shift    = 14,
1621         .parents        = xpu_parents,
1622 };
1623
1624 static struct clk aclk_gpu = {
1625         .name           = "aclk_gpu",
1626         .mode           = gate_mode,
1627         .gate_idx       = CLK_GATE_ACLK_GPU,
1628         .recalc         = clksel_recalc_div,
1629         .set_rate       = clksel_set_rate_div,
1630         .clksel_con     = CRU_CLKSEL17_CON,
1631         .clksel_mask    = 0x1F,
1632         .clksel_shift   = 23,
1633         .clksel_parent_mask     = 3,
1634         .clksel_parent_shift    = 21,
1635         .parents        = xpu_parents,
1636 };
1637
1638
1639 static struct clk vip_clkin = {
1640         .name           = "vip_clkin",
1641 };
1642
1643 static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
1644
1645 static struct clk clk_vip_out = {
1646         .name           = "vip_out",
1647         .mode           = gate_mode,
1648         .gate_idx       = CLK_GATE_VIP_OUT,
1649         .clksel_con     = CRU_CLKSEL1_CON,
1650         .clksel_parent_mask     = 3,
1651         .clksel_parent_shift    = 7,
1652         .parents        = clk_vip_parents,
1653 };
1654
1655
1656 #define GATE_CLK(NAME,PARENT,ID) \
1657 static struct clk clk_##NAME = { \
1658         .name           = #NAME, \
1659         .parent         = &PARENT, \
1660         .mode           = gate_mode, \
1661         .gate_idx       = CLK_GATE_##ID, \
1662 }
1663
1664 GATE_CLK(i2c0, pclk_cpu, I2C0);
1665 GATE_CLK(i2c1, pclk_periph, I2C1);
1666 GATE_CLK(i2c2, pclk_periph, I2C2);
1667 GATE_CLK(i2c3, pclk_periph, I2C3);
1668
1669 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1670 GATE_CLK(gpio1, pclk_periph, GPIO1);
1671 GATE_CLK(gpio2, pclk_periph, GPIO2);
1672 GATE_CLK(gpio3, pclk_periph, GPIO3);
1673 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1674 GATE_CLK(gpio5, pclk_periph, GPIO5);
1675 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1676
1677 GATE_CLK(dma1, aclk_cpu, DMA1);
1678 GATE_CLK(dma2, aclk_periph, DMA2);
1679
1680 GATE_CLK(gic, aclk_cpu, GIC);
1681 GATE_CLK(intmem, aclk_cpu, INTMEM);
1682 GATE_CLK(rom, hclk_cpu, ROM);
1683 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1684 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1685 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1686 GATE_CLK(efuse, pclk_cpu, EFUSE);
1687 GATE_CLK(tzpc, pclk_cpu, TZPC);
1688 GATE_CLK(debug, pclk_cpu, DEBUG);
1689 GATE_CLK(tpiu, pclk_cpu, TPIU);
1690 GATE_CLK(rtc, pclk_cpu, RTC);
1691 GATE_CLK(pmu, pclk_cpu, PMU);
1692 GATE_CLK(grf, pclk_cpu, GRF);
1693
1694 GATE_CLK(emem, hclk_periph, EMEM);
1695 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
1696 GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
1697 GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
1698 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
1699 GATE_CLK(smc, pclk_periph, SMC);
1700 GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
1701 GATE_CLK(mii_tx, hclk_periph, MII_TX);
1702 GATE_CLK(mii_rx, hclk_periph, MII_RX);
1703 GATE_CLK(hif, hclk_periph, HIF);
1704 GATE_CLK(nandc, hclk_periph, NANDC);
1705 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
1706 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1707 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1708 GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
1709 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1710
1711 GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
1712 GATE_CLK(wdt, pclk_periph, WDT);
1713 GATE_CLK(pwm, pclk_periph, PWM);
1714 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1715 GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
1716 GATE_CLK(vip_input, vip_clkin, VIP_INPUT);
1717 GATE_CLK(jtag, aclk_cpu, JTAG);
1718
1719 GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
1720 GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
1721 GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
1722 GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
1723 GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
1724 GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
1725 GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
1726 GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
1727 GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
1728 GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
1729 GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
1730 GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
1731
1732 GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
1733 GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
1734 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
1735
1736
1737 static void __sramfunc pmu_set_power_domain_sram(enum pmu_power_domain pd, bool on)
1738 {
1739         if (on)
1740                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1741         else
1742                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) |  (1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1743         dsb();
1744
1745         while (pmu_power_domain_is_on(pd) != on)
1746                 ;
1747 }
1748
1749 static noinline void do_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1750 {
1751         static unsigned long save_sp;
1752
1753         DDR_SAVE_SP(save_sp);
1754         pmu_set_power_domain_sram(pd, on);
1755         DDR_RESTORE_SP(save_sp);
1756 }
1757
1758 void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1759 {
1760         unsigned long flags;
1761
1762         mdelay(10);
1763         local_irq_save(flags);
1764         do_pmu_set_power_domain(pd, on);
1765         local_irq_restore(flags);
1766         mdelay(10);
1767 }
1768
1769 static int pd_vcodec_mode(struct clk *clk, int on)
1770 {
1771         if (on) {
1772                 u32 gate;
1773
1774                 gate = cru_clkgate3_con_mirror;
1775                 gate |= (1 << CLK_GATE_ACLK_DDR_VEPU % 32);
1776                 gate &= ~((1 << CLK_GATE_ACLK_VEPU % 32)
1777                         | (1 << CLK_GATE_HCLK_VEPU % 32)
1778                         | (1 << CLK_GATE_HCLK_CPU_VCODEC % 32));
1779                 cru_writel(gate, CRU_CLKGATE3_CON);
1780
1781                 pmu_set_power_domain(PD_VCODEC, true);
1782
1783                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1784         } else {
1785                 pmu_set_power_domain(PD_VCODEC, false);
1786         }
1787
1788         return 0;
1789 }
1790
1791 static struct clk pd_vcodec = {
1792         .name   = "pd_vcodec",
1793         .flags  = IS_PD,
1794         .mode   = pd_vcodec_mode,
1795         .gate_idx       = PD_VCODEC,
1796 };
1797
1798 static int pd_display_mode(struct clk *clk, int on)
1799 {
1800         if (on) {
1801                 u32 gate, gate2;
1802
1803                 gate = cru_clkgate3_con_mirror;
1804                 gate |= (1 << CLK_GATE_ACLK_DDR_LCDC % 32);
1805                 gate &= ~((1 << CLK_GATE_HCLK_CPU_DISPLAY % 32)
1806                         | (1 << CLK_GATE_HCLK_DISP_MATRIX % 32)
1807                         | (1 << CLK_GATE_ACLK_DISP_MATRIX % 32)
1808                         | (1 << CLK_GATE_DCLK_EBOOK % 32)
1809                         | (1 << CLK_GATE_HCLK_EBOOK % 32)
1810                         | (1 << CLK_GATE_HCLK_IPP % 32)
1811                         | (1 << CLK_GATE_ACLK_IPP % 32)
1812                         | (1 << CLK_GATE_DCLK_LCDC % 32)
1813                         | (1 << CLK_GATE_HCLK_LCDC % 32)
1814                         | (1 << CLK_GATE_ACLK_LCDC % 32));
1815                 cru_writel(gate, CRU_CLKGATE3_CON);
1816
1817                 gate2 = cru_readl(CRU_CLKGATE2_CON);
1818                 gate = gate2;
1819                 gate &= ~((1 << CLK_GATE_VIP_OUT % 32)
1820                         | (1 << CLK_GATE_VIP_SLAVE % 32)
1821                         | (1 << CLK_GATE_VIP_MATRIX % 32)
1822                         | (1 << CLK_GATE_VIP_BUS % 32));
1823                 cru_writel(gate, CRU_CLKGATE2_CON);
1824
1825                 pmu_set_power_domain(PD_DISPLAY, true);
1826
1827                 cru_writel(gate2, CRU_CLKGATE2_CON);
1828                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1829         } else {
1830                 pmu_set_power_domain(PD_DISPLAY, false);
1831         }
1832
1833         return 0;
1834 }
1835
1836 static struct clk pd_display = {
1837         .name   = "pd_display",
1838         .flags  = IS_PD,
1839         .mode   = pd_display_mode,
1840         .gate_idx       = PD_DISPLAY,
1841 };
1842
1843 static int pd_gpu_mode(struct clk *clk, int on)
1844 {
1845         if (on) {
1846                 pmu_set_power_domain(PD_GPU, true);
1847         } else {
1848                 pmu_set_power_domain(PD_GPU, false);
1849         }
1850
1851         return 0;
1852 }
1853
1854 static struct clk pd_gpu = {
1855         .name   = "pd_gpu",
1856         .flags  = IS_PD,
1857         .mode   = pd_gpu_mode,
1858         .gate_idx       = PD_GPU,
1859 };
1860
1861
1862 #define CLK(dev, con, ck) \
1863         { \
1864                 .dev_id = dev, \
1865                 .con_id = con, \
1866                 .clk = ck, \
1867         }
1868
1869 #define CLK1(name) \
1870         { \
1871                 .dev_id = NULL, \
1872                 .con_id = #name, \
1873                 .clk = &clk_##name, \
1874         }
1875
1876 static struct clk_lookup clks[] = {
1877         CLK(NULL, "xin24m", &xin24m),
1878         CLK(NULL, "xin27m", &xin27m),
1879         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1880         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1881         CLK(NULL, "gpsclk", &gpsclk),
1882         CLK(NULL, "vip_clkin", &vip_clkin),
1883
1884         CLK1(12m),
1885         CLK(NULL, "arm_pll", &arm_pll_clk),
1886         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1887         CLK(NULL, "codec_pll", &codec_pll_clk),
1888         CLK(NULL, "general_pll", &general_pll_clk),
1889
1890         CLK1(core),
1891         CLK(NULL, "aclk_cpu", &aclk_cpu),
1892         CLK(NULL, "hclk_cpu", &hclk_cpu),
1893         CLK(NULL, "pclk_cpu", &pclk_cpu),
1894
1895         CLK(NULL, "aclk_periph", &aclk_periph),
1896         CLK(NULL, "hclk_periph", &hclk_periph),
1897         CLK(NULL, "pclk_periph", &pclk_periph),
1898
1899         CLK1(vip_out),
1900         CLK1(otgphy0),
1901         CLK1(otgphy1),
1902         CLK1(uhost),
1903         CLK1(mac_ref_div),
1904         CLK1(mac_ref),
1905
1906         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
1907         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
1908         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
1909         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
1910         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
1911         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
1912         CLK(NULL, "spdif_div", &clk_spdif_div),
1913         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
1914         CLK(NULL, "spdif", &clk_spdif),
1915
1916         CLK1(spi_src),
1917         CLK("rk29xx_spim.0", "spi", &clk_spi0),
1918         CLK("rk29xx_spim.1", "spi", &clk_spi1),
1919
1920         CLK1(saradc),
1921         CLK1(timer0),
1922         CLK1(timer1),
1923         CLK1(timer2),
1924         CLK1(timer3),
1925
1926         CLK1(mmc_src),
1927         CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
1928         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
1929         CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
1930         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
1931         CLK1(emmc),
1932         CLK1(hclk_emmc),
1933         CLK1(ddr),
1934
1935         CLK1(uart01_src),
1936         CLK("rk29_serial.0", "uart", &clk_uart0),
1937         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
1938         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
1939         CLK("rk29_serial.1", "uart", &clk_uart1),
1940         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
1941         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
1942
1943         CLK1(uart23_src),
1944         CLK("rk29_serial.2", "uart", &clk_uart2),
1945         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
1946         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
1947         CLK("rk29_serial.3", "uart", &clk_uart3),
1948         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
1949         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
1950
1951         CLK1(hsadc_div),
1952         CLK1(hsadc_frac_div),
1953         CLK1(demod),
1954         CLK1(hsadc),
1955         CLK1(hsadc_div2),
1956         CLK1(hsadc_div2_inv),
1957         CLK1(hsadc_out),
1958
1959         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
1960         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
1961         CLK(NULL, "dclk_ebook", &dclk_ebook),
1962         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
1963         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
1964
1965         CLK(NULL, "aclk_vepu", &aclk_vepu),
1966         CLK(NULL, "hclk_vepu", &hclk_vepu),
1967         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
1968         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
1969         CLK1(gpu),
1970         CLK(NULL, "aclk_gpu", &aclk_gpu),
1971
1972         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
1973         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
1974         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
1975         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
1976
1977         CLK1(gpio0),
1978         CLK1(gpio1),
1979         CLK1(gpio2),
1980         CLK1(gpio3),
1981         CLK1(gpio4),
1982         CLK1(gpio5),
1983         CLK1(gpio6),
1984
1985         CLK1(dma1),
1986         CLK1(dma2),
1987
1988         CLK1(gic),
1989         CLK1(intmem),
1990         CLK1(rom),
1991         CLK1(ddr_phy),
1992         CLK1(ddr_reg),
1993         CLK1(ddr_cpu),
1994         CLK1(efuse),
1995         CLK1(tzpc),
1996         CLK1(debug),
1997         CLK1(tpiu),
1998         CLK1(rtc),
1999         CLK1(pmu),
2000         CLK1(grf),
2001
2002         CLK1(emem),
2003         CLK1(hclk_usb_peri),
2004         CLK1(aclk_ddr_peri),
2005         CLK1(aclk_cpu_peri),
2006         CLK1(aclk_smc),
2007         CLK1(smc),
2008         CLK1(hclk_mac),
2009         CLK1(mii_tx),
2010         CLK1(mii_rx),
2011         CLK1(hif),
2012         CLK1(nandc),
2013         CLK1(hclk_hsadc),
2014         CLK1(usbotg0),
2015         CLK1(usbotg1),
2016         CLK1(hclk_uhost),
2017         CLK1(pid_filter),
2018
2019         CLK1(vip_slave),
2020         CLK1(wdt),
2021         CLK1(pwm),
2022         CLK1(vip_bus),
2023         CLK1(vip_matrix),
2024         CLK1(vip_input),
2025         CLK1(jtag),
2026
2027         CLK1(aclk_ddr_lcdc),
2028         CLK1(aclk_ipp),
2029         CLK1(hclk_ipp),
2030         CLK1(hclk_ebook),
2031         CLK1(aclk_disp_matrix),
2032         CLK1(hclk_disp_matrix),
2033         CLK1(aclk_ddr_vepu),
2034         CLK1(aclk_ddr_vdpu),
2035         CLK1(aclk_ddr_gpu),
2036         CLK1(hclk_gpu),
2037         CLK1(hclk_cpu_vcodec),
2038         CLK1(hclk_cpu_display),
2039
2040         CLK(NULL, "pd_vcodec", &pd_vcodec),
2041         CLK(NULL, "pd_display", &pd_display),
2042         CLK(NULL, "pd_gpu", &pd_gpu),
2043 };
2044
2045 static LIST_HEAD(clocks);
2046 static DEFINE_MUTEX(clocks_mutex);
2047 static DEFINE_SPINLOCK(clockfw_lock);
2048 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
2049 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
2050
2051 static int clk_enable_nolock(struct clk *clk)
2052 {
2053         int ret = 0;
2054
2055         if (clk->usecount == 0) {
2056                 if (clk->parent) {
2057                         ret = clk_enable_nolock(clk->parent);
2058                         if (ret)
2059                                 return ret;
2060                 }
2061
2062                 if (clk->mode) {
2063                         ret = clk->mode(clk, 1);
2064                         if (ret) {
2065                                 if (clk->parent)
2066                                         clk_disable_nolock(clk->parent);
2067                                 return ret;
2068                         }
2069                 }
2070                 pr_debug("%s enabled\n", clk->name);
2071         }
2072         clk->usecount++;
2073
2074         return ret;
2075 }
2076
2077 int clk_enable(struct clk *clk)
2078 {
2079         int ret = 0;
2080
2081         if (clk == NULL || IS_ERR(clk))
2082                 return -EINVAL;
2083
2084         LOCK();
2085         ret = clk_enable_nolock(clk);
2086         UNLOCK();
2087
2088         return ret;
2089 }
2090 EXPORT_SYMBOL(clk_enable);
2091
2092 static void clk_disable_nolock(struct clk *clk)
2093 {
2094         if (clk->usecount == 0) {
2095                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
2096                 WARN_ON(1);
2097                 return;
2098         }
2099
2100         if (--clk->usecount == 0) {
2101                 if (clk->mode)
2102                         clk->mode(clk, 0);
2103                 pr_debug("%s disabled\n", clk->name);
2104                 if (clk->parent)
2105                         clk_disable_nolock(clk->parent);
2106         }
2107 }
2108
2109 void clk_disable(struct clk *clk)
2110 {
2111         if (clk == NULL || IS_ERR(clk))
2112                 return;
2113
2114         LOCK();
2115         clk_disable_nolock(clk);
2116         UNLOCK();
2117 }
2118 EXPORT_SYMBOL(clk_disable);
2119
2120 unsigned long clk_get_rate(struct clk *clk)
2121 {
2122         if (clk == NULL || IS_ERR(clk))
2123                 return 0;
2124
2125         return clk->rate;
2126 }
2127 EXPORT_SYMBOL(clk_get_rate);
2128
2129 /*-------------------------------------------------------------------------
2130  * Optional clock functions defined in include/linux/clk.h
2131  *-------------------------------------------------------------------------*/
2132
2133 /* Given a clock and a rate apply a clock specific rounding function */
2134 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
2135 {
2136         if (clk->round_rate)
2137                 return clk->round_rate(clk, rate);
2138
2139         if (clk->flags & RATE_FIXED)
2140                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
2141
2142         return clk->rate;
2143 }
2144
2145 long clk_round_rate(struct clk *clk, unsigned long rate)
2146 {
2147         long ret = 0;
2148
2149         if (clk == NULL || IS_ERR(clk))
2150                 return ret;
2151
2152         LOCK();
2153         ret = clk_round_rate_nolock(clk, rate);
2154         UNLOCK();
2155
2156         return ret;
2157 }
2158 EXPORT_SYMBOL(clk_round_rate);
2159
2160 static void __clk_recalc(struct clk *clk)
2161 {
2162         if (unlikely(clk->flags & RATE_FIXED))
2163                 return;
2164         if (clk->recalc)
2165                 clk->rate = clk->recalc(clk);
2166         else if (clk->parent)
2167                 clk->rate = clk->parent->rate;
2168         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
2169 }
2170
2171 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
2172 {
2173         int ret;
2174
2175         if (rate == clk->rate)
2176                 return 0;
2177
2178         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
2179
2180         if (clk->flags & CONFIG_PARTICIPANT)
2181                 return -EINVAL;
2182
2183         if (!clk->set_rate)
2184                 return -EINVAL;
2185
2186         ret = clk->set_rate(clk, rate);
2187
2188         if (ret == 0) {
2189                 __clk_recalc(clk);
2190                 __propagate_rate(clk);
2191         }
2192
2193         return ret;
2194 }
2195
2196 /* Set the clock rate for a clock source */
2197 int clk_set_rate(struct clk *clk, unsigned long rate)
2198 {
2199         int ret = -EINVAL;
2200
2201         if (clk == NULL || IS_ERR(clk))
2202                 return ret;
2203
2204         LOCK();
2205         ret = clk_set_rate_nolock(clk, rate);
2206         UNLOCK();
2207
2208         return ret;
2209 }
2210 EXPORT_SYMBOL(clk_set_rate);
2211
2212 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
2213 {
2214         int ret;
2215         int enabled = clk->usecount > 0;
2216         struct clk *old_parent = clk->parent;
2217
2218         if (clk->parent == parent)
2219                 return 0;
2220
2221         /* if clk is already enabled, enable new parent first and disable old parent later. */
2222         if (enabled)
2223                 clk_enable_nolock(parent);
2224
2225         if (clk->set_parent)
2226                 ret = clk->set_parent(clk, parent);
2227         else
2228                 ret = clksel_set_parent(clk, parent);
2229
2230         if (ret == 0) {
2231                 /* OK */
2232                 __clk_reparent(clk, parent);
2233                 __clk_recalc(clk);
2234                 __propagate_rate(clk);
2235                 if (enabled)
2236                         clk_disable_nolock(old_parent);
2237         } else {
2238                 if (enabled)
2239                         clk_disable_nolock(parent);
2240         }
2241
2242         return ret;
2243 }
2244
2245 int clk_set_parent(struct clk *clk, struct clk *parent)
2246 {
2247         int ret = -EINVAL;
2248
2249         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
2250                 return ret;
2251
2252         if (clk->set_parent == NULL && clk->parents == NULL)
2253                 return ret;
2254
2255         LOCK();
2256         if (clk->usecount == 0)
2257                 ret = clk_set_parent_nolock(clk, parent);
2258         else
2259                 ret = -EBUSY;
2260         UNLOCK();
2261
2262         return ret;
2263 }
2264 EXPORT_SYMBOL(clk_set_parent);
2265
2266 struct clk *clk_get_parent(struct clk *clk)
2267 {
2268         return clk->parent;
2269 }
2270 EXPORT_SYMBOL(clk_get_parent);
2271
2272 static void __clk_reparent(struct clk *child, struct clk *parent)
2273 {
2274         if (child->parent == parent)
2275                 return;
2276         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
2277
2278         list_del_init(&child->sibling);
2279         if (parent)
2280                 list_add(&child->sibling, &parent->children);
2281         child->parent = parent;
2282 }
2283
2284 /* Propagate rate to children */
2285 static void __propagate_rate(struct clk *tclk)
2286 {
2287         struct clk *clkp;
2288
2289         list_for_each_entry(clkp, &tclk->children, sibling) {
2290                 __clk_recalc(clkp);
2291                 __propagate_rate(clkp);
2292         }
2293 }
2294
2295 static LIST_HEAD(root_clks);
2296
2297 /**
2298  * recalculate_root_clocks - recalculate and propagate all root clocks
2299  *
2300  * Recalculates all root clocks (clocks with no parent), which if the
2301  * clock's .recalc is set correctly, should also propagate their rates.
2302  * Called at init.
2303  */
2304 static void clk_recalculate_root_clocks_nolock(void)
2305 {
2306         struct clk *clkp;
2307
2308         list_for_each_entry(clkp, &root_clks, sibling) {
2309                 __clk_recalc(clkp);
2310                 __propagate_rate(clkp);
2311         }
2312 }
2313
2314 void clk_recalculate_root_clocks(void)
2315 {
2316         LOCK();
2317         clk_recalculate_root_clocks_nolock();
2318         UNLOCK();
2319 }
2320
2321
2322 /**
2323  * clk_preinit - initialize any fields in the struct clk before clk init
2324  * @clk: struct clk * to initialize
2325  *
2326  * Initialize any struct clk fields needed before normal clk initialization
2327  * can run.  No return value.
2328  */
2329 static void clk_preinit(struct clk *clk)
2330 {
2331         INIT_LIST_HEAD(&clk->children);
2332 }
2333
2334 static int clk_register(struct clk *clk)
2335 {
2336         if (clk == NULL || IS_ERR(clk))
2337                 return -EINVAL;
2338
2339         /*
2340          * trap out already registered clocks
2341          */
2342         if (clk->node.next || clk->node.prev)
2343                 return 0;
2344
2345         mutex_lock(&clocks_mutex);
2346
2347         if (clk->get_parent)
2348                 clk->parent = clk->get_parent(clk);
2349         else if (clk->parents)
2350                 clk->parent = clksel_get_parent(clk);
2351
2352         if (clk->parent)
2353                 list_add(&clk->sibling, &clk->parent->children);
2354         else
2355                 list_add(&clk->sibling, &root_clks);
2356
2357         list_add(&clk->node, &clocks);
2358
2359         mutex_unlock(&clocks_mutex);
2360
2361         return 0;
2362 }
2363
2364 static unsigned int __initdata armclk = 300 * MHZ;
2365
2366 /*
2367  * You can override arm_clk rate with armclk= cmdline option.
2368  */
2369 static int __init armclk_setup(char *str)
2370 {
2371         get_option(&str, &armclk);
2372
2373         if (!armclk)
2374                 return 0;
2375
2376         if (armclk < 10000)
2377                 armclk *= MHZ;
2378
2379         clk_set_rate_nolock(&arm_pll_clk, armclk);
2380         return 0;
2381 }
2382 early_param("armclk", armclk_setup);
2383
2384 static void __init rk29_clock_common_init(unsigned long ppll_rate)
2385 {
2386         unsigned long aclk_p, hclk_p, pclk_p;
2387         struct clk *aclk_vepu_parent, *aclk_vdpu_parent, *aclk_gpu_parent;
2388         unsigned long aclk_vepu_rate, hclk_vepu_rate, aclk_ddr_vepu_rate, aclk_gpu_rate;
2389         unsigned long codec_pll = 552 * MHZ;
2390
2391         /* general pll */
2392         switch (ppll_rate) {
2393         case 96 * MHZ:
2394                 aclk_p = 96 * MHZ;
2395                 hclk_p = 48 * MHZ;
2396                 pclk_p = 24 * MHZ;
2397                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
2398                 aclk_gpu_rate = aclk_ddr_vepu_rate = aclk_vepu_rate = codec_pll / 2;
2399                 hclk_vepu_rate = codec_pll / 4;
2400                 break;
2401         case 144 * MHZ:
2402                 aclk_p = 144 * MHZ;
2403                 hclk_p = 72 * MHZ;
2404                 pclk_p = 36 * MHZ;
2405                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
2406                 aclk_gpu_rate = aclk_ddr_vepu_rate = aclk_vepu_rate = codec_pll / 2;
2407                 hclk_vepu_rate = codec_pll / 4;
2408                 break;
2409         default:
2410                 ppll_rate = 288 * MHZ;
2411         case 288 * MHZ:
2412         case 300 * MHZ:
2413                 aclk_p = ppll_rate / 2;
2414                 hclk_p = ppll_rate / 2;
2415                 pclk_p = ppll_rate / 8;
2416                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &general_pll_clk;
2417                 aclk_gpu_rate = aclk_ddr_vepu_rate = aclk_vepu_rate = ppll_rate;
2418                 hclk_vepu_rate = ppll_rate / 2;
2419                 break;
2420         }
2421
2422         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
2423         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2424         clk_set_rate_nolock(&aclk_periph, aclk_p);
2425         clk_set_rate_nolock(&hclk_periph, hclk_p);
2426         clk_set_rate_nolock(&pclk_periph, pclk_p);
2427         clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
2428         clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2429         clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
2430         clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
2431         clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
2432         clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
2433         clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
2434         clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
2435         clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
2436         clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
2437         clk_set_parent_nolock(&aclk_lcdc, &general_pll_clk);
2438         clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
2439         clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
2440
2441         /* codec pll */
2442         clk_set_rate_nolock(&codec_pll_clk, codec_pll);
2443         clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
2444
2445         /* arm pll */
2446         clk_set_rate_nolock(&arm_pll_clk, armclk);
2447
2448         /*you can choose clk parent form codec pll or periph pll for following logic*/
2449         clk_set_parent_nolock(&aclk_vepu, aclk_vepu_parent);
2450         clk_set_rate_nolock(&aclk_vepu, aclk_vepu_rate);
2451         clk_set_rate_nolock(&clk_aclk_ddr_vepu,aclk_ddr_vepu_rate);
2452         clk_set_rate_nolock(&hclk_vepu, hclk_vepu_rate);
2453         clk_set_parent_nolock(&aclk_vdpu, aclk_vdpu_parent);
2454         clk_set_parent_nolock(&aclk_gpu, aclk_gpu_parent);
2455         clk_set_rate_nolock(&aclk_gpu, aclk_gpu_rate);
2456 }
2457
2458 static void __init clk_enable_init_clocks(void)
2459 {
2460         clk_enable_nolock(&hclk_cpu);
2461         clk_enable_nolock(&pclk_cpu);
2462         clk_enable_nolock(&hclk_periph);
2463         clk_enable_nolock(&pclk_periph);
2464         clk_enable_nolock(&clk_nandc);
2465         clk_enable_nolock(&clk_aclk_cpu_peri);
2466         clk_enable_nolock(&clk_aclk_ddr_peri);
2467         clk_enable_nolock(&clk_grf);
2468         clk_enable_nolock(&clk_pmu);
2469         clk_enable_nolock(&clk_ddr_cpu);
2470         clk_enable_nolock(&clk_ddr_reg);
2471         clk_enable_nolock(&clk_ddr_phy);
2472         clk_enable_nolock(&clk_gic);
2473         clk_enable_nolock(&clk_dma2);
2474         clk_enable_nolock(&clk_dma1);
2475         clk_enable_nolock(&clk_emem);
2476         clk_enable_nolock(&clk_intmem);
2477         clk_enable_nolock(&clk_ddr);
2478         clk_enable_nolock(&clk_debug);
2479         clk_enable_nolock(&clk_jtag);
2480         clk_enable_nolock(&clk_uart1);
2481 }
2482
2483 static int __init clk_disable_unused(void)
2484 {
2485         struct clk *ck;
2486
2487         list_for_each_entry(ck, &clocks, node) {
2488                 if (ck->usecount > 0 || ck->mode == NULL || (ck->flags & IS_PD))
2489                         continue;
2490
2491                 LOCK();
2492                 clk_enable_nolock(ck);
2493                 clk_disable_nolock(ck);
2494                 UNLOCK();
2495         }
2496
2497         return 0;
2498 }
2499
2500 void __init rk29_clock_init(enum periph_pll ppll_rate)
2501 {
2502         struct clk_lookup *lk;
2503
2504         cru_clkgate3_con_mirror = cru_readl(CRU_CLKGATE3_CON);
2505         cru_softrst0_con_mirror = cru_readl(CRU_SOFTRST0_CON);
2506
2507         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2508                 clk_preinit(lk->clk);
2509
2510         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2511                 clkdev_add(lk);
2512                 clk_register(lk->clk);
2513         }
2514
2515         clk_recalculate_root_clocks_nolock();
2516
2517         /*
2518          * Only enable those clocks we will need, let the drivers
2519          * enable other clocks as necessary
2520          */
2521         clk_enable_init_clocks();
2522
2523         /*
2524          * Disable any unused clocks left on by the bootloader
2525          */
2526         clk_disable_unused();
2527
2528         rk29_clock_common_init(ppll_rate);
2529
2530         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
2531                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
2532                aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
2533 }
2534
2535 #ifdef CONFIG_PROC_FS
2536 #include <linux/proc_fs.h>
2537 #include <linux/seq_file.h>
2538
2539 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2540 {
2541         struct clk* ck;
2542         int i;
2543         unsigned long rate = clk->rate;
2544
2545         for (i = 0; i < deep; i++)
2546                 seq_printf(s, "    ");
2547
2548         seq_printf(s, "%-11s ", clk->name);
2549
2550         if (clk->flags & IS_PD) {
2551                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
2552         }
2553
2554         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
2555                 u32 reg;
2556                 int idx = clk->gate_idx;
2557                 u32 v;
2558
2559                 reg = CRU_CLKGATE0_CON;
2560                 reg += (idx >> 5) << 2;
2561                 idx &= 0x1F;
2562
2563                 if (reg == CRU_CLKGATE3_CON)
2564                         v = cru_clkgate3_con_mirror & (1 << idx);
2565                 else
2566                         v = cru_readl(reg) & (1 << idx);
2567
2568                 seq_printf(s, "%s ", v ? "off" : "on ");
2569         }
2570
2571         if (clk == &arm_pll_clk) {
2572                 switch (cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) {
2573                 case CRU_CPU_MODE_SLOW:   seq_printf(s, "slow   "); break;
2574                 case CRU_CPU_MODE_NORMAL: seq_printf(s, "normal "); break;
2575                 case CRU_CPU_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2576                 }
2577                 if (cru_readl(CRU_APLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2578         } else if (clk == &ddr_pll_clk) {
2579                 switch (cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) {
2580                 case CRU_DDR_MODE_SLOW:   seq_printf(s, "slow   "); break;
2581                 case CRU_DDR_MODE_NORMAL: seq_printf(s, "normal "); break;
2582                 case CRU_DDR_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2583                 }
2584                 if (cru_readl(CRU_DPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2585         } else if (clk == &codec_pll_clk) {
2586                 switch (cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) {
2587                 case CRU_CODEC_MODE_SLOW:   seq_printf(s, "slow   "); break;
2588                 case CRU_CODEC_MODE_NORMAL: seq_printf(s, "normal "); break;
2589                 case CRU_CODEC_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2590                 }
2591                 if (cru_readl(CRU_CPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2592         } else if (clk == &general_pll_clk) {
2593                 switch (cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) {
2594                 case CRU_GENERAL_MODE_SLOW:   seq_printf(s, "slow   "); break;
2595                 case CRU_GENERAL_MODE_NORMAL: seq_printf(s, "normal "); break;
2596                 case CRU_GENERAL_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2597                 }
2598                 if (cru_readl(CRU_GPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2599         }
2600
2601         if (rate >= MHZ) {
2602                 if (rate % MHZ)
2603                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2604                 else
2605                         seq_printf(s, "%ld MHz", rate / MHZ);
2606         } else if (rate >= KHZ) {
2607                 if (rate % KHZ)
2608                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2609                 else
2610                         seq_printf(s, "%ld KHz", rate / KHZ);
2611         } else {
2612                 seq_printf(s, "%ld Hz", rate);
2613         }
2614
2615         seq_printf(s, " usecount = %d", clk->usecount);
2616
2617         if (clk->parent)
2618                 seq_printf(s, " parent = %s", clk->parent->name);
2619
2620         seq_printf(s, "\n");
2621
2622         list_for_each_entry(ck, &clocks, node) {
2623                 if (ck->parent == clk)
2624                         dump_clock(s, ck, deep + 1);
2625         }
2626 }
2627
2628 static int proc_clk_show(struct seq_file *s, void *v)
2629 {
2630         struct clk* clk;
2631
2632         mutex_lock(&clocks_mutex);
2633         list_for_each_entry(clk, &clocks, node) {
2634                 if (!clk->parent)
2635                         dump_clock(s, clk, 0);
2636         }
2637         mutex_unlock(&clocks_mutex);
2638
2639         seq_printf(s, "\nCRU Registers:\n");
2640         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2641         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2642         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2643         seq_printf(s, "GPLL     : 0x%08x\n", cru_readl(CRU_GPLL_CON));
2644         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2645         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2646         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2647         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2648         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2649         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2650         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2651         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2652         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2653         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2654         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2655         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2656         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2657         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2658         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2659         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2660         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2661         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2662         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2663         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2664         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2665         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2666         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2667         seq_printf(s, "CLKGATE3M: 0x%08x\n", cru_clkgate3_con_mirror);
2668         seq_printf(s, "SOFTRST0 : 0x%08x\n", cru_readl(CRU_SOFTRST0_CON));
2669         seq_printf(s, "SOFTRST0M: 0x%08x\n", cru_softrst0_con_mirror);
2670         seq_printf(s, "SOFTRST1 : 0x%08x\n", cru_readl(CRU_SOFTRST1_CON));
2671         seq_printf(s, "SOFTRST2 : 0x%08x\n", cru_readl(CRU_SOFTRST2_CON));
2672
2673         seq_printf(s, "\nPMU Registers:\n");
2674         seq_printf(s, "WAKEUP_EN0 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN0));
2675         seq_printf(s, "WAKEUP_EN1 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN1));
2676         seq_printf(s, "WAKEUP_EN2 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN2));
2677         seq_printf(s, "PD_CON     : 0x%08x\n", pmu_readl(PMU_PD_CON));
2678         seq_printf(s, "MISC_CON   : 0x%08x\n", pmu_readl(PMU_MISC_CON));
2679         seq_printf(s, "PLL_CNT    : 0x%08x\n", pmu_readl(PMU_PLL_CNT));
2680         seq_printf(s, "PD_ST      : 0x%08x\n", pmu_readl(PMU_PD_ST));
2681         seq_printf(s, "INT_ST     : 0x%08x\n", pmu_readl(PMU_INT_ST));
2682
2683         return 0;
2684 }
2685
2686 static int proc_clk_open(struct inode *inode, struct file *file)
2687 {
2688         return single_open(file, proc_clk_show, NULL);
2689 }
2690
2691 static const struct file_operations proc_clk_fops = {
2692         .open           = proc_clk_open,
2693         .read           = seq_read,
2694         .llseek         = seq_lseek,
2695         .release        = single_release,
2696 };
2697
2698 static int __init clk_proc_init(void)
2699 {
2700         proc_create("clocks", 0, NULL, &proc_clk_fops);
2701         return 0;
2702
2703 }
2704 late_initcall(clk_proc_init);
2705 #endif /* CONFIG_PROC_FS */
2706