arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33 #include <mach/pmu.h>
  34
  35
  36 /* Clock flags */
  37 /* bit 0 is free */
  38 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  39 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  40
  41 #define cru_readl(offset)       readl(RK29_CRU_BASE + offset)
  42 #define cru_writel(v, offset)   writel(v, RK29_CRU_BASE + offset)
  43
  44 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  45 #define pmu_readl(offset)       readl(RK29_PMU_BASE + offset)
  46
  47 #define MHZ                     (1000*1000)
  48 #define KHZ                     1000
  49
  50 struct clk {
  51         struct list_head        node;
  52         const char              *name;
  53         struct clk              *parent;
  54         struct list_head        children;
  55         struct list_head        sibling;        /* node for children */
  56         unsigned long           rate;
  57         u32                     flags;
  58         int                     (*mode)(struct clk *clk, int on);
  59         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  60         int                     (*set_rate)(struct clk *, unsigned long);
  61         long                    (*round_rate)(struct clk *, unsigned long);
  62         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
  63         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
  64         s32                     usecount;
  65         u8                      gate_idx;
  66         u8                      pll_idx;
  67         u8                      clksel_con;
  68         u8                      clksel_mask;
  69         u8                      clksel_shift;
  70         u8                      clksel_maxdiv;
  71         u8                      clksel_parent_mask;
  72         u8                      clksel_parent_shift;
  73         struct clk              **parents;
  74 };
  75
  76 static int clk_enable_nolock(struct clk *clk);
  77 static void clk_disable_nolock(struct clk *clk);
  78 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
  79 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
  80 static void __clk_reparent(struct clk *child, struct clk *parent);
  81 static void __propagate_rate(struct clk *tclk);
  82 static struct clk codec_pll_clk;
  83 static struct clk general_pll_clk;
  84
  85 static unsigned long clksel_recalc_div(struct clk *clk)
  86 {
  87         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
  88         unsigned long rate = clk->parent->rate / div;
  89         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
  90         return rate;
  91 }
  92
  93 static unsigned long clksel_recalc_shift(struct clk *clk)
  94 {
  95         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
  96         unsigned long rate = clk->parent->rate >> shift;
  97         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
  98         return rate;
  99 }
 100
 101 static unsigned long clksel_recalc_frac(struct clk *clk)
 102 {
 103         unsigned long rate;
 104         u64 rate64;
 105         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 106         if (r == 0) // FPGA ?
 107                 return clk->parent->rate;
 108         numerator = r >> 16;
 109         denominator = r & 0xFFFF;
 110         rate64 = (u64)clk->parent->rate * numerator;
 111         do_div(rate64, denominator);
 112         rate = rate64;
 113         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 114         return rate;
 115 }
 116
 117 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 118 {
 119         u32 div;
 120
 121         for (div = 0; div <= clk->clksel_mask; div++) {
 122                 u32 new_rate = clk->parent->rate / (div + 1);
 123                 if (new_rate <= rate) {
 124                         u32 v = cru_readl(clk->clksel_con);
 125                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 126                         v |= div << clk->clksel_shift;
 127                         cru_writel(v, clk->clksel_con);
 128                         clk->rate = new_rate;
 129                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 130                         return 0;
 131                 }
 132         }
 133
 134         return -ENOENT;
 135 }
 136
 137 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 138 {
 139         u32 shift;
 140
 141         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 142                 u32 new_rate = clk->parent->rate >> shift;
 143                 if (new_rate <= rate) {
 144                         u32 v = cru_readl(clk->clksel_con);
 145                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 146                         v |= shift << clk->clksel_shift;
 147                         cru_writel(v, clk->clksel_con);
 148                         clk->rate = new_rate;
 149                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 150                         return 0;
 151                 }
 152         }
 153
 154         return -ENOENT;
 155 }
 156
 157 static struct clk* clksel_get_parent(struct clk *clk)
 158 {
 159         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 160 }
 161
 162 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 163 {
 164         struct clk **p = clk->parents;
 165         u32 i;
 166
 167         if (unlikely(!p))
 168                 return -EINVAL;
 169         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 170                 u32 v;
 171                 if (*p != parent)
 172                         continue;
 173                 v = cru_readl(clk->clksel_con);
 174                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 175                 v |= (i << clk->clksel_parent_shift);
 176                 cru_writel(v, clk->clksel_con);
 177                 return 0;
 178         }
 179         return -EINVAL;
 180 }
 181
 182 static int gate_mode(struct clk *clk, int on)
 183 {
 184         u32 reg;
 185         int idx = clk->gate_idx;
 186         u32 v;
 187
 188         if (idx >= CLK_GATE_MAX)
 189                 return -EINVAL;
 190
 191         reg = CRU_CLKGATE0_CON;
 192         reg += (idx >> 5) << 2;
 193         idx &= 0x1F;
 194
 195         v = cru_readl(reg);
 196         if (on) {
 197                 v &= ~(1 << idx);       // clear bit
 198         } else {
 199                 v |= (1 << idx);        // set bit
 200         }
 201         cru_writel(v, reg);
 202
 203         return 0;
 204 }
 205
 206 static struct clk xin24m = {
 207         .name           = "xin24m",
 208         .rate           = 24 * MHZ,
 209         .flags          = RATE_FIXED,
 210 };
 211
 212 static struct clk clk_12m = {
 213         .name           = "clk_12m",
 214         .rate           = 12 * MHZ,
 215         .parent         = &xin24m,
 216         .flags          = RATE_FIXED,
 217 };
 218
 219 static struct clk xin27m = {
 220         .name           = "xin27m",
 221         .rate           = 27 * MHZ,
 222         .flags          = RATE_FIXED,
 223 };
 224
 225 static struct clk otgphy0_clkin = {
 226         .name           = "otgphy0_clkin",
 227         .rate           = 480 * MHZ,
 228         .flags          = RATE_FIXED,
 229 };
 230
 231 static struct clk otgphy1_clkin = {
 232         .name           = "otgphy1_clkin",
 233         .rate           = 480 * MHZ,
 234         .flags          = RATE_FIXED,
 235 };
 236
 237
 238 static void delay_500ns(void)
 239 {
 240         int delay = 2000;
 241         while (delay--)
 242                 barrier();
 243 }
 244
 245 static void delay_300us(void)
 246 {
 247         int i;
 248         for (i = 0; i < 600; i++)
 249                 delay_500ns();
 250 }
 251
 252 #define GENERAL_PLL_IDX     0
 253 #define CODEC_PLL_IDX      1
 254 #define ARM_PLL_IDX        2
 255 #define DDR_PLL_IDX        3
 256
 257 #define GRF_SOC_CON0       0xbc
 258 static void pll_wait_lock(int pll_idx)
 259 {
 260         u32 bit = 0x2000000u << pll_idx;
 261         int delay = 2400000;
 262         while (delay > 0) {
 263                 if (regfile_readl(GRF_SOC_CON0) & bit)
 264                         break;
 265                 delay--;
 266         }
 267         if (delay == 0) {
 268                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 269         }
 270 }
 271
 272 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 273 {
 274         unsigned long rate;
 275
 276         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 277                 u32 v = cru_readl(CRU_APLL_CON);
 278                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 279                 do_div(rate64, PLL_NR(v));
 280                 rate = rate64 >> PLL_NO_SHIFT(v);
 281                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 282         } else {
 283                 rate = clk->parent->rate;
 284                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 285         }
 286
 287         return rate;
 288 }
 289
 290 struct arm_pll_set {
 291         unsigned long rate;
 292         u32 apll_con;
 293         u32 clksel0_con;
 294 };
 295
 296 #define CORE_ACLK_11    (0 << 5)
 297 #define CORE_ACLK_21    (1 << 5)
 298 #define CORE_ACLK_31    (2 << 5)
 299 #define CORE_ACLK_41    (3 << 5)
 300 #define CORE_ACLK_81    (4 << 5)
 301 #define CORE_ACLK_MASK  (7 << 5)
 302
 303 #define ACLK_HCLK_11    (0 << 8)
 304 #define ACLK_HCLK_21    (1 << 8)
 305 #define ACLK_HCLK_41    (2 << 8)
 306 #define ACLK_HCLK_MASK  (3 << 8)
 307
 308 #define ACLK_PCLK_11    (0 << 10)
 309 #define ACLK_PCLK_21    (1 << 10)
 310 #define ACLK_PCLK_41    (2 << 10)
 311 #define ACLK_PCLK_81    (3 << 10)
 312 #define ACLK_PCLK_MASK  (3 << 10)
 313
 314 #define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 315 { \
 316         .rate           = _mhz * MHZ, \
 317         .apll_con       = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 318         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 319 }
 320
 321 static const struct arm_pll_set arm_pll[] = {
 322         // rate = 24 * NF / (NR * NO)
 323         //      rate NR  NF NO adiv hdiv pdiv
 324         ARM_PLL(1200, 1, 50, 1, 41, 21, 81),
 325         ARM_PLL(1104, 1, 46, 1, 41, 21, 81),
 326         ARM_PLL(1008, 1, 42, 1, 41, 21, 81),
 327         ARM_PLL( 912, 1, 38, 1, 31, 21, 81),
 328         ARM_PLL( 888, 2, 74, 1, 31, 21, 81),
 329         ARM_PLL( 816, 1, 34, 1, 31, 21, 81),
 330         ARM_PLL( 696, 1, 58, 2, 31, 21, 81),
 331         ARM_PLL( 624, 1, 52, 2, 31, 21, 81),
 332         ARM_PLL( 600, 1, 50, 2, 21, 21, 81),
 333         ARM_PLL( 504, 1, 42, 2, 21, 21, 81),
 334         ARM_PLL( 408, 1, 34, 2, 21, 21, 81),
 335         ARM_PLL( 300, 1, 50, 4, 21, 21, 41),
 336         ARM_PLL( 204, 1, 34, 4, 21, 21, 41),
 337         ARM_PLL( 102, 1, 34, 8, 21, 21, 41),
 338         // last item, pll power down.
 339         ARM_PLL(  24, 1, 64, 8, 21, 21, 41),
 340 };
 341
 342 #define CORE_PARENT_MASK        (3 << 23)
 343 #define CORE_PARENT_ARM_PLL     (0 << 23)
 344 #define CORE_PARENT_GENERAL_PLL (1 << 23)
 345
 346 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 347 {
 348         const struct arm_pll_set *ps, *pt;
 349
 350         /* find the arm_pll we want. */
 351         ps = pt = &arm_pll[0];
 352         while (1) {
 353                 if (pt->rate == rate) {
 354                         ps = pt;
 355                         break;
 356                 }
 357                 // we are sorted, and ps->rate > pt->rate.
 358                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 359                         ps = pt;
 360                 if (pt->rate < rate || pt->rate == 24 * MHZ)
 361                         break;
 362                 pt++;
 363         }
 364
 365         /* make aclk safe & reparent to general pll */
 366         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_GENERAL_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 367
 368         /* enter slow mode */
 369         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 370
 371         /* power down */
 372         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 373
 374         delay_500ns();
 375
 376         cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
 377
 378         delay_500ns();
 379
 380         /* power up */
 381         cru_writel(ps->apll_con, CRU_APLL_CON);
 382
 383         delay_300us();
 384         pll_wait_lock(ARM_PLL_IDX);
 385
 386         /* reparent to arm pll & set aclk/hclk/pclk */
 387         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | ps->clksel0_con, CRU_CLKSEL0_CON);
 388
 389         /* enter normal mode */
 390         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 391
 392         return 0;
 393 }
 394
 395 static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
 396
 397 static struct clk arm_pll_clk = {
 398         .name           = "arm_pll",
 399         .parent         = &xin24m,
 400         .recalc         = arm_pll_clk_recalc,
 401         .set_rate       = arm_pll_clk_set_rate,
 402         .clksel_con     = CRU_MODE_CON,
 403         .clksel_parent_mask     = 1,
 404         .clksel_parent_shift    = 8,
 405         .parents        = arm_pll_parents,
 406 };
 407
 408 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 409 {
 410         unsigned long rate;
 411
 412         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 413                 u32 v = cru_readl(CRU_DPLL_CON);
 414                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 415                 do_div(rate64, PLL_NR(v));
 416                 rate = rate64 >> PLL_NO_SHIFT(v);
 417                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 418         } else {
 419                 rate = clk->parent->rate;
 420                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 421         }
 422
 423         return rate;
 424 }
 425
 426 static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &general_pll_clk };
 427
 428 static struct clk ddr_pll_clk = {
 429         .name           = "ddr_pll",
 430         .parent         = &xin24m,
 431         .recalc         = ddr_pll_clk_recalc,
 432         .clksel_con     = CRU_MODE_CON,
 433         .clksel_parent_mask     = 3,
 434         .clksel_parent_shift    = 13,
 435         .parents        = ddr_pll_parents,
 436 };
 437
 438
 439 static int codec_pll_clk_mode(struct clk *clk, int on)
 440 {
 441         u32 cpll = cru_readl(CRU_CPLL_CON);
 442         if (on) {
 443                 cru_writel(cpll & ~(PLL_PD | PLL_BYPASS), CRU_CPLL_CON);
 444                 delay_300us();
 445                 pll_wait_lock(CODEC_PLL_IDX);
 446                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
 447         } else {
 448                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 449                 cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 450                 cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 451                 delay_500ns();
 452         }
 453         return 0;
 454 }
 455
 456 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 457 {
 458         unsigned long rate;
 459         u32 v = cru_readl(CRU_CPLL_CON);
 460         u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 461         do_div(rate64, PLL_NR(v));
 462         rate = rate64 >> PLL_NO_SHIFT(v);
 463         pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 464         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) != CRU_CODEC_MODE_NORMAL)
 465                 pr_debug("%s rate is %ld (slow mode) actually\n", clk->name, clk->parent->rate);
 466         return rate;
 467 }
 468
 469 #define CODEC_PLL_PARENT_MASK   (3 << 11)
 470 #define CODEC_PLL_PARENT_XIN24M (0 << 11)
 471 #define CODEC_PLL_PARENT_XIN27M (1 << 11)
 472 #define CODEC_PLL_PARENT_DDR_PLL        (2 << 11)
 473 #define CODEC_PLL_PARENT_GENERAL_PLL    (3 << 11)
 474
 475 struct codec_pll_set {
 476         unsigned long rate;
 477         u32 pll_con;
 478         u32 parent_con;
 479 };
 480
 481 #define CODEC_PLL(_mhz, _parent, band, nr, nf, no) \
 482 { \
 483         .rate           = _mhz * MHZ, \
 484         .pll_con        = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
 485         .parent_con     = CODEC_PLL_PARENT_XIN##_parent##M, \
 486 }
 487
 488 static const struct codec_pll_set codec_pll[] = {
 489         //      rate parent band NR NF NO
 490         CODEC_PLL(108, 24,  LOW, 1, 18, 4),     // for TV
 491         CODEC_PLL(648, 24, HIGH, 1, 27, 1),
 492         CODEC_PLL(297, 27,  LOW, 1, 22, 2),     // for HDMI
 493         CODEC_PLL(594, 27,  LOW, 1, 22, 1),
 494         CODEC_PLL(360, 24,  LOW, 1, 15, 1),     // for GPU
 495         CODEC_PLL(408, 24,  LOW, 1, 17, 1),
 496         CODEC_PLL(456, 24,  LOW, 1, 19, 1),
 497         CODEC_PLL(504, 24,  LOW, 1, 21, 1),
 498         CODEC_PLL(552, 24,  LOW, 1, 23, 1),
 499         CODEC_PLL(600, 24, HIGH, 1, 25, 1),
 500 };
 501
 502 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 503 {
 504         int i;
 505         u32 work_mode;
 506
 507         const struct codec_pll_set *ps = NULL;
 508
 509         for (i = 0; i < ARRAY_SIZE(codec_pll); i++) {
 510                 if (codec_pll[i].rate == rate) {
 511                         ps = &codec_pll[i];
 512                         break;
 513                 }
 514         }
 515         if (!ps)
 516                 return  -ENOENT;
 517
 518         work_mode = cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK;
 519
 520         /* enter slow mode */
 521         cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | ps->parent_con, CRU_MODE_CON);
 522
 523         /* power down */
 524         cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
 525
 526         delay_500ns();
 527
 528         cru_writel(ps->pll_con | PLL_PD, CRU_CPLL_CON);
 529
 530         delay_500ns();
 531
 532         /* power up */
 533         cru_writel(ps->pll_con, CRU_CPLL_CON);
 534
 535         delay_300us();
 536         pll_wait_lock(CODEC_PLL_IDX);
 537
 538         /* enter normal mode */
 539         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | work_mode, CRU_MODE_CON);
 540
 541         clk_set_parent_nolock(clk, ps->parent_con == CODEC_PLL_PARENT_XIN24M ? &xin24m : &xin27m);
 542
 543         return 0;
 544 }
 545
 546 static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &general_pll_clk };
 547
 548 static struct clk codec_pll_clk = {
 549         .name           = "codec_pll",
 550         .parent         = &xin24m,
 551         .mode           = codec_pll_clk_mode,
 552         .recalc         = codec_pll_clk_recalc,
 553         .set_rate       = codec_pll_clk_set_rate,
 554         .clksel_con     = CRU_MODE_CON,
 555         .clksel_parent_mask     = 3,
 556         .clksel_parent_shift    = 11,
 557         .parents        = codec_pll_parents,
 558 };
 559
 560
 561 static unsigned long general_pll_clk_recalc(struct clk *clk)
 562 {
 563         unsigned long rate;
 564
 565         if ((cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) == CRU_GENERAL_MODE_NORMAL) {
 566                 u32 v = cru_readl(CRU_GPLL_CON);
 567                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 568                 do_div(rate64, PLL_NR(v));
 569                 rate = rate64 >> PLL_NO_SHIFT(v);
 570                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 571         } else {
 572                 rate = clk->parent->rate;
 573                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 574         }
 575
 576         return rate;
 577 }
 578
 579 static int general_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 580 {
 581         u32 pll_con;
 582
 583         switch (rate) {
 584         case 288 * MHZ:
 585                 /* 288M: low-band, NR=1, NF=24, NO=2 */
 586                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_2;
 587                 break;
 588         case 624 * MHZ:
 589                 /* 624M: high-band, NR=1, NF=26, NO=1 */
 590                 pll_con = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 591                 break;
 592         default:
 593                 return -ENOENT;
 594                 break;
 595         }
 596
 597         /* enter slow mode */
 598         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 599
 600         /* power down */
 601         cru_writel(cru_readl(CRU_GPLL_CON) | PLL_PD, CRU_GPLL_CON);
 602
 603         delay_500ns();
 604
 605         cru_writel(pll_con | PLL_PD, CRU_GPLL_CON);
 606
 607         delay_500ns();
 608
 609         /* power up */
 610         cru_writel(pll_con, CRU_GPLL_CON);
 611
 612         delay_300us();
 613         pll_wait_lock(GENERAL_PLL_IDX);
 614
 615         /* enter normal mode */
 616         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_NORMAL, CRU_MODE_CON);
 617
 618         return 0;
 619 }
 620
 621 static struct clk *general_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
 622
 623 static struct clk general_pll_clk = {
 624         .name           = "general_pll",
 625         .parent         = &xin24m,
 626         .recalc         = general_pll_clk_recalc,
 627         .set_rate       = general_pll_clk_set_rate,
 628         .clksel_con     = CRU_MODE_CON,
 629         .clksel_parent_mask     = 3,
 630         .clksel_parent_shift    = 9,
 631         .parents        = general_pll_parents,
 632 };
 633
 634
 635 static struct clk *clk_core_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 636
 637 static struct clk clk_core = {
 638         .name           = "core",
 639         .parent         = &arm_pll_clk,
 640         .recalc         = clksel_recalc_div,
 641         .clksel_con     = CRU_CLKSEL0_CON,
 642         .clksel_mask    = 0x1F,
 643         .clksel_shift   = 0,
 644         .clksel_parent_mask     = 3,
 645         .clksel_parent_shift    = 23,
 646         .parents        = clk_core_parents,
 647 };
 648
 649 static unsigned long aclk_cpu_recalc(struct clk *clk)
 650 {
 651         unsigned long rate;
 652         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 653
 654         BUG_ON(div > 5);
 655         if (div >= 5)
 656                 div = 8;
 657         rate = clk->parent->rate / div;
 658         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 659
 660         return rate;
 661 }
 662
 663 static struct clk aclk_cpu = {
 664         .name           = "aclk_cpu",
 665         .parent         = &clk_core,
 666         .recalc         = aclk_cpu_recalc,
 667 };
 668
 669 static struct clk hclk_cpu = {
 670         .name           = "hclk_cpu",
 671         .parent         = &aclk_cpu,
 672         .recalc         = clksel_recalc_shift,
 673         .set_rate       = clksel_set_rate_shift,
 674         .clksel_con     = CRU_CLKSEL0_CON,
 675         .clksel_mask    = 3,
 676         .clksel_shift   = 8,
 677         .clksel_maxdiv  = 4,
 678 };
 679
 680 static struct clk pclk_cpu = {
 681         .name           = "pclk_cpu",
 682         .parent         = &aclk_cpu,
 683         .recalc         = clksel_recalc_shift,
 684         .set_rate       = clksel_set_rate_shift,
 685         .clksel_con     = CRU_CLKSEL0_CON,
 686         .clksel_mask    = 3,
 687         .clksel_shift   = 10,
 688         .clksel_maxdiv  = 8,
 689 };
 690
 691 static struct clk *aclk_periph_parents[4] = { &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
 692
 693 static struct clk aclk_periph = {
 694         .name           = "aclk_periph",
 695         .mode           = gate_mode,
 696         .gate_idx       = CLK_GATE_ACLK_PEIRPH,
 697         .recalc         = clksel_recalc_div,
 698         .set_rate       = clksel_set_rate_div,
 699         .clksel_con     = CRU_CLKSEL0_CON,
 700         .clksel_mask    = 0x1F,
 701         .clksel_shift   = 14,
 702         .clksel_parent_mask     = 3,
 703         .clksel_parent_shift    = 12,
 704         .parents        = aclk_periph_parents,
 705 };
 706
 707 static struct clk pclk_periph = {
 708         .name           = "pclk_periph",
 709         .mode           = gate_mode,
 710         .gate_idx       = CLK_GATE_PCLK_PEIRPH,
 711         .parent         = &aclk_periph,
 712         .recalc         = clksel_recalc_shift,
 713         .set_rate       = clksel_set_rate_shift,
 714         .clksel_con     = CRU_CLKSEL0_CON,
 715         .clksel_mask    = 3,
 716         .clksel_shift   = 19,
 717         .clksel_maxdiv  = 8,
 718 };
 719
 720 static struct clk hclk_periph = {
 721         .name           = "hclk_periph",
 722         .mode           = gate_mode,
 723         .gate_idx       = CLK_GATE_HCLK_PEIRPH,
 724         .parent         = &aclk_periph,
 725         .recalc         = clksel_recalc_shift,
 726         .set_rate       = clksel_set_rate_shift,
 727         .clksel_con     = CRU_CLKSEL0_CON,
 728         .clksel_mask    = 3,
 729         .clksel_shift   = 21,
 730         .clksel_maxdiv  = 4,
 731 };
 732
 733
 734 static struct clk *clk_uhost_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 735
 736 static struct clk clk_uhost = {
 737         .name           = "uhost",
 738         .mode           = gate_mode,
 739         .recalc         = clksel_recalc_div,
 740         .set_rate       = clksel_set_rate_div,
 741         .gate_idx       = CLK_GATE_UHOST,
 742         .clksel_con     = CRU_CLKSEL1_CON,
 743         .clksel_mask    = 0x1F,
 744         .clksel_shift   = 16,
 745         .clksel_parent_mask     = 7,
 746         .clksel_parent_shift    = 13,
 747         .parents        = clk_uhost_parents,
 748 };
 749
 750 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 751
 752 static struct clk clk_otgphy0 = {
 753         .name           = "otgphy0",
 754         .mode           = gate_mode,
 755         .gate_idx       = CLK_GATE_USBPHY0,
 756         .clksel_con     = CRU_CLKSEL1_CON,
 757         .clksel_parent_mask     = 3,
 758         .clksel_parent_shift    = 9,
 759         .parents        = clk_otgphy_parents,
 760 };
 761
 762 static struct clk clk_otgphy1 = {
 763         .name           = "otgphy1",
 764         .mode           = gate_mode,
 765         .gate_idx       = CLK_GATE_USBPHY1,
 766         .clksel_con     = CRU_CLKSEL1_CON,
 767         .clksel_parent_mask     = 3,
 768         .clksel_parent_shift    = 11,
 769         .parents        = clk_otgphy_parents,
 770 };
 771
 772
 773 static struct clk rmii_clkin = {
 774         .name           = "rmii_clkin",
 775 };
 776
 777 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 778
 779 static struct clk clk_mac_ref_div = {
 780         .name           = "mac_ref_div",
 781         .recalc         = clksel_recalc_div,
 782         .set_rate       = clksel_set_rate_div,
 783         .clksel_con     = CRU_CLKSEL1_CON,
 784         .clksel_mask    = 0x1F,
 785         .clksel_shift   = 23,
 786         .clksel_parent_mask     = 3,
 787         .clksel_parent_shift    = 21,
 788         .parents        = clk_mac_ref_div_parents,
 789 };
 790
 791 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 792
 793 static struct clk clk_mac_ref = {
 794         .name           = "mac_ref",
 795         .mode           = gate_mode,
 796         .gate_idx       = CLK_GATE_MAC_REF,
 797         .clksel_con     = CRU_CLKSEL1_CON,
 798         .clksel_parent_mask     = 1,
 799         .clksel_parent_shift    = 28,
 800         .parents        = clk_mac_ref_parents,
 801 };
 802
 803
 804 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 805
 806 static struct clk clk_i2s0_div = {
 807         .name           = "i2s0_div",
 808         .recalc         = clksel_recalc_div,
 809         .set_rate       = clksel_set_rate_div,
 810         .clksel_con     = CRU_CLKSEL2_CON,
 811         .clksel_mask    = 0x1F,
 812         .clksel_shift   = 3,
 813         .clksel_parent_mask     = 7,
 814         .clksel_parent_shift    = 0,
 815         .parents        = clk_i2s_div_parents,
 816 };
 817
 818 static struct clk clk_i2s1_div = {
 819         .name           = "i2s1_div",
 820         .recalc         = clksel_recalc_div,
 821         .set_rate       = clksel_set_rate_div,
 822         .clksel_con     = CRU_CLKSEL2_CON,
 823         .clksel_mask    = 0x1F,
 824         .clksel_shift   = 13,
 825         .clksel_parent_mask     = 7,
 826         .clksel_parent_shift    = 10,
 827         .parents        = clk_i2s_div_parents,
 828 };
 829
 830 static struct clk clk_spdif_div = {
 831         .name           = "spdif_div",
 832         .recalc         = clksel_recalc_div,
 833         .set_rate       = clksel_set_rate_div,
 834         .clksel_con     = CRU_CLKSEL2_CON,
 835         .clksel_mask    = 0x1F,
 836         .clksel_shift   = 23,
 837         .clksel_parent_mask     = 7,
 838         .clksel_parent_shift    = 20,
 839         .parents        = clk_i2s_div_parents,
 840 };
 841
 842 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 843 {
 844         u16 numerator, denominator;
 845
 846         switch (rate) {
 847         case 8192000:   /* 288*32/1125 */
 848                 numerator = 32;
 849                 denominator = 1125;
 850                 break;
 851         case 11289600:  /* 288*49/1250 */
 852                 numerator = 49;
 853                 denominator = 1250;
 854                 break;
 855         case 12288000:  /* 288*16/375 */
 856                 numerator = 16;
 857                 denominator = 375;
 858                 break;
 859         default:
 860                 return -ENOENT;
 861         }
 862
 863         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 864         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
 865
 866         return 0;
 867 }
 868
 869 static struct clk clk_i2s0_frac_div = {
 870         .name           = "i2s0_frac_div",
 871         .parent         = &clk_i2s0_div,
 872         .recalc         = clksel_recalc_frac,
 873         .set_rate       = clk_i2s_frac_div_set_rate,
 874         .clksel_con     = CRU_CLKSEL3_CON,
 875 };
 876
 877 static struct clk clk_i2s1_frac_div = {
 878         .name           = "i2s1_frac_div",
 879         .parent         = &clk_i2s1_div,
 880         .recalc         = clksel_recalc_frac,
 881         .set_rate       = clk_i2s_frac_div_set_rate,
 882         .clksel_con     = CRU_CLKSEL4_CON,
 883 };
 884
 885 static struct clk clk_spdif_frac_div = {
 886         .name           = "spdif_frac_div",
 887         .parent         = &clk_spdif_div,
 888         .recalc         = clksel_recalc_frac,
 889         .set_rate       = clk_i2s_frac_div_set_rate,
 890         .clksel_con     = CRU_CLKSEL5_CON,
 891 };
 892
 893 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 894 {
 895         int ret;
 896         struct clk *parent;
 897
 898         if (rate == 12 * MHZ) {
 899                 parent = &clk_12m;
 900         } else {
 901                 parent = clk->parents[1]; /* frac div */
 902                 ret = clk_set_rate_nolock(parent, rate);
 903                 if (ret)
 904                         return ret;
 905         }
 906         if (clk->parent != parent)
 907                 clk_set_parent_nolock(clk, parent);
 908
 909         return ret;
 910 }
 911
 912 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
 913
 914 static struct clk clk_i2s0 = {
 915         .name           = "i2s0",
 916         .mode           = gate_mode,
 917         .gate_idx       = CLK_GATE_I2S0,
 918         .set_rate       = i2s_set_rate,
 919         .clksel_con     = CRU_CLKSEL2_CON,
 920         .clksel_parent_mask     = 3,
 921         .clksel_parent_shift    = 8,
 922         .parents        = clk_i2s0_parents,
 923 };
 924
 925 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
 926
 927 static struct clk clk_i2s1 = {
 928         .name           = "i2s1",
 929         .mode           = gate_mode,
 930         .gate_idx       = CLK_GATE_I2S1,
 931         .set_rate       = i2s_set_rate,
 932         .clksel_con     = CRU_CLKSEL2_CON,
 933         .clksel_parent_mask     = 3,
 934         .clksel_parent_shift    = 18,
 935         .parents        = clk_i2s1_parents,
 936 };
 937
 938 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
 939
 940 static struct clk clk_spdif = {
 941         .name           = "spdif",
 942         .mode           = gate_mode,
 943         .gate_idx       = CLK_GATE_SPDIF,
 944         .set_rate       = i2s_set_rate,
 945         .clksel_con     = CRU_CLKSEL2_CON,
 946         .clksel_parent_mask     = 3,
 947         .clksel_parent_shift    = 28,
 948         .parents        = clk_spdif_parents,
 949 };
 950
 951
 952 static struct clk *clk_spi_src_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
 953
 954 static struct clk clk_spi_src = {
 955         .name           = "spi_src",
 956         .clksel_con     = CRU_CLKSEL6_CON,
 957         .clksel_parent_mask     = 3,
 958         .clksel_parent_shift    = 0,
 959         .parents        = clk_spi_src_parents,
 960 };
 961
 962 static struct clk clk_spi0 = {
 963         .name           = "spi0",
 964         .parent         = &clk_spi_src,
 965         .mode           = gate_mode,
 966         .recalc         = clksel_recalc_div,
 967         .set_rate       = clksel_set_rate_div,
 968         .gate_idx       = CLK_GATE_SPI0,
 969         .clksel_con     = CRU_CLKSEL6_CON,
 970         .clksel_mask    = 0x7F,
 971         .clksel_shift   = 2,
 972 };
 973
 974 static struct clk clk_spi1 = {
 975         .name           = "spi1",
 976         .parent         = &clk_spi_src,
 977         .mode           = gate_mode,
 978         .recalc         = clksel_recalc_div,
 979         .set_rate       = clksel_set_rate_div,
 980         .gate_idx       = CLK_GATE_SPI1,
 981         .clksel_con     = CRU_CLKSEL6_CON,
 982         .clksel_mask    = 0x7F,
 983         .clksel_shift   = 11,
 984 };
 985
 986
 987 static struct clk clk_saradc = {
 988         .name           = "saradc",
 989         .parent         = &pclk_periph,
 990         .mode           = gate_mode,
 991         .recalc         = clksel_recalc_div,
 992         .set_rate       = clksel_set_rate_div,
 993         .gate_idx       = CLK_GATE_SARADC,
 994         .clksel_con     = CRU_CLKSEL6_CON,
 995         .clksel_mask    = 0xFF,
 996         .clksel_shift   = 18,
 997 };
 998
 999
1000 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
1001
1002 static struct clk clk_timer0 = {
1003         .name           = "timer0",
1004         .mode           = gate_mode,
1005         .gate_idx       = CLK_GATE_TIMER0,
1006         .clksel_con     = CRU_CLKSEL6_CON,
1007         .clksel_parent_mask     = 1,
1008         .clksel_parent_shift    = 26,
1009         .parents        = clk_cpu_timer_parents,
1010 };
1011
1012 static struct clk clk_timer1 = {
1013         .name           = "timer1",
1014         .mode           = gate_mode,
1015         .gate_idx       = CLK_GATE_TIMER1,
1016         .clksel_con     = CRU_CLKSEL6_CON,
1017         .clksel_parent_mask     = 1,
1018         .clksel_parent_shift    = 27,
1019         .parents        = clk_cpu_timer_parents,
1020 };
1021
1022 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
1023
1024 static struct clk clk_timer2 = {
1025         .name           = "timer2",
1026         .mode           = gate_mode,
1027         .gate_idx       = CLK_GATE_TIMER2,
1028         .clksel_con     = CRU_CLKSEL6_CON,
1029         .clksel_parent_mask     = 1,
1030         .clksel_parent_shift    = 28,
1031         .parents        = clk_periph_timer_parents,
1032 };
1033
1034 static struct clk clk_timer3 = {
1035         .name           = "timer3",
1036         .mode           = gate_mode,
1037         .gate_idx       = CLK_GATE_TIMER3,
1038         .clksel_con     = CRU_CLKSEL6_CON,
1039         .clksel_parent_mask     = 1,
1040         .clksel_parent_shift    = 29,
1041         .parents        = clk_periph_timer_parents,
1042 };
1043
1044
1045 static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1046
1047 static struct clk clk_mmc_src = {
1048         .name           = "mmc_src",
1049         .clksel_con     = CRU_CLKSEL7_CON,
1050         .clksel_parent_mask     = 3,
1051         .clksel_parent_shift    = 0,
1052         .parents        = clk_mmc_src_parents,
1053 };
1054
1055 static struct clk clk_mmc0 = {
1056         .name           = "mmc0",
1057         .parent         = &clk_mmc_src,
1058         .mode           = gate_mode,
1059         .recalc         = clksel_recalc_div,
1060         .set_rate       = clksel_set_rate_div,
1061         .gate_idx       = CLK_GATE_MMC0,
1062         .clksel_con     = CRU_CLKSEL7_CON,
1063         .clksel_mask    = 0x3F,
1064         .clksel_shift   = 2,
1065 };
1066
1067 static struct clk clk_mmc1 = {
1068         .name           = "mmc1",
1069         .parent         = &clk_mmc_src,
1070         .mode           = gate_mode,
1071         .recalc         = clksel_recalc_div,
1072         .set_rate       = clksel_set_rate_div,
1073         .gate_idx       = CLK_GATE_MMC1,
1074         .clksel_con     = CRU_CLKSEL7_CON,
1075         .clksel_mask    = 0x3F,
1076         .clksel_shift   = 10,
1077 };
1078
1079 static struct clk clk_emmc = {
1080         .name           = "emmc",
1081         .parent         = &clk_mmc_src,
1082         .mode           = gate_mode,
1083         .recalc         = clksel_recalc_div,
1084         .set_rate       = clksel_set_rate_div,
1085         .gate_idx       = CLK_GATE_EMMC,
1086         .clksel_con     = CRU_CLKSEL7_CON,
1087         .clksel_mask    = 0x3F,
1088         .clksel_shift   = 18,
1089 };
1090
1091
1092 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &general_pll_clk, &codec_pll_clk, &arm_pll_clk };
1093
1094 static struct clk clk_ddr = {
1095         .name           = "ddr",
1096         .recalc         = clksel_recalc_shift,
1097         .clksel_con     = CRU_CLKSEL7_CON,
1098         .clksel_mask    = 7,
1099         .clksel_shift   = 26,
1100         .clksel_maxdiv  = 32,
1101         .clksel_parent_mask     = 3,
1102         .clksel_parent_shift    = 24,
1103         .parents        = clk_ddr_parents,
1104 };
1105
1106
1107 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1108 {
1109         int ret;
1110         struct clk *parent;
1111         struct clk *clk_div = clk->parents[0];
1112
1113         switch (rate) {
1114         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
1115                 parent = clk->parents[2]; /* xin24m */
1116                 break;
1117         case 19200*16:
1118         case 38400*16:
1119         case 57600*16:
1120         case 115200*16:
1121         case 230400*16:
1122         case 460800*16:
1123         case 576000*16:
1124                 parent = clk->parents[1]; /* frac div */
1125                 /* reset div to 1 */
1126                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1127                 if (ret)
1128                         return ret;
1129                 break;
1130         default:
1131                 parent = clk_div;
1132                 break;
1133         }
1134
1135         if (parent->set_rate) {
1136                 ret = clk_set_rate_nolock(parent, rate);
1137                 if (ret)
1138                         return ret;
1139         }
1140
1141         if (clk->parent != parent)
1142                 clk_set_parent_nolock(clk, parent);
1143
1144         return 0;
1145 }
1146
1147 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1148 {
1149         u16 numerator, denominator;
1150
1151         switch (rate) {
1152         case 19200*16:  /* 288*2/1875 */
1153                 numerator = 2;
1154                 denominator = 1875;
1155                 break;
1156         case 38400*16:  /* 288*4/1875 */
1157                 numerator = 4;
1158                 denominator = 1875;
1159                 break;
1160         case 57600*16:  /* 288*2/625 */
1161                 numerator = 2;
1162                 denominator = 625;
1163                 break;
1164         case 115200*16: /* 288*8/1250 */
1165                 numerator = 8;
1166                 denominator = 1250;
1167                 break;
1168         case 230400*16: /* 288*8/625 */
1169                 numerator = 8;
1170                 denominator = 625;
1171                 break;
1172         case 460800*16: /* 288*16/25 */
1173                 numerator = 16;
1174                 denominator = 625;
1175                 break;
1176         case 576000*16: /* 288*20/625 */
1177                 numerator = 20;
1178                 denominator = 625;
1179                 break;
1180         default:
1181                 return -ENOENT;
1182         }
1183
1184         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1185         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
1186
1187         return 0;
1188 }
1189 static struct clk *clk_uart_src_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1190
1191 static struct clk clk_uart01_src = {
1192         .name           = "uart01_src",
1193         .clksel_con     = CRU_CLKSEL8_CON,
1194         .clksel_parent_mask     = 7,
1195         .clksel_parent_shift    = 0,
1196         .parents        = clk_uart_src_parents,
1197 };
1198
1199 static struct clk clk_uart0_div = {
1200         .name           = "uart0_div",
1201         .parent         = &clk_uart01_src,
1202         .recalc         = clksel_recalc_div,
1203         .set_rate       = clksel_set_rate_div,
1204         .clksel_con     = CRU_CLKSEL8_CON,
1205         .clksel_mask    = 0x3F,
1206         .clksel_shift   = 3,
1207 };
1208
1209 static struct clk clk_uart0_frac_div = {
1210         .name           = "uart0_frac_div",
1211         .parent         = &clk_uart0_div,
1212         .recalc         = clksel_recalc_frac,
1213         .set_rate       = clk_uart_frac_div_set_rate,
1214         .clksel_con     = CRU_CLKSEL10_CON,
1215 };
1216
1217 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1218
1219 static struct clk clk_uart0 = {
1220         .name           = "uart0",
1221         .mode           = gate_mode,
1222         .set_rate       = clk_uart_set_rate,
1223         .gate_idx       = CLK_GATE_UART0,
1224         .clksel_con     = CRU_CLKSEL8_CON,
1225         .clksel_parent_mask     = 3,
1226         .clksel_parent_shift    = 9,
1227         .parents        = clk_uart0_parents,
1228 };
1229
1230 static struct clk clk_uart1_div = {
1231         .name           = "uart1_div",
1232         .parent         = &clk_uart01_src,
1233         .recalc         = clksel_recalc_div,
1234         .set_rate       = clksel_set_rate_div,
1235         .clksel_con     = CRU_CLKSEL8_CON,
1236         .clksel_mask    = 0x3F,
1237         .clksel_shift   = 14,
1238 };
1239
1240 static struct clk clk_uart1_frac_div = {
1241         .name           = "uart1_frac_div",
1242         .parent         = &clk_uart1_div,
1243         .recalc         = clksel_recalc_frac,
1244         .set_rate       = clk_uart_frac_div_set_rate,
1245         .clksel_con     = CRU_CLKSEL11_CON,
1246 };
1247
1248 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1249
1250 static struct clk clk_uart1 = {
1251         .name           = "uart1",
1252         .mode           = gate_mode,
1253         .set_rate       = clk_uart_set_rate,
1254         .gate_idx       = CLK_GATE_UART1,
1255         .clksel_con     = CRU_CLKSEL8_CON,
1256         .clksel_parent_mask     = 3,
1257         .clksel_parent_shift    = 20,
1258         .parents        = clk_uart1_parents,
1259 };
1260
1261 static struct clk clk_uart23_src = {
1262         .name           = "uart23_src",
1263         .clksel_con     = CRU_CLKSEL9_CON,
1264         .clksel_parent_mask     = 7,
1265         .clksel_parent_shift    = 0,
1266         .parents        = clk_uart_src_parents,
1267 };
1268
1269 static struct clk clk_uart2_div = {
1270         .name           = "uart2_div",
1271         .parent         = &clk_uart23_src,
1272         .recalc         = clksel_recalc_div,
1273         .set_rate       = clksel_set_rate_div,
1274         .clksel_con     = CRU_CLKSEL9_CON,
1275         .clksel_mask    = 0x3F,
1276         .clksel_shift   = 3,
1277 };
1278
1279 static struct clk clk_uart2_frac_div = {
1280         .name           = "uart2_frac_div",
1281         .parent         = &clk_uart2_div,
1282         .recalc         = clksel_recalc_frac,
1283         .set_rate       = clk_uart_frac_div_set_rate,
1284         .clksel_con     = CRU_CLKSEL12_CON,
1285 };
1286
1287 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1288
1289 static struct clk clk_uart2 = {
1290         .name           = "uart2",
1291         .mode           = gate_mode,
1292         .set_rate       = clk_uart_set_rate,
1293         .gate_idx       = CLK_GATE_UART2,
1294         .clksel_con     = CRU_CLKSEL9_CON,
1295         .clksel_parent_mask     = 3,
1296         .clksel_parent_shift    = 9,
1297         .parents        = clk_uart2_parents,
1298 };
1299
1300 static struct clk clk_uart3_div = {
1301         .name           = "uart3_div",
1302         .parent         = &clk_uart23_src,
1303         .recalc         = clksel_recalc_div,
1304         .set_rate       = clksel_set_rate_div,
1305         .clksel_con     = CRU_CLKSEL9_CON,
1306         .clksel_mask    = 0x3F,
1307         .clksel_shift   = 14,
1308 };
1309
1310 static struct clk clk_uart3_frac_div = {
1311         .name           = "uart3_frac_div",
1312         .parent         = &clk_uart3_div,
1313         .recalc         = clksel_recalc_frac,
1314         .set_rate       = clk_uart_frac_div_set_rate,
1315         .clksel_con     = CRU_CLKSEL13_CON,
1316 };
1317
1318 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1319
1320 static struct clk clk_uart3 = {
1321         .name           = "uart3",
1322         .mode           = gate_mode,
1323         .set_rate       = clk_uart_set_rate,
1324         .gate_idx       = CLK_GATE_UART3,
1325         .clksel_con     = CRU_CLKSEL9_CON,
1326         .clksel_parent_mask     = 3,
1327         .clksel_parent_shift    = 20,
1328         .parents        = clk_uart3_parents,
1329 };
1330
1331
1332 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1333
1334 static struct clk clk_hsadc_div = {
1335         .name           = "hsadc_div",
1336         .recalc         = clksel_recalc_div,
1337         .set_rate       = clksel_set_rate_div,
1338         .clksel_con     = CRU_CLKSEL14_CON,
1339         .clksel_mask    = 0xFF,
1340         .clksel_shift   = 10,
1341         .clksel_parent_mask     = 7,
1342         .clksel_parent_shift    = 7,
1343         .parents        = clk_hsadc_div_parents,
1344 };
1345
1346 static struct clk clk_hsadc_frac_div = {
1347         .name           = "hsadc_frac_div",
1348         .parent         = &clk_hsadc_div,
1349         .recalc         = clksel_recalc_frac,
1350         .clksel_con     = CRU_CLKSEL15_CON,
1351 };
1352
1353 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
1354
1355 static struct clk clk_demod = {
1356         .name           = "demod",
1357         .clksel_con     = CRU_CLKSEL14_CON,
1358         .clksel_parent_mask     = 3,
1359         .clksel_parent_shift    = 18,
1360         .parents        = clk_demod_parents,
1361 };
1362
1363 static struct clk gpsclk = {
1364         .name           = "gpsclk",
1365 };
1366
1367 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1368
1369 static struct clk clk_hsadc = {
1370         .name           = "hsadc",
1371         .mode           = gate_mode,
1372         .gate_idx       = CLK_GATE_HSADC,
1373         .clksel_con     = CRU_CLKSEL14_CON,
1374         .clksel_parent_mask     = 1,
1375         .clksel_parent_shift    = 21,
1376         .parents        = clk_hsadc_parents,
1377 };
1378
1379 static unsigned long div2_recalc(struct clk *clk)
1380 {
1381         return clk->parent->rate >> 1;
1382 }
1383
1384 static struct clk clk_hsadc_div2 = {
1385         .name           = "hsadc_div2",
1386         .parent         = &clk_demod,
1387         .recalc         = div2_recalc,
1388 };
1389
1390 static struct clk clk_hsadc_div2_inv = {
1391         .name           = "hsadc_div2_inv",
1392         .parent         = &clk_demod,
1393         .recalc         = div2_recalc,
1394 };
1395
1396 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1397
1398 static struct clk clk_hsadc_out = {
1399         .name           = "hsadc_out",
1400         .clksel_con     = CRU_CLKSEL14_CON,
1401         .clksel_parent_mask     = 1,
1402         .clksel_parent_shift    = 20,
1403         .parents        = clk_hsadc_out_parents,
1404 };
1405
1406
1407 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
1408
1409 static struct clk dclk_lcdc_div = {
1410         .name           = "dclk_lcdc_div",
1411         .recalc         = clksel_recalc_div,
1412         .set_rate       = clksel_set_rate_div,
1413         .clksel_con     = CRU_CLKSEL16_CON,
1414         .clksel_mask    = 0xFF,
1415         .clksel_shift   = 2,
1416         .clksel_parent_mask     = 3,
1417         .clksel_parent_shift    = 0,
1418         .parents        = dclk_lcdc_div_parents,
1419 };
1420
1421 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
1422
1423 static struct clk dclk_lcdc = {
1424         .name           = "dclk_lcdc",
1425         .mode           = gate_mode,
1426         .gate_idx       = CLK_GATE_DCLK_LCDC,
1427         .clksel_con     = CRU_CLKSEL16_CON,
1428         .clksel_parent_mask     = 1,
1429         .clksel_parent_shift    = 10,
1430         .parents        = dclk_lcdc_parents,
1431 };
1432
1433 static struct clk dclk_ebook = {
1434         .name           = "dclk_ebook",
1435         .mode           = gate_mode,
1436         .gate_idx       = CLK_GATE_DCLK_EBOOK,
1437         .recalc         = clksel_recalc_div,
1438         .set_rate       = clksel_set_rate_div,
1439         .clksel_con     = CRU_CLKSEL16_CON,
1440         .clksel_mask    = 0x1F,
1441         .clksel_shift   = 13,
1442         .clksel_parent_mask     = 3,
1443         .clksel_parent_shift    = 11,
1444         .parents        = dclk_lcdc_div_parents,
1445 };
1446
1447 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &general_pll_clk, &arm_pll_clk };
1448
1449 static struct clk aclk_lcdc = {
1450         .name           = "aclk_lcdc",
1451         .mode           = gate_mode,
1452         .gate_idx       = CLK_GATE_ACLK_LCDC,
1453         .recalc         = clksel_recalc_div,
1454         .set_rate       = clksel_set_rate_div,
1455         .clksel_con     = CRU_CLKSEL16_CON,
1456         .clksel_mask    = 0x1F,
1457         .clksel_shift   = 20,
1458         .clksel_parent_mask     = 3,
1459         .clksel_parent_shift    = 18,
1460         .parents        = aclk_lcdc_parents,
1461 };
1462
1463 static struct clk hclk_lcdc = {
1464         .name           = "hclk_lcdc",
1465         .mode           = gate_mode,
1466         .gate_idx       = CLK_GATE_HCLK_LCDC,
1467         .parent         = &aclk_lcdc,
1468         .clksel_con     = CRU_CLKSEL16_CON,
1469         .recalc         = clksel_recalc_shift,
1470         .set_rate       = clksel_set_rate_shift,
1471         .clksel_mask    = 3,
1472         .clksel_shift   = 25,
1473         .clksel_maxdiv  = 4,
1474 };
1475
1476 static struct clk *xpu_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1477
1478 static struct clk aclk_vepu = {
1479         .name           = "aclk_vepu",
1480         .mode           = gate_mode,
1481         .recalc         = clksel_recalc_div,
1482         .set_rate       = clksel_set_rate_div,
1483         .gate_idx       = CLK_GATE_ACLK_VEPU,
1484         .clksel_con     = CRU_CLKSEL17_CON,
1485         .clksel_mask    = 0x1F,
1486         .clksel_shift   = 2,
1487         .clksel_parent_mask     = 3,
1488         .clksel_parent_shift    = 0,
1489         .parents        = xpu_parents,
1490 };
1491
1492 static struct clk hclk_vepu = {
1493         .name           = "hclk_vepu",
1494         .parent         = &aclk_vepu,
1495         .mode           = gate_mode,
1496         .recalc         = clksel_recalc_shift,
1497         .set_rate       = clksel_set_rate_shift,
1498         .gate_idx       = CLK_GATE_HCLK_VEPU,
1499         .clksel_con     = CRU_CLKSEL17_CON,
1500         .clksel_mask    = 3,
1501         .clksel_shift   = 28,
1502         .clksel_maxdiv  = 4,
1503 };
1504
1505 static struct clk aclk_vdpu = {
1506         .name           = "aclk_vdpu",
1507         .parent         = &general_pll_clk,
1508         .mode           = gate_mode,
1509         .recalc         = clksel_recalc_div,
1510         .set_rate       = clksel_set_rate_div,
1511         .gate_idx       = CLK_GATE_ACLK_VDPU,
1512         .clksel_con     = CRU_CLKSEL17_CON,
1513         .clksel_mask    = 0x1F,
1514         .clksel_shift   = 9,
1515         .clksel_parent_mask     = 3,
1516         .clksel_parent_shift    = 7,
1517         .parents        = xpu_parents,
1518 };
1519
1520 static struct clk hclk_vdpu = {
1521         .name           = "hclk_vdpu",
1522         .parent         = &aclk_vdpu,
1523         .mode           = gate_mode,
1524         .recalc         = clksel_recalc_shift,
1525         .set_rate       = clksel_set_rate_shift,
1526         .gate_idx       = CLK_GATE_HCLK_VDPU,
1527         .clksel_con     = CRU_CLKSEL17_CON,
1528         .clksel_mask    = 3,
1529         .clksel_shift   = 30,
1530         .clksel_maxdiv  = 4,
1531 };
1532
1533 static struct clk clk_gpu = {
1534         .name           = "gpu",
1535         .mode           = gate_mode,
1536         .gate_idx       = CLK_GATE_GPU,
1537         .recalc         = clksel_recalc_div,
1538         .set_rate       = clksel_set_rate_div,
1539         .clksel_con     = CRU_CLKSEL17_CON,
1540         .clksel_mask    = 0x1F,
1541         .clksel_shift   = 16,
1542         .clksel_parent_mask     = 3,
1543         .clksel_parent_shift    = 14,
1544         .parents        = xpu_parents,
1545 };
1546
1547 static struct clk aclk_gpu = {
1548         .name           = "aclk_gpu",
1549         .mode           = gate_mode,
1550         .gate_idx       = CLK_GATE_ACLK_GPU,
1551         .recalc         = clksel_recalc_div,
1552         .set_rate       = clksel_set_rate_div,
1553         .clksel_con     = CRU_CLKSEL17_CON,
1554         .clksel_mask    = 0x1F,
1555         .clksel_shift   = 23,
1556         .clksel_parent_mask     = 3,
1557         .clksel_parent_shift    = 21,
1558         .parents        = xpu_parents,
1559 };
1560
1561
1562 static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
1563
1564 static struct clk clk_vip = {
1565         .name           = "vip",
1566         .mode           = gate_mode,
1567         .gate_idx       = CLK_GATE_VIP,
1568         .clksel_con     = CRU_CLKSEL1_CON,
1569         .clksel_parent_mask     = 3,
1570         .clksel_parent_shift    = 7,
1571         .parents        = clk_vip_parents,
1572 };
1573
1574
1575 #define GATE_CLK(NAME,PARENT,ID) \
1576 static struct clk clk_##NAME = { \
1577         .name           = #NAME, \
1578         .parent         = &PARENT, \
1579         .mode           = gate_mode, \
1580         .gate_idx       = CLK_GATE_##ID, \
1581 }
1582
1583 GATE_CLK(i2c0, pclk_cpu, I2C0);
1584 GATE_CLK(i2c1, pclk_periph, I2C1);
1585 GATE_CLK(i2c2, pclk_periph, I2C2);
1586 GATE_CLK(i2c3, pclk_periph, I2C3);
1587
1588 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1589 GATE_CLK(gpio1, pclk_periph, GPIO1);
1590 GATE_CLK(gpio2, pclk_periph, GPIO2);
1591 GATE_CLK(gpio3, pclk_periph, GPIO3);
1592 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1593 GATE_CLK(gpio5, pclk_periph, GPIO5);
1594 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1595
1596 GATE_CLK(dma1, aclk_cpu, DMA1);
1597 GATE_CLK(dma2, aclk_periph, DMA2);
1598
1599 GATE_CLK(gic, aclk_cpu, GIC);
1600 GATE_CLK(intmem, aclk_cpu, INTMEM);
1601 GATE_CLK(rom, hclk_cpu, ROM);
1602 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1603 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1604 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1605 GATE_CLK(efuse, pclk_cpu, EFUSE);
1606 GATE_CLK(tzpc, pclk_cpu, TZPC);
1607 GATE_CLK(debug, pclk_cpu, DEBUG);
1608 GATE_CLK(tpiu, pclk_cpu, TPIU);
1609 GATE_CLK(rtc, pclk_cpu, RTC);
1610 GATE_CLK(pmu, pclk_cpu, PMU);
1611 GATE_CLK(grf, pclk_cpu, GRF);
1612
1613 GATE_CLK(emem, hclk_periph, EMEM);
1614 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
1615 GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
1616 GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
1617 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
1618 GATE_CLK(smc, pclk_periph, SMC);
1619 GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
1620 GATE_CLK(mii_tx, hclk_periph, MII_TX);
1621 GATE_CLK(mii_rx, hclk_periph, MII_RX);
1622 GATE_CLK(hif, hclk_periph, HIF);
1623 GATE_CLK(nandc, hclk_periph, NANDC);
1624 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
1625 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1626 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1627 GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
1628 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1629
1630 GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
1631 GATE_CLK(wdt, pclk_periph, WDT);
1632 GATE_CLK(pwm, pclk_periph, PWM);
1633 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1634 GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
1635 GATE_CLK(vip_input, hclk_cpu, VIP_INPUT);
1636 GATE_CLK(jtag, aclk_cpu, JTAG);
1637
1638 GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
1639 GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
1640 GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
1641 GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
1642 GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
1643 GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
1644 GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
1645 GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
1646 GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
1647 GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
1648 GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
1649 GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
1650
1651 GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
1652 GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
1653 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
1654
1655 #define CLK(dev, con, ck) \
1656         { \
1657                 .dev_id = dev, \
1658                 .con_id = con, \
1659                 .clk = ck, \
1660         }
1661
1662 #define CLK1(name) \
1663         { \
1664                 .dev_id = NULL, \
1665                 .con_id = #name, \
1666                 .clk = &clk_##name, \
1667         }
1668
1669 static struct clk_lookup clks[] = {
1670         CLK(NULL, "xin24m", &xin24m),
1671         CLK(NULL, "xin27m", &xin27m),
1672         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1673         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1674         CLK(NULL, "gpsclk", &gpsclk),
1675
1676         CLK1(12m),
1677         CLK(NULL, "arm_pll", &arm_pll_clk),
1678         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1679         CLK(NULL, "codec_pll", &codec_pll_clk),
1680         CLK(NULL, "general_pll", &general_pll_clk),
1681
1682         CLK1(core),
1683         CLK(NULL, "aclk_cpu", &aclk_cpu),
1684         CLK(NULL, "hclk_cpu", &hclk_cpu),
1685         CLK(NULL, "pclk_cpu", &pclk_cpu),
1686
1687         CLK(NULL, "aclk_periph", &aclk_periph),
1688         CLK(NULL, "hclk_periph", &hclk_periph),
1689         CLK(NULL, "pclk_periph", &pclk_periph),
1690
1691         CLK1(vip),
1692         CLK1(otgphy0),
1693         CLK1(otgphy1),
1694         CLK1(uhost),
1695         CLK1(mac_ref_div),
1696         CLK1(mac_ref),
1697
1698         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
1699         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
1700         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
1701         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
1702         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
1703         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
1704         CLK(NULL, "spdif_div", &clk_spdif_div),
1705         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
1706         CLK(NULL, "spdif", &clk_spdif),
1707
1708         CLK1(spi_src),
1709         CLK("rk29xx_spim.0", "spi", &clk_spi0),
1710         CLK("rk29xx_spim.1", "spi", &clk_spi1),
1711
1712         CLK1(saradc),
1713         CLK1(timer0),
1714         CLK1(timer1),
1715         CLK1(timer2),
1716         CLK1(timer3),
1717
1718         CLK1(mmc_src),
1719         CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
1720         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
1721         CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
1722         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
1723         CLK1(emmc),
1724         CLK1(hclk_emmc),
1725         CLK1(ddr),
1726
1727         CLK1(uart01_src),
1728         CLK("rk29_serial.0", "uart", &clk_uart0),
1729         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
1730         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
1731         CLK("rk29_serial.1", "uart", &clk_uart1),
1732         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
1733         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
1734
1735         CLK1(uart23_src),
1736         CLK("rk29_serial.2", "uart", &clk_uart2),
1737         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
1738         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
1739         CLK("rk29_serial.3", "uart", &clk_uart3),
1740         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
1741         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
1742
1743         CLK1(hsadc_div),
1744         CLK1(hsadc_frac_div),
1745         CLK1(demod),
1746         CLK1(hsadc),
1747         CLK1(hsadc_div2),
1748         CLK1(hsadc_div2_inv),
1749         CLK1(hsadc_out),
1750
1751         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
1752         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
1753         CLK(NULL, "dclk_ebook", &dclk_ebook),
1754         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
1755         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
1756
1757         CLK(NULL, "aclk_vepu", &aclk_vepu),
1758         CLK(NULL, "hclk_vepu", &hclk_vepu),
1759         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
1760         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
1761         CLK1(gpu),
1762         CLK(NULL, "aclk_gpu", &aclk_gpu),
1763
1764         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
1765         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
1766         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
1767         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
1768
1769         CLK1(gpio0),
1770         CLK1(gpio1),
1771         CLK1(gpio2),
1772         CLK1(gpio3),
1773         CLK1(gpio4),
1774         CLK1(gpio5),
1775         CLK1(gpio6),
1776
1777         CLK1(dma1),
1778         CLK1(dma2),
1779
1780         CLK1(gic),
1781         CLK1(intmem),
1782         CLK1(rom),
1783         CLK1(ddr_phy),
1784         CLK1(ddr_reg),
1785         CLK1(ddr_cpu),
1786         CLK1(efuse),
1787         CLK1(tzpc),
1788         CLK1(debug),
1789         CLK1(tpiu),
1790         CLK1(rtc),
1791         CLK1(pmu),
1792         CLK1(grf),
1793
1794         CLK1(emem),
1795         CLK1(hclk_usb_peri),
1796         CLK1(aclk_ddr_peri),
1797         CLK1(aclk_cpu_peri),
1798         CLK1(aclk_smc),
1799         CLK1(smc),
1800         CLK1(hclk_mac),
1801         CLK1(mii_tx),
1802         CLK1(mii_rx),
1803         CLK1(hif),
1804         CLK1(nandc),
1805         CLK1(hclk_hsadc),
1806         CLK1(usbotg0),
1807         CLK1(usbotg1),
1808         CLK1(hclk_uhost),
1809         CLK1(pid_filter),
1810
1811         CLK1(vip_slave),
1812         CLK1(wdt),
1813         CLK1(pwm),
1814         CLK1(vip_bus),
1815         CLK1(vip_matrix),
1816         CLK1(vip_input),
1817         CLK1(jtag),
1818
1819         CLK1(aclk_ddr_lcdc),
1820         CLK1(aclk_ipp),
1821         CLK1(hclk_ipp),
1822         CLK1(hclk_ebook),
1823         CLK1(aclk_disp_matrix),
1824         CLK1(hclk_disp_matrix),
1825         CLK1(aclk_ddr_vepu),
1826         CLK1(aclk_ddr_vdpu),
1827         CLK1(aclk_ddr_gpu),
1828         CLK1(hclk_gpu),
1829         CLK1(hclk_cpu_vcodec),
1830         CLK1(hclk_cpu_display),
1831 };
1832
1833 static LIST_HEAD(clocks);
1834 static DEFINE_MUTEX(clocks_mutex);
1835 static DEFINE_SPINLOCK(clockfw_lock);
1836 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
1837 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
1838
1839 static int clk_enable_nolock(struct clk *clk)
1840 {
1841         int ret = 0;
1842
1843         if (clk->usecount == 0) {
1844                 if (clk->parent) {
1845                         ret = clk_enable_nolock(clk->parent);
1846                         if (ret)
1847                                 return ret;
1848                 }
1849
1850                 if (clk->mode) {
1851                         ret = clk->mode(clk, 1);
1852                         if (ret) {
1853                                 if (clk->parent)
1854                                         clk_disable_nolock(clk->parent);
1855                                 return ret;
1856                         }
1857                 }
1858                 pr_debug("%s enabled\n", clk->name);
1859         }
1860         clk->usecount++;
1861
1862         return ret;
1863 }
1864
1865 int clk_enable(struct clk *clk)
1866 {
1867         int ret = 0;
1868
1869         if (clk == NULL || IS_ERR(clk))
1870                 return -EINVAL;
1871
1872         LOCK();
1873         ret = clk_enable_nolock(clk);
1874         UNLOCK();
1875
1876         return ret;
1877 }
1878 EXPORT_SYMBOL(clk_enable);
1879
1880 static void clk_disable_nolock(struct clk *clk)
1881 {
1882         if (clk->usecount == 0) {
1883                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
1884                 WARN_ON(1);
1885                 return;
1886         }
1887
1888         if (--clk->usecount == 0) {
1889                 if (clk->mode)
1890                         clk->mode(clk, 0);
1891                 pr_debug("%s disabled\n", clk->name);
1892                 if (clk->parent)
1893                         clk_disable_nolock(clk->parent);
1894         }
1895 }
1896
1897 void clk_disable(struct clk *clk)
1898 {
1899         if (clk == NULL || IS_ERR(clk))
1900                 return;
1901
1902         LOCK();
1903         clk_disable_nolock(clk);
1904         UNLOCK();
1905 }
1906 EXPORT_SYMBOL(clk_disable);
1907
1908 unsigned long clk_get_rate(struct clk *clk)
1909 {
1910         if (clk == NULL || IS_ERR(clk))
1911                 return 0;
1912
1913         return clk->rate;
1914 }
1915 EXPORT_SYMBOL(clk_get_rate);
1916
1917 /*-------------------------------------------------------------------------
1918  * Optional clock functions defined in include/linux/clk.h
1919  *-------------------------------------------------------------------------*/
1920
1921 /* Given a clock and a rate apply a clock specific rounding function */
1922 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
1923 {
1924         if (clk->round_rate)
1925                 return clk->round_rate(clk, rate);
1926
1927         if (clk->flags & RATE_FIXED)
1928                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
1929
1930         return clk->rate;
1931 }
1932
1933 long clk_round_rate(struct clk *clk, unsigned long rate)
1934 {
1935         long ret = 0;
1936
1937         if (clk == NULL || IS_ERR(clk))
1938                 return ret;
1939
1940         LOCK();
1941         ret = clk_round_rate_nolock(clk, rate);
1942         UNLOCK();
1943
1944         return ret;
1945 }
1946 EXPORT_SYMBOL(clk_round_rate);
1947
1948 static void __clk_recalc(struct clk *clk)
1949 {
1950         if (unlikely(clk->flags & RATE_FIXED))
1951                 return;
1952         if (clk->recalc)
1953                 clk->rate = clk->recalc(clk);
1954         else if (clk->parent)
1955                 clk->rate = clk->parent->rate;
1956         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
1957 }
1958
1959 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
1960 {
1961         int ret;
1962
1963         if (rate == clk->rate)
1964                 return 0;
1965
1966         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
1967
1968         if (clk->flags & CONFIG_PARTICIPANT)
1969                 return -EINVAL;
1970
1971         if (!clk->set_rate)
1972                 return -EINVAL;
1973
1974         ret = clk->set_rate(clk, rate);
1975
1976         if (ret == 0) {
1977                 __clk_recalc(clk);
1978                 __propagate_rate(clk);
1979         }
1980
1981         return ret;
1982 }
1983
1984 /* Set the clock rate for a clock source */
1985 int clk_set_rate(struct clk *clk, unsigned long rate)
1986 {
1987         int ret = -EINVAL;
1988
1989         if (clk == NULL || IS_ERR(clk))
1990                 return ret;
1991
1992         LOCK();
1993         ret = clk_set_rate_nolock(clk, rate);
1994         UNLOCK();
1995
1996         return ret;
1997 }
1998 EXPORT_SYMBOL(clk_set_rate);
1999
2000 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
2001 {
2002         int ret;
2003         int enabled = clk->usecount > 0;
2004         struct clk *old_parent = clk->parent;
2005
2006         if (clk->parent == parent)
2007                 return 0;
2008
2009         /* if clk is already enabled, enable new parent first and disable old parent later. */
2010         if (enabled)
2011                 clk_enable_nolock(parent);
2012
2013         if (clk->set_parent)
2014                 ret = clk->set_parent(clk, parent);
2015         else
2016                 ret = clksel_set_parent(clk, parent);
2017
2018         if (ret == 0) {
2019                 /* OK */
2020                 __clk_reparent(clk, parent);
2021                 __clk_recalc(clk);
2022                 __propagate_rate(clk);
2023                 if (enabled)
2024                         clk_disable_nolock(old_parent);
2025         } else {
2026                 if (enabled)
2027                         clk_disable_nolock(parent);
2028         }
2029
2030         return ret;
2031 }
2032
2033 int clk_set_parent(struct clk *clk, struct clk *parent)
2034 {
2035         int ret = -EINVAL;
2036
2037         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
2038                 return ret;
2039
2040         if (clk->set_parent == NULL && clk->parents == NULL)
2041                 return ret;
2042
2043         LOCK();
2044         if (clk->usecount == 0)
2045                 ret = clk_set_parent_nolock(clk, parent);
2046         else
2047                 ret = -EBUSY;
2048         UNLOCK();
2049
2050         return ret;
2051 }
2052 EXPORT_SYMBOL(clk_set_parent);
2053
2054 struct clk *clk_get_parent(struct clk *clk)
2055 {
2056         return clk->parent;
2057 }
2058 EXPORT_SYMBOL(clk_get_parent);
2059
2060 static void __clk_reparent(struct clk *child, struct clk *parent)
2061 {
2062         if (child->parent == parent)
2063                 return;
2064         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
2065
2066         list_del_init(&child->sibling);
2067         if (parent)
2068                 list_add(&child->sibling, &parent->children);
2069         child->parent = parent;
2070 }
2071
2072 /* Propagate rate to children */
2073 static void __propagate_rate(struct clk *tclk)
2074 {
2075         struct clk *clkp;
2076
2077         list_for_each_entry(clkp, &tclk->children, sibling) {
2078                 __clk_recalc(clkp);
2079                 __propagate_rate(clkp);
2080         }
2081 }
2082
2083 static LIST_HEAD(root_clks);
2084
2085 /**
2086  * recalculate_root_clocks - recalculate and propagate all root clocks
2087  *
2088  * Recalculates all root clocks (clocks with no parent), which if the
2089  * clock's .recalc is set correctly, should also propagate their rates.
2090  * Called at init.
2091  */
2092 static void clk_recalculate_root_clocks_nolock(void)
2093 {
2094         struct clk *clkp;
2095
2096         list_for_each_entry(clkp, &root_clks, sibling) {
2097                 __clk_recalc(clkp);
2098                 __propagate_rate(clkp);
2099         }
2100 }
2101
2102 void clk_recalculate_root_clocks(void)
2103 {
2104         LOCK();
2105         clk_recalculate_root_clocks_nolock();
2106         UNLOCK();
2107 }
2108
2109
2110 /**
2111  * clk_preinit - initialize any fields in the struct clk before clk init
2112  * @clk: struct clk * to initialize
2113  *
2114  * Initialize any struct clk fields needed before normal clk initialization
2115  * can run.  No return value.
2116  */
2117 static void clk_preinit(struct clk *clk)
2118 {
2119         INIT_LIST_HEAD(&clk->children);
2120 }
2121
2122 static int clk_register(struct clk *clk)
2123 {
2124         if (clk == NULL || IS_ERR(clk))
2125                 return -EINVAL;
2126
2127         /*
2128          * trap out already registered clocks
2129          */
2130         if (clk->node.next || clk->node.prev)
2131                 return 0;
2132
2133         mutex_lock(&clocks_mutex);
2134
2135         if (clk->get_parent)
2136                 clk->parent = clk->get_parent(clk);
2137         else if (clk->parents)
2138                 clk->parent = clksel_get_parent(clk);
2139
2140         if (clk->parent)
2141                 list_add(&clk->sibling, &clk->parent->children);
2142         else
2143                 list_add(&clk->sibling, &root_clks);
2144
2145         list_add(&clk->node, &clocks);
2146
2147         mutex_unlock(&clocks_mutex);
2148
2149         return 0;
2150 }
2151
2152 static unsigned int __initdata armclk = 600 * MHZ;
2153
2154 /*
2155  * You can override arm_clk rate with armclk= cmdline option.
2156  */
2157 static int __init armclk_setup(char *str)
2158 {
2159         get_option(&str, &armclk);
2160
2161         if (!armclk)
2162                 return 0;
2163
2164         if (armclk < 10000)
2165                 armclk *= MHZ;
2166
2167         clk_set_rate_nolock(&arm_pll_clk, armclk);
2168         return 0;
2169 }
2170 early_param("armclk", armclk_setup);
2171
2172 static void __init rk29_clock_common_init(void)
2173 {
2174         /* general pll */
2175         clk_set_rate_nolock(&general_pll_clk, 288 * MHZ);
2176         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2177         clk_set_rate_nolock(&aclk_periph, 144 * MHZ);
2178         clk_set_rate_nolock(&hclk_periph, 144 * MHZ);
2179         clk_set_rate_nolock(&pclk_periph, 36 * MHZ);
2180         clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
2181         clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2182         clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
2183         clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
2184         clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
2185         clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
2186         clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
2187         clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
2188         clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
2189         clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
2190         clk_set_parent_nolock(&aclk_lcdc, &general_pll_clk);
2191         clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
2192         clk_set_rate_nolock(&aclk_vepu, 288 * MHZ);
2193         clk_set_rate_nolock(&clk_aclk_ddr_vepu, 288 * MHZ);
2194         clk_set_rate_nolock(&hclk_vepu, 144 * MHZ);
2195         clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
2196         clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
2197         clk_set_rate_nolock(&aclk_gpu, 288 * MHZ);
2198         clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
2199         clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
2200
2201         /* codec pll */
2202         clk_set_rate_nolock(&codec_pll_clk, 552 * MHZ);
2203         clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
2204
2205         /* arm pll */
2206         clk_set_rate_nolock(&arm_pll_clk, armclk);
2207         clk_set_parent_nolock(&clk_mac_ref_div, &arm_pll_clk);
2208 }
2209
2210 static void __init clk_enable_init_clocks(void)
2211 {
2212         clk_enable_nolock(&hclk_cpu);
2213         clk_enable_nolock(&pclk_cpu);
2214         clk_enable_nolock(&hclk_periph);
2215         clk_enable_nolock(&pclk_periph);
2216         clk_enable_nolock(&clk_nandc);
2217         clk_enable_nolock(&clk_aclk_cpu_peri);
2218         clk_enable_nolock(&clk_aclk_ddr_peri);
2219         clk_enable_nolock(&clk_grf);
2220         clk_enable_nolock(&clk_pmu);
2221         clk_enable_nolock(&clk_ddr_cpu);
2222         clk_enable_nolock(&clk_ddr_reg);
2223         clk_enable_nolock(&clk_ddr_phy);
2224         clk_enable_nolock(&clk_gic);
2225         clk_enable_nolock(&clk_dma2);
2226         clk_enable_nolock(&clk_dma1);
2227         clk_enable_nolock(&clk_emem);
2228         clk_enable_nolock(&clk_intmem);
2229         clk_enable_nolock(&clk_ddr);
2230         clk_enable_nolock(&clk_debug);
2231         clk_enable_nolock(&clk_jtag);
2232 #ifdef CONFIG_DEBUG_LL
2233         clk_enable_nolock(&clk_uart1);
2234 #endif
2235 }
2236
2237 static int __init clk_disable_unused(void)
2238 {
2239         struct clk *ck;
2240
2241         list_for_each_entry(ck, &clocks, node) {
2242                 if (ck->usecount > 0 || ck->mode == NULL)
2243                         continue;
2244
2245                 LOCK();
2246                 clk_enable_nolock(ck);
2247                 clk_disable_nolock(ck);
2248                 UNLOCK();
2249         }
2250
2251         pmu_set_power_domain(PD_VCODEC, false);
2252 //      pmu_set_power_domain(PD_DISPLAY, false);
2253         pmu_set_power_domain(PD_GPU, false);
2254
2255         return 0;
2256 }
2257
2258 void __init rk29_clock_init(void)
2259 {
2260         struct clk_lookup *lk;
2261
2262         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2263                 clk_preinit(lk->clk);
2264
2265         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2266                 clkdev_add(lk);
2267                 clk_register(lk->clk);
2268         }
2269
2270         clk_recalculate_root_clocks_nolock();
2271
2272         /*
2273          * Only enable those clocks we will need, let the drivers
2274          * enable other clocks as necessary
2275          */
2276         clk_enable_init_clocks();
2277
2278         /*
2279          * Disable any unused clocks left on by the bootloader
2280          */
2281         clk_disable_unused();
2282
2283         rk29_clock_common_init();
2284
2285         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
2286                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
2287                aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
2288 }
2289
2290 #ifdef CONFIG_PROC_FS
2291 #include <linux/proc_fs.h>
2292 #include <linux/seq_file.h>
2293
2294 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2295 {
2296         struct clk* ck;
2297         int i;
2298         unsigned long rate = clk->rate;
2299
2300         for (i = 0; i < deep; i++)
2301                 seq_printf(s, "    ");
2302
2303         seq_printf(s, "%-9s ", clk->name);
2304
2305         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
2306                 u32 reg;
2307                 int idx = clk->gate_idx;
2308                 u32 v;
2309
2310                 reg = CRU_CLKGATE0_CON;
2311                 reg += (idx >> 5) << 2;
2312                 idx &= 0x1F;
2313
2314                 v = cru_readl(reg) & (1 << idx);
2315
2316                 seq_printf(s, "%s ", v ? "off" : "on ");
2317         }
2318
2319         if (clk == &arm_pll_clk) {
2320                 switch (cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) {
2321                 case CRU_CPU_MODE_SLOW:   seq_printf(s, "slow   "); break;
2322                 case CRU_CPU_MODE_NORMAL: seq_printf(s, "normal "); break;
2323                 case CRU_CPU_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2324                 }
2325                 if (cru_readl(CRU_APLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2326         } else if (clk == &ddr_pll_clk) {
2327                 switch (cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) {
2328                 case CRU_DDR_MODE_SLOW:   seq_printf(s, "slow   "); break;
2329                 case CRU_DDR_MODE_NORMAL: seq_printf(s, "normal "); break;
2330                 case CRU_DDR_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2331                 }
2332                 if (cru_readl(CRU_DPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2333         } else if (clk == &codec_pll_clk) {
2334                 switch (cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) {
2335                 case CRU_CODEC_MODE_SLOW:   seq_printf(s, "slow   "); break;
2336                 case CRU_CODEC_MODE_NORMAL: seq_printf(s, "normal "); break;
2337                 case CRU_CODEC_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2338                 }
2339                 if (cru_readl(CRU_CPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2340         } else if (clk == &general_pll_clk) {
2341                 switch (cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) {
2342                 case CRU_GENERAL_MODE_SLOW:   seq_printf(s, "slow   "); break;
2343                 case CRU_GENERAL_MODE_NORMAL: seq_printf(s, "normal "); break;
2344                 case CRU_GENERAL_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2345                 }
2346                 if (cru_readl(CRU_GPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2347         }
2348
2349         if (rate >= MHZ) {
2350                 if (rate % MHZ)
2351                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2352                 else
2353                         seq_printf(s, "%ld MHz", rate / MHZ);
2354         } else if (rate >= KHZ) {
2355                 if (rate % KHZ)
2356                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2357                 else
2358                         seq_printf(s, "%ld KHz", rate / KHZ);
2359         } else {
2360                 seq_printf(s, "%ld Hz", rate);
2361         }
2362
2363         seq_printf(s, " usecount = %d", clk->usecount);
2364
2365         seq_printf(s, " parent = %s\n", clk->parent ? clk->parent->name : "NULL");
2366
2367         list_for_each_entry(ck, &clocks, node) {
2368                 if (ck->parent == clk)
2369                         dump_clock(s, ck, deep + 1);
2370         }
2371 }
2372
2373 static int proc_clk_show(struct seq_file *s, void *v)
2374 {
2375         struct clk* clk;
2376
2377         mutex_lock(&clocks_mutex);
2378         list_for_each_entry(clk, &clocks, node) {
2379                 if (!clk->parent)
2380                         dump_clock(s, clk, 0);
2381         }
2382         mutex_unlock(&clocks_mutex);
2383
2384         seq_printf(s, "\nCRU Registers:\n");
2385         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2386         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2387         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2388         seq_printf(s, "GPLL     : 0x%08x\n", cru_readl(CRU_GPLL_CON));
2389         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2390         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2391         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2392         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2393         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2394         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2395         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2396         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2397         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2398         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2399         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2400         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2401         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2402         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2403         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2404         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2405         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2406         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2407         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2408         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2409         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2410         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2411         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2412
2413         seq_printf(s, "\nPMU Registers:\n");
2414         seq_printf(s, "WAKEUP_EN0 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN0));
2415         seq_printf(s, "WAKEUP_EN1 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN1));
2416         seq_printf(s, "WAKEUP_EN2 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN2));
2417         seq_printf(s, "PD_CON     : 0x%08x\n", pmu_readl(PMU_PD_CON));
2418         seq_printf(s, "MISC_CON   : 0x%08x\n", pmu_readl(PMU_MISC_CON));
2419         seq_printf(s, "PLL_CNT    : 0x%08x\n", pmu_readl(PMU_PLL_CNT));
2420         seq_printf(s, "PD_ST      : 0x%08x\n", pmu_readl(PMU_PD_ST));
2421         seq_printf(s, "INT_ST     : 0x%08x\n", pmu_readl(PMU_INT_ST));
2422
2423         return 0;
2424 }
2425
2426 static int proc_clk_open(struct inode *inode, struct file *file)
2427 {
2428         return single_open(file, proc_clk_show, NULL);
2429 }
2430
2431 static const struct file_operations proc_clk_fops = {
2432         .open           = proc_clk_open,
2433         .read           = seq_read,
2434         .llseek         = seq_lseek,
2435         .release        = single_release,
2436 };
2437
2438 static int __init clk_proc_init(void)
2439 {
2440         proc_create("clocks", 0, NULL, &proc_clk_fops);
2441         return 0;
2442
2443 }
2444 late_initcall(clk_proc_init);
2445 #endif /* CONFIG_PROC_FS */
2446