arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33
  34
  35 #define PWM_VCORE_120   40
  36 #define PWM_VCORE_125   32
  37 #define PWM_VCORE_130   21
  38 #define PWM_VCORE_135   10
  39 #define PWM_VCORE_140   0
  40
  41 /* CRU PLL CON */
  42 #define PLL_HIGH_BAND   (0x01 << 16)
  43 #define PLL_LOW_BAND    (0x00 << 16)
  44 #define PLL_PD          (0x01 << 15)
  45
  46 #define PLL_CLKR(i)     ((((i) - 1) & 0x1f) << 10)
  47 #define PLL_NR(v)       ((((v) >> 10) & 0x1f) + 1)
  48
  49 #define PLL_CLKF(i)     ((((i) - 1) & 0x7f) << 3)
  50 #define PLL_NF(v)       ((((v) >> 3) & 0x7f) + 1)
  51 #define PLL_NF2(v)      (((((v) >> 3) & 0x7f) + 1) << 1)
  52
  53 #define PLL_CLKOD(i)    (((i) & 0x03) << 1)
  54 #define PLL_NO_1        PLL_CLKOD(0)
  55 #define PLL_NO_2        PLL_CLKOD(1)
  56 #define PLL_NO_4        PLL_CLKOD(2)
  57 #define PLL_NO_8        PLL_CLKOD(3)
  58 #define PLL_NO_SHIFT(v) (((v) >> 1) & 0x03)
  59
  60 #define PLL_BYPASS      (0x01)
  61
  62 /* CRU MODE CON */
  63 #define CRU_CPU_MODE_MASK       (0x03u << 0)
  64 #define CRU_CPU_MODE_SLOW       (0x00u << 0)
  65 #define CRU_CPU_MODE_NORMAL     (0x01u << 0)
  66 #define CRU_CPU_MODE_DSLOW      (0x02u << 0)
  67
  68 #define CRU_PERIPH_MODE_MASK    (0x03u << 2)
  69 #define CRU_PERIPH_MODE_SLOW    (0x00u << 2)
  70 #define CRU_PERIPH_MODE_NORMAL  (0x01u << 2)
  71 #define CRU_PERIPH_MODE_DSLOW   (0x02u << 2)
  72
  73 #define CRU_CODEC_MODE_MASK     (0x03u << 4)
  74 #define CRU_CODEC_MODE_SLOW     (0x00u << 4)
  75 #define CRU_CODEC_MODE_NORMAL   (0x01u << 4)
  76 #define CRU_CODEC_MODE_DSLOW    (0x02u << 4)
  77
  78 #define CRU_DDR_MODE_MASK       (0x03u << 6)
  79 #define CRU_DDR_MODE_SLOW       (0x00u << 6)
  80 #define CRU_DDR_MODE_NORMAL     (0x01u << 6)
  81 #define CRU_DDR_MODE_DSLOW      (0x02u << 6)
  82
  83 /* Clock flags */
  84 /* bit 0 is free */
  85 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  86 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  87 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
  88
  89 #define cru_readl(offset)       readl(RK29_CRU_BASE + offset)
  90 #define cru_writel(v, offset)   writel(v, RK29_CRU_BASE + offset)
  91 #define cru_writel_force(v, offset)     do { u32 _v = v; u32 _count = 5; do { cru_writel(_v, offset); } while (cru_readl(offset) != _v && _count--); } while (0)        /* huangtao: when write CRU_xPLL_CON, first time may failed, so try again. unknown why. */
  92
  93 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  94
  95 #define MHZ                     (1000*1000)
  96 #define KHZ                     1000
  97
  98 struct clk {
  99         struct list_head        node;
 100         const char              *name;
 101         struct clk              *parent;
 102         struct list_head        children;
 103         struct list_head        sibling;        /* node for children */
 104         unsigned long           rate;
 105         u32                     flags;
 106         int                     (*mode)(struct clk *clk, int on);
 107         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
 108         int                     (*set_rate)(struct clk *, unsigned long);
 109         long                    (*round_rate)(struct clk *, unsigned long);
 110         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
 111         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
 112         s32                     usecount;
 113         u8                      gate_idx;
 114         u8                      pll_idx;
 115         u8                      clksel_con;
 116         u8                      clksel_mask;
 117         u8                      clksel_shift;
 118         u8                      clksel_maxdiv;
 119         u8                      clksel_parent_mask;
 120         u8                      clksel_parent_shift;
 121         struct clk              **parents;
 122 };
 123
 124 static int clk_enable_nolock(struct clk *clk);
 125 static void clk_disable_nolock(struct clk *clk);
 126 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
 127 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
 128 static void __clk_reparent(struct clk *child, struct clk *parent);
 129 static void __propagate_rate(struct clk *tclk);
 130 static struct clk codec_pll_clk;
 131 static struct clk periph_pll_clk;
 132
 133 static unsigned long clksel_recalc_div(struct clk *clk)
 134 {
 135         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
 136         unsigned long rate = clk->parent->rate / div;
 137         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 138         return rate;
 139 }
 140
 141 static unsigned long clksel_recalc_shift(struct clk *clk)
 142 {
 143         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
 144         unsigned long rate = clk->parent->rate >> shift;
 145         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 146         return rate;
 147 }
 148
 149 static unsigned long clksel_recalc_frac(struct clk *clk)
 150 {
 151         unsigned long rate;
 152         u64 rate64;
 153         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 154         if (r == 0) // FPGA ?
 155                 return clk->parent->rate;
 156         numerator = r >> 16;
 157         denominator = r & 0xFFFF;
 158         rate64 = (u64)clk->parent->rate * numerator;
 159         do_div(rate64, denominator);
 160         rate = rate64;
 161         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 162         return rate;
 163 }
 164
 165 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 166 {
 167         u32 div;
 168
 169         for (div = 0; div <= clk->clksel_mask; div++) {
 170                 u32 new_rate = clk->parent->rate / (div + 1);
 171                 if (new_rate <= rate) {
 172                         u32 v = cru_readl(clk->clksel_con);
 173                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 174                         v |= div << clk->clksel_shift;
 175                         cru_writel(v, clk->clksel_con);
 176                         clk->rate = new_rate;
 177                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 178                         return 0;
 179                 }
 180         }
 181
 182         return -ENOENT;
 183 }
 184
 185 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 186 {
 187         u32 shift;
 188
 189         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 190                 u32 new_rate = clk->parent->rate >> shift;
 191                 if (new_rate <= rate) {
 192                         u32 v = cru_readl(clk->clksel_con);
 193                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 194                         v |= shift << clk->clksel_shift;
 195                         cru_writel(v, clk->clksel_con);
 196                         clk->rate = new_rate;
 197                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 198                         return 0;
 199                 }
 200         }
 201
 202         return -ENOENT;
 203 }
 204
 205 static struct clk* clksel_get_parent(struct clk *clk)
 206 {
 207         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 208 }
 209
 210 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 211 {
 212         struct clk **p = clk->parents;
 213         u32 i;
 214
 215         if (unlikely(!p))
 216                 return -EINVAL;
 217         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 218                 u32 v;
 219                 if (*p != parent)
 220                         continue;
 221                 v = cru_readl(clk->clksel_con);
 222                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 223                 v |= (i << clk->clksel_parent_shift);
 224                 cru_writel(v, clk->clksel_con);
 225                 return 0;
 226         }
 227         return -EINVAL;
 228 }
 229
 230 static int gate_mode(struct clk *clk, int on)
 231 {
 232         u32 reg;
 233         int idx = clk->gate_idx;
 234         u32 v;
 235
 236         if (idx >= CLK_GATE_MAX)
 237                 return -EINVAL;
 238
 239         reg = CRU_CLKGATE0_CON;
 240         reg += (idx >> 5) << 2;
 241         idx &= 0x1F;
 242
 243         v = cru_readl(reg);
 244         if (on) {
 245                 v &= ~(1 << idx);       // clear bit
 246         } else {
 247                 v |= (1 << idx);        // set bit
 248         }
 249         cru_writel(v, reg);
 250
 251         return 0;
 252 }
 253
 254 static struct clk xin24m = {
 255         .name           = "xin24m",
 256         .rate           = 24 * MHZ,
 257         .flags          = RATE_FIXED,
 258 };
 259
 260 static struct clk clk_12m = {
 261         .name           = "clk_12m",
 262         .rate           = 12 * MHZ,
 263         .parent         = &xin24m,
 264         .flags          = RATE_FIXED,
 265 };
 266
 267 static struct clk xin27m = {
 268         .name           = "xin27m",
 269         .rate           = 27 * MHZ,
 270         .flags          = RATE_FIXED,
 271 };
 272
 273 static struct clk otgphy0_clkin = {
 274         .name           = "otgphy0_clkin",
 275         .rate           = 480 * MHZ,
 276         .flags          = RATE_FIXED,
 277 };
 278
 279 static struct clk otgphy1_clkin = {
 280         .name           = "otgphy1_clkin",
 281         .rate           = 480 * MHZ,
 282         .flags          = RATE_FIXED,
 283 };
 284
 285
 286 static void delay_500ns(void)
 287 {
 288         int delay = 2000;
 289         while (delay--)
 290            barrier();
 291 }
 292
 293
 294 #define PERIPH_PLL_IDX     0
 295 #define CODEC_PLL_IDX      1
 296 #define ARM_PLL_IDX        2
 297 #define DDR_PLL_IDX        3
 298
 299 #define GRF_SOC_CON0       0xbc
 300 static void pll_wait_lock(int pll_idx, int delay)
 301 {
 302         u32 bit = 0x2000000u << pll_idx;
 303         while (delay > 0) {
 304                 if (regfile_readl(GRF_SOC_CON0) & bit)
 305                         break;
 306                 delay--;
 307         }
 308         if (delay == 0) {
 309                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 310         }
 311 }
 312
 313 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 314 {
 315         unsigned long rate;
 316
 317         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 318                 u32 v = cru_readl(CRU_APLL_CON);
 319                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 320                 do_div(rate64, PLL_NR(v));
 321                 rate = rate64 >> PLL_NO_SHIFT(v);
 322                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 323         } else {
 324                 rate = clk->parent->rate;
 325                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 326         }
 327
 328         return rate;
 329 }
 330
 331 struct arm_pll_set {
 332         unsigned long rate;
 333         u32 apll_con;
 334         u32 clksel0_con;
 335 };
 336
 337 #define CORE_ACLK_11    (0 << 5)
 338 #define CORE_ACLK_21    (1 << 5)
 339 #define CORE_ACLK_31    (2 << 5)
 340 #define CORE_ACLK_41    (3 << 5)
 341 #define CORE_ACLK_81    (4 << 5)
 342 #define CORE_ACLK_MASK  (7 << 5)
 343
 344 #define ACLK_HCLK_11    (0 << 8)
 345 #define ACLK_HCLK_21    (1 << 8)
 346 #define ACLK_HCLK_41    (2 << 8)
 347 #define ACLK_HCLK_MASK  (3 << 8)
 348
 349 #define ACLK_PCLK_11    (0 << 10)
 350 #define ACLK_PCLK_21    (1 << 10)
 351 #define ACLK_PCLK_41    (2 << 10)
 352 #define ACLK_PCLK_81    (3 << 10)
 353 #define ACLK_PCLK_MASK  (3 << 10)
 354
 355 #define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 356 { \
 357         .rate           = _mhz * MHZ, \
 358         .apll_con       = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 359         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 360 }
 361
 362 static const struct arm_pll_set arm_pll[] = {
 363         // rate = 24 * NF / (NR * NO)
 364         //      rate NR  NF NO adiv hdiv pdiv
 365         ARM_PLL(1200, 1, 50, 1, 41, 21, 81),
 366         ARM_PLL(1176, 2, 98, 1, 41, 21, 81),
 367         ARM_PLL(1152, 1, 48, 1, 41, 21, 81),
 368         ARM_PLL(1104, 1, 46, 1, 41, 21, 81),
 369         ARM_PLL(1056, 1, 44, 1, 41, 21, 81),
 370         ARM_PLL(1008, 1, 42, 1, 41, 21, 81),
 371         ARM_PLL( 960, 1, 40, 1, 41, 21, 81),
 372         ARM_PLL( 912, 1, 38, 1, 41, 21, 81),
 373         ARM_PLL( 888, 2, 74, 1, 31, 21, 81),
 374         ARM_PLL( 624, 1, 52, 2, 31, 21, 81),
 375         // last item, pll power down.
 376         ARM_PLL(  24, 1, 64, 8, 21, 21, 41),
 377 };
 378
 379 #define CORE_PARENT_MASK        (3 << 23)
 380 #define CORE_PARENT_ARM_PLL     (0 << 23)
 381 #define CORE_PARENT_PERIPH_PLL  (1 << 23)
 382
 383 #define PWM_DIV2            (0<<9)
 384 #define PWM_DIV4            (1<<9)
 385 #define PWM_DIV8            (2<<9)
 386 #define PWM_DIV16           (3<<9)
 387 #define PWM_DIV32           (4<<9)
 388 #define PWM_DIV64           (5<<9)
 389 #define PWM_DIV128          (6<<9)
 390 #define PWM_DIV256          (7<<9)
 391 #define PWM_DIV512          (8<<9)
 392 #define PWM_DIV1024         (9<<9)
 393
 394 #define PWM_CAPTURE         (1<<8)
 395 #define PWM_RESET           (1<<7)
 396 #define PWM_INTCLR          (1<<6)
 397 #define PWM_INTEN           (1<<5)
 398 #define PWM_SINGLE          (1<<6)
 399
 400 #define PWM_ENABLE          (1<<3)
 401 #define PWM_TimeEN          (1)
 402
 403 #define PWM_DIV    PWM_DIV2
 404
 405 static struct clk pclk_periph;
 406 void PWMInit(u32 nHz, u32 rate)
 407 {
 408         u32 divh;
 409
 410         // iomux to pwm2
 411 #define     REG_FILE_BASE_ADDR         RK29_GRF_BASE
 412         volatile unsigned int * pGRF_GPIO2L_IOMUX =  (volatile unsigned int *)(REG_FILE_BASE_ADDR + 0x58);
 413         *pGRF_GPIO2L_IOMUX &= ~(0x3<<6);
 414         *pGRF_GPIO2L_IOMUX |= (0x2<<6);
 415         // pwm2 clk enable
 416
 417         // set pwm rate
 418 #define     PWM_BASE_ADDR              RK29_PWM_BASE
 419         volatile unsigned int * pPWM2_CTRL = (volatile unsigned int *)(PWM_BASE_ADDR + 0x2C);
 420         volatile unsigned int * pPWM2_LRC = (volatile unsigned int *)(PWM_BASE_ADDR + 0x28);
 421         volatile unsigned int * pPWM2_HRC = (volatile unsigned int *)(PWM_BASE_ADDR + 0x24);
 422         volatile unsigned int * pPWM2_CNTR = (volatile unsigned int *)(PWM_BASE_ADDR + 0x20);
 423
 424 #define     GPIO2_BASE_ADDR            RK29_GPIO2_BASE
 425         volatile unsigned int *pGPIO2_DIR = (volatile unsigned int *)(GPIO2_BASE_ADDR + 0x4);
 426         volatile unsigned int *pGPIO2_LEVEL = (volatile unsigned int *)GPIO2_BASE_ADDR;
 427
 428         if (rate == 0) {
 429                 // iomux pwm2 to gpio2_a[3]
 430                 *pGRF_GPIO2L_IOMUX &= ~(0x3<<6);
 431                 // set gpio to low level
 432                 *pGPIO2_DIR |= 0x1<<3;
 433                 *pGPIO2_LEVEL &= ~(0x1<<3);
 434         } else {
 435                 *pPWM2_CTRL= PWM_DIV|PWM_RESET;
 436                 divh = pclk_periph.rate / nHz;
 437                 divh = divh >> (1+(PWM_DIV>>9));
 438                 *pPWM2_LRC = (divh == 0)?1:divh;
 439
 440                 divh = (*pPWM2_LRC)*rate/100;
 441                 *pPWM2_HRC = divh?divh:1;
 442
 443                 *pPWM2_CNTR = 0x0;
 444                 *pPWM2_CTRL = PWM_DIV|PWM_ENABLE|PWM_TimeEN;
 445                 printk("pclk_periph %d LRC %08x HRC %08x\n", pclk_periph.rate, *pPWM2_LRC, *pPWM2_HRC);
 446         }
 447
 448         int i; for (i = 0; i < 6000; i++)
 449                 delay_500ns();
 450 }
 451
 452 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 453 {
 454         const struct arm_pll_set *ps, *pt;
 455         int i;
 456
 457         /* find the arm_pll we want. */
 458         ps = pt = &arm_pll[0];
 459         while (1) {
 460                 if (pt->rate == rate) {
 461                         ps = pt;
 462                         break;
 463                 }
 464                 // we are sorted, and ps->rate > pt->rate.
 465                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 466                         ps = pt;
 467                 if (pt->rate < rate || pt->rate == 24 * MHZ)
 468                         break;
 469                 pt++;
 470         }
 471
 472         PWMInit(1 * MHZ, PWM_VCORE_135);        // 1.35V
 473
 474         /* make aclk safe & reparent to periph pll */
 475         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_PERIPH_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 476
 477         /* enter slow mode */
 478         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 479
 480         /* power down */
 481         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 482
 483         delay_500ns();
 484
 485         cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
 486
 487         delay_500ns();
 488
 489         /* power up */
 490         cru_writel(ps->apll_con, CRU_APLL_CON);
 491
 492         for (i = 0; i < 600; i++)
 493                 delay_500ns();
 494         pll_wait_lock(ARM_PLL_IDX, 2400000);
 495
 496         /* reparent to arm pll & set aclk/hclk/pclk */
 497         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | ps->clksel0_con, CRU_CLKSEL0_CON);
 498
 499         /* enter normal mode */
 500         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 501
 502         return 0;
 503 }
 504
 505 static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
 506
 507 static struct clk arm_pll_clk = {
 508         .name           = "arm_pll",
 509         .parent         = &xin24m,
 510         .recalc         = arm_pll_clk_recalc,
 511         .set_rate       = arm_pll_clk_set_rate,
 512         .clksel_con     = CRU_MODE_CON,
 513         .clksel_parent_mask     = 1,
 514         .clksel_parent_shift    = 8,
 515         .parents        = arm_pll_parents,
 516 };
 517
 518 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 519 {
 520         unsigned long rate;
 521
 522         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 523                 u32 v = cru_readl(CRU_DPLL_CON);
 524                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 525                 do_div(rate64, PLL_NR(v));
 526                 rate = rate64 >> PLL_NO_SHIFT(v);
 527                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 528         } else {
 529                 rate = clk->parent->rate;
 530                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 531         }
 532
 533         return rate;
 534 }
 535
 536 static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &periph_pll_clk };
 537
 538 static struct clk ddr_pll_clk = {
 539         .name           = "ddr_pll",
 540         .parent         = &xin24m,
 541         .recalc         = ddr_pll_clk_recalc,
 542         .clksel_con     = CRU_MODE_CON,
 543         .clksel_parent_mask     = 3,
 544         .clksel_parent_shift    = 13,
 545         .parents        = ddr_pll_parents,
 546 };
 547
 548
 549 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 550 {
 551         unsigned long rate;
 552
 553         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) == CRU_CODEC_MODE_NORMAL) {
 554                 u32 v = cru_readl(CRU_CPLL_CON);
 555                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 556                 do_div(rate64, PLL_NR(v));
 557                 rate = rate64 >> PLL_NO_SHIFT(v);
 558                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 559         } else {
 560                 rate = clk->parent->rate;
 561                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 562         }
 563
 564         return rate;
 565 }
 566
 567 #define CODEC_PLL_PARENT_MASK   (3 << 11)
 568 #define CODEC_PLL_PARENT_XIN24M (0 << 11)
 569 #define CODEC_PLL_PARENT_XIN27M (1 << 11)
 570 #define CODEC_PLL_PARENT_DDR_PLL        (2 << 11)
 571 #define CODEC_PLL_PARENT_PERIPH_PLL     (3 << 11)
 572
 573 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 574 {
 575         u32 cpll_con;
 576         u32 mode_con;
 577         struct clk *parent;
 578         int i;
 579
 580         switch (rate) {
 581         case 108 * MHZ:
 582                 /* 24 * 18 / 4 */
 583                 cpll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(18) | PLL_NO_4;
 584                 mode_con = CODEC_PLL_PARENT_XIN24M;
 585                 parent = &xin24m;
 586                 break;
 587         case 297 * MHZ:
 588                 /* 27 * 22 / 2 */
 589                 cpll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(22) | PLL_NO_2;
 590                 mode_con = CODEC_PLL_PARENT_XIN27M;
 591                 parent = &xin27m;
 592                 break;
 593         default:
 594                 return -ENOENT;
 595                 break;
 596         }
 597
 598         /* enter slow mode */
 599         cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | mode_con, CRU_MODE_CON);
 600
 601         /* power down */
 602         cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
 603
 604         delay_500ns();
 605
 606         cru_writel(cpll_con | PLL_PD, CRU_CPLL_CON);
 607
 608         delay_500ns();
 609
 610         /* power up */
 611         cru_writel(cpll_con, CRU_CPLL_CON);
 612
 613         for (i = 0; i < 600; i++)
 614                 delay_500ns();
 615         pll_wait_lock(CODEC_PLL_IDX, 2400000);
 616
 617         /* enter normal mode */
 618         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
 619
 620         clk_set_parent_nolock(clk, parent);
 621
 622         return 0;
 623 }
 624
 625 static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &periph_pll_clk };
 626
 627 static struct clk codec_pll_clk = {
 628         .name           = "codec_pll",
 629         .parent         = &xin24m,
 630         .recalc         = codec_pll_clk_recalc,
 631         .set_rate       = codec_pll_clk_set_rate,
 632         .clksel_con     = CRU_MODE_CON,
 633         .clksel_parent_mask     = 3,
 634         .clksel_parent_shift    = 11,
 635         .parents        = codec_pll_parents,
 636 };
 637
 638
 639 static unsigned long periph_pll_clk_recalc(struct clk *clk)
 640 {
 641         unsigned long rate;
 642
 643         if ((cru_readl(CRU_MODE_CON) & CRU_PERIPH_MODE_MASK) == CRU_PERIPH_MODE_NORMAL) {
 644                 u32 v = cru_readl(CRU_PPLL_CON);
 645                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 646                 do_div(rate64, PLL_NR(v));
 647                 rate = rate64 >> PLL_NO_SHIFT(v);
 648                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 649         } else {
 650                 rate = clk->parent->rate;
 651                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 652         }
 653
 654         return rate;
 655 }
 656
 657 static int periph_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 658 {
 659         int i;
 660         /* 624M: high-band, NR=1, NF=26, NO=1 */
 661         u32 v = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 662
 663         /* enter slow mode */
 664         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_PERIPH_MODE_MASK) | CRU_PERIPH_MODE_SLOW, CRU_MODE_CON);
 665
 666         /* power down */
 667         cru_writel(cru_readl(CRU_PPLL_CON) | PLL_PD, CRU_PPLL_CON);
 668
 669         delay_500ns();
 670
 671         cru_writel(v | PLL_PD, CRU_PPLL_CON);
 672
 673         delay_500ns();
 674
 675         /* power up */
 676         cru_writel(v, CRU_PPLL_CON);
 677
 678         for (i = 0; i < 600; i++)
 679                 delay_500ns();
 680         pll_wait_lock(PERIPH_PLL_IDX, 2400000);
 681
 682         /* enter normal mode */
 683         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_PERIPH_MODE_MASK) | CRU_PERIPH_MODE_NORMAL, CRU_MODE_CON);
 684
 685         return 0;
 686 }
 687
 688 static struct clk *periph_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
 689
 690 static struct clk periph_pll_clk = {
 691         .name           = "periph_pll",
 692         .parent         = &xin24m,
 693         .recalc         = periph_pll_clk_recalc,
 694         .set_rate       = periph_pll_clk_set_rate,
 695         .clksel_con     = CRU_MODE_CON,
 696         .clksel_parent_mask     = 3,
 697         .clksel_parent_shift    = 9,
 698         .parents        = periph_pll_parents,
 699 };
 700
 701
 702 static struct clk *clk_core_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 703
 704 static struct clk clk_core = {
 705         .name           = "core",
 706         .parent         = &arm_pll_clk,
 707         .recalc         = clksel_recalc_div,
 708         .clksel_con     = CRU_CLKSEL0_CON,
 709         .clksel_mask    = 0x1F,
 710         .clksel_shift   = 0,
 711         .clksel_parent_mask     = 3,
 712         .clksel_parent_shift    = 23,
 713         .parents        = clk_core_parents,
 714 };
 715
 716 static unsigned long aclk_cpu_recalc(struct clk *clk)
 717 {
 718         unsigned long rate;
 719         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 720
 721         BUG_ON(div > 5);
 722         if (div >= 5)
 723                 div = 8;
 724         rate = clk->parent->rate / div;
 725         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 726
 727         return rate;
 728 }
 729
 730 static struct clk aclk_cpu = {
 731         .name           = "aclk_cpu",
 732         .parent         = &clk_core,
 733         .recalc         = aclk_cpu_recalc,
 734 };
 735
 736 static struct clk hclk_cpu = {
 737         .name           = "hclk_cpu",
 738         .parent         = &aclk_cpu,
 739         .recalc         = clksel_recalc_shift,
 740         .set_rate       = clksel_set_rate_shift,
 741         .clksel_con     = CRU_CLKSEL0_CON,
 742         .clksel_mask    = 3,
 743         .clksel_shift   = 8,
 744         .clksel_maxdiv  = 4,
 745 };
 746
 747 static struct clk pclk_cpu = {
 748         .name           = "pclk_cpu",
 749         .parent         = &aclk_cpu,
 750         .recalc         = clksel_recalc_shift,
 751         .set_rate       = clksel_set_rate_shift,
 752         .clksel_con     = CRU_CLKSEL0_CON,
 753         .clksel_mask    = 3,
 754         .clksel_shift   = 10,
 755         .clksel_maxdiv  = 8,
 756 };
 757
 758 static struct clk *aclk_periph_parents[4] = { &periph_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
 759
 760 static struct clk aclk_periph = {
 761         .name           = "aclk_periph",
 762         .mode           = gate_mode,
 763         .gate_idx       = CLK_GATE_PEIRPH_AXI,
 764         .recalc         = clksel_recalc_div,
 765         .set_rate       = clksel_set_rate_div,
 766         .clksel_con     = CRU_CLKSEL0_CON,
 767         .clksel_mask    = 0x1F,
 768         .clksel_shift   = 14,
 769         .clksel_parent_mask     = 3,
 770         .clksel_parent_shift    = 12,
 771         .parents        = aclk_periph_parents,
 772 };
 773
 774 static struct clk pclk_periph = {
 775         .name           = "pclk_periph",
 776         .mode           = gate_mode,
 777         .gate_idx       = CLK_GATE_PEIRPH_APB,
 778         .parent         = &aclk_periph,
 779         .recalc         = clksel_recalc_shift,
 780         .set_rate       = clksel_set_rate_shift,
 781         .clksel_con     = CRU_CLKSEL0_CON,
 782         .clksel_mask    = 3,
 783         .clksel_shift   = 19,
 784         .clksel_maxdiv  = 8,
 785 };
 786
 787 static struct clk hclk_periph = {
 788         .name           = "hclk_periph",
 789         .mode           = gate_mode,
 790         .gate_idx       = CLK_GATE_PEIRPH_AHB,
 791         .parent         = &aclk_periph,
 792         .recalc         = clksel_recalc_shift,
 793         .set_rate       = clksel_set_rate_shift,
 794         .clksel_con     = CRU_CLKSEL0_CON,
 795         .clksel_mask    = 3,
 796         .clksel_shift   = 21,
 797         .clksel_maxdiv  = 4,
 798 };
 799
 800
 801 static struct clk *clk_uhost_parents[8] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 802
 803 static struct clk clk_uhost = {
 804         .name           = "uhost",
 805         .mode           = gate_mode,
 806         .recalc         = clksel_recalc_div,
 807         .set_rate       = clksel_set_rate_div,
 808         .gate_idx       = CLK_GATE_UHOST,
 809         .clksel_con     = CRU_CLKSEL1_CON,
 810         .clksel_mask    = 0x1F,
 811         .clksel_shift   = 16,
 812         .clksel_parent_mask     = 7,
 813         .clksel_parent_shift    = 13,
 814         .parents        = clk_uhost_parents,
 815 };
 816
 817 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 818
 819 static struct clk clk_otgphy0 = {
 820         .name           = "otgphy0",
 821         .mode           = gate_mode,
 822         .gate_idx       = CLK_GATE_USBPHY0,
 823         .clksel_con     = CRU_CLKSEL1_CON,
 824         .clksel_parent_mask     = 3,
 825         .clksel_parent_shift    = 9,
 826         .parents        = clk_otgphy_parents,
 827 };
 828
 829 static struct clk clk_otgphy1 = {
 830         .name           = "otgphy1",
 831         .mode           = gate_mode,
 832         .gate_idx       = CLK_GATE_USBPHY1,
 833         .clksel_con     = CRU_CLKSEL1_CON,
 834         .clksel_parent_mask     = 3,
 835         .clksel_parent_shift    = 11,
 836         .parents        = clk_otgphy_parents,
 837 };
 838
 839
 840 static struct clk rmii_clkin = {
 841         .name           = "rmii_clkin",
 842 };
 843
 844 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 845
 846 static struct clk clk_mac_ref_div = {
 847         .name           = "mac_ref_div",
 848         .recalc         = clksel_recalc_div,
 849         .set_rate       = clksel_set_rate_div,
 850         .clksel_con     = CRU_CLKSEL1_CON,
 851         .clksel_mask    = 0x1F,
 852         .clksel_shift   = 23,
 853         .clksel_parent_mask     = 3,
 854         .clksel_parent_shift    = 21,
 855         .parents        = clk_mac_ref_div_parents,
 856 };
 857
 858 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 859
 860 static struct clk clk_mac_ref = {
 861         .name           = "mac_ref",
 862         .mode           = gate_mode,
 863         .gate_idx       = CLK_GATE_MAC_PHY,
 864         .clksel_con     = CRU_CLKSEL1_CON,
 865         .clksel_parent_mask     = 1,
 866         .clksel_parent_shift    = 28,
 867         .parents        = clk_mac_ref_parents,
 868 };
 869
 870
 871 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &periph_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 872
 873 static struct clk clk_i2s0_div = {
 874         .name           = "i2s0_div",
 875         .recalc         = clksel_recalc_div,
 876         .set_rate       = clksel_set_rate_div,
 877         .clksel_con     = CRU_CLKSEL2_CON,
 878         .clksel_mask    = 0x1F,
 879         .clksel_shift   = 3,
 880         .clksel_parent_mask     = 7,
 881         .clksel_parent_shift    = 0,
 882         .parents        = clk_i2s_div_parents,
 883 };
 884
 885 static struct clk clk_i2s1_div = {
 886         .name           = "i2s1_div",
 887         .recalc         = clksel_recalc_div,
 888         .set_rate       = clksel_set_rate_div,
 889         .clksel_con     = CRU_CLKSEL2_CON,
 890         .clksel_mask    = 0x1F,
 891         .clksel_shift   = 13,
 892         .clksel_parent_mask     = 7,
 893         .clksel_parent_shift    = 10,
 894         .parents        = clk_i2s_div_parents,
 895 };
 896
 897 static struct clk clk_spdif_div = {
 898         .name           = "spdif_div",
 899         .recalc         = clksel_recalc_div,
 900         .set_rate       = clksel_set_rate_div,
 901         .clksel_con     = CRU_CLKSEL2_CON,
 902         .clksel_mask    = 0x1F,
 903         .clksel_shift   = 23,
 904         .clksel_parent_mask     = 7,
 905         .clksel_parent_shift    = 20,
 906         .parents        = clk_i2s_div_parents,
 907 };
 908
 909 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 910 {
 911         u16 numerator, denominator;
 912
 913         switch (rate) {
 914         case 8192000:   /* 624*128/9750 */
 915                 numerator = 128;
 916                 denominator = 9750;
 917                 break;
 918         case 11289600:  /* 624*294/16250 */
 919                 numerator = 294;
 920                 denominator = 16250;
 921                 break;
 922         case 12288000:  /* 624*64/3250 */
 923                 numerator = 64;
 924                 denominator = 3250;
 925                 break;
 926         case 22579200:  /* 624*294/8125 */
 927                 numerator = 294;
 928                 denominator = 8125;
 929                 break;
 930         case 24576000:  /* 624*64/1625 */
 931                 numerator = 64;
 932                 denominator = 1625;
 933                 break;
 934         case 45158400:  /* 624*588/8125 */
 935                 numerator = 588;
 936                 denominator = 8125;
 937                 break;
 938         case 49152000:  /* 624*128/1625 */
 939                 numerator = 128;
 940                 denominator = 1625;
 941                 break;
 942         default:
 943                 return -ENOENT;
 944         }
 945
 946         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 947         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
 948
 949         return 0;
 950 }
 951
 952 static struct clk clk_i2s0_frac_div = {
 953         .name           = "i2s0_frac_div",
 954         .parent         = &clk_i2s0_div,
 955         .recalc         = clksel_recalc_frac,
 956         .set_rate       = clk_i2s_frac_div_set_rate,
 957         .clksel_con     = CRU_CLKSEL3_CON,
 958 };
 959
 960 static struct clk clk_i2s1_frac_div = {
 961         .name           = "i2s1_frac_div",
 962         .parent         = &clk_i2s1_div,
 963         .recalc         = clksel_recalc_frac,
 964         .set_rate       = clk_i2s_frac_div_set_rate,
 965         .clksel_con     = CRU_CLKSEL4_CON,
 966 };
 967
 968 static struct clk clk_spdif_frac_div = {
 969         .name           = "spdif_frac_div",
 970         .parent         = &clk_spdif_div,
 971         .recalc         = clksel_recalc_frac,
 972         .set_rate       = clk_i2s_frac_div_set_rate,
 973         .clksel_con     = CRU_CLKSEL5_CON,
 974 };
 975
 976 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 977 {
 978         int ret;
 979         struct clk *parent;
 980
 981         if (rate == 12 * MHZ) {
 982                 parent = &clk_12m;
 983         } else {
 984                 parent = clk->parents[1]; /* frac div */
 985                 ret = clk_set_rate_nolock(parent, rate);
 986                 if (ret)
 987                         return ret;
 988         }
 989         if (clk->parent != parent)
 990                 clk_set_parent_nolock(clk, parent);
 991
 992         return ret;
 993 }
 994
 995 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
 996
 997 static struct clk clk_i2s0 = {
 998         .name           = "i2s0",
 999         .mode           = gate_mode,
1000         .gate_idx       = CLK_GATE_I2S0,
1001         .set_rate       = i2s_set_rate,
1002         .clksel_con     = CRU_CLKSEL2_CON,
1003         .clksel_parent_mask     = 3,
1004         .clksel_parent_shift    = 8,
1005         .parents        = clk_i2s0_parents,
1006 };
1007
1008 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
1009
1010 static struct clk clk_i2s1 = {
1011         .name           = "i2s1",
1012         .mode           = gate_mode,
1013         .gate_idx       = CLK_GATE_I2S1,
1014         .set_rate       = i2s_set_rate,
1015         .clksel_con     = CRU_CLKSEL2_CON,
1016         .clksel_parent_mask     = 3,
1017         .clksel_parent_shift    = 18,
1018         .parents        = clk_i2s1_parents,
1019 };
1020
1021 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
1022
1023 static struct clk clk_spdif = {
1024         .name           = "spdif",
1025         .mode           = gate_mode,
1026         .gate_idx       = CLK_GATE_SPDIF,
1027         .set_rate       = i2s_set_rate,
1028         .clksel_con     = CRU_CLKSEL2_CON,
1029         .clksel_parent_mask     = 3,
1030         .clksel_parent_shift    = 28,
1031         .parents        = clk_spdif_parents,
1032 };
1033
1034
1035 static struct clk *clk_spi_src_parents[4] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1036
1037 static struct clk clk_spi_src = {
1038         .name           = "spi_src",
1039         .clksel_con     = CRU_CLKSEL6_CON,
1040         .clksel_parent_mask     = 3,
1041         .clksel_parent_shift    = 0,
1042         .parents        = clk_spi_src_parents,
1043 };
1044
1045 static struct clk clk_spi0 = {
1046         .name           = "spi0",
1047         .parent         = &clk_spi_src,
1048         .mode           = gate_mode,
1049         .recalc         = clksel_recalc_div,
1050         .set_rate       = clksel_set_rate_div,
1051         .gate_idx       = CLK_GATE_SPI0,
1052         .clksel_con     = CRU_CLKSEL6_CON,
1053         .clksel_mask    = 0x7F,
1054         .clksel_shift   = 2,
1055 };
1056
1057 static struct clk clk_spi1 = {
1058         .name           = "spi1",
1059         .parent         = &clk_spi_src,
1060         .mode           = gate_mode,
1061         .recalc         = clksel_recalc_div,
1062         .set_rate       = clksel_set_rate_div,
1063         .gate_idx       = CLK_GATE_SPI1,
1064         .clksel_con     = CRU_CLKSEL6_CON,
1065         .clksel_mask    = 0x7F,
1066         .clksel_shift   = 11,
1067 };
1068
1069
1070 static struct clk clk_saradc = {
1071         .name           = "saradc",
1072         .parent         = &pclk_periph,
1073         .mode           = gate_mode,
1074         .recalc         = clksel_recalc_div,
1075         .set_rate       = clksel_set_rate_div,
1076         .gate_idx       = CLK_GATE_SARADC,
1077         .clksel_con     = CRU_CLKSEL6_CON,
1078         .clksel_mask    = 0xFF,
1079         .clksel_shift   = 18,
1080 };
1081
1082
1083 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
1084
1085 static struct clk clk_timer0 = {
1086         .name           = "timer0",
1087         .mode           = gate_mode,
1088         .gate_idx       = CLK_GATE_TIMER0,
1089         .clksel_con     = CRU_CLKSEL6_CON,
1090         .clksel_parent_mask     = 1,
1091         .clksel_parent_shift    = 26,
1092         .parents        = clk_cpu_timer_parents,
1093 };
1094
1095 static struct clk clk_timer1 = {
1096         .name           = "timer1",
1097         .mode           = gate_mode,
1098         .gate_idx       = CLK_GATE_TIMER1,
1099         .clksel_con     = CRU_CLKSEL6_CON,
1100         .clksel_parent_mask     = 1,
1101         .clksel_parent_shift    = 27,
1102         .parents        = clk_cpu_timer_parents,
1103 };
1104
1105 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
1106
1107 static struct clk clk_timer2 = {
1108         .name           = "timer2",
1109         .mode           = gate_mode,
1110         .gate_idx       = CLK_GATE_TIMER2,
1111         .clksel_con     = CRU_CLKSEL6_CON,
1112         .clksel_parent_mask     = 1,
1113         .clksel_parent_shift    = 28,
1114         .parents        = clk_periph_timer_parents,
1115 };
1116
1117 static struct clk clk_timer3 = {
1118         .name           = "timer3",
1119         .mode           = gate_mode,
1120         .gate_idx       = CLK_GATE_TIMER3,
1121         .clksel_con     = CRU_CLKSEL6_CON,
1122         .clksel_parent_mask     = 1,
1123         .clksel_parent_shift    = 29,
1124         .parents        = clk_periph_timer_parents,
1125 };
1126
1127
1128 static struct clk *clk_sdmmc_src_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1129
1130 static struct clk clk_sdmmc_src = {
1131         .name           = "sdmmc_src",
1132         .clksel_con     = CRU_CLKSEL7_CON,
1133         .clksel_parent_mask     = 3,
1134         .clksel_parent_shift    = 0,
1135         .parents        = clk_sdmmc_src_parents,
1136 };
1137
1138 static struct clk clk_sdmmc0 = {
1139         .name           = "sdmmc0",
1140         .parent         = &clk_sdmmc_src,
1141         .mode           = gate_mode,
1142         .recalc         = clksel_recalc_div,
1143         .set_rate       = clksel_set_rate_div,
1144         .gate_idx       = CLK_GATE_SDMMC0,
1145         .clksel_con     = CRU_CLKSEL7_CON,
1146         .clksel_mask    = 0x3F,
1147         .clksel_shift   = 2,
1148 };
1149
1150 static struct clk clk_sdmmc1 = {
1151         .name           = "sdmmc1",
1152         .parent         = &clk_sdmmc_src,
1153         .mode           = gate_mode,
1154         .recalc         = clksel_recalc_div,
1155         .set_rate       = clksel_set_rate_div,
1156         .gate_idx       = CLK_GATE_SDMMC1,
1157         .clksel_con     = CRU_CLKSEL7_CON,
1158         .clksel_mask    = 0x3F,
1159         .clksel_shift   = 10,
1160 };
1161
1162 static struct clk clk_emmc = {
1163         .name           = "emmc",
1164         .parent         = &clk_sdmmc_src,
1165         .mode           = gate_mode,
1166         .recalc         = clksel_recalc_div,
1167         .set_rate       = clksel_set_rate_div,
1168         .gate_idx       = CLK_GATE_EMMC,
1169         .clksel_con     = CRU_CLKSEL7_CON,
1170         .clksel_mask    = 0x3F,
1171         .clksel_shift   = 18,
1172 };
1173
1174
1175 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &periph_pll_clk, &codec_pll_clk, &arm_pll_clk };
1176
1177 static struct clk clk_ddr = {
1178         .name           = "ddr",
1179         .recalc         = clksel_recalc_shift,
1180         .clksel_con     = CRU_CLKSEL7_CON,
1181         .clksel_mask    = 7,
1182         .clksel_shift   = 26,
1183         .clksel_maxdiv  = 32,
1184         .clksel_parent_mask     = 3,
1185         .clksel_parent_shift    = 24,
1186         .parents        = clk_ddr_parents,
1187 };
1188
1189
1190 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1191 {
1192         int ret;
1193         struct clk *parent;
1194         struct clk *clk_div = clk->parents[0];
1195
1196         switch (rate) {
1197         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
1198                 parent = clk->parents[2]; /* xin24m */
1199                 break;
1200         case 9600*16:
1201         case 19200*16:
1202         case 38400*16:
1203         case 57600*16:
1204         case 115200*16:
1205         case 230400*16:
1206         case 460800*16:
1207         case 576000*16:
1208         case 921600*16:
1209         case 1152000*16:
1210                 parent = clk->parents[1]; /* frac div */
1211                 /* reset div to 1 */
1212                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1213                 if (ret)
1214                         return ret;
1215                 break;
1216         default:
1217                 parent = clk_div;
1218                 break;
1219         }
1220
1221         if (parent->set_rate) {
1222                 ret = clk_set_rate_nolock(parent, rate);
1223                 if (ret)
1224                         return ret;
1225         }
1226
1227         if (clk->parent != parent)
1228                 clk_set_parent_nolock(clk, parent);
1229
1230         return 0;
1231 }
1232
1233 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1234 {
1235         u16 numerator, denominator;
1236
1237         switch (rate) {
1238         case 9600*16:
1239                 numerator = 2;
1240                 denominator = 8125;
1241                 break;
1242         case 19200*16:
1243                 numerator = 4;
1244                 denominator = 8125;
1245                 break;
1246         case 38400*16:
1247                 numerator = 8;
1248                 denominator = 8125;
1249                 break;
1250         case 57600*16:
1251                 numerator = 12;
1252                 denominator = 8125;
1253                 break;
1254         case 115200*16:
1255                 numerator = 24;
1256                 denominator = 8125;
1257                 break;
1258         case 230400*16:
1259                 numerator = 48;
1260                 denominator = 8125;
1261                 break;
1262         case 460800*16:
1263                 numerator = 96;
1264                 denominator = 8125;
1265                 break;
1266         case 576000*16:
1267                 numerator = 24;
1268                 denominator = 1625;
1269                 break;
1270         case 921600*16:
1271                 numerator = 192;
1272                 denominator = 8125;
1273                 break;
1274         case 1152000*16:
1275                 numerator = 48;
1276                 denominator = 1625;
1277                 break;
1278         default:
1279                 return -ENOENT;
1280         }
1281
1282         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1283         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
1284
1285         return 0;
1286 }
1287 static struct clk *clk_uart_src_parents[8] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1288
1289 static struct clk clk_uart01_src = {
1290         .name           = "uart01_src",
1291         .clksel_con     = CRU_CLKSEL8_CON,
1292         .clksel_parent_mask     = 7,
1293         .clksel_parent_shift    = 0,
1294         .parents        = clk_uart_src_parents,
1295 };
1296
1297 static struct clk clk_uart0_div = {
1298         .name           = "uart0_div",
1299         .parent         = &clk_uart01_src,
1300         .recalc         = clksel_recalc_div,
1301         .set_rate       = clksel_set_rate_div,
1302         .clksel_con     = CRU_CLKSEL8_CON,
1303         .clksel_mask    = 0x3F,
1304         .clksel_shift   = 3,
1305 };
1306
1307 static struct clk clk_uart0_frac_div = {
1308         .name           = "uart0_frac_div",
1309         .parent         = &clk_uart0_div,
1310         .recalc         = clksel_recalc_frac,
1311         .set_rate       = clk_uart_frac_div_set_rate,
1312         .clksel_con     = CRU_CLKSEL10_CON,
1313 };
1314
1315 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1316
1317 static struct clk clk_uart0 = {
1318         .name           = "uart0",
1319         .mode           = gate_mode,
1320         .set_rate       = clk_uart_set_rate,
1321         .gate_idx       = CLK_GATE_UART0,
1322         .clksel_con     = CRU_CLKSEL8_CON,
1323         .clksel_parent_mask     = 3,
1324         .clksel_parent_shift    = 9,
1325         .parents        = clk_uart0_parents,
1326 };
1327
1328 static struct clk clk_uart1_div = {
1329         .name           = "uart1_div",
1330         .parent         = &clk_uart01_src,
1331         .recalc         = clksel_recalc_div,
1332         .set_rate       = clksel_set_rate_div,
1333         .clksel_con     = CRU_CLKSEL8_CON,
1334         .clksel_mask    = 0x3F,
1335         .clksel_shift   = 14,
1336 };
1337
1338 static struct clk clk_uart1_frac_div = {
1339         .name           = "uart1_frac_div",
1340         .parent         = &clk_uart1_div,
1341         .recalc         = clksel_recalc_frac,
1342         .set_rate       = clk_uart_frac_div_set_rate,
1343         .clksel_con     = CRU_CLKSEL11_CON,
1344 };
1345
1346 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1347
1348 static struct clk clk_uart1 = {
1349         .name           = "uart1",
1350         .mode           = gate_mode,
1351         .set_rate       = clk_uart_set_rate,
1352         .gate_idx       = CLK_GATE_UART1,
1353         .clksel_con     = CRU_CLKSEL8_CON,
1354         .clksel_parent_mask     = 3,
1355         .clksel_parent_shift    = 20,
1356         .parents        = clk_uart1_parents,
1357 };
1358
1359 static struct clk clk_uart23_src = {
1360         .name           = "uart23_src",
1361         .clksel_con     = CRU_CLKSEL9_CON,
1362         .clksel_parent_mask     = 7,
1363         .clksel_parent_shift    = 0,
1364         .parents        = clk_uart_src_parents,
1365 };
1366
1367 static struct clk clk_uart2_div = {
1368         .name           = "uart2_div",
1369         .parent         = &clk_uart23_src,
1370         .recalc         = clksel_recalc_div,
1371         .set_rate       = clksel_set_rate_div,
1372         .clksel_con     = CRU_CLKSEL9_CON,
1373         .clksel_mask    = 0x3F,
1374         .clksel_shift   = 3,
1375 };
1376
1377 static struct clk clk_uart2_frac_div = {
1378         .name           = "uart2_frac_div",
1379         .parent         = &clk_uart2_div,
1380         .recalc         = clksel_recalc_frac,
1381         .set_rate       = clk_uart_frac_div_set_rate,
1382         .clksel_con     = CRU_CLKSEL12_CON,
1383 };
1384
1385 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1386
1387 static struct clk clk_uart2 = {
1388         .name           = "uart2",
1389         .mode           = gate_mode,
1390         .set_rate       = clk_uart_set_rate,
1391         .gate_idx       = CLK_GATE_UART2,
1392         .clksel_con     = CRU_CLKSEL9_CON,
1393         .clksel_parent_mask     = 3,
1394         .clksel_parent_shift    = 9,
1395         .parents        = clk_uart2_parents,
1396 };
1397
1398 static struct clk clk_uart3_div = {
1399         .name           = "uart3_div",
1400         .parent         = &clk_uart23_src,
1401         .recalc         = clksel_recalc_div,
1402         .set_rate       = clksel_set_rate_div,
1403         .clksel_con     = CRU_CLKSEL9_CON,
1404         .clksel_mask    = 0x3F,
1405         .clksel_shift   = 14,
1406 };
1407
1408 static struct clk clk_uart3_frac_div = {
1409         .name           = "uart3_frac_div",
1410         .parent         = &clk_uart3_div,
1411         .recalc         = clksel_recalc_frac,
1412         .set_rate       = clk_uart_frac_div_set_rate,
1413         .clksel_con     = CRU_CLKSEL13_CON,
1414 };
1415
1416 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1417
1418 static struct clk clk_uart3 = {
1419         .name           = "uart3",
1420         .mode           = gate_mode,
1421         .set_rate       = clk_uart_set_rate,
1422         .gate_idx       = CLK_GATE_UART3,
1423         .clksel_con     = CRU_CLKSEL9_CON,
1424         .clksel_parent_mask     = 3,
1425         .clksel_parent_shift    = 20,
1426         .parents        = clk_uart3_parents,
1427 };
1428
1429
1430 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &periph_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1431
1432 static struct clk clk_hsadc_div = {
1433         .name           = "hsadc_div",
1434         .recalc         = clksel_recalc_div,
1435         .set_rate       = clksel_set_rate_div,
1436         .clksel_con     = CRU_CLKSEL14_CON,
1437         .clksel_mask    = 0xFF,
1438         .clksel_shift   = 10,
1439         .clksel_parent_mask     = 7,
1440         .clksel_parent_shift    = 7,
1441         .parents        = clk_hsadc_div_parents,
1442 };
1443
1444 static struct clk clk_hsadc_frac_div = {
1445         .name           = "hsadc_frac_div",
1446         .parent         = &clk_hsadc_div,
1447         .recalc         = clksel_recalc_frac,
1448         .clksel_con     = CRU_CLKSEL15_CON,
1449 };
1450
1451 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
1452
1453 static struct clk clk_demod = {
1454         .name           = "demod",
1455         .clksel_con     = CRU_CLKSEL14_CON,
1456         .clksel_parent_mask     = 3,
1457         .clksel_parent_shift    = 18,
1458         .parents        = clk_demod_parents,
1459 };
1460
1461 static struct clk gpsclk = {
1462         .name           = "gpsclk",
1463 };
1464
1465 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1466
1467 static struct clk clk_hsadc = {
1468         .name           = "hsadc",
1469         .mode           = gate_mode,
1470         .gate_idx       = CLK_GATE_HSADC,
1471         .clksel_con     = CRU_CLKSEL14_CON,
1472         .clksel_parent_mask     = 1,
1473         .clksel_parent_shift    = 21,
1474         .parents        = clk_hsadc_parents,
1475 };
1476
1477 static unsigned long div2_recalc(struct clk *clk)
1478 {
1479         return clk->parent->rate >> 1;
1480 }
1481
1482 static struct clk clk_hsadc_div2 = {
1483         .name           = "hsadc_div2",
1484         .parent         = &clk_demod,
1485         .recalc         = div2_recalc,
1486 };
1487
1488 static struct clk clk_hsadc_div2_inv = {
1489         .name           = "hsadc_div2_inv",
1490         .parent         = &clk_demod,
1491         .recalc         = div2_recalc,
1492 };
1493
1494 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1495
1496 static struct clk clk_hsadc_out = {
1497         .name           = "hsadc_out",
1498         .clksel_con     = CRU_CLKSEL14_CON,
1499         .clksel_parent_mask     = 1,
1500         .clksel_parent_shift    = 20,
1501         .parents        = clk_hsadc_out_parents,
1502 };
1503
1504
1505 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &periph_pll_clk, &arm_pll_clk };
1506
1507 static struct clk dclk_lcdc_div = {
1508         .name           = "dclk_lcdc_div",
1509         .recalc         = clksel_recalc_div,
1510         .set_rate       = clksel_set_rate_div,
1511         .clksel_con     = CRU_CLKSEL16_CON,
1512         .clksel_mask    = 0xFF,
1513         .clksel_shift   = 2,
1514         .clksel_parent_mask     = 3,
1515         .clksel_parent_shift    = 0,
1516         .parents        = dclk_lcdc_div_parents,
1517 };
1518
1519 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
1520
1521 static struct clk dclk_lcdc = {
1522         .name           = "dclk_lcdc",
1523         .mode           = gate_mode,
1524         .gate_idx       = CLK_GATE_LCDC,
1525         .clksel_con     = CRU_CLKSEL16_CON,
1526         .clksel_parent_mask     = 1,
1527         .clksel_parent_shift    = 10,
1528         .parents        = dclk_lcdc_parents,
1529 };
1530
1531 static struct clk dclk_ebook = {
1532         .name           = "dclk_ebook",
1533         .mode           = gate_mode,
1534         .gate_idx       = CLK_GATE_EBOOK,
1535         .recalc         = clksel_recalc_div,
1536         .set_rate       = clksel_set_rate_div,
1537         .clksel_con     = CRU_CLKSEL16_CON,
1538         .clksel_mask    = 0x1F,
1539         .clksel_shift   = 13,
1540         .clksel_parent_mask     = 3,
1541         .clksel_parent_shift    = 11,
1542         .parents        = dclk_lcdc_div_parents,
1543 };
1544
1545 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &periph_pll_clk, &arm_pll_clk };
1546
1547 static struct clk aclk_lcdc = {
1548         .name           = "aclk_lcdc",
1549         .mode           = gate_mode,
1550         .gate_idx       = CLK_GATE_LCDC_AXI,
1551         .recalc         = clksel_recalc_div,
1552         .set_rate       = clksel_set_rate_div,
1553         .clksel_con     = CRU_CLKSEL16_CON,
1554         .clksel_mask    = 0x1F,
1555         .clksel_shift   = 20,
1556         .clksel_parent_mask     = 3,
1557         .clksel_parent_shift    = 18,
1558         .parents        = aclk_lcdc_parents,
1559 };
1560
1561 static struct clk hclk_lcdc = {
1562         .name           = "hclk_lcdc",
1563         .mode           = gate_mode,
1564         .gate_idx       = CLK_GATE_LCDC_AHB,
1565         .parent         = &aclk_lcdc,
1566         .clksel_con     = CRU_CLKSEL16_CON,
1567         .recalc         = clksel_recalc_shift,
1568         .set_rate       = clksel_set_rate_shift,
1569         .clksel_mask    = 3,
1570         .clksel_shift   = 25,
1571         .clksel_maxdiv  = 4,
1572 };
1573
1574 static struct clk *xpu_parents[4] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1575
1576 static struct clk aclk_vepu = {
1577         .name           = "aclk_vepu",
1578         .mode           = gate_mode,
1579         .recalc         = clksel_recalc_div,
1580         .set_rate       = clksel_set_rate_div,
1581         .gate_idx       = CLK_GAET_VEPU_AXI,
1582         .clksel_con     = CRU_CLKSEL17_CON,
1583         .clksel_mask    = 0x1F,
1584         .clksel_shift   = 2,
1585         .clksel_parent_mask     = 3,
1586         .clksel_parent_shift    = 0,
1587         .parents        = xpu_parents,
1588 };
1589
1590 static struct clk hclk_vepu = {
1591         .name           = "hclk_vepu",
1592         .parent         = &aclk_vepu,
1593         .mode           = gate_mode,
1594         .recalc         = clksel_recalc_shift,
1595         .set_rate       = clksel_set_rate_shift,
1596         .gate_idx       = CLK_GATE_VEPU_AHB,
1597         .clksel_con     = CRU_CLKSEL17_CON,
1598         .clksel_mask    = 3,
1599         .clksel_shift   = 28,
1600         .clksel_maxdiv  = 4,
1601 };
1602
1603 static struct clk aclk_vdpu = {
1604         .name           = "aclk_vdpu",
1605         .parent         = &periph_pll_clk,
1606         .mode           = gate_mode,
1607         .recalc         = clksel_recalc_div,
1608         .set_rate       = clksel_set_rate_div,
1609         .gate_idx       = CLK_GATE_VDPU_AXI,
1610         .clksel_con     = CRU_CLKSEL17_CON,
1611         .clksel_mask    = 0x1F,
1612         .clksel_shift   = 9,
1613         .clksel_parent_mask     = 3,
1614         .clksel_parent_shift    = 7,
1615         .parents        = xpu_parents,
1616 };
1617
1618 static struct clk hclk_vdpu = {
1619         .name           = "hclk_vdpu",
1620         .parent         = &aclk_vdpu,
1621         .mode           = gate_mode,
1622         .recalc         = clksel_recalc_shift,
1623         .set_rate       = clksel_set_rate_shift,
1624         .gate_idx       = CLK_GATE_VDPU_AHB,
1625         .clksel_con     = CRU_CLKSEL17_CON,
1626         .clksel_mask    = 3,
1627         .clksel_shift   = 30,
1628         .clksel_maxdiv  = 4,
1629 };
1630
1631 static struct clk clk_gpu = {
1632         .name           = "gpu",
1633         .mode           = gate_mode,
1634         .gate_idx       = CLK_GATE_GPU,
1635         .recalc         = clksel_recalc_div,
1636         .set_rate       = clksel_set_rate_div,
1637         .clksel_con     = CRU_CLKSEL17_CON,
1638         .clksel_mask    = 0x1F,
1639         .clksel_shift   = 16,
1640         .clksel_parent_mask     = 3,
1641         .clksel_parent_shift    = 14,
1642         .parents        = xpu_parents,
1643 };
1644
1645 static struct clk aclk_gpu = {
1646         .name           = "aclk_gpu",
1647         .mode           = gate_mode,
1648         .gate_idx       = CLK_GATE_GPU_AXI,
1649         .recalc         = clksel_recalc_div,
1650         .set_rate       = clksel_set_rate_div,
1651         .clksel_con     = CRU_CLKSEL17_CON,
1652         .clksel_mask    = 0x1F,
1653         .clksel_shift   = 23,
1654         .clksel_parent_mask     = 3,
1655         .clksel_parent_shift    = 21,
1656         .parents        = xpu_parents,
1657 };
1658
1659
1660 static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
1661
1662 static struct clk clk_vip = {
1663         .name           = "vip",
1664         .mode           = gate_mode,
1665         .gate_idx       = CLK_GATE_VIP,
1666         .clksel_con     = CRU_CLKSEL1_CON,
1667         .clksel_parent_mask     = 3,
1668         .clksel_parent_shift    = 7,
1669         .parents        = clk_vip_parents,
1670 };
1671
1672
1673 #define GATE_CLK(NAME,PARENT,ID) \
1674 static struct clk clk_##NAME = { \
1675         .name           = #NAME, \
1676         .parent         = &PARENT, \
1677         .mode           = gate_mode, \
1678         .gate_idx       = CLK_GATE_##ID, \
1679 }
1680
1681 GATE_CLK(i2c0, pclk_cpu, I2C0);
1682 GATE_CLK(i2c1, pclk_periph, I2C1);
1683 GATE_CLK(i2c2, pclk_periph, I2C2);
1684 GATE_CLK(i2c3, pclk_periph, I2C3);
1685
1686 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1687 GATE_CLK(gpio1, pclk_periph, GPIO1);
1688 GATE_CLK(gpio2, pclk_periph, GPIO2);
1689 GATE_CLK(gpio3, pclk_periph, GPIO3);
1690 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1691 GATE_CLK(gpio5, pclk_periph, GPIO5);
1692 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1693
1694 GATE_CLK(dma0, aclk_cpu, DMA0);
1695 GATE_CLK(dma1, aclk_periph, DMA1);
1696 GATE_CLK(dma2, aclk_periph, DMA2);
1697
1698 GATE_CLK(gic, aclk_cpu, GIC);
1699 GATE_CLK(imem, aclk_cpu, IMEM);
1700 GATE_CLK(ebrom, hclk_cpu, EBROM);
1701 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1702 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1703 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1704 GATE_CLK(efuse, pclk_cpu, EFUSE);
1705 GATE_CLK(tzpc, pclk_cpu, TZPC);
1706 GATE_CLK(debug, pclk_cpu, DEBUG);
1707 GATE_CLK(tpiu, pclk_cpu, TPIU);
1708 GATE_CLK(rtc, pclk_cpu, RTC);
1709 GATE_CLK(pmu, pclk_cpu, PMU);
1710 GATE_CLK(grf, pclk_cpu, GRF);
1711
1712 GATE_CLK(emem, hclk_periph, EMEM);
1713 GATE_CLK(usb, hclk_periph, USB);
1714 GATE_CLK(ddr_periph, aclk_periph, DDR_PERIPH);
1715 GATE_CLK(periph_cpu, aclk_cpu, PERIPH_CPU);
1716 GATE_CLK(smc_axi, aclk_periph, SMC_AXI);
1717 GATE_CLK(smc, pclk_periph, SMC);
1718 GATE_CLK(mac_ahb, hclk_periph, MAC_AHB);
1719 GATE_CLK(mac_tx, hclk_periph, MAC_TX);
1720 GATE_CLK(mac_rx, hclk_periph, MAC_RX);
1721 GATE_CLK(hif, hclk_periph, HIF);
1722 GATE_CLK(nandc, hclk_periph, NANDC);
1723 GATE_CLK(hsadc_ahb, hclk_periph, HSADC_AHB);
1724 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1725 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1726 GATE_CLK(uhost_ahb, hclk_periph, UHOST_AHB);
1727 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1728
1729 GATE_CLK(vip_slave, hclk_cpu, VIP_SLAVE);
1730 GATE_CLK(wdt, pclk_periph, WDT);
1731 GATE_CLK(pwm, pclk_periph, PWM);
1732 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1733 GATE_CLK(vip_matrix, hclk_cpu, VIP_MATRIX);
1734 GATE_CLK(vip_input, hclk_cpu, VIP_INPUT);
1735 GATE_CLK(jtag, aclk_cpu, JTAG);
1736
1737 GATE_CLK(ddr_lcdc_axi, aclk_cpu, DDR_LCDC_AXI);
1738 GATE_CLK(ipp_axi, aclk_cpu, IPP_AXI);
1739 GATE_CLK(ipp_ahb, hclk_cpu, IPP_AHB);
1740 GATE_CLK(ebook_ahb, hclk_cpu, EBOOK_AHB);
1741 GATE_CLK(display_matrix_axi, aclk_cpu, DISPLAY_MATRIX_AXI);
1742 GATE_CLK(display_matrix_ahb, hclk_cpu, DISPLAY_MATRIX_AHB);
1743 GATE_CLK(ddr_vepu_axi, aclk_cpu, DDR_VEPU_AXI);
1744 GATE_CLK(ddr_vdpu_axi, aclk_cpu, DDR_VDPU_AXI);
1745 GATE_CLK(ddr_gpu_axi, aclk_cpu, DDR_GPU_AXI);
1746 GATE_CLK(gpu_ahb, hclk_cpu, GPU_AHB);
1747 GATE_CLK(cpu_vcodec_ahb, hclk_cpu, CPU_VCODEC_AHB);
1748 GATE_CLK(cpu_display_ahb, hclk_cpu, CPU_DISPLAY_AHB);
1749
1750 GATE_CLK(sdmmc0_ahb, hclk_periph, SDMMC0_AHB);
1751 GATE_CLK(sdmmc1_ahb, hclk_periph, SDMMC1_AHB);
1752 GATE_CLK(emmc_ahb, hclk_periph, EMMC_AHB);
1753
1754 #define CLK(dev, con, ck) \
1755         { \
1756                 .dev_id = dev, \
1757                 .con_id = con, \
1758                 .clk = ck, \
1759         }
1760
1761 #define CLK1(name) \
1762         { \
1763                 .dev_id = NULL, \
1764                 .con_id = #name, \
1765                 .clk = &clk_##name, \
1766         }
1767
1768 static struct clk_lookup clks[] = {
1769         CLK(NULL, "xin24m", &xin24m),
1770         CLK(NULL, "xin27m", &xin27m),
1771         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1772         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1773         CLK(NULL, "gpsclk", &gpsclk),
1774
1775         CLK1(12m),
1776         CLK(NULL, "arm_pll", &arm_pll_clk),
1777         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1778         CLK(NULL, "codec_pll", &codec_pll_clk),
1779         CLK(NULL, "periph_pll", &periph_pll_clk),
1780
1781         CLK1(core),
1782         CLK(NULL, "aclk_cpu", &aclk_cpu),
1783         CLK(NULL, "hclk_cpu", &hclk_cpu),
1784         CLK(NULL, "pclk_cpu", &pclk_cpu),
1785
1786         CLK(NULL, "aclk_periph", &aclk_periph),
1787         CLK(NULL, "hclk_periph", &hclk_periph),
1788         CLK(NULL, "pclk_periph", &pclk_periph),
1789
1790         CLK1(vip),
1791         CLK("rk29_otgphy.0", "otgphy", &clk_otgphy0),
1792         CLK("rk29_otgphy.1", "otgphy", &clk_otgphy1),
1793         CLK(NULL, "uhost", &clk_uhost),
1794         CLK(NULL, "mac_ref_div", &clk_mac_ref_div),
1795         CLK(NULL, "mac_ref", &clk_mac_ref),
1796
1797         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
1798         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
1799         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
1800         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
1801         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
1802         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
1803         CLK(NULL, "spdif_div", &clk_spdif_div),
1804         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
1805         CLK(NULL, "spdif", &clk_spdif),
1806
1807         CLK1(spi_src),
1808         CLK("rk29xx_spim.0", "spi0", &clk_spi0),
1809         CLK("rk29xx_spim.1", "spi1", &clk_spi1),
1810
1811         CLK1(saradc),
1812         CLK1(timer0),
1813         CLK1(timer1),
1814         CLK1(timer2),
1815         CLK1(timer3),
1816
1817         CLK1(sdmmc_src),
1818         CLK("rk29_sdmmc.0", "sdmmc", &clk_sdmmc0),
1819         CLK("rk29_sdmmc.0", "sdmmc_ahb", &clk_sdmmc0_ahb),
1820         CLK("rk29_sdmmc.1", "sdmmc", &clk_sdmmc1),
1821         CLK("rk29_sdmmc.1", "sdmmc_ahb", &clk_sdmmc1_ahb),
1822         CLK1(emmc),
1823         CLK1(emmc_ahb),
1824         CLK1(ddr),
1825
1826         CLK1(uart01_src),
1827         CLK("rk29_serial.0", "uart", &clk_uart0),
1828         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
1829         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
1830         CLK("rk29_serial.1", "uart", &clk_uart1),
1831         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
1832         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
1833
1834         CLK1(uart23_src),
1835         CLK("rk29_serial.2", "uart", &clk_uart2),
1836         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
1837         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
1838         CLK("rk29_serial.3", "uart", &clk_uart3),
1839         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
1840         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
1841
1842         CLK1(hsadc_div),
1843         CLK1(hsadc_frac_div),
1844         CLK1(demod),
1845         CLK1(hsadc),
1846         CLK1(hsadc_div2),
1847         CLK1(hsadc_div2_inv),
1848         CLK1(hsadc_out),
1849
1850         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
1851         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
1852         CLK(NULL, "dclk_ebook", &dclk_ebook),
1853         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
1854         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
1855
1856         CLK(NULL, "aclk_vepu", &aclk_vepu),
1857         CLK(NULL, "hclk_vepu", &hclk_vepu),
1858         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
1859         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
1860         CLK1(gpu),
1861         CLK(NULL, "aclk_gpu", &aclk_gpu),
1862
1863         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
1864         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
1865         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
1866         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
1867
1868         CLK1(gpio0),
1869         CLK1(gpio1),
1870         CLK1(gpio2),
1871         CLK1(gpio3),
1872         CLK1(gpio4),
1873         CLK1(gpio5),
1874         CLK1(gpio6),
1875
1876         CLK1(dma0),
1877         CLK1(dma1),
1878         CLK1(dma2),
1879
1880         CLK1(gic),
1881         CLK1(imem),
1882         CLK1(ebrom),
1883         CLK1(ddr_phy),
1884         CLK1(ddr_reg),
1885         CLK1(ddr_cpu),
1886         CLK1(efuse),
1887         CLK1(tzpc),
1888         CLK1(debug),
1889         CLK1(tpiu),
1890         CLK1(rtc),
1891         CLK1(pmu),
1892         CLK1(grf),
1893
1894         CLK1(emem),
1895         CLK1(usb),
1896         CLK1(ddr_periph),
1897         CLK1(periph_cpu),
1898         CLK1(smc_axi),
1899         CLK1(smc),
1900         CLK1(mac_ahb),
1901         CLK1(mac_tx),
1902         CLK1(mac_rx),
1903         CLK1(hif),
1904         CLK1(nandc),
1905         CLK1(hsadc_ahb),
1906         CLK1(usbotg0),
1907         CLK1(usbotg1),
1908         CLK1(uhost_ahb),
1909         CLK1(pid_filter),
1910
1911         CLK1(vip_slave),
1912         CLK1(wdt),
1913         CLK1(pwm),
1914         CLK1(vip_bus),
1915         CLK1(vip_matrix),
1916         CLK1(vip_input),
1917         CLK1(jtag),
1918
1919         CLK1(ddr_lcdc_axi),
1920         CLK1(ipp_axi),
1921         CLK1(ipp_ahb),
1922         CLK1(ebook_ahb),
1923         CLK1(display_matrix_axi),
1924         CLK1(display_matrix_ahb),
1925         CLK1(ddr_vepu_axi),
1926         CLK1(ddr_vdpu_axi),
1927         CLK1(ddr_gpu_axi),
1928         CLK1(gpu_ahb),
1929         CLK1(cpu_vcodec_ahb),
1930         CLK1(cpu_display_ahb),
1931 };
1932
1933 static LIST_HEAD(clocks);
1934 static DEFINE_MUTEX(clocks_mutex);
1935 static DEFINE_SPINLOCK(clockfw_lock);
1936 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
1937 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
1938
1939 static int clk_enable_nolock(struct clk *clk)
1940 {
1941         int ret = 0;
1942
1943         if (clk->usecount == 0) {
1944                 if (clk->parent) {
1945                         ret = clk_enable_nolock(clk->parent);
1946                         if (ret)
1947                                 return ret;
1948                 }
1949
1950                 if (clk->mode) {
1951                         ret = clk->mode(clk, 1);
1952                         if (ret) {
1953                                 if (clk->parent)
1954                                         clk_disable_nolock(clk->parent);
1955                                 return ret;
1956                         }
1957                 }
1958                 pr_debug("%s enabled\n", clk->name);
1959         }
1960         clk->usecount++;
1961
1962         return ret;
1963 }
1964
1965 int clk_enable(struct clk *clk)
1966 {
1967         int ret = 0;
1968
1969         if (clk == NULL || IS_ERR(clk))
1970                 return -EINVAL;
1971
1972         LOCK();
1973         ret = clk_enable_nolock(clk);
1974         UNLOCK();
1975
1976         return ret;
1977 }
1978 EXPORT_SYMBOL(clk_enable);
1979
1980 static void clk_disable_nolock(struct clk *clk)
1981 {
1982         if (clk->usecount == 0) {
1983                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
1984                 WARN_ON(1);
1985                 return;
1986         }
1987
1988         if (--clk->usecount == 0) {
1989                 if (clk->mode)
1990                         clk->mode(clk, 0);
1991                 pr_debug("%s disabled\n", clk->name);
1992                 if (clk->parent)
1993                         clk_disable_nolock(clk->parent);
1994         }
1995 }
1996
1997 void clk_disable(struct clk *clk)
1998 {
1999         if (clk == NULL || IS_ERR(clk))
2000                 return;
2001
2002         LOCK();
2003         clk_disable_nolock(clk);
2004         UNLOCK();
2005 }
2006 EXPORT_SYMBOL(clk_disable);
2007
2008 unsigned long clk_get_rate(struct clk *clk)
2009 {
2010         if (clk == NULL || IS_ERR(clk))
2011                 return 0;
2012
2013         return clk->rate;
2014 }
2015 EXPORT_SYMBOL(clk_get_rate);
2016
2017 /*-------------------------------------------------------------------------
2018  * Optional clock functions defined in include/linux/clk.h
2019  *-------------------------------------------------------------------------*/
2020
2021 /* Given a clock and a rate apply a clock specific rounding function */
2022 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
2023 {
2024         if (clk->round_rate)
2025                 return clk->round_rate(clk, rate);
2026
2027         if (clk->flags & RATE_FIXED)
2028                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
2029
2030         return clk->rate;
2031 }
2032
2033 long clk_round_rate(struct clk *clk, unsigned long rate)
2034 {
2035         long ret = 0;
2036
2037         if (clk == NULL || IS_ERR(clk))
2038                 return ret;
2039
2040         LOCK();
2041         ret = clk_round_rate_nolock(clk, rate);
2042         UNLOCK();
2043
2044         return ret;
2045 }
2046 EXPORT_SYMBOL(clk_round_rate);
2047
2048 static void __clk_recalc(struct clk *clk)
2049 {
2050         if (unlikely(clk->flags & RATE_FIXED))
2051                 return;
2052         if (clk->recalc)
2053                 clk->rate = clk->recalc(clk);
2054         else if (clk->parent)
2055                 clk->rate = clk->parent->rate;
2056         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
2057 }
2058
2059 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
2060 {
2061         int ret;
2062
2063         if (rate == clk->rate)
2064                 return 0;
2065
2066         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
2067
2068         if (clk->flags & CONFIG_PARTICIPANT)
2069                 return -EINVAL;
2070
2071         if (!clk->set_rate)
2072                 return -EINVAL;
2073
2074         ret = clk->set_rate(clk, rate);
2075
2076         if (ret == 0) {
2077                 __clk_recalc(clk);
2078                 __propagate_rate(clk);
2079         }
2080
2081         return ret;
2082 }
2083
2084 /* Set the clock rate for a clock source */
2085 int clk_set_rate(struct clk *clk, unsigned long rate)
2086 {
2087         int ret = -EINVAL;
2088
2089         if (clk == NULL || IS_ERR(clk))
2090                 return ret;
2091
2092         LOCK();
2093         ret = clk_set_rate_nolock(clk, rate);
2094         UNLOCK();
2095
2096         return ret;
2097 }
2098 EXPORT_SYMBOL(clk_set_rate);
2099
2100 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
2101 {
2102         int ret;
2103         int enabled = clk->usecount > 0;
2104         struct clk *old_parent = clk->parent;
2105
2106         if (clk->parent == parent)
2107                 return 0;
2108
2109         /* if clk is already enabled, enable new parent first and disable old parent later. */
2110         if (enabled)
2111                 clk_enable_nolock(parent);
2112
2113         if (clk->set_parent)
2114                 ret = clk->set_parent(clk, parent);
2115         else
2116                 ret = clksel_set_parent(clk, parent);
2117
2118         if (ret == 0) {
2119                 /* OK */
2120                 __clk_reparent(clk, parent);
2121                 __clk_recalc(clk);
2122                 __propagate_rate(clk);
2123                 if (enabled)
2124                         clk_disable_nolock(old_parent);
2125         } else {
2126                 if (enabled)
2127                         clk_disable_nolock(parent);
2128         }
2129
2130         return ret;
2131 }
2132
2133 int clk_set_parent(struct clk *clk, struct clk *parent)
2134 {
2135         int ret = -EINVAL;
2136
2137         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
2138                 return ret;
2139
2140         if (clk->set_parent == NULL && clk->parents == NULL)
2141                 return ret;
2142
2143         LOCK();
2144         if (clk->usecount == 0)
2145                 ret = clk_set_parent_nolock(clk, parent);
2146         else
2147                 ret = -EBUSY;
2148         UNLOCK();
2149
2150         return ret;
2151 }
2152 EXPORT_SYMBOL(clk_set_parent);
2153
2154 struct clk *clk_get_parent(struct clk *clk)
2155 {
2156         return clk->parent;
2157 }
2158 EXPORT_SYMBOL(clk_get_parent);
2159
2160 static void __clk_reparent(struct clk *child, struct clk *parent)
2161 {
2162         if (child->parent == parent)
2163                 return;
2164         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
2165
2166         list_del_init(&child->sibling);
2167         if (parent)
2168                 list_add(&child->sibling, &parent->children);
2169         child->parent = parent;
2170 }
2171
2172 /* Propagate rate to children */
2173 static void __propagate_rate(struct clk *tclk)
2174 {
2175         struct clk *clkp;
2176
2177         list_for_each_entry(clkp, &tclk->children, sibling) {
2178                 __clk_recalc(clkp);
2179                 __propagate_rate(clkp);
2180         }
2181 }
2182
2183 static LIST_HEAD(root_clks);
2184
2185 /**
2186  * recalculate_root_clocks - recalculate and propagate all root clocks
2187  *
2188  * Recalculates all root clocks (clocks with no parent), which if the
2189  * clock's .recalc is set correctly, should also propagate their rates.
2190  * Called at init.
2191  */
2192 static void clk_recalculate_root_clocks_nolock(void)
2193 {
2194         struct clk *clkp;
2195
2196         list_for_each_entry(clkp, &root_clks, sibling) {
2197                 __clk_recalc(clkp);
2198                 __propagate_rate(clkp);
2199         }
2200 }
2201
2202 void clk_recalculate_root_clocks(void)
2203 {
2204         LOCK();
2205         clk_recalculate_root_clocks_nolock();
2206         UNLOCK();
2207 }
2208
2209
2210 /**
2211  * clk_preinit - initialize any fields in the struct clk before clk init
2212  * @clk: struct clk * to initialize
2213  *
2214  * Initialize any struct clk fields needed before normal clk initialization
2215  * can run.  No return value.
2216  */
2217 static void clk_preinit(struct clk *clk)
2218 {
2219         INIT_LIST_HEAD(&clk->children);
2220 }
2221
2222 static int clk_register(struct clk *clk)
2223 {
2224         if (clk == NULL || IS_ERR(clk))
2225                 return -EINVAL;
2226
2227         /*
2228          * trap out already registered clocks
2229          */
2230         if (clk->node.next || clk->node.prev)
2231                 return 0;
2232
2233         mutex_lock(&clocks_mutex);
2234
2235         if (clk->get_parent)
2236                 clk->parent = clk->get_parent(clk);
2237         else if (clk->parents)
2238                 clk->parent = clksel_get_parent(clk);
2239
2240         if (clk->parent)
2241                 list_add(&clk->sibling, &clk->parent->children);
2242         else
2243                 list_add(&clk->sibling, &root_clks);
2244
2245         list_add(&clk->node, &clocks);
2246
2247         mutex_unlock(&clocks_mutex);
2248
2249         return 0;
2250 }
2251
2252 static void clk_enable_init_clocks(void)
2253 {
2254         struct clk *clkp;
2255
2256         list_for_each_entry(clkp, &clocks, node) {
2257                 if (clkp->flags & ENABLE_ON_INIT)
2258                         clk_enable(clkp);
2259         }
2260 }
2261
2262 static void rk29_clock_common_init(void)
2263 {
2264         /* periph pll */
2265         clk_set_rate_nolock(&periph_pll_clk, 624 * MHZ);
2266         clk_set_parent_nolock(&aclk_periph, &periph_pll_clk);
2267         clk_set_rate_nolock(&aclk_periph, 208 * MHZ);
2268         clk_set_rate_nolock(&hclk_periph, 104 * MHZ);
2269         clk_set_rate_nolock(&pclk_periph, 52 * MHZ);
2270         clk_set_parent_nolock(&clk_uhost, &periph_pll_clk);
2271         clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2272         clk_set_parent_nolock(&clk_i2s0_div, &periph_pll_clk);
2273         clk_set_parent_nolock(&clk_i2s1_div, &periph_pll_clk);
2274         clk_set_parent_nolock(&clk_spdif_div, &periph_pll_clk);
2275         clk_set_parent_nolock(&clk_spi_src, &periph_pll_clk);
2276         clk_set_parent_nolock(&clk_sdmmc_src, &periph_pll_clk);
2277         clk_set_parent_nolock(&clk_uart01_src, &periph_pll_clk);
2278         clk_set_parent_nolock(&clk_uart23_src, &periph_pll_clk);
2279         clk_set_parent_nolock(&dclk_lcdc_div, &periph_pll_clk);
2280         clk_set_parent_nolock(&aclk_lcdc, &periph_pll_clk);
2281         clk_set_parent_nolock(&aclk_vepu, &periph_pll_clk);
2282         clk_set_parent_nolock(&aclk_vdpu, &periph_pll_clk);
2283         clk_set_parent_nolock(&clk_gpu, &periph_pll_clk);
2284         clk_set_parent_nolock(&aclk_gpu, &periph_pll_clk);
2285         clk_set_parent_nolock(&clk_mac_ref_div, &periph_pll_clk);
2286         clk_set_parent_nolock(&clk_hsadc_div, &periph_pll_clk);
2287
2288         /* arm pll */
2289         clk_set_rate_nolock(&arm_pll_clk, 624 * MHZ);
2290 }
2291
2292 void __init rk29_clock_init(void)
2293 {
2294         struct clk_lookup *lk;
2295
2296         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2297                 clk_preinit(lk->clk);
2298
2299         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2300                 clkdev_add(lk);
2301                 clk_register(lk->clk);
2302         }
2303
2304         clk_recalculate_root_clocks_nolock();
2305
2306         rk29_clock_common_init();
2307
2308         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/ppll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
2309                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, periph_pll_clk.rate / MHZ, clk_core.rate / MHZ,
2310                aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
2311
2312         /*
2313          * Only enable those clocks we will need, let the drivers
2314          * enable other clocks as necessary
2315          */
2316         clk_enable_init_clocks();
2317 }
2318
2319 #ifdef CONFIG_PROC_FS
2320 #include <linux/proc_fs.h>
2321 #include <linux/seq_file.h>
2322
2323 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2324 {
2325         struct clk* ck;
2326         int i;
2327         unsigned long rate = clk->rate;
2328
2329         for (i = 0; i < deep; i++)
2330                 seq_printf(s, "    ");
2331
2332         seq_printf(s, "%-9s ", clk->name);
2333
2334         if (clk->mode && (clk->gate_idx < CLK_GATE_MAX)) {
2335                 u32 reg;
2336                 int idx = clk->gate_idx;
2337                 u32 v;
2338
2339                 reg = CRU_CLKGATE0_CON;
2340                 reg += (idx >> 5) << 2;
2341                 idx &= 0x1F;
2342
2343                 v = cru_readl(reg) & (1 << idx);
2344
2345                 seq_printf(s, "%s ", v ? "off" : "on ");
2346         }
2347
2348         if (rate >= MHZ) {
2349                 if (rate % MHZ)
2350                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2351                 else
2352                         seq_printf(s, "%ld MHz", rate / MHZ);
2353         } else if (rate >= KHZ) {
2354                 if (rate % KHZ)
2355                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2356                 else
2357                         seq_printf(s, "%ld KHz", rate / KHZ);
2358         } else {
2359                 seq_printf(s, "%ld Hz", rate);
2360         }
2361
2362         seq_printf(s, " usecount = %d", clk->usecount);
2363
2364         seq_printf(s, " parent = %s\n", clk->parent ? clk->parent->name : "NULL");
2365
2366         list_for_each_entry(ck, &clocks, node) {
2367                 if (ck->parent == clk)
2368                         dump_clock(s, ck, deep + 1);
2369         }
2370 }
2371
2372 static int proc_clk_show(struct seq_file *s, void *v)
2373 {
2374         struct clk* clk;
2375
2376         mutex_lock(&clocks_mutex);
2377         list_for_each_entry(clk, &clocks, node) {
2378                 if (!clk->parent)
2379                         dump_clock(s, clk, 0);
2380         }
2381         mutex_unlock(&clocks_mutex);
2382
2383         seq_printf(s, "\nRegisters:\n");
2384         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2385         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2386         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2387         seq_printf(s, "PPLL     : 0x%08x\n", cru_readl(CRU_PPLL_CON));
2388         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2389         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2390         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2391         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2392         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2393         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2394         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2395         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2396         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2397         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2398         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2399         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2400         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2401         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2402         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2403         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2404         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2405         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2406         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2407         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2408         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2409         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2410         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2411
2412         return 0;
2413 }
2414
2415 static int proc_clk_open(struct inode *inode, struct file *file)
2416 {
2417         return single_open(file, proc_clk_show, NULL);
2418 }
2419
2420 static const struct file_operations proc_clk_fops = {
2421         .open           = proc_clk_open,
2422         .read           = seq_read,
2423         .llseek         = seq_lseek,
2424         .release        = single_release,
2425 };
2426
2427 static int __init clk_proc_init(void)
2428 {
2429         proc_create("clocks", 0, NULL, &proc_clk_fops);
2430         return 0;
2431
2432 }
2433 late_initcall(clk_proc_init);
2434 #endif /* CONFIG_PROC_FS */
2435