2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
43 #include <asm/mach/time.h>
44 #include <asm/smp_twd.h>
45 #include <asm/sched_clock.h>
47 #include <asm/arch_timer.h>
48 #include "omap_hwmod.h"
49 #include "omap_device.h"
50 #include <plat/counter-32k.h>
51 #include <plat/dmtimer.h>
56 #include "powerdomain.h"
58 /* Parent clocks, eventually these will come from the clock framework */
60 #define OMAP2_MPU_SOURCE "sys_ck"
61 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
62 #define OMAP4_MPU_SOURCE "sys_clkin_ck"
63 #define OMAP2_32K_SOURCE "func_32k_ck"
64 #define OMAP3_32K_SOURCE "omap_32k_fck"
65 #define OMAP4_32K_SOURCE "sys_32k_ck"
67 #ifdef CONFIG_OMAP_32K_TIMER
68 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
69 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
70 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
71 #define OMAP3_SECURE_TIMER 12
72 #define TIMER_PROP_SECURE "ti,timer-secure"
74 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
75 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
76 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
77 #define OMAP3_SECURE_TIMER 1
78 #define TIMER_PROP_SECURE "ti,timer-alwon"
81 #define REALTIME_COUNTER_BASE 0x48243200
82 #define INCREMENTER_NUMERATOR_OFFSET 0x10
83 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
84 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
88 static struct omap_dm_timer clkev;
89 static struct clock_event_device clockevent_gpt;
91 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
93 struct clock_event_device *evt = &clockevent_gpt;
95 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
97 evt->event_handler(evt);
101 static struct irqaction omap2_gp_timer_irq = {
103 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
104 .handler = omap2_gp_timer_interrupt,
107 static int omap2_gp_timer_set_next_event(unsigned long cycles,
108 struct clock_event_device *evt)
110 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
111 0xffffffff - cycles, 1);
116 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
117 struct clock_event_device *evt)
121 __omap_dm_timer_stop(&clkev, 1, clkev.rate);
124 case CLOCK_EVT_MODE_PERIODIC:
125 period = clkev.rate / HZ;
127 /* Looks like we need to first set the load value separately */
128 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
129 0xffffffff - period, 1);
130 __omap_dm_timer_load_start(&clkev,
131 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
132 0xffffffff - period, 1);
134 case CLOCK_EVT_MODE_ONESHOT:
136 case CLOCK_EVT_MODE_UNUSED:
137 case CLOCK_EVT_MODE_SHUTDOWN:
138 case CLOCK_EVT_MODE_RESUME:
143 static struct clock_event_device clockevent_gpt = {
145 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
148 .set_next_event = omap2_gp_timer_set_next_event,
149 .set_mode = omap2_gp_timer_set_mode,
152 static struct property device_disabled = {
154 .length = sizeof("disabled"),
158 static struct of_device_id omap_timer_match[] __initdata = {
159 { .compatible = "ti,omap2-timer", },
163 static struct of_device_id omap_counter_match[] __initdata = {
164 { .compatible = "ti,omap-counter32k", },
169 * omap_get_timer_dt - get a timer using device-tree
170 * @match - device-tree match structure for matching a device type
171 * @property - optional timer property to match
173 * Helper function to get a timer during early boot using device-tree for use
174 * as kernel system timer. Optionally, the property argument can be used to
175 * select a timer with a specific property. Once a timer is found then mark
176 * the timer node in device-tree as disabled, to prevent the kernel from
177 * registering this timer as a platform device and so no one else can use it.
179 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
180 const char *property)
182 struct device_node *np;
184 for_each_matching_node(np, match) {
185 if (!of_device_is_available(np)) {
190 if (property && !of_get_property(np, property, NULL)) {
195 prom_add_property(np, &device_disabled);
203 * omap_dmtimer_init - initialisation function when device tree is used
205 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
206 * be used by the kernel as they are reserved. Therefore, to prevent the
207 * kernel registering these devices remove them dynamically from the device
210 void __init omap_dmtimer_init(void)
212 struct device_node *np;
214 if (!cpu_is_omap34xx())
217 /* If we are a secure device, remove any secure timer nodes */
218 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
219 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
225 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
227 const char *fck_source,
228 const char *property)
230 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
232 struct device_node *np;
233 struct omap_hwmod *oh;
234 struct resource irq_rsrc, mem_rsrc;
239 if (of_have_populated_dt()) {
240 np = omap_get_timer_dt(omap_timer_match, NULL);
244 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
248 timer->irq = irq_of_parse_and_map(np, 0);
252 timer->io_base = of_iomap(np, 0);
256 if (omap_dm_timer_reserve_systimer(gptimer_id))
259 sprintf(name, "timer%d", gptimer_id);
263 omap_hwmod_setup_one(oh_name);
264 oh = omap_hwmod_lookup(oh_name);
269 if (!of_have_populated_dt()) {
270 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
274 timer->irq = irq_rsrc.start;
276 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
280 timer->phys_base = mem_rsrc.start;
281 size = mem_rsrc.end - mem_rsrc.start;
283 /* Static mapping, never released */
284 timer->io_base = ioremap(timer->phys_base, size);
290 /* After the dmtimer is using hwmod these clocks won't be needed */
291 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
292 if (IS_ERR(timer->fclk))
295 omap_hwmod_enable(oh);
297 /* FIXME: Need to remove hard-coded test on timer ID */
298 if (gptimer_id != 12) {
301 src = clk_get(NULL, fck_source);
305 res = __omap_dm_timer_set_source(timer->fclk, src);
306 if (IS_ERR_VALUE(res))
307 pr_warn("%s: %s cannot set source\n",
312 __omap_dm_timer_init_regs(timer);
313 __omap_dm_timer_reset(timer, 1, 1);
316 timer->rate = clk_get_rate(timer->fclk);
323 static void __init omap2_gp_clockevent_init(int gptimer_id,
324 const char *fck_source,
325 const char *property)
329 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property);
332 omap2_gp_timer_irq.dev_id = &clkev;
333 setup_irq(clkev.irq, &omap2_gp_timer_irq);
335 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
337 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
338 clockevent_gpt.shift);
339 clockevent_gpt.max_delta_ns =
340 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
341 clockevent_gpt.min_delta_ns =
342 clockevent_delta2ns(3, &clockevent_gpt);
343 /* Timer internal resynch latency. */
345 clockevent_gpt.cpumask = cpu_possible_mask;
346 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
347 clockevents_register_device(&clockevent_gpt);
349 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
350 gptimer_id, clkev.rate);
353 /* Clocksource code */
354 static struct omap_dm_timer clksrc;
355 static bool use_gptimer_clksrc;
360 static cycle_t clocksource_read_cycles(struct clocksource *cs)
362 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
365 static struct clocksource clocksource_gpt = {
368 .read = clocksource_read_cycles,
369 .mask = CLOCKSOURCE_MASK(32),
370 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
373 static u32 notrace dmtimer_read_sched_clock(void)
376 return __omap_dm_timer_read_counter(&clksrc, 1);
381 #ifdef CONFIG_OMAP_32K_TIMER
382 /* Setup free-running counter for clocksource */
383 static int __init omap2_sync32k_clocksource_init(void)
386 struct device_node *np = NULL;
387 struct omap_hwmod *oh;
389 const char *oh_name = "counter_32k";
392 * If device-tree is present, then search the DT blob
393 * to see if the 32kHz counter is supported.
395 if (of_have_populated_dt()) {
396 np = omap_get_timer_dt(omap_counter_match, NULL);
400 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
406 * First check hwmod data is available for sync32k counter
408 oh = omap_hwmod_lookup(oh_name);
409 if (!oh || oh->slaves_cnt == 0)
412 omap_hwmod_setup_one(oh_name);
415 vbase = of_iomap(np, 0);
418 vbase = omap_hwmod_get_mpu_rt_va(oh);
422 pr_warn("%s: failed to get counter_32k resource\n", __func__);
426 ret = omap_hwmod_enable(oh);
428 pr_warn("%s: failed to enable counter_32k module (%d)\n",
433 ret = omap_init_clocksource_32k(vbase);
435 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
443 static inline int omap2_sync32k_clocksource_init(void)
449 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
450 const char *fck_source)
454 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL);
457 __omap_dm_timer_load_start(&clksrc,
458 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
459 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
461 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
462 pr_err("Could not register clocksource %s\n",
463 clocksource_gpt.name);
465 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
466 gptimer_id, clksrc.rate);
469 static void __init omap2_clocksource_init(int gptimer_id,
470 const char *fck_source)
473 * First give preference to kernel parameter configuration
474 * by user (clocksource="gp_timer").
476 * In case of missing kernel parameter for clocksource,
477 * first check for availability for 32k-sync timer, in case
478 * of failure in finding 32k_counter module or registering
479 * it as clocksource, execution will fallback to gp-timer.
481 if (use_gptimer_clksrc == true)
482 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
483 else if (omap2_sync32k_clocksource_init())
484 /* Fall back to gp-timer code */
485 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
488 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
490 * The realtime counter also called master counter, is a free-running
491 * counter, which is related to real time. It produces the count used
492 * by the CPU local timer peripherals in the MPU cluster. The timer counts
493 * at a rate of 6.144 MHz. Because the device operates on different clocks
494 * in different power modes, the master counter shifts operation between
495 * clocks, adjusting the increment per clock in hardware accordingly to
496 * maintain a constant count rate.
498 static void __init realtime_counter_init(void)
501 static struct clk *sys_clk;
503 unsigned int reg, num, den;
505 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
507 pr_err("%s: ioremap failed\n", __func__);
510 sys_clk = clk_get(NULL, "sys_clkin_ck");
511 if (IS_ERR(sys_clk)) {
512 pr_err("%s: failed to get system clock handle\n", __func__);
517 rate = clk_get_rate(sys_clk);
518 /* Numerator/denumerator values refer TRM Realtime Counter section */
542 /* Program it for 38.4 MHz */
548 /* Program numerator and denumerator registers */
549 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
550 NUMERATOR_DENUMERATOR_MASK;
552 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
554 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
555 NUMERATOR_DENUMERATOR_MASK;
557 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
562 static inline void __init realtime_counter_init(void)
566 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
567 clksrc_nr, clksrc_src) \
568 static void __init omap##name##_timer_init(void) \
570 omap_dmtimer_init(); \
571 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
572 omap2_clocksource_init((clksrc_nr), clksrc_src); \
575 #define OMAP_SYS_TIMER(name) \
576 struct sys_timer omap##name##_timer = { \
577 .init = omap##name##_timer_init, \
580 #ifdef CONFIG_ARCH_OMAP2
581 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon",
586 #ifdef CONFIG_ARCH_OMAP3
587 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon",
590 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
591 TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE)
592 OMAP_SYS_TIMER(3_secure)
595 #ifdef CONFIG_SOC_AM33XX
596 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
598 OMAP_SYS_TIMER(3_am33xx)
601 #ifdef CONFIG_ARCH_OMAP4
602 #ifdef CONFIG_LOCAL_TIMERS
603 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
604 OMAP44XX_LOCAL_TWD_BASE, 29);
607 static void __init omap4_timer_init(void)
609 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
610 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
611 #ifdef CONFIG_LOCAL_TIMERS
612 /* Local timers are not supprted on OMAP4430 ES1.0 */
613 if (omap_rev() != OMAP4430_REV_ES1_0) {
616 if (of_have_populated_dt()) {
617 twd_local_timer_of_register();
621 err = twd_local_timer_register(&twd_local_timer);
623 pr_err("twd_local_timer_register failed %d\n", err);
630 #ifdef CONFIG_SOC_OMAP5
631 static void __init omap5_timer_init(void)
635 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
636 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
637 realtime_counter_init();
639 err = arch_timer_of_register();
641 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
647 * omap_timer_init - build and register timer device with an
648 * associated timer hwmod
649 * @oh: timer hwmod pointer to be used to build timer device
650 * @user: parameter that can be passed from calling hwmod API
652 * Called by omap_hwmod_for_each_by_class to register each of the timer
653 * devices present in the system. The number of timer devices is known
654 * by parsing through the hwmod database for a given class name. At the
655 * end of function call memory is allocated for timer device and it is
656 * registered to the framework ready to be proved by the driver.
658 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
662 char *name = "omap_timer";
663 struct dmtimer_platform_data *pdata;
664 struct platform_device *pdev;
665 struct omap_timer_capability_dev_attr *timer_dev_attr;
667 pr_debug("%s: %s\n", __func__, oh->name);
669 /* on secure device, do not register secure timer */
670 timer_dev_attr = oh->dev_attr;
671 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
672 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
675 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
677 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
682 * Extract the IDs from name field in hwmod database
683 * and use the same for constructing ids' for the
684 * timer devices. In a way, we are avoiding usage of
685 * static variable witin the function to do the same.
686 * CAUTION: We have to be careful and make sure the
687 * name in hwmod database does not change in which case
688 * we might either make corresponding change here or
689 * switch back static variable mechanism.
691 sscanf(oh->name, "timer%2d", &id);
694 pdata->timer_capability = timer_dev_attr->timer_capability;
696 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
698 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
702 pr_err("%s: Can't build omap_device for %s: %s.\n",
703 __func__, name, oh->name);
713 * omap2_dm_timer_init - top level regular device initialization
715 * Uses dedicated hwmod api to parse through hwmod database for
716 * given class name and then build and register the timer device.
718 static int __init omap2_dm_timer_init(void)
722 /* If dtb is there, the devices will be created dynamically */
723 if (of_have_populated_dt())
726 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
728 pr_err("%s: device registration failed.\n", __func__);
734 arch_initcall(omap2_dm_timer_init);
737 * omap2_override_clocksource - clocksource override with user configuration
739 * Allows user to override default clocksource, using kernel parameter
740 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
742 * Note that, here we are using same standard kernel parameter "clocksource=",
743 * and not introducing any OMAP specific interface.
745 static int __init omap2_override_clocksource(char *str)
750 * For OMAP architecture, we only have two options
751 * - sync_32k (default)
752 * - gp_timer (sys_clk based)
754 if (!strcmp(str, "gp_timer"))
755 use_gptimer_clksrc = true;
759 early_param("clocksource", omap2_override_clocksource);