2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
41 #include <asm/mach/time.h>
42 #include <asm/smp_twd.h>
43 #include <asm/sched_clock.h>
45 #include <asm/arch_timer.h>
46 #include "omap_hwmod.h"
47 #include "omap_device.h"
48 #include <plat/counter-32k.h>
49 #include <plat/dmtimer.h>
54 #include "powerdomain.h"
56 /* Parent clocks, eventually these will come from the clock framework */
58 #define OMAP2_MPU_SOURCE "sys_ck"
59 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
60 #define OMAP4_MPU_SOURCE "sys_clkin_ck"
61 #define OMAP2_32K_SOURCE "func_32k_ck"
62 #define OMAP3_32K_SOURCE "omap_32k_fck"
63 #define OMAP4_32K_SOURCE "sys_32k_ck"
65 #ifdef CONFIG_OMAP_32K_TIMER
66 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
67 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
68 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
69 #define OMAP3_SECURE_TIMER 12
71 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
72 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
73 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
74 #define OMAP3_SECURE_TIMER 1
77 #define REALTIME_COUNTER_BASE 0x48243200
78 #define INCREMENTER_NUMERATOR_OFFSET 0x10
79 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
80 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
84 static struct omap_dm_timer clkev;
85 static struct clock_event_device clockevent_gpt;
87 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
89 struct clock_event_device *evt = &clockevent_gpt;
91 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
93 evt->event_handler(evt);
97 static struct irqaction omap2_gp_timer_irq = {
99 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
100 .handler = omap2_gp_timer_interrupt,
103 static int omap2_gp_timer_set_next_event(unsigned long cycles,
104 struct clock_event_device *evt)
106 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
107 0xffffffff - cycles, 1);
112 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
113 struct clock_event_device *evt)
117 __omap_dm_timer_stop(&clkev, 1, clkev.rate);
120 case CLOCK_EVT_MODE_PERIODIC:
121 period = clkev.rate / HZ;
123 /* Looks like we need to first set the load value separately */
124 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
125 0xffffffff - period, 1);
126 __omap_dm_timer_load_start(&clkev,
127 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
128 0xffffffff - period, 1);
130 case CLOCK_EVT_MODE_ONESHOT:
132 case CLOCK_EVT_MODE_UNUSED:
133 case CLOCK_EVT_MODE_SHUTDOWN:
134 case CLOCK_EVT_MODE_RESUME:
139 static struct clock_event_device clockevent_gpt = {
141 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
144 .set_next_event = omap2_gp_timer_set_next_event,
145 .set_mode = omap2_gp_timer_set_mode,
148 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
150 const char *fck_source)
152 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
153 struct omap_hwmod *oh;
154 struct resource irq_rsrc, mem_rsrc;
159 sprintf(name, "timer%d", gptimer_id);
160 omap_hwmod_setup_one(name);
161 oh = omap_hwmod_lookup(name);
165 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
168 timer->irq = irq_rsrc.start;
170 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
173 timer->phys_base = mem_rsrc.start;
174 size = mem_rsrc.end - mem_rsrc.start;
176 /* Static mapping, never released */
177 timer->io_base = ioremap(timer->phys_base, size);
181 /* After the dmtimer is using hwmod these clocks won't be needed */
182 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
183 if (IS_ERR(timer->fclk))
186 omap_hwmod_enable(oh);
188 if (omap_dm_timer_reserve_systimer(gptimer_id))
191 if (gptimer_id != 12) {
194 src = clk_get(NULL, fck_source);
198 res = __omap_dm_timer_set_source(timer->fclk, src);
199 if (IS_ERR_VALUE(res))
200 pr_warning("%s: timer%i cannot set source\n",
201 __func__, gptimer_id);
205 __omap_dm_timer_init_regs(timer);
206 __omap_dm_timer_reset(timer, 1, 1);
209 timer->rate = clk_get_rate(timer->fclk);
216 static void __init omap2_gp_clockevent_init(int gptimer_id,
217 const char *fck_source)
221 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
224 omap2_gp_timer_irq.dev_id = &clkev;
225 setup_irq(clkev.irq, &omap2_gp_timer_irq);
227 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
229 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
230 clockevent_gpt.shift);
231 clockevent_gpt.max_delta_ns =
232 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
233 clockevent_gpt.min_delta_ns =
234 clockevent_delta2ns(3, &clockevent_gpt);
235 /* Timer internal resynch latency. */
237 clockevent_gpt.cpumask = cpu_possible_mask;
238 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
239 clockevents_register_device(&clockevent_gpt);
241 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
242 gptimer_id, clkev.rate);
245 /* Clocksource code */
246 static struct omap_dm_timer clksrc;
247 static bool use_gptimer_clksrc;
252 static cycle_t clocksource_read_cycles(struct clocksource *cs)
254 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
257 static struct clocksource clocksource_gpt = {
260 .read = clocksource_read_cycles,
261 .mask = CLOCKSOURCE_MASK(32),
262 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
265 static u32 notrace dmtimer_read_sched_clock(void)
268 return __omap_dm_timer_read_counter(&clksrc, 1);
273 #ifdef CONFIG_OMAP_32K_TIMER
274 /* Setup free-running counter for clocksource */
275 static int __init omap2_sync32k_clocksource_init(void)
278 struct omap_hwmod *oh;
280 const char *oh_name = "counter_32k";
283 * First check hwmod data is available for sync32k counter
285 oh = omap_hwmod_lookup(oh_name);
286 if (!oh || oh->slaves_cnt == 0)
289 omap_hwmod_setup_one(oh_name);
291 vbase = omap_hwmod_get_mpu_rt_va(oh);
293 pr_warn("%s: failed to get counter_32k resource\n", __func__);
297 ret = omap_hwmod_enable(oh);
299 pr_warn("%s: failed to enable counter_32k module (%d)\n",
304 ret = omap_init_clocksource_32k(vbase);
306 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
314 static inline int omap2_sync32k_clocksource_init(void)
320 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
321 const char *fck_source)
325 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
328 __omap_dm_timer_load_start(&clksrc,
329 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
330 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
332 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
333 pr_err("Could not register clocksource %s\n",
334 clocksource_gpt.name);
336 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
337 gptimer_id, clksrc.rate);
340 static void __init omap2_clocksource_init(int gptimer_id,
341 const char *fck_source)
344 * First give preference to kernel parameter configuration
345 * by user (clocksource="gp_timer").
347 * In case of missing kernel parameter for clocksource,
348 * first check for availability for 32k-sync timer, in case
349 * of failure in finding 32k_counter module or registering
350 * it as clocksource, execution will fallback to gp-timer.
352 if (use_gptimer_clksrc == true)
353 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
354 else if (omap2_sync32k_clocksource_init())
355 /* Fall back to gp-timer code */
356 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
359 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
361 * The realtime counter also called master counter, is a free-running
362 * counter, which is related to real time. It produces the count used
363 * by the CPU local timer peripherals in the MPU cluster. The timer counts
364 * at a rate of 6.144 MHz. Because the device operates on different clocks
365 * in different power modes, the master counter shifts operation between
366 * clocks, adjusting the increment per clock in hardware accordingly to
367 * maintain a constant count rate.
369 static void __init realtime_counter_init(void)
372 static struct clk *sys_clk;
374 unsigned int reg, num, den;
376 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
378 pr_err("%s: ioremap failed\n", __func__);
381 sys_clk = clk_get(NULL, "sys_clkin_ck");
382 if (IS_ERR(sys_clk)) {
383 pr_err("%s: failed to get system clock handle\n", __func__);
388 rate = clk_get_rate(sys_clk);
389 /* Numerator/denumerator values refer TRM Realtime Counter section */
413 /* Program it for 38.4 MHz */
419 /* Program numerator and denumerator registers */
420 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
421 NUMERATOR_DENUMERATOR_MASK;
423 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
425 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
426 NUMERATOR_DENUMERATOR_MASK;
428 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
433 static inline void __init realtime_counter_init(void)
437 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
438 clksrc_nr, clksrc_src) \
439 static void __init omap##name##_timer_init(void) \
441 omap2_gp_clockevent_init((clkev_nr), clkev_src); \
442 omap2_clocksource_init((clksrc_nr), clksrc_src); \
445 #define OMAP_SYS_TIMER(name) \
446 struct sys_timer omap##name##_timer = { \
447 .init = omap##name##_timer_init, \
450 #ifdef CONFIG_ARCH_OMAP2
451 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
455 #ifdef CONFIG_ARCH_OMAP3
456 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
458 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
460 OMAP_SYS_TIMER(3_secure)
463 #ifdef CONFIG_SOC_AM33XX
464 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
465 OMAP_SYS_TIMER(3_am33xx)
468 #ifdef CONFIG_ARCH_OMAP4
469 #ifdef CONFIG_LOCAL_TIMERS
470 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
471 OMAP44XX_LOCAL_TWD_BASE, 29);
474 static void __init omap4_timer_init(void)
476 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
477 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
478 #ifdef CONFIG_LOCAL_TIMERS
479 /* Local timers are not supprted on OMAP4430 ES1.0 */
480 if (omap_rev() != OMAP4430_REV_ES1_0) {
483 if (of_have_populated_dt()) {
484 twd_local_timer_of_register();
488 err = twd_local_timer_register(&twd_local_timer);
490 pr_err("twd_local_timer_register failed %d\n", err);
497 #ifdef CONFIG_SOC_OMAP5
498 static void __init omap5_timer_init(void)
502 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
503 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
504 realtime_counter_init();
506 err = arch_timer_of_register();
508 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
514 * omap_timer_init - build and register timer device with an
515 * associated timer hwmod
516 * @oh: timer hwmod pointer to be used to build timer device
517 * @user: parameter that can be passed from calling hwmod API
519 * Called by omap_hwmod_for_each_by_class to register each of the timer
520 * devices present in the system. The number of timer devices is known
521 * by parsing through the hwmod database for a given class name. At the
522 * end of function call memory is allocated for timer device and it is
523 * registered to the framework ready to be proved by the driver.
525 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
529 char *name = "omap_timer";
530 struct dmtimer_platform_data *pdata;
531 struct platform_device *pdev;
532 struct omap_timer_capability_dev_attr *timer_dev_attr;
534 pr_debug("%s: %s\n", __func__, oh->name);
536 /* on secure device, do not register secure timer */
537 timer_dev_attr = oh->dev_attr;
538 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
539 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
542 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
544 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
549 * Extract the IDs from name field in hwmod database
550 * and use the same for constructing ids' for the
551 * timer devices. In a way, we are avoiding usage of
552 * static variable witin the function to do the same.
553 * CAUTION: We have to be careful and make sure the
554 * name in hwmod database does not change in which case
555 * we might either make corresponding change here or
556 * switch back static variable mechanism.
558 sscanf(oh->name, "timer%2d", &id);
561 pdata->timer_capability = timer_dev_attr->timer_capability;
563 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
565 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
569 pr_err("%s: Can't build omap_device for %s: %s.\n",
570 __func__, name, oh->name);
580 * omap2_dm_timer_init - top level regular device initialization
582 * Uses dedicated hwmod api to parse through hwmod database for
583 * given class name and then build and register the timer device.
585 static int __init omap2_dm_timer_init(void)
589 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
591 pr_err("%s: device registration failed.\n", __func__);
597 arch_initcall(omap2_dm_timer_init);
600 * omap2_override_clocksource - clocksource override with user configuration
602 * Allows user to override default clocksource, using kernel parameter
603 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
605 * Note that, here we are using same standard kernel parameter "clocksource=",
606 * and not introducing any OMAP specific interface.
608 static int __init omap2_override_clocksource(char *str)
613 * For OMAP architecture, we only have two options
614 * - sync_32k (default)
615 * - gp_timer (sys_clk based)
617 if (!strcmp(str, "gp_timer"))
618 use_gptimer_clksrc = true;
622 early_param("clocksource", omap2_override_clocksource);