arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44 #include <linux/sched_clock.h>
  45
  46 #include <asm/mach/time.h>
  47 #include <asm/smp_twd.h>
  48
  49 #include "omap_hwmod.h"
  50 #include "omap_device.h"
  51 #include <plat/counter-32k.h>
  52 #include <plat/dmtimer.h>
  53 #include "omap-pm.h"
  54
  55 #include "soc.h"
  56 #include "common.h"
  57 #include "control.h"
  58 #include "powerdomain.h"
  59 #include "omap-secure.h"
  60
  61 #define REALTIME_COUNTER_BASE                           0x48243200
  62 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  64 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  65
  66 /* Clockevent code */
  67
  68 static struct omap_dm_timer clkev;
  69 static struct clock_event_device clockevent_gpt;
  70
  71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
  72 static unsigned long arch_timer_freq;
  73
  74 void set_cntfreq(void)
  75 {
  76         omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
  77 }
  78 #endif
  79
  80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  81 {
  82         struct clock_event_device *evt = &clockevent_gpt;
  83
  84         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  85
  86         evt->event_handler(evt);
  87         return IRQ_HANDLED;
  88 }
  89
  90 static struct irqaction omap2_gp_timer_irq = {
  91         .name           = "gp_timer",
  92         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
  93         .handler        = omap2_gp_timer_interrupt,
  94 };
  95
  96 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  97                                          struct clock_event_device *evt)
  98 {
  99         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 100                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 101
 102         return 0;
 103 }
 104
 105 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 106                                     struct clock_event_device *evt)
 107 {
 108         u32 period;
 109
 110         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 111
 112         switch (mode) {
 113         case CLOCK_EVT_MODE_PERIODIC:
 114                 period = clkev.rate / HZ;
 115                 period -= 1;
 116                 /* Looks like we need to first set the load value separately */
 117                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 118                                       0xffffffff - period, OMAP_TIMER_POSTED);
 119                 __omap_dm_timer_load_start(&clkev,
 120                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 121                                         0xffffffff - period, OMAP_TIMER_POSTED);
 122                 break;
 123         case CLOCK_EVT_MODE_ONESHOT:
 124                 break;
 125         case CLOCK_EVT_MODE_UNUSED:
 126         case CLOCK_EVT_MODE_SHUTDOWN:
 127         case CLOCK_EVT_MODE_RESUME:
 128                 break;
 129         }
 130 }
 131
 132 static struct clock_event_device clockevent_gpt = {
 133         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 134         .rating         = 300,
 135         .set_next_event = omap2_gp_timer_set_next_event,
 136         .set_mode       = omap2_gp_timer_set_mode,
 137 };
 138
 139 static struct property device_disabled = {
 140         .name = "status",
 141         .length = sizeof("disabled"),
 142         .value = "disabled",
 143 };
 144
 145 static const struct of_device_id omap_timer_match[] __initconst = {
 146         { .compatible = "ti,omap2420-timer", },
 147         { .compatible = "ti,omap3430-timer", },
 148         { .compatible = "ti,omap4430-timer", },
 149         { .compatible = "ti,omap5430-timer", },
 150         { .compatible = "ti,am335x-timer", },
 151         { .compatible = "ti,am335x-timer-1ms", },
 152         { }
 153 };
 154
 155 /**
 156  * omap_get_timer_dt - get a timer using device-tree
 157  * @match       - device-tree match structure for matching a device type
 158  * @property    - optional timer property to match
 159  *
 160  * Helper function to get a timer during early boot using device-tree for use
 161  * as kernel system timer. Optionally, the property argument can be used to
 162  * select a timer with a specific property. Once a timer is found then mark
 163  * the timer node in device-tree as disabled, to prevent the kernel from
 164  * registering this timer as a platform device and so no one else can use it.
 165  */
 166 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
 167                                                      const char *property)
 168 {
 169         struct device_node *np;
 170
 171         for_each_matching_node(np, match) {
 172                 if (!of_device_is_available(np))
 173                         continue;
 174
 175                 if (property && !of_get_property(np, property, NULL))
 176                         continue;
 177
 178                 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
 179                                   of_get_property(np, "ti,timer-dsp", NULL) ||
 180                                   of_get_property(np, "ti,timer-pwm", NULL) ||
 181                                   of_get_property(np, "ti,timer-secure", NULL)))
 182                         continue;
 183
 184                 of_add_property(np, &device_disabled);
 185                 return np;
 186         }
 187
 188         return NULL;
 189 }
 190
 191 /**
 192  * omap_dmtimer_init - initialisation function when device tree is used
 193  *
 194  * For secure OMAP3 devices, timers with device type "timer-secure" cannot
 195  * be used by the kernel as they are reserved. Therefore, to prevent the
 196  * kernel registering these devices remove them dynamically from the device
 197  * tree on boot.
 198  */
 199 static void __init omap_dmtimer_init(void)
 200 {
 201         struct device_node *np;
 202
 203         if (!cpu_is_omap34xx())
 204                 return;
 205
 206         /* If we are a secure device, remove any secure timer nodes */
 207         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 208                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 209                 if (np)
 210                         of_node_put(np);
 211         }
 212 }
 213
 214 /**
 215  * omap_dm_timer_get_errata - get errata flags for a timer
 216  *
 217  * Get the timer errata flags that are specific to the OMAP device being used.
 218  */
 219 static u32 __init omap_dm_timer_get_errata(void)
 220 {
 221         if (cpu_is_omap24xx())
 222                 return 0;
 223
 224         return OMAP_TIMER_ERRATA_I103_I767;
 225 }
 226
 227 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 228                                          const char *fck_source,
 229                                          const char *property,
 230                                          const char **timer_name,
 231                                          int posted)
 232 {
 233         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 234         const char *oh_name = NULL;
 235         struct device_node *np;
 236         struct omap_hwmod *oh;
 237         struct resource irq, mem;
 238         struct clk *src;
 239         int r = 0;
 240
 241         if (of_have_populated_dt()) {
 242                 np = omap_get_timer_dt(omap_timer_match, property);
 243                 if (!np)
 244                         return -ENODEV;
 245
 246                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 247                 if (!oh_name)
 248                         return -ENODEV;
 249
 250                 timer->irq = irq_of_parse_and_map(np, 0);
 251                 if (!timer->irq)
 252                         return -ENXIO;
 253
 254                 timer->io_base = of_iomap(np, 0);
 255
 256                 of_node_put(np);
 257         } else {
 258                 if (omap_dm_timer_reserve_systimer(timer->id))
 259                         return -ENODEV;
 260
 261                 sprintf(name, "timer%d", timer->id);
 262                 oh_name = name;
 263         }
 264
 265         oh = omap_hwmod_lookup(oh_name);
 266         if (!oh)
 267                 return -ENODEV;
 268
 269         *timer_name = oh->name;
 270
 271         if (!of_have_populated_dt()) {
 272                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
 273                                                    &irq);
 274                 if (r)
 275                         return -ENXIO;
 276                 timer->irq = irq.start;
 277
 278                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
 279                                                    &mem);
 280                 if (r)
 281                         return -ENXIO;
 282
 283                 /* Static mapping, never released */
 284                 timer->io_base = ioremap(mem.start, mem.end - mem.start);
 285         }
 286
 287         if (!timer->io_base)
 288                 return -ENXIO;
 289
 290         /* After the dmtimer is using hwmod these clocks won't be needed */
 291         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 292         if (IS_ERR(timer->fclk))
 293                 return PTR_ERR(timer->fclk);
 294
 295         src = clk_get(NULL, fck_source);
 296         if (IS_ERR(src))
 297                 return PTR_ERR(src);
 298
 299         if (clk_get_parent(timer->fclk) != src) {
 300                 r = clk_set_parent(timer->fclk, src);
 301                 if (r < 0) {
 302                         pr_warn("%s: %s cannot set source\n", __func__,
 303                                 oh->name);
 304                         clk_put(src);
 305                         return r;
 306                 }
 307         }
 308
 309         clk_put(src);
 310
 311         omap_hwmod_setup_one(oh_name);
 312         omap_hwmod_enable(oh);
 313         __omap_dm_timer_init_regs(timer);
 314
 315         if (posted)
 316                 __omap_dm_timer_enable_posted(timer);
 317
 318         /* Check that the intended posted configuration matches the actual */
 319         if (posted != timer->posted)
 320                 return -EINVAL;
 321
 322         timer->rate = clk_get_rate(timer->fclk);
 323         timer->reserved = 1;
 324
 325         return r;
 326 }
 327
 328 static void __init omap2_gp_clockevent_init(int gptimer_id,
 329                                                 const char *fck_source,
 330                                                 const char *property)
 331 {
 332         int res;
 333
 334         clkev.id = gptimer_id;
 335         clkev.errata = omap_dm_timer_get_errata();
 336
 337         /*
 338          * For clock-event timers we never read the timer counter and
 339          * so we are not impacted by errata i103 and i767. Therefore,
 340          * we can safely ignore this errata for clock-event timers.
 341          */
 342         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 343
 344         res = omap_dm_timer_init_one(&clkev, fck_source, property,
 345                                      &clockevent_gpt.name, OMAP_TIMER_POSTED);
 346         BUG_ON(res);
 347
 348         omap2_gp_timer_irq.dev_id = &clkev;
 349         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 350
 351         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 352
 353         clockevent_gpt.cpumask = cpu_possible_mask;
 354         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 355         clockevents_config_and_register(&clockevent_gpt, clkev.rate,
 356                                         3, /* Timer internal resynch latency */
 357                                         0xffffffff);
 358
 359         pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
 360                 clkev.rate);
 361 }
 362
 363 /* Clocksource code */
 364 static struct omap_dm_timer clksrc;
 365 static bool use_gptimer_clksrc __initdata;
 366
 367 /*
 368  * clocksource
 369  */
 370 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 371 {
 372         return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
 373                                                      OMAP_TIMER_NONPOSTED);
 374 }
 375
 376 static struct clocksource clocksource_gpt = {
 377         .rating         = 300,
 378         .read           = clocksource_read_cycles,
 379         .mask           = CLOCKSOURCE_MASK(32),
 380         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 381 };
 382
 383 static u64 notrace dmtimer_read_sched_clock(void)
 384 {
 385         if (clksrc.reserved)
 386                 return __omap_dm_timer_read_counter(&clksrc,
 387                                                     OMAP_TIMER_NONPOSTED);
 388
 389         return 0;
 390 }
 391
 392 static const struct of_device_id omap_counter_match[] __initconst = {
 393         { .compatible = "ti,omap-counter32k", },
 394         { }
 395 };
 396
 397 /* Setup free-running counter for clocksource */
 398 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 399 {
 400         int ret;
 401         struct device_node *np = NULL;
 402         struct omap_hwmod *oh;
 403         void __iomem *vbase;
 404         const char *oh_name = "counter_32k";
 405
 406         /*
 407          * If device-tree is present, then search the DT blob
 408          * to see if the 32kHz counter is supported.
 409          */
 410         if (of_have_populated_dt()) {
 411                 np = omap_get_timer_dt(omap_counter_match, NULL);
 412                 if (!np)
 413                         return -ENODEV;
 414
 415                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 416                 if (!oh_name)
 417                         return -ENODEV;
 418         }
 419
 420         /*
 421          * First check hwmod data is available for sync32k counter
 422          */
 423         oh = omap_hwmod_lookup(oh_name);
 424         if (!oh || oh->slaves_cnt == 0)
 425                 return -ENODEV;
 426
 427         omap_hwmod_setup_one(oh_name);
 428
 429         if (np) {
 430                 vbase = of_iomap(np, 0);
 431                 of_node_put(np);
 432         } else {
 433                 vbase = omap_hwmod_get_mpu_rt_va(oh);
 434         }
 435
 436         if (!vbase) {
 437                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
 438                 return -ENXIO;
 439         }
 440
 441         ret = omap_hwmod_enable(oh);
 442         if (ret) {
 443                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 444                                                         __func__, ret);
 445                 return ret;
 446         }
 447
 448         ret = omap_init_clocksource_32k(vbase);
 449         if (ret) {
 450                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 451                                                         __func__, ret);
 452                 omap_hwmod_idle(oh);
 453         }
 454
 455         return ret;
 456 }
 457
 458 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 459                                                   const char *fck_source,
 460                                                   const char *property)
 461 {
 462         int res;
 463
 464         clksrc.id = gptimer_id;
 465         clksrc.errata = omap_dm_timer_get_errata();
 466
 467         res = omap_dm_timer_init_one(&clksrc, fck_source, property,
 468                                      &clocksource_gpt.name,
 469                                      OMAP_TIMER_NONPOSTED);
 470         BUG_ON(res);
 471
 472         __omap_dm_timer_load_start(&clksrc,
 473                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 474                                    OMAP_TIMER_NONPOSTED);
 475         sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
 476
 477         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 478                 pr_err("Could not register clocksource %s\n",
 479                         clocksource_gpt.name);
 480         else
 481                 pr_info("OMAP clocksource: %s at %lu Hz\n",
 482                         clocksource_gpt.name, clksrc.rate);
 483 }
 484
 485 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 486 /*
 487  * The realtime counter also called master counter, is a free-running
 488  * counter, which is related to real time. It produces the count used
 489  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 490  * at a rate of 6.144 MHz. Because the device operates on different clocks
 491  * in different power modes, the master counter shifts operation between
 492  * clocks, adjusting the increment per clock in hardware accordingly to
 493  * maintain a constant count rate.
 494  */
 495 static void __init realtime_counter_init(void)
 496 {
 497         void __iomem *base;
 498         static struct clk *sys_clk;
 499         unsigned long rate;
 500         unsigned int reg;
 501         unsigned long long num, den;
 502
 503         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 504         if (!base) {
 505                 pr_err("%s: ioremap failed\n", __func__);
 506                 return;
 507         }
 508         sys_clk = clk_get(NULL, "sys_clkin");
 509         if (IS_ERR(sys_clk)) {
 510                 pr_err("%s: failed to get system clock handle\n", __func__);
 511                 iounmap(base);
 512                 return;
 513         }
 514
 515         rate = clk_get_rate(sys_clk);
 516
 517         if (soc_is_dra7xx()) {
 518                 /*
 519                  * Errata i856 says the 32.768KHz crystal does not start at
 520                  * power on, so the CPU falls back to an emulated 32KHz clock
 521                  * based on sysclk / 610 instead. This causes the master counter
 522                  * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
 523                  * (OR sysclk * 75 / 244)
 524                  *
 525                  * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
 526                  * Of course any board built without a populated 32.768KHz
 527                  * crystal would also need this fix even if the CPU is fixed
 528                  * later.
 529                  *
 530                  * Either case can be detected by using the two speedselect bits
 531                  * If they are not 0, then the 32.768KHz clock driving the
 532                  * coarse counter that corrects the fine counter every time it
 533                  * ticks is actually rate/610 rather than 32.768KHz and we
 534                  * should compensate to avoid the 570ppm (at 20MHz, much worse
 535                  * at other rates) too fast system time.
 536                  */
 537                 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
 538                 if (reg & DRA7_SPEEDSELECT_MASK) {
 539                         num = 75;
 540                         den = 244;
 541                         goto sysclk1_based;
 542                 }
 543         }
 544
 545         /* Numerator/denumerator values refer TRM Realtime Counter section */
 546         switch (rate) {
 547         case 12000000:
 548                 num = 64;
 549                 den = 125;
 550                 break;
 551         case 13000000:
 552                 num = 768;
 553                 den = 1625;
 554                 break;
 555         case 19200000:
 556                 num = 8;
 557                 den = 25;
 558                 break;
 559         case 20000000:
 560                 num = 192;
 561                 den = 625;
 562                 break;
 563         case 26000000:
 564                 num = 384;
 565                 den = 1625;
 566                 break;
 567         case 27000000:
 568                 num = 256;
 569                 den = 1125;
 570                 break;
 571         case 38400000:
 572         default:
 573                 /* Program it for 38.4 MHz */
 574                 num = 4;
 575                 den = 25;
 576                 break;
 577         }
 578
 579 sysclk1_based:
 580         /* Program numerator and denumerator registers */
 581         reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
 582                         NUMERATOR_DENUMERATOR_MASK;
 583         reg |= num;
 584         writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 585
 586         reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
 587                         NUMERATOR_DENUMERATOR_MASK;
 588         reg |= den;
 589         writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 590
 591         arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
 592         set_cntfreq();
 593
 594         iounmap(base);
 595 }
 596 #else
 597 static inline void __init realtime_counter_init(void)
 598 {}
 599 #endif
 600
 601 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
 602                                clksrc_nr, clksrc_src, clksrc_prop)      \
 603 void __init omap##name##_gptimer_timer_init(void)                       \
 604 {                                                                       \
 605         omap_clk_init();                                        \
 606         omap_dmtimer_init();                                            \
 607         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 608         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
 609                                         clksrc_prop);                   \
 610 }
 611
 612 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
 613                                 clksrc_nr, clksrc_src, clksrc_prop)     \
 614 void __init omap##name##_sync32k_timer_init(void)               \
 615 {                                                                       \
 616         omap_clk_init();                                        \
 617         omap_dmtimer_init();                                            \
 618         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 619         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
 620         if (use_gptimer_clksrc)                                         \
 621                 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
 622                                                 clksrc_prop);           \
 623         else                                                            \
 624                 omap2_sync32k_clocksource_init();                       \
 625 }
 626
 627 #ifdef CONFIG_ARCH_OMAP2
 628 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
 629                         2, "timer_sys_ck", NULL);
 630 #endif /* CONFIG_ARCH_OMAP2 */
 631
 632 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 633 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
 634                         2, "timer_sys_ck", NULL);
 635 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
 636                         2, "timer_sys_ck", NULL);
 637 #endif /* CONFIG_ARCH_OMAP3 */
 638
 639 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
 640         defined(CONFIG_SOC_AM43XX)
 641 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
 642                        1, "timer_sys_ck", "ti,timer-alwon");
 643 #endif
 644
 645 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 646         defined(CONFIG_SOC_DRA7XX)
 647 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
 648                                2, "sys_clkin_ck", NULL);
 649 #endif
 650
 651 #ifdef CONFIG_ARCH_OMAP4
 652 #ifdef CONFIG_HAVE_ARM_TWD
 653 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 654 void __init omap4_local_timer_init(void)
 655 {
 656         omap4_sync32k_timer_init();
 657         /* Local timers are not supprted on OMAP4430 ES1.0 */
 658         if (omap_rev() != OMAP4430_REV_ES1_0) {
 659                 int err;
 660
 661                 if (of_have_populated_dt()) {
 662                         clocksource_of_init();
 663                         return;
 664                 }
 665
 666                 err = twd_local_timer_register(&twd_local_timer);
 667                 if (err)
 668                         pr_err("twd_local_timer_register failed %d\n", err);
 669         }
 670 }
 671 #else
 672 void __init omap4_local_timer_init(void)
 673 {
 674         omap4_sync32k_timer_init();
 675 }
 676 #endif /* CONFIG_HAVE_ARM_TWD */
 677 #endif /* CONFIG_ARCH_OMAP4 */
 678
 679 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 680 void __init omap5_realtime_timer_init(void)
 681 {
 682         omap4_sync32k_timer_init();
 683         realtime_counter_init();
 684
 685         clocksource_of_init();
 686 }
 687 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
 688
 689 /**
 690  * omap_timer_init - build and register timer device with an
 691  * associated timer hwmod
 692  * @oh: timer hwmod pointer to be used to build timer device
 693  * @user:       parameter that can be passed from calling hwmod API
 694  *
 695  * Called by omap_hwmod_for_each_by_class to register each of the timer
 696  * devices present in the system. The number of timer devices is known
 697  * by parsing through the hwmod database for a given class name. At the
 698  * end of function call memory is allocated for timer device and it is
 699  * registered to the framework ready to be proved by the driver.
 700  */
 701 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 702 {
 703         int id;
 704         int ret = 0;
 705         char *name = "omap_timer";
 706         struct dmtimer_platform_data *pdata;
 707         struct platform_device *pdev;
 708         struct omap_timer_capability_dev_attr *timer_dev_attr;
 709
 710         pr_debug("%s: %s\n", __func__, oh->name);
 711
 712         /* on secure device, do not register secure timer */
 713         timer_dev_attr = oh->dev_attr;
 714         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 715                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 716                         return ret;
 717
 718         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 719         if (!pdata) {
 720                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 721                 return -ENOMEM;
 722         }
 723
 724         /*
 725          * Extract the IDs from name field in hwmod database
 726          * and use the same for constructing ids' for the
 727          * timer devices. In a way, we are avoiding usage of
 728          * static variable witin the function to do the same.
 729          * CAUTION: We have to be careful and make sure the
 730          * name in hwmod database does not change in which case
 731          * we might either make corresponding change here or
 732          * switch back static variable mechanism.
 733          */
 734         sscanf(oh->name, "timer%2d", &id);
 735
 736         if (timer_dev_attr)
 737                 pdata->timer_capability = timer_dev_attr->timer_capability;
 738
 739         pdata->timer_errata = omap_dm_timer_get_errata();
 740         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 741
 742         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
 743
 744         if (IS_ERR(pdev)) {
 745                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 746                         __func__, name, oh->name);
 747                 ret = -EINVAL;
 748         }
 749
 750         kfree(pdata);
 751
 752         return ret;
 753 }
 754
 755 /**
 756  * omap2_dm_timer_init - top level regular device initialization
 757  *
 758  * Uses dedicated hwmod api to parse through hwmod database for
 759  * given class name and then build and register the timer device.
 760  */
 761 static int __init omap2_dm_timer_init(void)
 762 {
 763         int ret;
 764
 765         /* If dtb is there, the devices will be created dynamically */
 766         if (of_have_populated_dt())
 767                 return -ENODEV;
 768
 769         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 770         if (unlikely(ret)) {
 771                 pr_err("%s: device registration failed.\n", __func__);
 772                 return -EINVAL;
 773         }
 774
 775         return 0;
 776 }
 777 omap_arch_initcall(omap2_dm_timer_init);
 778
 779 /**
 780  * omap2_override_clocksource - clocksource override with user configuration
 781  *
 782  * Allows user to override default clocksource, using kernel parameter
 783  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 784  *
 785  * Note that, here we are using same standard kernel parameter "clocksource=",
 786  * and not introducing any OMAP specific interface.
 787  */
 788 static int __init omap2_override_clocksource(char *str)
 789 {
 790         if (!str)
 791                 return 0;
 792         /*
 793          * For OMAP architecture, we only have two options
 794          *    - sync_32k (default)
 795          *    - gp_timer (sys_clk based)
 796          */
 797         if (!strcmp(str, "gp_timer"))
 798                 use_gptimer_clksrc = true;
 799
 800         return 0;
 801 }
 802 early_param("clocksource", omap2_override_clocksource);